pmap.c revision 267964
1/*- 2 * Copyright (c) 1991 Regents of the University of California. 3 * All rights reserved. 4 * Copyright (c) 1994 John S. Dyson 5 * All rights reserved. 6 * Copyright (c) 1994 David Greenman 7 * All rights reserved. 8 * Copyright (c) 2005-2010 Alan L. Cox <alc@cs.rice.edu> 9 * All rights reserved. 10 * 11 * This code is derived from software contributed to Berkeley by 12 * the Systems Programming Group of the University of Utah Computer 13 * Science Department and William Jolitz of UUNET Technologies Inc. 14 * 15 * Redistribution and use in source and binary forms, with or without 16 * modification, are permitted provided that the following conditions 17 * are met: 18 * 1. Redistributions of source code must retain the above copyright 19 * notice, this list of conditions and the following disclaimer. 20 * 2. Redistributions in binary form must reproduce the above copyright 21 * notice, this list of conditions and the following disclaimer in the 22 * documentation and/or other materials provided with the distribution. 23 * 3. All advertising materials mentioning features or use of this software 24 * must display the following acknowledgement: 25 * This product includes software developed by the University of 26 * California, Berkeley and its contributors. 27 * 4. Neither the name of the University nor the names of its contributors 28 * may be used to endorse or promote products derived from this software 29 * without specific prior written permission. 30 * 31 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 32 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 33 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 34 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 35 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 36 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 37 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 38 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 39 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 40 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 41 * SUCH DAMAGE. 42 * 43 * from: @(#)pmap.c 7.7 (Berkeley) 5/12/91 44 */ 45/*- 46 * Copyright (c) 2003 Networks Associates Technology, Inc. 47 * All rights reserved. 48 * 49 * This software was developed for the FreeBSD Project by Jake Burkholder, 50 * Safeport Network Services, and Network Associates Laboratories, the 51 * Security Research Division of Network Associates, Inc. under 52 * DARPA/SPAWAR contract N66001-01-C-8035 ("CBOSS"), as part of the DARPA 53 * CHATS research program. 54 * 55 * Redistribution and use in source and binary forms, with or without 56 * modification, are permitted provided that the following conditions 57 * are met: 58 * 1. Redistributions of source code must retain the above copyright 59 * notice, this list of conditions and the following disclaimer. 60 * 2. Redistributions in binary form must reproduce the above copyright 61 * notice, this list of conditions and the following disclaimer in the 62 * documentation and/or other materials provided with the distribution. 63 * 64 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 65 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 66 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 67 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 68 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 69 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 70 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 71 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 72 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 73 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 74 * SUCH DAMAGE. 75 */ 76 77#include <sys/cdefs.h> 78__FBSDID("$FreeBSD: stable/10/sys/i386/i386/pmap.c 267964 2014-06-27 17:22:18Z jhb $"); 79 80/* 81 * Manages physical address maps. 82 * 83 * Since the information managed by this module is 84 * also stored by the logical address mapping module, 85 * this module may throw away valid virtual-to-physical 86 * mappings at almost any time. However, invalidations 87 * of virtual-to-physical mappings must be done as 88 * requested. 89 * 90 * In order to cope with hardware architectures which 91 * make virtual-to-physical map invalidates expensive, 92 * this module may delay invalidate or reduced protection 93 * operations until such time as they are actually 94 * necessary. This module is given full information as 95 * to which processors are currently using which maps, 96 * and to when physical maps must be made correct. 97 */ 98 99#include "opt_apic.h" 100#include "opt_cpu.h" 101#include "opt_pmap.h" 102#include "opt_smp.h" 103#include "opt_xbox.h" 104 105#include <sys/param.h> 106#include <sys/systm.h> 107#include <sys/kernel.h> 108#include <sys/ktr.h> 109#include <sys/lock.h> 110#include <sys/malloc.h> 111#include <sys/mman.h> 112#include <sys/msgbuf.h> 113#include <sys/mutex.h> 114#include <sys/proc.h> 115#include <sys/rwlock.h> 116#include <sys/sf_buf.h> 117#include <sys/sx.h> 118#include <sys/vmmeter.h> 119#include <sys/sched.h> 120#include <sys/sysctl.h> 121#ifdef SMP 122#include <sys/smp.h> 123#else 124#include <sys/cpuset.h> 125#endif 126 127#include <vm/vm.h> 128#include <vm/vm_param.h> 129#include <vm/vm_kern.h> 130#include <vm/vm_page.h> 131#include <vm/vm_map.h> 132#include <vm/vm_object.h> 133#include <vm/vm_extern.h> 134#include <vm/vm_pageout.h> 135#include <vm/vm_pager.h> 136#include <vm/vm_radix.h> 137#include <vm/vm_reserv.h> 138#include <vm/uma.h> 139 140#ifdef DEV_APIC 141#include <sys/bus.h> 142#include <machine/intr_machdep.h> 143#include <machine/apicvar.h> 144#endif 145#include <machine/cpu.h> 146#include <machine/cputypes.h> 147#include <machine/md_var.h> 148#include <machine/pcb.h> 149#include <machine/specialreg.h> 150#ifdef SMP 151#include <machine/smp.h> 152#endif 153 154#ifdef XBOX 155#include <machine/xbox.h> 156#endif 157 158#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU) 159#define CPU_ENABLE_SSE 160#endif 161 162#ifndef PMAP_SHPGPERPROC 163#define PMAP_SHPGPERPROC 200 164#endif 165 166#if !defined(DIAGNOSTIC) 167#ifdef __GNUC_GNU_INLINE__ 168#define PMAP_INLINE __attribute__((__gnu_inline__)) inline 169#else 170#define PMAP_INLINE extern inline 171#endif 172#else 173#define PMAP_INLINE 174#endif 175 176#ifdef PV_STATS 177#define PV_STAT(x) do { x ; } while (0) 178#else 179#define PV_STAT(x) do { } while (0) 180#endif 181 182#define pa_index(pa) ((pa) >> PDRSHIFT) 183#define pa_to_pvh(pa) (&pv_table[pa_index(pa)]) 184 185/* 186 * Get PDEs and PTEs for user/kernel address space 187 */ 188#define pmap_pde(m, v) (&((m)->pm_pdir[(vm_offset_t)(v) >> PDRSHIFT])) 189#define pdir_pde(m, v) (m[(vm_offset_t)(v) >> PDRSHIFT]) 190 191#define pmap_pde_v(pte) ((*(int *)pte & PG_V) != 0) 192#define pmap_pte_w(pte) ((*(int *)pte & PG_W) != 0) 193#define pmap_pte_m(pte) ((*(int *)pte & PG_M) != 0) 194#define pmap_pte_u(pte) ((*(int *)pte & PG_A) != 0) 195#define pmap_pte_v(pte) ((*(int *)pte & PG_V) != 0) 196 197#define pmap_pte_set_w(pte, v) ((v) ? atomic_set_int((u_int *)(pte), PG_W) : \ 198 atomic_clear_int((u_int *)(pte), PG_W)) 199#define pmap_pte_set_prot(pte, v) ((*(int *)pte &= ~PG_PROT), (*(int *)pte |= (v))) 200 201struct pmap kernel_pmap_store; 202LIST_HEAD(pmaplist, pmap); 203static struct pmaplist allpmaps; 204static struct mtx allpmaps_lock; 205 206vm_offset_t virtual_avail; /* VA of first avail page (after kernel bss) */ 207vm_offset_t virtual_end; /* VA of last avail page (end of kernel AS) */ 208int pgeflag = 0; /* PG_G or-in */ 209int pseflag = 0; /* PG_PS or-in */ 210 211static int nkpt = NKPT; 212vm_offset_t kernel_vm_end = KERNBASE + NKPT * NBPDR; 213extern u_int32_t KERNend; 214extern u_int32_t KPTphys; 215 216#ifdef PAE 217pt_entry_t pg_nx; 218static uma_zone_t pdptzone; 219#endif 220 221static SYSCTL_NODE(_vm, OID_AUTO, pmap, CTLFLAG_RD, 0, "VM/pmap parameters"); 222 223static int pat_works = 1; 224SYSCTL_INT(_vm_pmap, OID_AUTO, pat_works, CTLFLAG_RD, &pat_works, 1, 225 "Is page attribute table fully functional?"); 226 227static int pg_ps_enabled = 1; 228SYSCTL_INT(_vm_pmap, OID_AUTO, pg_ps_enabled, CTLFLAG_RDTUN, &pg_ps_enabled, 0, 229 "Are large page mappings enabled?"); 230 231#define PAT_INDEX_SIZE 8 232static int pat_index[PAT_INDEX_SIZE]; /* cache mode to PAT index conversion */ 233 234static struct rwlock_padalign pvh_global_lock; 235 236/* 237 * Data for the pv entry allocation mechanism 238 */ 239static TAILQ_HEAD(pch, pv_chunk) pv_chunks = TAILQ_HEAD_INITIALIZER(pv_chunks); 240static int pv_entry_count = 0, pv_entry_max = 0, pv_entry_high_water = 0; 241static struct md_page *pv_table; 242static int shpgperproc = PMAP_SHPGPERPROC; 243 244struct pv_chunk *pv_chunkbase; /* KVA block for pv_chunks */ 245int pv_maxchunks; /* How many chunks we have KVA for */ 246vm_offset_t pv_vafree; /* freelist stored in the PTE */ 247 248/* 249 * All those kernel PT submaps that BSD is so fond of 250 */ 251struct sysmaps { 252 struct mtx lock; 253 pt_entry_t *CMAP1; 254 pt_entry_t *CMAP2; 255 caddr_t CADDR1; 256 caddr_t CADDR2; 257}; 258static struct sysmaps sysmaps_pcpu[MAXCPU]; 259pt_entry_t *CMAP3; 260static pd_entry_t *KPTD; 261caddr_t ptvmmap = 0; 262caddr_t CADDR3; 263struct msgbuf *msgbufp = 0; 264 265/* 266 * Crashdump maps. 267 */ 268static caddr_t crashdumpmap; 269 270static pt_entry_t *PMAP1 = 0, *PMAP2; 271static pt_entry_t *PADDR1 = 0, *PADDR2; 272#ifdef SMP 273static int PMAP1cpu; 274static int PMAP1changedcpu; 275SYSCTL_INT(_debug, OID_AUTO, PMAP1changedcpu, CTLFLAG_RD, 276 &PMAP1changedcpu, 0, 277 "Number of times pmap_pte_quick changed CPU with same PMAP1"); 278#endif 279static int PMAP1changed; 280SYSCTL_INT(_debug, OID_AUTO, PMAP1changed, CTLFLAG_RD, 281 &PMAP1changed, 0, 282 "Number of times pmap_pte_quick changed PMAP1"); 283static int PMAP1unchanged; 284SYSCTL_INT(_debug, OID_AUTO, PMAP1unchanged, CTLFLAG_RD, 285 &PMAP1unchanged, 0, 286 "Number of times pmap_pte_quick didn't change PMAP1"); 287static struct mtx PMAP2mutex; 288 289static void free_pv_chunk(struct pv_chunk *pc); 290static void free_pv_entry(pmap_t pmap, pv_entry_t pv); 291static pv_entry_t get_pv_entry(pmap_t pmap, boolean_t try); 292static void pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa); 293static boolean_t pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa); 294static void pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa); 295static void pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va); 296static pv_entry_t pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, 297 vm_offset_t va); 298static int pmap_pvh_wired_mappings(struct md_page *pvh, int count); 299 300static boolean_t pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va); 301static boolean_t pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, 302 vm_prot_t prot); 303static vm_page_t pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, 304 vm_page_t m, vm_prot_t prot, vm_page_t mpte); 305static void pmap_flush_page(vm_page_t m); 306static int pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte); 307static void pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte); 308static boolean_t pmap_is_modified_pvh(struct md_page *pvh); 309static boolean_t pmap_is_referenced_pvh(struct md_page *pvh); 310static void pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode); 311static void pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde); 312static vm_page_t pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va); 313static void pmap_pde_attr(pd_entry_t *pde, int cache_bits); 314static void pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va); 315static boolean_t pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, 316 vm_prot_t prot); 317static void pmap_pte_attr(pt_entry_t *pte, int cache_bits); 318static void pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva, 319 struct spglist *free); 320static int pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t sva, 321 struct spglist *free); 322static void pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte); 323static void pmap_remove_page(struct pmap *pmap, vm_offset_t va, 324 struct spglist *free); 325static void pmap_remove_entry(struct pmap *pmap, vm_page_t m, 326 vm_offset_t va); 327static void pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m); 328static boolean_t pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, 329 vm_page_t m); 330static void pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, 331 pd_entry_t newpde); 332static void pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde); 333 334static vm_page_t pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags); 335 336static vm_page_t _pmap_allocpte(pmap_t pmap, u_int ptepindex, int flags); 337static void _pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free); 338static pt_entry_t *pmap_pte_quick(pmap_t pmap, vm_offset_t va); 339static void pmap_pte_release(pt_entry_t *pte); 340static int pmap_unuse_pt(pmap_t, vm_offset_t, struct spglist *); 341#ifdef PAE 342static void *pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait); 343#endif 344static void pmap_set_pg(void); 345 346static __inline void pagezero(void *page); 347 348CTASSERT(1 << PDESHIFT == sizeof(pd_entry_t)); 349CTASSERT(1 << PTESHIFT == sizeof(pt_entry_t)); 350 351/* 352 * If you get an error here, then you set KVA_PAGES wrong! See the 353 * description of KVA_PAGES in sys/i386/include/pmap.h. It must be 354 * multiple of 4 for a normal kernel, or a multiple of 8 for a PAE. 355 */ 356CTASSERT(KERNBASE % (1 << 24) == 0); 357 358/* 359 * Bootstrap the system enough to run with virtual memory. 360 * 361 * On the i386 this is called after mapping has already been enabled 362 * and just syncs the pmap module with what has already been done. 363 * [We can't call it easily with mapping off since the kernel is not 364 * mapped with PA == VA, hence we would have to relocate every address 365 * from the linked base (virtual) address "KERNBASE" to the actual 366 * (physical) address starting relative to 0] 367 */ 368void 369pmap_bootstrap(vm_paddr_t firstaddr) 370{ 371 vm_offset_t va; 372 pt_entry_t *pte, *unused; 373 struct sysmaps *sysmaps; 374 int i; 375 376 /* 377 * Initialize the first available kernel virtual address. However, 378 * using "firstaddr" may waste a few pages of the kernel virtual 379 * address space, because locore may not have mapped every physical 380 * page that it allocated. Preferably, locore would provide a first 381 * unused virtual address in addition to "firstaddr". 382 */ 383 virtual_avail = (vm_offset_t) KERNBASE + firstaddr; 384 385 virtual_end = VM_MAX_KERNEL_ADDRESS; 386 387 /* 388 * Initialize the kernel pmap (which is statically allocated). 389 */ 390 PMAP_LOCK_INIT(kernel_pmap); 391 kernel_pmap->pm_pdir = (pd_entry_t *) (KERNBASE + (u_int)IdlePTD); 392#ifdef PAE 393 kernel_pmap->pm_pdpt = (pdpt_entry_t *) (KERNBASE + (u_int)IdlePDPT); 394#endif 395 CPU_FILL(&kernel_pmap->pm_active); /* don't allow deactivation */ 396 TAILQ_INIT(&kernel_pmap->pm_pvchunk); 397 398 /* 399 * Initialize the global pv list lock. 400 */ 401 rw_init(&pvh_global_lock, "pmap pv global"); 402 403 LIST_INIT(&allpmaps); 404 405 /* 406 * Request a spin mutex so that changes to allpmaps cannot be 407 * preempted by smp_rendezvous_cpus(). Otherwise, 408 * pmap_update_pde_kernel() could access allpmaps while it is 409 * being changed. 410 */ 411 mtx_init(&allpmaps_lock, "allpmaps", NULL, MTX_SPIN); 412 mtx_lock_spin(&allpmaps_lock); 413 LIST_INSERT_HEAD(&allpmaps, kernel_pmap, pm_list); 414 mtx_unlock_spin(&allpmaps_lock); 415 416 /* 417 * Reserve some special page table entries/VA space for temporary 418 * mapping of pages. 419 */ 420#define SYSMAP(c, p, v, n) \ 421 v = (c)va; va += ((n)*PAGE_SIZE); p = pte; pte += (n); 422 423 va = virtual_avail; 424 pte = vtopte(va); 425 426 /* 427 * CMAP1/CMAP2 are used for zeroing and copying pages. 428 * CMAP3 is used for the idle process page zeroing. 429 */ 430 for (i = 0; i < MAXCPU; i++) { 431 sysmaps = &sysmaps_pcpu[i]; 432 mtx_init(&sysmaps->lock, "SYSMAPS", NULL, MTX_DEF); 433 SYSMAP(caddr_t, sysmaps->CMAP1, sysmaps->CADDR1, 1) 434 SYSMAP(caddr_t, sysmaps->CMAP2, sysmaps->CADDR2, 1) 435 } 436 SYSMAP(caddr_t, CMAP3, CADDR3, 1) 437 438 /* 439 * Crashdump maps. 440 */ 441 SYSMAP(caddr_t, unused, crashdumpmap, MAXDUMPPGS) 442 443 /* 444 * ptvmmap is used for reading arbitrary physical pages via /dev/mem. 445 */ 446 SYSMAP(caddr_t, unused, ptvmmap, 1) 447 448 /* 449 * msgbufp is used to map the system message buffer. 450 */ 451 SYSMAP(struct msgbuf *, unused, msgbufp, atop(round_page(msgbufsize))) 452 453 /* 454 * KPTmap is used by pmap_kextract(). 455 * 456 * KPTmap is first initialized by locore. However, that initial 457 * KPTmap can only support NKPT page table pages. Here, a larger 458 * KPTmap is created that can support KVA_PAGES page table pages. 459 */ 460 SYSMAP(pt_entry_t *, KPTD, KPTmap, KVA_PAGES) 461 462 for (i = 0; i < NKPT; i++) 463 KPTD[i] = (KPTphys + (i << PAGE_SHIFT)) | pgeflag | PG_RW | PG_V; 464 465 /* 466 * Adjust the start of the KPTD and KPTmap so that the implementation 467 * of pmap_kextract() and pmap_growkernel() can be made simpler. 468 */ 469 KPTD -= KPTDI; 470 KPTmap -= i386_btop(KPTDI << PDRSHIFT); 471 472 /* 473 * PADDR1 and PADDR2 are used by pmap_pte_quick() and pmap_pte(), 474 * respectively. 475 */ 476 SYSMAP(pt_entry_t *, PMAP1, PADDR1, 1) 477 SYSMAP(pt_entry_t *, PMAP2, PADDR2, 1) 478 479 mtx_init(&PMAP2mutex, "PMAP2", NULL, MTX_DEF); 480 481 virtual_avail = va; 482 483 /* 484 * Leave in place an identity mapping (virt == phys) for the low 1 MB 485 * physical memory region that is used by the ACPI wakeup code. This 486 * mapping must not have PG_G set. 487 */ 488#ifdef XBOX 489 /* FIXME: This is gross, but needed for the XBOX. Since we are in such 490 * an early stadium, we cannot yet neatly map video memory ... :-( 491 * Better fixes are very welcome! */ 492 if (!arch_i386_is_xbox) 493#endif 494 for (i = 1; i < NKPT; i++) 495 PTD[i] = 0; 496 497 /* Initialize the PAT MSR if present. */ 498 pmap_init_pat(); 499 500 /* Turn on PG_G on kernel page(s) */ 501 pmap_set_pg(); 502} 503 504/* 505 * Setup the PAT MSR. 506 */ 507void 508pmap_init_pat(void) 509{ 510 int pat_table[PAT_INDEX_SIZE]; 511 uint64_t pat_msr; 512 u_long cr0, cr4; 513 int i; 514 515 /* Set default PAT index table. */ 516 for (i = 0; i < PAT_INDEX_SIZE; i++) 517 pat_table[i] = -1; 518 pat_table[PAT_WRITE_BACK] = 0; 519 pat_table[PAT_WRITE_THROUGH] = 1; 520 pat_table[PAT_UNCACHEABLE] = 3; 521 pat_table[PAT_WRITE_COMBINING] = 3; 522 pat_table[PAT_WRITE_PROTECTED] = 3; 523 pat_table[PAT_UNCACHED] = 3; 524 525 /* Bail if this CPU doesn't implement PAT. */ 526 if ((cpu_feature & CPUID_PAT) == 0) { 527 for (i = 0; i < PAT_INDEX_SIZE; i++) 528 pat_index[i] = pat_table[i]; 529 pat_works = 0; 530 return; 531 } 532 533 /* 534 * Due to some Intel errata, we can only safely use the lower 4 535 * PAT entries. 536 * 537 * Intel Pentium III Processor Specification Update 538 * Errata E.27 (Upper Four PAT Entries Not Usable With Mode B 539 * or Mode C Paging) 540 * 541 * Intel Pentium IV Processor Specification Update 542 * Errata N46 (PAT Index MSB May Be Calculated Incorrectly) 543 */ 544 if (cpu_vendor_id == CPU_VENDOR_INTEL && 545 !(CPUID_TO_FAMILY(cpu_id) == 6 && CPUID_TO_MODEL(cpu_id) >= 0xe)) 546 pat_works = 0; 547 548 /* Initialize default PAT entries. */ 549 pat_msr = PAT_VALUE(0, PAT_WRITE_BACK) | 550 PAT_VALUE(1, PAT_WRITE_THROUGH) | 551 PAT_VALUE(2, PAT_UNCACHED) | 552 PAT_VALUE(3, PAT_UNCACHEABLE) | 553 PAT_VALUE(4, PAT_WRITE_BACK) | 554 PAT_VALUE(5, PAT_WRITE_THROUGH) | 555 PAT_VALUE(6, PAT_UNCACHED) | 556 PAT_VALUE(7, PAT_UNCACHEABLE); 557 558 if (pat_works) { 559 /* 560 * Leave the indices 0-3 at the default of WB, WT, UC-, and UC. 561 * Program 5 and 6 as WP and WC. 562 * Leave 4 and 7 as WB and UC. 563 */ 564 pat_msr &= ~(PAT_MASK(5) | PAT_MASK(6)); 565 pat_msr |= PAT_VALUE(5, PAT_WRITE_PROTECTED) | 566 PAT_VALUE(6, PAT_WRITE_COMBINING); 567 pat_table[PAT_UNCACHED] = 2; 568 pat_table[PAT_WRITE_PROTECTED] = 5; 569 pat_table[PAT_WRITE_COMBINING] = 6; 570 } else { 571 /* 572 * Just replace PAT Index 2 with WC instead of UC-. 573 */ 574 pat_msr &= ~PAT_MASK(2); 575 pat_msr |= PAT_VALUE(2, PAT_WRITE_COMBINING); 576 pat_table[PAT_WRITE_COMBINING] = 2; 577 } 578 579 /* Disable PGE. */ 580 cr4 = rcr4(); 581 load_cr4(cr4 & ~CR4_PGE); 582 583 /* Disable caches (CD = 1, NW = 0). */ 584 cr0 = rcr0(); 585 load_cr0((cr0 & ~CR0_NW) | CR0_CD); 586 587 /* Flushes caches and TLBs. */ 588 wbinvd(); 589 invltlb(); 590 591 /* Update PAT and index table. */ 592 wrmsr(MSR_PAT, pat_msr); 593 for (i = 0; i < PAT_INDEX_SIZE; i++) 594 pat_index[i] = pat_table[i]; 595 596 /* Flush caches and TLBs again. */ 597 wbinvd(); 598 invltlb(); 599 600 /* Restore caches and PGE. */ 601 load_cr0(cr0); 602 load_cr4(cr4); 603} 604 605/* 606 * Set PG_G on kernel pages. Only the BSP calls this when SMP is turned on. 607 */ 608static void 609pmap_set_pg(void) 610{ 611 pt_entry_t *pte; 612 vm_offset_t va, endva; 613 614 if (pgeflag == 0) 615 return; 616 617 endva = KERNBASE + KERNend; 618 619 if (pseflag) { 620 va = KERNBASE + KERNLOAD; 621 while (va < endva) { 622 pdir_pde(PTD, va) |= pgeflag; 623 invltlb(); /* Play it safe, invltlb() every time */ 624 va += NBPDR; 625 } 626 } else { 627 va = (vm_offset_t)btext; 628 while (va < endva) { 629 pte = vtopte(va); 630 if (*pte) 631 *pte |= pgeflag; 632 invltlb(); /* Play it safe, invltlb() every time */ 633 va += PAGE_SIZE; 634 } 635 } 636} 637 638/* 639 * Initialize a vm_page's machine-dependent fields. 640 */ 641void 642pmap_page_init(vm_page_t m) 643{ 644 645 TAILQ_INIT(&m->md.pv_list); 646 m->md.pat_mode = PAT_WRITE_BACK; 647} 648 649#ifdef PAE 650static void * 651pmap_pdpt_allocf(uma_zone_t zone, int bytes, u_int8_t *flags, int wait) 652{ 653 654 /* Inform UMA that this allocator uses kernel_map/object. */ 655 *flags = UMA_SLAB_KERNEL; 656 return ((void *)kmem_alloc_contig(kernel_arena, bytes, wait, 0x0ULL, 657 0xffffffffULL, 1, 0, VM_MEMATTR_DEFAULT)); 658} 659#endif 660 661/* 662 * ABuse the pte nodes for unmapped kva to thread a kva freelist through. 663 * Requirements: 664 * - Must deal with pages in order to ensure that none of the PG_* bits 665 * are ever set, PG_V in particular. 666 * - Assumes we can write to ptes without pte_store() atomic ops, even 667 * on PAE systems. This should be ok. 668 * - Assumes nothing will ever test these addresses for 0 to indicate 669 * no mapping instead of correctly checking PG_V. 670 * - Assumes a vm_offset_t will fit in a pte (true for i386). 671 * Because PG_V is never set, there can be no mappings to invalidate. 672 */ 673static vm_offset_t 674pmap_ptelist_alloc(vm_offset_t *head) 675{ 676 pt_entry_t *pte; 677 vm_offset_t va; 678 679 va = *head; 680 if (va == 0) 681 panic("pmap_ptelist_alloc: exhausted ptelist KVA"); 682 pte = vtopte(va); 683 *head = *pte; 684 if (*head & PG_V) 685 panic("pmap_ptelist_alloc: va with PG_V set!"); 686 *pte = 0; 687 return (va); 688} 689 690static void 691pmap_ptelist_free(vm_offset_t *head, vm_offset_t va) 692{ 693 pt_entry_t *pte; 694 695 if (va & PG_V) 696 panic("pmap_ptelist_free: freeing va with PG_V set!"); 697 pte = vtopte(va); 698 *pte = *head; /* virtual! PG_V is 0 though */ 699 *head = va; 700} 701 702static void 703pmap_ptelist_init(vm_offset_t *head, void *base, int npages) 704{ 705 int i; 706 vm_offset_t va; 707 708 *head = 0; 709 for (i = npages - 1; i >= 0; i--) { 710 va = (vm_offset_t)base + i * PAGE_SIZE; 711 pmap_ptelist_free(head, va); 712 } 713} 714 715 716/* 717 * Initialize the pmap module. 718 * Called by vm_init, to initialize any structures that the pmap 719 * system needs to map virtual memory. 720 */ 721void 722pmap_init(void) 723{ 724 vm_page_t mpte; 725 vm_size_t s; 726 int i, pv_npg; 727 728 /* 729 * Initialize the vm page array entries for the kernel pmap's 730 * page table pages. 731 */ 732 for (i = 0; i < NKPT; i++) { 733 mpte = PHYS_TO_VM_PAGE(KPTphys + (i << PAGE_SHIFT)); 734 KASSERT(mpte >= vm_page_array && 735 mpte < &vm_page_array[vm_page_array_size], 736 ("pmap_init: page table page is out of range")); 737 mpte->pindex = i + KPTDI; 738 mpte->phys_addr = KPTphys + (i << PAGE_SHIFT); 739 } 740 741 /* 742 * Initialize the address space (zone) for the pv entries. Set a 743 * high water mark so that the system can recover from excessive 744 * numbers of pv entries. 745 */ 746 TUNABLE_INT_FETCH("vm.pmap.shpgperproc", &shpgperproc); 747 pv_entry_max = shpgperproc * maxproc + cnt.v_page_count; 748 TUNABLE_INT_FETCH("vm.pmap.pv_entries", &pv_entry_max); 749 pv_entry_max = roundup(pv_entry_max, _NPCPV); 750 pv_entry_high_water = 9 * (pv_entry_max / 10); 751 752 /* 753 * If the kernel is running on a virtual machine, then it must assume 754 * that MCA is enabled by the hypervisor. Moreover, the kernel must 755 * be prepared for the hypervisor changing the vendor and family that 756 * are reported by CPUID. Consequently, the workaround for AMD Family 757 * 10h Erratum 383 is enabled if the processor's feature set does not 758 * include at least one feature that is only supported by older Intel 759 * or newer AMD processors. 760 */ 761 if (vm_guest == VM_GUEST_VM && (cpu_feature & CPUID_SS) == 0 && 762 (cpu_feature2 & (CPUID2_SSSE3 | CPUID2_SSE41 | CPUID2_AESNI | 763 CPUID2_AVX | CPUID2_XSAVE)) == 0 && (amd_feature2 & (AMDID2_XOP | 764 AMDID2_FMA4)) == 0) 765 workaround_erratum383 = 1; 766 767 /* 768 * Are large page mappings supported and enabled? 769 */ 770 TUNABLE_INT_FETCH("vm.pmap.pg_ps_enabled", &pg_ps_enabled); 771 if (pseflag == 0) 772 pg_ps_enabled = 0; 773 else if (pg_ps_enabled) { 774 KASSERT(MAXPAGESIZES > 1 && pagesizes[1] == 0, 775 ("pmap_init: can't assign to pagesizes[1]")); 776 pagesizes[1] = NBPDR; 777 } 778 779 /* 780 * Calculate the size of the pv head table for superpages. 781 */ 782 for (i = 0; phys_avail[i + 1]; i += 2); 783 pv_npg = round_4mpage(phys_avail[(i - 2) + 1]) / NBPDR; 784 785 /* 786 * Allocate memory for the pv head table for superpages. 787 */ 788 s = (vm_size_t)(pv_npg * sizeof(struct md_page)); 789 s = round_page(s); 790 pv_table = (struct md_page *)kmem_malloc(kernel_arena, s, 791 M_WAITOK | M_ZERO); 792 for (i = 0; i < pv_npg; i++) 793 TAILQ_INIT(&pv_table[i].pv_list); 794 795 pv_maxchunks = MAX(pv_entry_max / _NPCPV, maxproc); 796 pv_chunkbase = (struct pv_chunk *)kva_alloc(PAGE_SIZE * pv_maxchunks); 797 if (pv_chunkbase == NULL) 798 panic("pmap_init: not enough kvm for pv chunks"); 799 pmap_ptelist_init(&pv_vafree, pv_chunkbase, pv_maxchunks); 800#ifdef PAE 801 pdptzone = uma_zcreate("PDPT", NPGPTD * sizeof(pdpt_entry_t), NULL, 802 NULL, NULL, NULL, (NPGPTD * sizeof(pdpt_entry_t)) - 1, 803 UMA_ZONE_VM | UMA_ZONE_NOFREE); 804 uma_zone_set_allocf(pdptzone, pmap_pdpt_allocf); 805#endif 806} 807 808 809SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_max, CTLFLAG_RD, &pv_entry_max, 0, 810 "Max number of PV entries"); 811SYSCTL_INT(_vm_pmap, OID_AUTO, shpgperproc, CTLFLAG_RD, &shpgperproc, 0, 812 "Page share factor per proc"); 813 814static SYSCTL_NODE(_vm_pmap, OID_AUTO, pde, CTLFLAG_RD, 0, 815 "2/4MB page mapping counters"); 816 817static u_long pmap_pde_demotions; 818SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, demotions, CTLFLAG_RD, 819 &pmap_pde_demotions, 0, "2/4MB page demotions"); 820 821static u_long pmap_pde_mappings; 822SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, mappings, CTLFLAG_RD, 823 &pmap_pde_mappings, 0, "2/4MB page mappings"); 824 825static u_long pmap_pde_p_failures; 826SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, p_failures, CTLFLAG_RD, 827 &pmap_pde_p_failures, 0, "2/4MB page promotion failures"); 828 829static u_long pmap_pde_promotions; 830SYSCTL_ULONG(_vm_pmap_pde, OID_AUTO, promotions, CTLFLAG_RD, 831 &pmap_pde_promotions, 0, "2/4MB page promotions"); 832 833/*************************************************** 834 * Low level helper routines..... 835 ***************************************************/ 836 837/* 838 * Determine the appropriate bits to set in a PTE or PDE for a specified 839 * caching mode. 840 */ 841int 842pmap_cache_bits(int mode, boolean_t is_pde) 843{ 844 int cache_bits, pat_flag, pat_idx; 845 846 if (mode < 0 || mode >= PAT_INDEX_SIZE || pat_index[mode] < 0) 847 panic("Unknown caching mode %d\n", mode); 848 849 /* The PAT bit is different for PTE's and PDE's. */ 850 pat_flag = is_pde ? PG_PDE_PAT : PG_PTE_PAT; 851 852 /* Map the caching mode to a PAT index. */ 853 pat_idx = pat_index[mode]; 854 855 /* Map the 3-bit index value into the PAT, PCD, and PWT bits. */ 856 cache_bits = 0; 857 if (pat_idx & 0x4) 858 cache_bits |= pat_flag; 859 if (pat_idx & 0x2) 860 cache_bits |= PG_NC_PCD; 861 if (pat_idx & 0x1) 862 cache_bits |= PG_NC_PWT; 863 return (cache_bits); 864} 865 866/* 867 * The caller is responsible for maintaining TLB consistency. 868 */ 869static void 870pmap_kenter_pde(vm_offset_t va, pd_entry_t newpde) 871{ 872 pd_entry_t *pde; 873 pmap_t pmap; 874 boolean_t PTD_updated; 875 876 PTD_updated = FALSE; 877 mtx_lock_spin(&allpmaps_lock); 878 LIST_FOREACH(pmap, &allpmaps, pm_list) { 879 if ((pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & 880 PG_FRAME)) 881 PTD_updated = TRUE; 882 pde = pmap_pde(pmap, va); 883 pde_store(pde, newpde); 884 } 885 mtx_unlock_spin(&allpmaps_lock); 886 KASSERT(PTD_updated, 887 ("pmap_kenter_pde: current page table is not in allpmaps")); 888} 889 890/* 891 * After changing the page size for the specified virtual address in the page 892 * table, flush the corresponding entries from the processor's TLB. Only the 893 * calling processor's TLB is affected. 894 * 895 * The calling thread must be pinned to a processor. 896 */ 897static void 898pmap_update_pde_invalidate(vm_offset_t va, pd_entry_t newpde) 899{ 900 u_long cr4; 901 902 if ((newpde & PG_PS) == 0) 903 /* Demotion: flush a specific 2MB page mapping. */ 904 invlpg(va); 905 else if ((newpde & PG_G) == 0) 906 /* 907 * Promotion: flush every 4KB page mapping from the TLB 908 * because there are too many to flush individually. 909 */ 910 invltlb(); 911 else { 912 /* 913 * Promotion: flush every 4KB page mapping from the TLB, 914 * including any global (PG_G) mappings. 915 */ 916 cr4 = rcr4(); 917 load_cr4(cr4 & ~CR4_PGE); 918 /* 919 * Although preemption at this point could be detrimental to 920 * performance, it would not lead to an error. PG_G is simply 921 * ignored if CR4.PGE is clear. Moreover, in case this block 922 * is re-entered, the load_cr4() either above or below will 923 * modify CR4.PGE flushing the TLB. 924 */ 925 load_cr4(cr4 | CR4_PGE); 926 } 927} 928#ifdef SMP 929/* 930 * For SMP, these functions have to use the IPI mechanism for coherence. 931 * 932 * N.B.: Before calling any of the following TLB invalidation functions, 933 * the calling processor must ensure that all stores updating a non- 934 * kernel page table are globally performed. Otherwise, another 935 * processor could cache an old, pre-update entry without being 936 * invalidated. This can happen one of two ways: (1) The pmap becomes 937 * active on another processor after its pm_active field is checked by 938 * one of the following functions but before a store updating the page 939 * table is globally performed. (2) The pmap becomes active on another 940 * processor before its pm_active field is checked but due to 941 * speculative loads one of the following functions stills reads the 942 * pmap as inactive on the other processor. 943 * 944 * The kernel page table is exempt because its pm_active field is 945 * immutable. The kernel page table is always active on every 946 * processor. 947 */ 948void 949pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 950{ 951 cpuset_t other_cpus; 952 u_int cpuid; 953 954 sched_pin(); 955 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 956 invlpg(va); 957 smp_invlpg(va); 958 } else { 959 cpuid = PCPU_GET(cpuid); 960 other_cpus = all_cpus; 961 CPU_CLR(cpuid, &other_cpus); 962 if (CPU_ISSET(cpuid, &pmap->pm_active)) 963 invlpg(va); 964 CPU_AND(&other_cpus, &pmap->pm_active); 965 if (!CPU_EMPTY(&other_cpus)) 966 smp_masked_invlpg(other_cpus, va); 967 } 968 sched_unpin(); 969} 970 971void 972pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 973{ 974 cpuset_t other_cpus; 975 vm_offset_t addr; 976 u_int cpuid; 977 978 sched_pin(); 979 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 980 for (addr = sva; addr < eva; addr += PAGE_SIZE) 981 invlpg(addr); 982 smp_invlpg_range(sva, eva); 983 } else { 984 cpuid = PCPU_GET(cpuid); 985 other_cpus = all_cpus; 986 CPU_CLR(cpuid, &other_cpus); 987 if (CPU_ISSET(cpuid, &pmap->pm_active)) 988 for (addr = sva; addr < eva; addr += PAGE_SIZE) 989 invlpg(addr); 990 CPU_AND(&other_cpus, &pmap->pm_active); 991 if (!CPU_EMPTY(&other_cpus)) 992 smp_masked_invlpg_range(other_cpus, sva, eva); 993 } 994 sched_unpin(); 995} 996 997void 998pmap_invalidate_all(pmap_t pmap) 999{ 1000 cpuset_t other_cpus; 1001 u_int cpuid; 1002 1003 sched_pin(); 1004 if (pmap == kernel_pmap || !CPU_CMP(&pmap->pm_active, &all_cpus)) { 1005 invltlb(); 1006 smp_invltlb(); 1007 } else { 1008 cpuid = PCPU_GET(cpuid); 1009 other_cpus = all_cpus; 1010 CPU_CLR(cpuid, &other_cpus); 1011 if (CPU_ISSET(cpuid, &pmap->pm_active)) 1012 invltlb(); 1013 CPU_AND(&other_cpus, &pmap->pm_active); 1014 if (!CPU_EMPTY(&other_cpus)) 1015 smp_masked_invltlb(other_cpus); 1016 } 1017 sched_unpin(); 1018} 1019 1020void 1021pmap_invalidate_cache(void) 1022{ 1023 1024 sched_pin(); 1025 wbinvd(); 1026 smp_cache_flush(); 1027 sched_unpin(); 1028} 1029 1030struct pde_action { 1031 cpuset_t invalidate; /* processors that invalidate their TLB */ 1032 vm_offset_t va; 1033 pd_entry_t *pde; 1034 pd_entry_t newpde; 1035 u_int store; /* processor that updates the PDE */ 1036}; 1037 1038static void 1039pmap_update_pde_kernel(void *arg) 1040{ 1041 struct pde_action *act = arg; 1042 pd_entry_t *pde; 1043 pmap_t pmap; 1044 1045 if (act->store == PCPU_GET(cpuid)) { 1046 1047 /* 1048 * Elsewhere, this operation requires allpmaps_lock for 1049 * synchronization. Here, it does not because it is being 1050 * performed in the context of an all_cpus rendezvous. 1051 */ 1052 LIST_FOREACH(pmap, &allpmaps, pm_list) { 1053 pde = pmap_pde(pmap, act->va); 1054 pde_store(pde, act->newpde); 1055 } 1056 } 1057} 1058 1059static void 1060pmap_update_pde_user(void *arg) 1061{ 1062 struct pde_action *act = arg; 1063 1064 if (act->store == PCPU_GET(cpuid)) 1065 pde_store(act->pde, act->newpde); 1066} 1067 1068static void 1069pmap_update_pde_teardown(void *arg) 1070{ 1071 struct pde_action *act = arg; 1072 1073 if (CPU_ISSET(PCPU_GET(cpuid), &act->invalidate)) 1074 pmap_update_pde_invalidate(act->va, act->newpde); 1075} 1076 1077/* 1078 * Change the page size for the specified virtual address in a way that 1079 * prevents any possibility of the TLB ever having two entries that map the 1080 * same virtual address using different page sizes. This is the recommended 1081 * workaround for Erratum 383 on AMD Family 10h processors. It prevents a 1082 * machine check exception for a TLB state that is improperly diagnosed as a 1083 * hardware error. 1084 */ 1085static void 1086pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde) 1087{ 1088 struct pde_action act; 1089 cpuset_t active, other_cpus; 1090 u_int cpuid; 1091 1092 sched_pin(); 1093 cpuid = PCPU_GET(cpuid); 1094 other_cpus = all_cpus; 1095 CPU_CLR(cpuid, &other_cpus); 1096 if (pmap == kernel_pmap) 1097 active = all_cpus; 1098 else 1099 active = pmap->pm_active; 1100 if (CPU_OVERLAP(&active, &other_cpus)) { 1101 act.store = cpuid; 1102 act.invalidate = active; 1103 act.va = va; 1104 act.pde = pde; 1105 act.newpde = newpde; 1106 CPU_SET(cpuid, &active); 1107 smp_rendezvous_cpus(active, 1108 smp_no_rendevous_barrier, pmap == kernel_pmap ? 1109 pmap_update_pde_kernel : pmap_update_pde_user, 1110 pmap_update_pde_teardown, &act); 1111 } else { 1112 if (pmap == kernel_pmap) 1113 pmap_kenter_pde(va, newpde); 1114 else 1115 pde_store(pde, newpde); 1116 if (CPU_ISSET(cpuid, &active)) 1117 pmap_update_pde_invalidate(va, newpde); 1118 } 1119 sched_unpin(); 1120} 1121#else /* !SMP */ 1122/* 1123 * Normal, non-SMP, 486+ invalidation functions. 1124 * We inline these within pmap.c for speed. 1125 */ 1126PMAP_INLINE void 1127pmap_invalidate_page(pmap_t pmap, vm_offset_t va) 1128{ 1129 1130 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 1131 invlpg(va); 1132} 1133 1134PMAP_INLINE void 1135pmap_invalidate_range(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 1136{ 1137 vm_offset_t addr; 1138 1139 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 1140 for (addr = sva; addr < eva; addr += PAGE_SIZE) 1141 invlpg(addr); 1142} 1143 1144PMAP_INLINE void 1145pmap_invalidate_all(pmap_t pmap) 1146{ 1147 1148 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 1149 invltlb(); 1150} 1151 1152PMAP_INLINE void 1153pmap_invalidate_cache(void) 1154{ 1155 1156 wbinvd(); 1157} 1158 1159static void 1160pmap_update_pde(pmap_t pmap, vm_offset_t va, pd_entry_t *pde, pd_entry_t newpde) 1161{ 1162 1163 if (pmap == kernel_pmap) 1164 pmap_kenter_pde(va, newpde); 1165 else 1166 pde_store(pde, newpde); 1167 if (pmap == kernel_pmap || !CPU_EMPTY(&pmap->pm_active)) 1168 pmap_update_pde_invalidate(va, newpde); 1169} 1170#endif /* !SMP */ 1171 1172#define PMAP_CLFLUSH_THRESHOLD (2 * 1024 * 1024) 1173 1174void 1175pmap_invalidate_cache_range(vm_offset_t sva, vm_offset_t eva) 1176{ 1177 1178 KASSERT((sva & PAGE_MASK) == 0, 1179 ("pmap_invalidate_cache_range: sva not page-aligned")); 1180 KASSERT((eva & PAGE_MASK) == 0, 1181 ("pmap_invalidate_cache_range: eva not page-aligned")); 1182 1183 if (cpu_feature & CPUID_SS) 1184 ; /* If "Self Snoop" is supported, do nothing. */ 1185 else if ((cpu_feature & CPUID_CLFSH) != 0 && 1186 eva - sva < PMAP_CLFLUSH_THRESHOLD) { 1187 1188#ifdef DEV_APIC 1189 /* 1190 * XXX: Some CPUs fault, hang, or trash the local APIC 1191 * registers if we use CLFLUSH on the local APIC 1192 * range. The local APIC is always uncached, so we 1193 * don't need to flush for that range anyway. 1194 */ 1195 if (pmap_kextract(sva) == lapic_paddr) 1196 return; 1197#endif 1198 /* 1199 * Otherwise, do per-cache line flush. Use the mfence 1200 * instruction to insure that previous stores are 1201 * included in the write-back. The processor 1202 * propagates flush to other processors in the cache 1203 * coherence domain. 1204 */ 1205 mfence(); 1206 for (; sva < eva; sva += cpu_clflush_line_size) 1207 clflush(sva); 1208 mfence(); 1209 } else { 1210 1211 /* 1212 * No targeted cache flush methods are supported by CPU, 1213 * or the supplied range is bigger than 2MB. 1214 * Globally invalidate cache. 1215 */ 1216 pmap_invalidate_cache(); 1217 } 1218} 1219 1220void 1221pmap_invalidate_cache_pages(vm_page_t *pages, int count) 1222{ 1223 int i; 1224 1225 if (count >= PMAP_CLFLUSH_THRESHOLD / PAGE_SIZE || 1226 (cpu_feature & CPUID_CLFSH) == 0) { 1227 pmap_invalidate_cache(); 1228 } else { 1229 for (i = 0; i < count; i++) 1230 pmap_flush_page(pages[i]); 1231 } 1232} 1233 1234/* 1235 * Are we current address space or kernel? N.B. We return FALSE when 1236 * a pmap's page table is in use because a kernel thread is borrowing 1237 * it. The borrowed page table can change spontaneously, making any 1238 * dependence on its continued use subject to a race condition. 1239 */ 1240static __inline int 1241pmap_is_current(pmap_t pmap) 1242{ 1243 1244 return (pmap == kernel_pmap || 1245 (pmap == vmspace_pmap(curthread->td_proc->p_vmspace) && 1246 (pmap->pm_pdir[PTDPTDI] & PG_FRAME) == (PTDpde[0] & PG_FRAME))); 1247} 1248 1249/* 1250 * If the given pmap is not the current or kernel pmap, the returned pte must 1251 * be released by passing it to pmap_pte_release(). 1252 */ 1253pt_entry_t * 1254pmap_pte(pmap_t pmap, vm_offset_t va) 1255{ 1256 pd_entry_t newpf; 1257 pd_entry_t *pde; 1258 1259 pde = pmap_pde(pmap, va); 1260 if (*pde & PG_PS) 1261 return (pde); 1262 if (*pde != 0) { 1263 /* are we current address space or kernel? */ 1264 if (pmap_is_current(pmap)) 1265 return (vtopte(va)); 1266 mtx_lock(&PMAP2mutex); 1267 newpf = *pde & PG_FRAME; 1268 if ((*PMAP2 & PG_FRAME) != newpf) { 1269 *PMAP2 = newpf | PG_RW | PG_V | PG_A | PG_M; 1270 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2); 1271 } 1272 return (PADDR2 + (i386_btop(va) & (NPTEPG - 1))); 1273 } 1274 return (NULL); 1275} 1276 1277/* 1278 * Releases a pte that was obtained from pmap_pte(). Be prepared for the pte 1279 * being NULL. 1280 */ 1281static __inline void 1282pmap_pte_release(pt_entry_t *pte) 1283{ 1284 1285 if ((pt_entry_t *)((vm_offset_t)pte & ~PAGE_MASK) == PADDR2) 1286 mtx_unlock(&PMAP2mutex); 1287} 1288 1289static __inline void 1290invlcaddr(void *caddr) 1291{ 1292 1293 invlpg((u_int)caddr); 1294} 1295 1296/* 1297 * Super fast pmap_pte routine best used when scanning 1298 * the pv lists. This eliminates many coarse-grained 1299 * invltlb calls. Note that many of the pv list 1300 * scans are across different pmaps. It is very wasteful 1301 * to do an entire invltlb for checking a single mapping. 1302 * 1303 * If the given pmap is not the current pmap, pvh_global_lock 1304 * must be held and curthread pinned to a CPU. 1305 */ 1306static pt_entry_t * 1307pmap_pte_quick(pmap_t pmap, vm_offset_t va) 1308{ 1309 pd_entry_t newpf; 1310 pd_entry_t *pde; 1311 1312 pde = pmap_pde(pmap, va); 1313 if (*pde & PG_PS) 1314 return (pde); 1315 if (*pde != 0) { 1316 /* are we current address space or kernel? */ 1317 if (pmap_is_current(pmap)) 1318 return (vtopte(va)); 1319 rw_assert(&pvh_global_lock, RA_WLOCKED); 1320 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 1321 newpf = *pde & PG_FRAME; 1322 if ((*PMAP1 & PG_FRAME) != newpf) { 1323 *PMAP1 = newpf | PG_RW | PG_V | PG_A | PG_M; 1324#ifdef SMP 1325 PMAP1cpu = PCPU_GET(cpuid); 1326#endif 1327 invlcaddr(PADDR1); 1328 PMAP1changed++; 1329 } else 1330#ifdef SMP 1331 if (PMAP1cpu != PCPU_GET(cpuid)) { 1332 PMAP1cpu = PCPU_GET(cpuid); 1333 invlcaddr(PADDR1); 1334 PMAP1changedcpu++; 1335 } else 1336#endif 1337 PMAP1unchanged++; 1338 return (PADDR1 + (i386_btop(va) & (NPTEPG - 1))); 1339 } 1340 return (0); 1341} 1342 1343/* 1344 * Routine: pmap_extract 1345 * Function: 1346 * Extract the physical page address associated 1347 * with the given map/virtual_address pair. 1348 */ 1349vm_paddr_t 1350pmap_extract(pmap_t pmap, vm_offset_t va) 1351{ 1352 vm_paddr_t rtval; 1353 pt_entry_t *pte; 1354 pd_entry_t pde; 1355 1356 rtval = 0; 1357 PMAP_LOCK(pmap); 1358 pde = pmap->pm_pdir[va >> PDRSHIFT]; 1359 if (pde != 0) { 1360 if ((pde & PG_PS) != 0) 1361 rtval = (pde & PG_PS_FRAME) | (va & PDRMASK); 1362 else { 1363 pte = pmap_pte(pmap, va); 1364 rtval = (*pte & PG_FRAME) | (va & PAGE_MASK); 1365 pmap_pte_release(pte); 1366 } 1367 } 1368 PMAP_UNLOCK(pmap); 1369 return (rtval); 1370} 1371 1372/* 1373 * Routine: pmap_extract_and_hold 1374 * Function: 1375 * Atomically extract and hold the physical page 1376 * with the given pmap and virtual address pair 1377 * if that mapping permits the given protection. 1378 */ 1379vm_page_t 1380pmap_extract_and_hold(pmap_t pmap, vm_offset_t va, vm_prot_t prot) 1381{ 1382 pd_entry_t pde; 1383 pt_entry_t pte, *ptep; 1384 vm_page_t m; 1385 vm_paddr_t pa; 1386 1387 pa = 0; 1388 m = NULL; 1389 PMAP_LOCK(pmap); 1390retry: 1391 pde = *pmap_pde(pmap, va); 1392 if (pde != 0) { 1393 if (pde & PG_PS) { 1394 if ((pde & PG_RW) || (prot & VM_PROT_WRITE) == 0) { 1395 if (vm_page_pa_tryrelock(pmap, (pde & 1396 PG_PS_FRAME) | (va & PDRMASK), &pa)) 1397 goto retry; 1398 m = PHYS_TO_VM_PAGE((pde & PG_PS_FRAME) | 1399 (va & PDRMASK)); 1400 vm_page_hold(m); 1401 } 1402 } else { 1403 ptep = pmap_pte(pmap, va); 1404 pte = *ptep; 1405 pmap_pte_release(ptep); 1406 if (pte != 0 && 1407 ((pte & PG_RW) || (prot & VM_PROT_WRITE) == 0)) { 1408 if (vm_page_pa_tryrelock(pmap, pte & PG_FRAME, 1409 &pa)) 1410 goto retry; 1411 m = PHYS_TO_VM_PAGE(pte & PG_FRAME); 1412 vm_page_hold(m); 1413 } 1414 } 1415 } 1416 PA_UNLOCK_COND(pa); 1417 PMAP_UNLOCK(pmap); 1418 return (m); 1419} 1420 1421/*************************************************** 1422 * Low level mapping routines..... 1423 ***************************************************/ 1424 1425/* 1426 * Add a wired page to the kva. 1427 * Note: not SMP coherent. 1428 * 1429 * This function may be used before pmap_bootstrap() is called. 1430 */ 1431PMAP_INLINE void 1432pmap_kenter(vm_offset_t va, vm_paddr_t pa) 1433{ 1434 pt_entry_t *pte; 1435 1436 pte = vtopte(va); 1437 pte_store(pte, pa | PG_RW | PG_V | pgeflag); 1438} 1439 1440static __inline void 1441pmap_kenter_attr(vm_offset_t va, vm_paddr_t pa, int mode) 1442{ 1443 pt_entry_t *pte; 1444 1445 pte = vtopte(va); 1446 pte_store(pte, pa | PG_RW | PG_V | pgeflag | pmap_cache_bits(mode, 0)); 1447} 1448 1449/* 1450 * Remove a page from the kernel pagetables. 1451 * Note: not SMP coherent. 1452 * 1453 * This function may be used before pmap_bootstrap() is called. 1454 */ 1455PMAP_INLINE void 1456pmap_kremove(vm_offset_t va) 1457{ 1458 pt_entry_t *pte; 1459 1460 pte = vtopte(va); 1461 pte_clear(pte); 1462} 1463 1464/* 1465 * Used to map a range of physical addresses into kernel 1466 * virtual address space. 1467 * 1468 * The value passed in '*virt' is a suggested virtual address for 1469 * the mapping. Architectures which can support a direct-mapped 1470 * physical to virtual region can return the appropriate address 1471 * within that region, leaving '*virt' unchanged. Other 1472 * architectures should map the pages starting at '*virt' and 1473 * update '*virt' with the first usable address after the mapped 1474 * region. 1475 */ 1476vm_offset_t 1477pmap_map(vm_offset_t *virt, vm_paddr_t start, vm_paddr_t end, int prot) 1478{ 1479 vm_offset_t va, sva; 1480 vm_paddr_t superpage_offset; 1481 pd_entry_t newpde; 1482 1483 va = *virt; 1484 /* 1485 * Does the physical address range's size and alignment permit at 1486 * least one superpage mapping to be created? 1487 */ 1488 superpage_offset = start & PDRMASK; 1489 if ((end - start) - ((NBPDR - superpage_offset) & PDRMASK) >= NBPDR) { 1490 /* 1491 * Increase the starting virtual address so that its alignment 1492 * does not preclude the use of superpage mappings. 1493 */ 1494 if ((va & PDRMASK) < superpage_offset) 1495 va = (va & ~PDRMASK) + superpage_offset; 1496 else if ((va & PDRMASK) > superpage_offset) 1497 va = ((va + PDRMASK) & ~PDRMASK) + superpage_offset; 1498 } 1499 sva = va; 1500 while (start < end) { 1501 if ((start & PDRMASK) == 0 && end - start >= NBPDR && 1502 pseflag) { 1503 KASSERT((va & PDRMASK) == 0, 1504 ("pmap_map: misaligned va %#x", va)); 1505 newpde = start | PG_PS | pgeflag | PG_RW | PG_V; 1506 pmap_kenter_pde(va, newpde); 1507 va += NBPDR; 1508 start += NBPDR; 1509 } else { 1510 pmap_kenter(va, start); 1511 va += PAGE_SIZE; 1512 start += PAGE_SIZE; 1513 } 1514 } 1515 pmap_invalidate_range(kernel_pmap, sva, va); 1516 *virt = va; 1517 return (sva); 1518} 1519 1520 1521/* 1522 * Add a list of wired pages to the kva 1523 * this routine is only used for temporary 1524 * kernel mappings that do not need to have 1525 * page modification or references recorded. 1526 * Note that old mappings are simply written 1527 * over. The page *must* be wired. 1528 * Note: SMP coherent. Uses a ranged shootdown IPI. 1529 */ 1530void 1531pmap_qenter(vm_offset_t sva, vm_page_t *ma, int count) 1532{ 1533 pt_entry_t *endpte, oldpte, pa, *pte; 1534 vm_page_t m; 1535 1536 oldpte = 0; 1537 pte = vtopte(sva); 1538 endpte = pte + count; 1539 while (pte < endpte) { 1540 m = *ma++; 1541 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0); 1542 if ((*pte & (PG_FRAME | PG_PTE_CACHE)) != pa) { 1543 oldpte |= *pte; 1544 pte_store(pte, pa | pgeflag | PG_RW | PG_V); 1545 } 1546 pte++; 1547 } 1548 if (__predict_false((oldpte & PG_V) != 0)) 1549 pmap_invalidate_range(kernel_pmap, sva, sva + count * 1550 PAGE_SIZE); 1551} 1552 1553/* 1554 * This routine tears out page mappings from the 1555 * kernel -- it is meant only for temporary mappings. 1556 * Note: SMP coherent. Uses a ranged shootdown IPI. 1557 */ 1558void 1559pmap_qremove(vm_offset_t sva, int count) 1560{ 1561 vm_offset_t va; 1562 1563 va = sva; 1564 while (count-- > 0) { 1565 pmap_kremove(va); 1566 va += PAGE_SIZE; 1567 } 1568 pmap_invalidate_range(kernel_pmap, sva, va); 1569} 1570 1571/*************************************************** 1572 * Page table page management routines..... 1573 ***************************************************/ 1574static __inline void 1575pmap_free_zero_pages(struct spglist *free) 1576{ 1577 vm_page_t m; 1578 1579 while ((m = SLIST_FIRST(free)) != NULL) { 1580 SLIST_REMOVE_HEAD(free, plinks.s.ss); 1581 /* Preserve the page's PG_ZERO setting. */ 1582 vm_page_free_toq(m); 1583 } 1584} 1585 1586/* 1587 * Schedule the specified unused page table page to be freed. Specifically, 1588 * add the page to the specified list of pages that will be released to the 1589 * physical memory manager after the TLB has been updated. 1590 */ 1591static __inline void 1592pmap_add_delayed_free_list(vm_page_t m, struct spglist *free, 1593 boolean_t set_PG_ZERO) 1594{ 1595 1596 if (set_PG_ZERO) 1597 m->flags |= PG_ZERO; 1598 else 1599 m->flags &= ~PG_ZERO; 1600 SLIST_INSERT_HEAD(free, m, plinks.s.ss); 1601} 1602 1603/* 1604 * Inserts the specified page table page into the specified pmap's collection 1605 * of idle page table pages. Each of a pmap's page table pages is responsible 1606 * for mapping a distinct range of virtual addresses. The pmap's collection is 1607 * ordered by this virtual address range. 1608 */ 1609static __inline int 1610pmap_insert_pt_page(pmap_t pmap, vm_page_t mpte) 1611{ 1612 1613 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1614 return (vm_radix_insert(&pmap->pm_root, mpte)); 1615} 1616 1617/* 1618 * Looks for a page table page mapping the specified virtual address in the 1619 * specified pmap's collection of idle page table pages. Returns NULL if there 1620 * is no page table page corresponding to the specified virtual address. 1621 */ 1622static __inline vm_page_t 1623pmap_lookup_pt_page(pmap_t pmap, vm_offset_t va) 1624{ 1625 1626 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1627 return (vm_radix_lookup(&pmap->pm_root, va >> PDRSHIFT)); 1628} 1629 1630/* 1631 * Removes the specified page table page from the specified pmap's collection 1632 * of idle page table pages. The specified page table page must be a member of 1633 * the pmap's collection. 1634 */ 1635static __inline void 1636pmap_remove_pt_page(pmap_t pmap, vm_page_t mpte) 1637{ 1638 1639 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 1640 vm_radix_remove(&pmap->pm_root, mpte->pindex); 1641} 1642 1643/* 1644 * Decrements a page table page's wire count, which is used to record the 1645 * number of valid page table entries within the page. If the wire count 1646 * drops to zero, then the page table page is unmapped. Returns TRUE if the 1647 * page table page was unmapped and FALSE otherwise. 1648 */ 1649static inline boolean_t 1650pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free) 1651{ 1652 1653 --m->wire_count; 1654 if (m->wire_count == 0) { 1655 _pmap_unwire_ptp(pmap, m, free); 1656 return (TRUE); 1657 } else 1658 return (FALSE); 1659} 1660 1661static void 1662_pmap_unwire_ptp(pmap_t pmap, vm_page_t m, struct spglist *free) 1663{ 1664 vm_offset_t pteva; 1665 1666 /* 1667 * unmap the page table page 1668 */ 1669 pmap->pm_pdir[m->pindex] = 0; 1670 --pmap->pm_stats.resident_count; 1671 1672 /* 1673 * This is a release store so that the ordinary store unmapping 1674 * the page table page is globally performed before TLB shoot- 1675 * down is begun. 1676 */ 1677 atomic_subtract_rel_int(&cnt.v_wire_count, 1); 1678 1679 /* 1680 * Do an invltlb to make the invalidated mapping 1681 * take effect immediately. 1682 */ 1683 pteva = VM_MAXUSER_ADDRESS + i386_ptob(m->pindex); 1684 pmap_invalidate_page(pmap, pteva); 1685 1686 /* 1687 * Put page on a list so that it is released after 1688 * *ALL* TLB shootdown is done 1689 */ 1690 pmap_add_delayed_free_list(m, free, TRUE); 1691} 1692 1693/* 1694 * After removing a page table entry, this routine is used to 1695 * conditionally free the page, and manage the hold/wire counts. 1696 */ 1697static int 1698pmap_unuse_pt(pmap_t pmap, vm_offset_t va, struct spglist *free) 1699{ 1700 pd_entry_t ptepde; 1701 vm_page_t mpte; 1702 1703 if (va >= VM_MAXUSER_ADDRESS) 1704 return (0); 1705 ptepde = *pmap_pde(pmap, va); 1706 mpte = PHYS_TO_VM_PAGE(ptepde & PG_FRAME); 1707 return (pmap_unwire_ptp(pmap, mpte, free)); 1708} 1709 1710/* 1711 * Initialize the pmap for the swapper process. 1712 */ 1713void 1714pmap_pinit0(pmap_t pmap) 1715{ 1716 1717 PMAP_LOCK_INIT(pmap); 1718 /* 1719 * Since the page table directory is shared with the kernel pmap, 1720 * which is already included in the list "allpmaps", this pmap does 1721 * not need to be inserted into that list. 1722 */ 1723 pmap->pm_pdir = (pd_entry_t *)(KERNBASE + (vm_offset_t)IdlePTD); 1724#ifdef PAE 1725 pmap->pm_pdpt = (pdpt_entry_t *)(KERNBASE + (vm_offset_t)IdlePDPT); 1726#endif 1727 pmap->pm_root.rt_root = 0; 1728 CPU_ZERO(&pmap->pm_active); 1729 PCPU_SET(curpmap, pmap); 1730 TAILQ_INIT(&pmap->pm_pvchunk); 1731 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1732} 1733 1734/* 1735 * Initialize a preallocated and zeroed pmap structure, 1736 * such as one in a vmspace structure. 1737 */ 1738int 1739pmap_pinit(pmap_t pmap) 1740{ 1741 vm_page_t m, ptdpg[NPGPTD]; 1742 vm_paddr_t pa; 1743 int i; 1744 1745 /* 1746 * No need to allocate page table space yet but we do need a valid 1747 * page directory table. 1748 */ 1749 if (pmap->pm_pdir == NULL) { 1750 pmap->pm_pdir = (pd_entry_t *)kva_alloc(NBPTD); 1751 if (pmap->pm_pdir == NULL) { 1752 PMAP_LOCK_DESTROY(pmap); 1753 return (0); 1754 } 1755#ifdef PAE 1756 pmap->pm_pdpt = uma_zalloc(pdptzone, M_WAITOK | M_ZERO); 1757 KASSERT(((vm_offset_t)pmap->pm_pdpt & 1758 ((NPGPTD * sizeof(pdpt_entry_t)) - 1)) == 0, 1759 ("pmap_pinit: pdpt misaligned")); 1760 KASSERT(pmap_kextract((vm_offset_t)pmap->pm_pdpt) < (4ULL<<30), 1761 ("pmap_pinit: pdpt above 4g")); 1762#endif 1763 pmap->pm_root.rt_root = 0; 1764 } 1765 KASSERT(vm_radix_is_empty(&pmap->pm_root), 1766 ("pmap_pinit: pmap has reserved page table page(s)")); 1767 1768 /* 1769 * allocate the page directory page(s) 1770 */ 1771 for (i = 0; i < NPGPTD;) { 1772 m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | VM_ALLOC_NOOBJ | 1773 VM_ALLOC_WIRED | VM_ALLOC_ZERO); 1774 if (m == NULL) 1775 VM_WAIT; 1776 else { 1777 ptdpg[i++] = m; 1778 } 1779 } 1780 1781 pmap_qenter((vm_offset_t)pmap->pm_pdir, ptdpg, NPGPTD); 1782 1783 for (i = 0; i < NPGPTD; i++) 1784 if ((ptdpg[i]->flags & PG_ZERO) == 0) 1785 pagezero(pmap->pm_pdir + (i * NPDEPG)); 1786 1787 mtx_lock_spin(&allpmaps_lock); 1788 LIST_INSERT_HEAD(&allpmaps, pmap, pm_list); 1789 /* Copy the kernel page table directory entries. */ 1790 bcopy(PTD + KPTDI, pmap->pm_pdir + KPTDI, nkpt * sizeof(pd_entry_t)); 1791 mtx_unlock_spin(&allpmaps_lock); 1792 1793 /* install self-referential address mapping entry(s) */ 1794 for (i = 0; i < NPGPTD; i++) { 1795 pa = VM_PAGE_TO_PHYS(ptdpg[i]); 1796 pmap->pm_pdir[PTDPTDI + i] = pa | PG_V | PG_RW | PG_A | PG_M; 1797#ifdef PAE 1798 pmap->pm_pdpt[i] = pa | PG_V; 1799#endif 1800 } 1801 1802 CPU_ZERO(&pmap->pm_active); 1803 TAILQ_INIT(&pmap->pm_pvchunk); 1804 bzero(&pmap->pm_stats, sizeof pmap->pm_stats); 1805 1806 return (1); 1807} 1808 1809/* 1810 * this routine is called if the page table page is not 1811 * mapped correctly. 1812 */ 1813static vm_page_t 1814_pmap_allocpte(pmap_t pmap, u_int ptepindex, int flags) 1815{ 1816 vm_paddr_t ptepa; 1817 vm_page_t m; 1818 1819 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1820 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1821 ("_pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1822 1823 /* 1824 * Allocate a page table page. 1825 */ 1826 if ((m = vm_page_alloc(NULL, ptepindex, VM_ALLOC_NOOBJ | 1827 VM_ALLOC_WIRED | VM_ALLOC_ZERO)) == NULL) { 1828 if (flags & M_WAITOK) { 1829 PMAP_UNLOCK(pmap); 1830 rw_wunlock(&pvh_global_lock); 1831 VM_WAIT; 1832 rw_wlock(&pvh_global_lock); 1833 PMAP_LOCK(pmap); 1834 } 1835 1836 /* 1837 * Indicate the need to retry. While waiting, the page table 1838 * page may have been allocated. 1839 */ 1840 return (NULL); 1841 } 1842 if ((m->flags & PG_ZERO) == 0) 1843 pmap_zero_page(m); 1844 1845 /* 1846 * Map the pagetable page into the process address space, if 1847 * it isn't already there. 1848 */ 1849 1850 pmap->pm_stats.resident_count++; 1851 1852 ptepa = VM_PAGE_TO_PHYS(m); 1853 pmap->pm_pdir[ptepindex] = 1854 (pd_entry_t) (ptepa | PG_U | PG_RW | PG_V | PG_A | PG_M); 1855 1856 return (m); 1857} 1858 1859static vm_page_t 1860pmap_allocpte(pmap_t pmap, vm_offset_t va, int flags) 1861{ 1862 u_int ptepindex; 1863 pd_entry_t ptepa; 1864 vm_page_t m; 1865 1866 KASSERT((flags & (M_NOWAIT | M_WAITOK)) == M_NOWAIT || 1867 (flags & (M_NOWAIT | M_WAITOK)) == M_WAITOK, 1868 ("pmap_allocpte: flags is neither M_NOWAIT nor M_WAITOK")); 1869 1870 /* 1871 * Calculate pagetable page index 1872 */ 1873 ptepindex = va >> PDRSHIFT; 1874retry: 1875 /* 1876 * Get the page directory entry 1877 */ 1878 ptepa = pmap->pm_pdir[ptepindex]; 1879 1880 /* 1881 * This supports switching from a 4MB page to a 1882 * normal 4K page. 1883 */ 1884 if (ptepa & PG_PS) { 1885 (void)pmap_demote_pde(pmap, &pmap->pm_pdir[ptepindex], va); 1886 ptepa = pmap->pm_pdir[ptepindex]; 1887 } 1888 1889 /* 1890 * If the page table page is mapped, we just increment the 1891 * hold count, and activate it. 1892 */ 1893 if (ptepa) { 1894 m = PHYS_TO_VM_PAGE(ptepa & PG_FRAME); 1895 m->wire_count++; 1896 } else { 1897 /* 1898 * Here if the pte page isn't mapped, or if it has 1899 * been deallocated. 1900 */ 1901 m = _pmap_allocpte(pmap, ptepindex, flags); 1902 if (m == NULL && (flags & M_WAITOK)) 1903 goto retry; 1904 } 1905 return (m); 1906} 1907 1908 1909/*************************************************** 1910* Pmap allocation/deallocation routines. 1911 ***************************************************/ 1912 1913#ifdef SMP 1914/* 1915 * Deal with a SMP shootdown of other users of the pmap that we are 1916 * trying to dispose of. This can be a bit hairy. 1917 */ 1918static cpuset_t *lazymask; 1919static u_int lazyptd; 1920static volatile u_int lazywait; 1921 1922void pmap_lazyfix_action(void); 1923 1924void 1925pmap_lazyfix_action(void) 1926{ 1927 1928#ifdef COUNT_IPIS 1929 (*ipi_lazypmap_counts[PCPU_GET(cpuid)])++; 1930#endif 1931 if (rcr3() == lazyptd) 1932 load_cr3(curpcb->pcb_cr3); 1933 CPU_CLR_ATOMIC(PCPU_GET(cpuid), lazymask); 1934 atomic_store_rel_int(&lazywait, 1); 1935} 1936 1937static void 1938pmap_lazyfix_self(u_int cpuid) 1939{ 1940 1941 if (rcr3() == lazyptd) 1942 load_cr3(curpcb->pcb_cr3); 1943 CPU_CLR_ATOMIC(cpuid, lazymask); 1944} 1945 1946 1947static void 1948pmap_lazyfix(pmap_t pmap) 1949{ 1950 cpuset_t mymask, mask; 1951 u_int cpuid, spins; 1952 int lsb; 1953 1954 mask = pmap->pm_active; 1955 while (!CPU_EMPTY(&mask)) { 1956 spins = 50000000; 1957 1958 /* Find least significant set bit. */ 1959 lsb = CPU_FFS(&mask); 1960 MPASS(lsb != 0); 1961 lsb--; 1962 CPU_SETOF(lsb, &mask); 1963 mtx_lock_spin(&smp_ipi_mtx); 1964#ifdef PAE 1965 lazyptd = vtophys(pmap->pm_pdpt); 1966#else 1967 lazyptd = vtophys(pmap->pm_pdir); 1968#endif 1969 cpuid = PCPU_GET(cpuid); 1970 1971 /* Use a cpuset just for having an easy check. */ 1972 CPU_SETOF(cpuid, &mymask); 1973 if (!CPU_CMP(&mask, &mymask)) { 1974 lazymask = &pmap->pm_active; 1975 pmap_lazyfix_self(cpuid); 1976 } else { 1977 atomic_store_rel_int((u_int *)&lazymask, 1978 (u_int)&pmap->pm_active); 1979 atomic_store_rel_int(&lazywait, 0); 1980 ipi_selected(mask, IPI_LAZYPMAP); 1981 while (lazywait == 0) { 1982 ia32_pause(); 1983 if (--spins == 0) 1984 break; 1985 } 1986 } 1987 mtx_unlock_spin(&smp_ipi_mtx); 1988 if (spins == 0) 1989 printf("pmap_lazyfix: spun for 50000000\n"); 1990 mask = pmap->pm_active; 1991 } 1992} 1993 1994#else /* SMP */ 1995 1996/* 1997 * Cleaning up on uniprocessor is easy. For various reasons, we're 1998 * unlikely to have to even execute this code, including the fact 1999 * that the cleanup is deferred until the parent does a wait(2), which 2000 * means that another userland process has run. 2001 */ 2002static void 2003pmap_lazyfix(pmap_t pmap) 2004{ 2005 u_int cr3; 2006 2007 cr3 = vtophys(pmap->pm_pdir); 2008 if (cr3 == rcr3()) { 2009 load_cr3(curpcb->pcb_cr3); 2010 CPU_CLR(PCPU_GET(cpuid), &pmap->pm_active); 2011 } 2012} 2013#endif /* SMP */ 2014 2015/* 2016 * Release any resources held by the given physical map. 2017 * Called when a pmap initialized by pmap_pinit is being released. 2018 * Should only be called if the map contains no valid mappings. 2019 */ 2020void 2021pmap_release(pmap_t pmap) 2022{ 2023 vm_page_t m, ptdpg[NPGPTD]; 2024 int i; 2025 2026 KASSERT(pmap->pm_stats.resident_count == 0, 2027 ("pmap_release: pmap resident count %ld != 0", 2028 pmap->pm_stats.resident_count)); 2029 KASSERT(vm_radix_is_empty(&pmap->pm_root), 2030 ("pmap_release: pmap has reserved page table page(s)")); 2031 2032 pmap_lazyfix(pmap); 2033 mtx_lock_spin(&allpmaps_lock); 2034 LIST_REMOVE(pmap, pm_list); 2035 mtx_unlock_spin(&allpmaps_lock); 2036 2037 for (i = 0; i < NPGPTD; i++) 2038 ptdpg[i] = PHYS_TO_VM_PAGE(pmap->pm_pdir[PTDPTDI + i] & 2039 PG_FRAME); 2040 2041 bzero(pmap->pm_pdir + PTDPTDI, (nkpt + NPGPTD) * 2042 sizeof(*pmap->pm_pdir)); 2043 2044 pmap_qremove((vm_offset_t)pmap->pm_pdir, NPGPTD); 2045 2046 for (i = 0; i < NPGPTD; i++) { 2047 m = ptdpg[i]; 2048#ifdef PAE 2049 KASSERT(VM_PAGE_TO_PHYS(m) == (pmap->pm_pdpt[i] & PG_FRAME), 2050 ("pmap_release: got wrong ptd page")); 2051#endif 2052 m->wire_count--; 2053 atomic_subtract_int(&cnt.v_wire_count, 1); 2054 vm_page_free_zero(m); 2055 } 2056} 2057 2058static int 2059kvm_size(SYSCTL_HANDLER_ARGS) 2060{ 2061 unsigned long ksize = VM_MAX_KERNEL_ADDRESS - KERNBASE; 2062 2063 return (sysctl_handle_long(oidp, &ksize, 0, req)); 2064} 2065SYSCTL_PROC(_vm, OID_AUTO, kvm_size, CTLTYPE_LONG|CTLFLAG_RD, 2066 0, 0, kvm_size, "IU", "Size of KVM"); 2067 2068static int 2069kvm_free(SYSCTL_HANDLER_ARGS) 2070{ 2071 unsigned long kfree = VM_MAX_KERNEL_ADDRESS - kernel_vm_end; 2072 2073 return (sysctl_handle_long(oidp, &kfree, 0, req)); 2074} 2075SYSCTL_PROC(_vm, OID_AUTO, kvm_free, CTLTYPE_LONG|CTLFLAG_RD, 2076 0, 0, kvm_free, "IU", "Amount of KVM free"); 2077 2078/* 2079 * grow the number of kernel page table entries, if needed 2080 */ 2081void 2082pmap_growkernel(vm_offset_t addr) 2083{ 2084 vm_paddr_t ptppaddr; 2085 vm_page_t nkpg; 2086 pd_entry_t newpdir; 2087 2088 mtx_assert(&kernel_map->system_mtx, MA_OWNED); 2089 addr = roundup2(addr, NBPDR); 2090 if (addr - 1 >= kernel_map->max_offset) 2091 addr = kernel_map->max_offset; 2092 while (kernel_vm_end < addr) { 2093 if (pdir_pde(PTD, kernel_vm_end)) { 2094 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 2095 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 2096 kernel_vm_end = kernel_map->max_offset; 2097 break; 2098 } 2099 continue; 2100 } 2101 2102 nkpg = vm_page_alloc(NULL, kernel_vm_end >> PDRSHIFT, 2103 VM_ALLOC_INTERRUPT | VM_ALLOC_NOOBJ | VM_ALLOC_WIRED | 2104 VM_ALLOC_ZERO); 2105 if (nkpg == NULL) 2106 panic("pmap_growkernel: no memory to grow kernel"); 2107 2108 nkpt++; 2109 2110 if ((nkpg->flags & PG_ZERO) == 0) 2111 pmap_zero_page(nkpg); 2112 ptppaddr = VM_PAGE_TO_PHYS(nkpg); 2113 newpdir = (pd_entry_t) (ptppaddr | PG_V | PG_RW | PG_A | PG_M); 2114 pdir_pde(KPTD, kernel_vm_end) = pgeflag | newpdir; 2115 2116 pmap_kenter_pde(kernel_vm_end, newpdir); 2117 kernel_vm_end = (kernel_vm_end + NBPDR) & ~PDRMASK; 2118 if (kernel_vm_end - 1 >= kernel_map->max_offset) { 2119 kernel_vm_end = kernel_map->max_offset; 2120 break; 2121 } 2122 } 2123} 2124 2125 2126/*************************************************** 2127 * page management routines. 2128 ***************************************************/ 2129 2130CTASSERT(sizeof(struct pv_chunk) == PAGE_SIZE); 2131CTASSERT(_NPCM == 11); 2132CTASSERT(_NPCPV == 336); 2133 2134static __inline struct pv_chunk * 2135pv_to_chunk(pv_entry_t pv) 2136{ 2137 2138 return ((struct pv_chunk *)((uintptr_t)pv & ~(uintptr_t)PAGE_MASK)); 2139} 2140 2141#define PV_PMAP(pv) (pv_to_chunk(pv)->pc_pmap) 2142 2143#define PC_FREE0_9 0xfffffffful /* Free values for index 0 through 9 */ 2144#define PC_FREE10 0x0000fffful /* Free values for index 10 */ 2145 2146static const uint32_t pc_freemask[_NPCM] = { 2147 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 2148 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 2149 PC_FREE0_9, PC_FREE0_9, PC_FREE0_9, 2150 PC_FREE0_9, PC_FREE10 2151}; 2152 2153SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_count, CTLFLAG_RD, &pv_entry_count, 0, 2154 "Current number of pv entries"); 2155 2156#ifdef PV_STATS 2157static int pc_chunk_count, pc_chunk_allocs, pc_chunk_frees, pc_chunk_tryfail; 2158 2159SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_count, CTLFLAG_RD, &pc_chunk_count, 0, 2160 "Current number of pv entry chunks"); 2161SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_allocs, CTLFLAG_RD, &pc_chunk_allocs, 0, 2162 "Current number of pv entry chunks allocated"); 2163SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_frees, CTLFLAG_RD, &pc_chunk_frees, 0, 2164 "Current number of pv entry chunks frees"); 2165SYSCTL_INT(_vm_pmap, OID_AUTO, pc_chunk_tryfail, CTLFLAG_RD, &pc_chunk_tryfail, 0, 2166 "Number of times tried to get a chunk page but failed."); 2167 2168static long pv_entry_frees, pv_entry_allocs; 2169static int pv_entry_spare; 2170 2171SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_frees, CTLFLAG_RD, &pv_entry_frees, 0, 2172 "Current number of pv entry frees"); 2173SYSCTL_LONG(_vm_pmap, OID_AUTO, pv_entry_allocs, CTLFLAG_RD, &pv_entry_allocs, 0, 2174 "Current number of pv entry allocs"); 2175SYSCTL_INT(_vm_pmap, OID_AUTO, pv_entry_spare, CTLFLAG_RD, &pv_entry_spare, 0, 2176 "Current number of spare pv entries"); 2177#endif 2178 2179/* 2180 * We are in a serious low memory condition. Resort to 2181 * drastic measures to free some pages so we can allocate 2182 * another pv entry chunk. 2183 */ 2184static vm_page_t 2185pmap_pv_reclaim(pmap_t locked_pmap) 2186{ 2187 struct pch newtail; 2188 struct pv_chunk *pc; 2189 struct md_page *pvh; 2190 pd_entry_t *pde; 2191 pmap_t pmap; 2192 pt_entry_t *pte, tpte; 2193 pv_entry_t pv; 2194 vm_offset_t va; 2195 vm_page_t m, m_pc; 2196 struct spglist free; 2197 uint32_t inuse; 2198 int bit, field, freed; 2199 2200 PMAP_LOCK_ASSERT(locked_pmap, MA_OWNED); 2201 pmap = NULL; 2202 m_pc = NULL; 2203 SLIST_INIT(&free); 2204 TAILQ_INIT(&newtail); 2205 while ((pc = TAILQ_FIRST(&pv_chunks)) != NULL && (pv_vafree == 0 || 2206 SLIST_EMPTY(&free))) { 2207 TAILQ_REMOVE(&pv_chunks, pc, pc_lru); 2208 if (pmap != pc->pc_pmap) { 2209 if (pmap != NULL) { 2210 pmap_invalidate_all(pmap); 2211 if (pmap != locked_pmap) 2212 PMAP_UNLOCK(pmap); 2213 } 2214 pmap = pc->pc_pmap; 2215 /* Avoid deadlock and lock recursion. */ 2216 if (pmap > locked_pmap) 2217 PMAP_LOCK(pmap); 2218 else if (pmap != locked_pmap && !PMAP_TRYLOCK(pmap)) { 2219 pmap = NULL; 2220 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 2221 continue; 2222 } 2223 } 2224 2225 /* 2226 * Destroy every non-wired, 4 KB page mapping in the chunk. 2227 */ 2228 freed = 0; 2229 for (field = 0; field < _NPCM; field++) { 2230 for (inuse = ~pc->pc_map[field] & pc_freemask[field]; 2231 inuse != 0; inuse &= ~(1UL << bit)) { 2232 bit = bsfl(inuse); 2233 pv = &pc->pc_pventry[field * 32 + bit]; 2234 va = pv->pv_va; 2235 pde = pmap_pde(pmap, va); 2236 if ((*pde & PG_PS) != 0) 2237 continue; 2238 pte = pmap_pte(pmap, va); 2239 tpte = *pte; 2240 if ((tpte & PG_W) == 0) 2241 tpte = pte_load_clear(pte); 2242 pmap_pte_release(pte); 2243 if ((tpte & PG_W) != 0) 2244 continue; 2245 KASSERT(tpte != 0, 2246 ("pmap_pv_reclaim: pmap %p va %x zero pte", 2247 pmap, va)); 2248 if ((tpte & PG_G) != 0) 2249 pmap_invalidate_page(pmap, va); 2250 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 2251 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2252 vm_page_dirty(m); 2253 if ((tpte & PG_A) != 0) 2254 vm_page_aflag_set(m, PGA_REFERENCED); 2255 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 2256 if (TAILQ_EMPTY(&m->md.pv_list) && 2257 (m->flags & PG_FICTITIOUS) == 0) { 2258 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 2259 if (TAILQ_EMPTY(&pvh->pv_list)) { 2260 vm_page_aflag_clear(m, 2261 PGA_WRITEABLE); 2262 } 2263 } 2264 pc->pc_map[field] |= 1UL << bit; 2265 pmap_unuse_pt(pmap, va, &free); 2266 freed++; 2267 } 2268 } 2269 if (freed == 0) { 2270 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 2271 continue; 2272 } 2273 /* Every freed mapping is for a 4 KB page. */ 2274 pmap->pm_stats.resident_count -= freed; 2275 PV_STAT(pv_entry_frees += freed); 2276 PV_STAT(pv_entry_spare += freed); 2277 pv_entry_count -= freed; 2278 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2279 for (field = 0; field < _NPCM; field++) 2280 if (pc->pc_map[field] != pc_freemask[field]) { 2281 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, 2282 pc_list); 2283 TAILQ_INSERT_TAIL(&newtail, pc, pc_lru); 2284 2285 /* 2286 * One freed pv entry in locked_pmap is 2287 * sufficient. 2288 */ 2289 if (pmap == locked_pmap) 2290 goto out; 2291 break; 2292 } 2293 if (field == _NPCM) { 2294 PV_STAT(pv_entry_spare -= _NPCPV); 2295 PV_STAT(pc_chunk_count--); 2296 PV_STAT(pc_chunk_frees++); 2297 /* Entire chunk is free; return it. */ 2298 m_pc = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 2299 pmap_qremove((vm_offset_t)pc, 1); 2300 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 2301 break; 2302 } 2303 } 2304out: 2305 TAILQ_CONCAT(&pv_chunks, &newtail, pc_lru); 2306 if (pmap != NULL) { 2307 pmap_invalidate_all(pmap); 2308 if (pmap != locked_pmap) 2309 PMAP_UNLOCK(pmap); 2310 } 2311 if (m_pc == NULL && pv_vafree != 0 && SLIST_EMPTY(&free)) { 2312 m_pc = SLIST_FIRST(&free); 2313 SLIST_REMOVE_HEAD(&free, plinks.s.ss); 2314 /* Recycle a freed page table page. */ 2315 m_pc->wire_count = 1; 2316 atomic_add_int(&cnt.v_wire_count, 1); 2317 } 2318 pmap_free_zero_pages(&free); 2319 return (m_pc); 2320} 2321 2322/* 2323 * free the pv_entry back to the free list 2324 */ 2325static void 2326free_pv_entry(pmap_t pmap, pv_entry_t pv) 2327{ 2328 struct pv_chunk *pc; 2329 int idx, field, bit; 2330 2331 rw_assert(&pvh_global_lock, RA_WLOCKED); 2332 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2333 PV_STAT(pv_entry_frees++); 2334 PV_STAT(pv_entry_spare++); 2335 pv_entry_count--; 2336 pc = pv_to_chunk(pv); 2337 idx = pv - &pc->pc_pventry[0]; 2338 field = idx / 32; 2339 bit = idx % 32; 2340 pc->pc_map[field] |= 1ul << bit; 2341 for (idx = 0; idx < _NPCM; idx++) 2342 if (pc->pc_map[idx] != pc_freemask[idx]) { 2343 /* 2344 * 98% of the time, pc is already at the head of the 2345 * list. If it isn't already, move it to the head. 2346 */ 2347 if (__predict_false(TAILQ_FIRST(&pmap->pm_pvchunk) != 2348 pc)) { 2349 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2350 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, 2351 pc_list); 2352 } 2353 return; 2354 } 2355 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2356 free_pv_chunk(pc); 2357} 2358 2359static void 2360free_pv_chunk(struct pv_chunk *pc) 2361{ 2362 vm_page_t m; 2363 2364 TAILQ_REMOVE(&pv_chunks, pc, pc_lru); 2365 PV_STAT(pv_entry_spare -= _NPCPV); 2366 PV_STAT(pc_chunk_count--); 2367 PV_STAT(pc_chunk_frees++); 2368 /* entire chunk is free, return it */ 2369 m = PHYS_TO_VM_PAGE(pmap_kextract((vm_offset_t)pc)); 2370 pmap_qremove((vm_offset_t)pc, 1); 2371 vm_page_unwire(m, 0); 2372 vm_page_free(m); 2373 pmap_ptelist_free(&pv_vafree, (vm_offset_t)pc); 2374} 2375 2376/* 2377 * get a new pv_entry, allocating a block from the system 2378 * when needed. 2379 */ 2380static pv_entry_t 2381get_pv_entry(pmap_t pmap, boolean_t try) 2382{ 2383 static const struct timeval printinterval = { 60, 0 }; 2384 static struct timeval lastprint; 2385 int bit, field; 2386 pv_entry_t pv; 2387 struct pv_chunk *pc; 2388 vm_page_t m; 2389 2390 rw_assert(&pvh_global_lock, RA_WLOCKED); 2391 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2392 PV_STAT(pv_entry_allocs++); 2393 pv_entry_count++; 2394 if (pv_entry_count > pv_entry_high_water) 2395 if (ratecheck(&lastprint, &printinterval)) 2396 printf("Approaching the limit on PV entries, consider " 2397 "increasing either the vm.pmap.shpgperproc or the " 2398 "vm.pmap.pv_entry_max tunable.\n"); 2399retry: 2400 pc = TAILQ_FIRST(&pmap->pm_pvchunk); 2401 if (pc != NULL) { 2402 for (field = 0; field < _NPCM; field++) { 2403 if (pc->pc_map[field]) { 2404 bit = bsfl(pc->pc_map[field]); 2405 break; 2406 } 2407 } 2408 if (field < _NPCM) { 2409 pv = &pc->pc_pventry[field * 32 + bit]; 2410 pc->pc_map[field] &= ~(1ul << bit); 2411 /* If this was the last item, move it to tail */ 2412 for (field = 0; field < _NPCM; field++) 2413 if (pc->pc_map[field] != 0) { 2414 PV_STAT(pv_entry_spare--); 2415 return (pv); /* not full, return */ 2416 } 2417 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 2418 TAILQ_INSERT_TAIL(&pmap->pm_pvchunk, pc, pc_list); 2419 PV_STAT(pv_entry_spare--); 2420 return (pv); 2421 } 2422 } 2423 /* 2424 * Access to the ptelist "pv_vafree" is synchronized by the pvh 2425 * global lock. If "pv_vafree" is currently non-empty, it will 2426 * remain non-empty until pmap_ptelist_alloc() completes. 2427 */ 2428 if (pv_vafree == 0 || (m = vm_page_alloc(NULL, 0, VM_ALLOC_NORMAL | 2429 VM_ALLOC_NOOBJ | VM_ALLOC_WIRED)) == NULL) { 2430 if (try) { 2431 pv_entry_count--; 2432 PV_STAT(pc_chunk_tryfail++); 2433 return (NULL); 2434 } 2435 m = pmap_pv_reclaim(pmap); 2436 if (m == NULL) 2437 goto retry; 2438 } 2439 PV_STAT(pc_chunk_count++); 2440 PV_STAT(pc_chunk_allocs++); 2441 pc = (struct pv_chunk *)pmap_ptelist_alloc(&pv_vafree); 2442 pmap_qenter((vm_offset_t)pc, &m, 1); 2443 pc->pc_pmap = pmap; 2444 pc->pc_map[0] = pc_freemask[0] & ~1ul; /* preallocated bit 0 */ 2445 for (field = 1; field < _NPCM; field++) 2446 pc->pc_map[field] = pc_freemask[field]; 2447 TAILQ_INSERT_TAIL(&pv_chunks, pc, pc_lru); 2448 pv = &pc->pc_pventry[0]; 2449 TAILQ_INSERT_HEAD(&pmap->pm_pvchunk, pc, pc_list); 2450 PV_STAT(pv_entry_spare += _NPCPV - 1); 2451 return (pv); 2452} 2453 2454static __inline pv_entry_t 2455pmap_pvh_remove(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2456{ 2457 pv_entry_t pv; 2458 2459 rw_assert(&pvh_global_lock, RA_WLOCKED); 2460 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 2461 if (pmap == PV_PMAP(pv) && va == pv->pv_va) { 2462 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next); 2463 break; 2464 } 2465 } 2466 return (pv); 2467} 2468 2469static void 2470pmap_pv_demote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa) 2471{ 2472 struct md_page *pvh; 2473 pv_entry_t pv; 2474 vm_offset_t va_last; 2475 vm_page_t m; 2476 2477 rw_assert(&pvh_global_lock, RA_WLOCKED); 2478 KASSERT((pa & PDRMASK) == 0, 2479 ("pmap_pv_demote_pde: pa is not 4mpage aligned")); 2480 2481 /* 2482 * Transfer the 4mpage's pv entry for this mapping to the first 2483 * page's pv list. 2484 */ 2485 pvh = pa_to_pvh(pa); 2486 va = trunc_4mpage(va); 2487 pv = pmap_pvh_remove(pvh, pmap, va); 2488 KASSERT(pv != NULL, ("pmap_pv_demote_pde: pv not found")); 2489 m = PHYS_TO_VM_PAGE(pa); 2490 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 2491 /* Instantiate the remaining NPTEPG - 1 pv entries. */ 2492 va_last = va + NBPDR - PAGE_SIZE; 2493 do { 2494 m++; 2495 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 2496 ("pmap_pv_demote_pde: page %p is not managed", m)); 2497 va += PAGE_SIZE; 2498 pmap_insert_entry(pmap, va, m); 2499 } while (va < va_last); 2500} 2501 2502static void 2503pmap_pv_promote_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa) 2504{ 2505 struct md_page *pvh; 2506 pv_entry_t pv; 2507 vm_offset_t va_last; 2508 vm_page_t m; 2509 2510 rw_assert(&pvh_global_lock, RA_WLOCKED); 2511 KASSERT((pa & PDRMASK) == 0, 2512 ("pmap_pv_promote_pde: pa is not 4mpage aligned")); 2513 2514 /* 2515 * Transfer the first page's pv entry for this mapping to the 2516 * 4mpage's pv list. Aside from avoiding the cost of a call 2517 * to get_pv_entry(), a transfer avoids the possibility that 2518 * get_pv_entry() calls pmap_collect() and that pmap_collect() 2519 * removes one of the mappings that is being promoted. 2520 */ 2521 m = PHYS_TO_VM_PAGE(pa); 2522 va = trunc_4mpage(va); 2523 pv = pmap_pvh_remove(&m->md, pmap, va); 2524 KASSERT(pv != NULL, ("pmap_pv_promote_pde: pv not found")); 2525 pvh = pa_to_pvh(pa); 2526 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next); 2527 /* Free the remaining NPTEPG - 1 pv entries. */ 2528 va_last = va + NBPDR - PAGE_SIZE; 2529 do { 2530 m++; 2531 va += PAGE_SIZE; 2532 pmap_pvh_free(&m->md, pmap, va); 2533 } while (va < va_last); 2534} 2535 2536static void 2537pmap_pvh_free(struct md_page *pvh, pmap_t pmap, vm_offset_t va) 2538{ 2539 pv_entry_t pv; 2540 2541 pv = pmap_pvh_remove(pvh, pmap, va); 2542 KASSERT(pv != NULL, ("pmap_pvh_free: pv not found")); 2543 free_pv_entry(pmap, pv); 2544} 2545 2546static void 2547pmap_remove_entry(pmap_t pmap, vm_page_t m, vm_offset_t va) 2548{ 2549 struct md_page *pvh; 2550 2551 rw_assert(&pvh_global_lock, RA_WLOCKED); 2552 pmap_pvh_free(&m->md, pmap, va); 2553 if (TAILQ_EMPTY(&m->md.pv_list) && (m->flags & PG_FICTITIOUS) == 0) { 2554 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 2555 if (TAILQ_EMPTY(&pvh->pv_list)) 2556 vm_page_aflag_clear(m, PGA_WRITEABLE); 2557 } 2558} 2559 2560/* 2561 * Create a pv entry for page at pa for 2562 * (pmap, va). 2563 */ 2564static void 2565pmap_insert_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2566{ 2567 pv_entry_t pv; 2568 2569 rw_assert(&pvh_global_lock, RA_WLOCKED); 2570 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2571 pv = get_pv_entry(pmap, FALSE); 2572 pv->pv_va = va; 2573 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 2574} 2575 2576/* 2577 * Conditionally create a pv entry. 2578 */ 2579static boolean_t 2580pmap_try_insert_pv_entry(pmap_t pmap, vm_offset_t va, vm_page_t m) 2581{ 2582 pv_entry_t pv; 2583 2584 rw_assert(&pvh_global_lock, RA_WLOCKED); 2585 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2586 if (pv_entry_count < pv_entry_high_water && 2587 (pv = get_pv_entry(pmap, TRUE)) != NULL) { 2588 pv->pv_va = va; 2589 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 2590 return (TRUE); 2591 } else 2592 return (FALSE); 2593} 2594 2595/* 2596 * Create the pv entries for each of the pages within a superpage. 2597 */ 2598static boolean_t 2599pmap_pv_insert_pde(pmap_t pmap, vm_offset_t va, vm_paddr_t pa) 2600{ 2601 struct md_page *pvh; 2602 pv_entry_t pv; 2603 2604 rw_assert(&pvh_global_lock, RA_WLOCKED); 2605 if (pv_entry_count < pv_entry_high_water && 2606 (pv = get_pv_entry(pmap, TRUE)) != NULL) { 2607 pv->pv_va = va; 2608 pvh = pa_to_pvh(pa); 2609 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next); 2610 return (TRUE); 2611 } else 2612 return (FALSE); 2613} 2614 2615/* 2616 * Fills a page table page with mappings to consecutive physical pages. 2617 */ 2618static void 2619pmap_fill_ptp(pt_entry_t *firstpte, pt_entry_t newpte) 2620{ 2621 pt_entry_t *pte; 2622 2623 for (pte = firstpte; pte < firstpte + NPTEPG; pte++) { 2624 *pte = newpte; 2625 newpte += PAGE_SIZE; 2626 } 2627} 2628 2629/* 2630 * Tries to demote a 2- or 4MB page mapping. If demotion fails, the 2631 * 2- or 4MB page mapping is invalidated. 2632 */ 2633static boolean_t 2634pmap_demote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va) 2635{ 2636 pd_entry_t newpde, oldpde; 2637 pt_entry_t *firstpte, newpte; 2638 vm_paddr_t mptepa; 2639 vm_page_t mpte; 2640 struct spglist free; 2641 2642 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2643 oldpde = *pde; 2644 KASSERT((oldpde & (PG_PS | PG_V)) == (PG_PS | PG_V), 2645 ("pmap_demote_pde: oldpde is missing PG_PS and/or PG_V")); 2646 if ((oldpde & PG_A) != 0 && (mpte = pmap_lookup_pt_page(pmap, va)) != 2647 NULL) 2648 pmap_remove_pt_page(pmap, mpte); 2649 else { 2650 KASSERT((oldpde & PG_W) == 0, 2651 ("pmap_demote_pde: page table page for a wired mapping" 2652 " is missing")); 2653 2654 /* 2655 * Invalidate the 2- or 4MB page mapping and return 2656 * "failure" if the mapping was never accessed or the 2657 * allocation of the new page table page fails. 2658 */ 2659 if ((oldpde & PG_A) == 0 || (mpte = vm_page_alloc(NULL, 2660 va >> PDRSHIFT, VM_ALLOC_NOOBJ | VM_ALLOC_NORMAL | 2661 VM_ALLOC_WIRED)) == NULL) { 2662 SLIST_INIT(&free); 2663 pmap_remove_pde(pmap, pde, trunc_4mpage(va), &free); 2664 pmap_invalidate_page(pmap, trunc_4mpage(va)); 2665 pmap_free_zero_pages(&free); 2666 CTR2(KTR_PMAP, "pmap_demote_pde: failure for va %#x" 2667 " in pmap %p", va, pmap); 2668 return (FALSE); 2669 } 2670 if (va < VM_MAXUSER_ADDRESS) 2671 pmap->pm_stats.resident_count++; 2672 } 2673 mptepa = VM_PAGE_TO_PHYS(mpte); 2674 2675 /* 2676 * If the page mapping is in the kernel's address space, then the 2677 * KPTmap can provide access to the page table page. Otherwise, 2678 * temporarily map the page table page (mpte) into the kernel's 2679 * address space at either PADDR1 or PADDR2. 2680 */ 2681 if (va >= KERNBASE) 2682 firstpte = &KPTmap[i386_btop(trunc_4mpage(va))]; 2683 else if (curthread->td_pinned > 0 && rw_wowned(&pvh_global_lock)) { 2684 if ((*PMAP1 & PG_FRAME) != mptepa) { 2685 *PMAP1 = mptepa | PG_RW | PG_V | PG_A | PG_M; 2686#ifdef SMP 2687 PMAP1cpu = PCPU_GET(cpuid); 2688#endif 2689 invlcaddr(PADDR1); 2690 PMAP1changed++; 2691 } else 2692#ifdef SMP 2693 if (PMAP1cpu != PCPU_GET(cpuid)) { 2694 PMAP1cpu = PCPU_GET(cpuid); 2695 invlcaddr(PADDR1); 2696 PMAP1changedcpu++; 2697 } else 2698#endif 2699 PMAP1unchanged++; 2700 firstpte = PADDR1; 2701 } else { 2702 mtx_lock(&PMAP2mutex); 2703 if ((*PMAP2 & PG_FRAME) != mptepa) { 2704 *PMAP2 = mptepa | PG_RW | PG_V | PG_A | PG_M; 2705 pmap_invalidate_page(kernel_pmap, (vm_offset_t)PADDR2); 2706 } 2707 firstpte = PADDR2; 2708 } 2709 newpde = mptepa | PG_M | PG_A | (oldpde & PG_U) | PG_RW | PG_V; 2710 KASSERT((oldpde & PG_A) != 0, 2711 ("pmap_demote_pde: oldpde is missing PG_A")); 2712 KASSERT((oldpde & (PG_M | PG_RW)) != PG_RW, 2713 ("pmap_demote_pde: oldpde is missing PG_M")); 2714 newpte = oldpde & ~PG_PS; 2715 if ((newpte & PG_PDE_PAT) != 0) 2716 newpte ^= PG_PDE_PAT | PG_PTE_PAT; 2717 2718 /* 2719 * If the page table page is new, initialize it. 2720 */ 2721 if (mpte->wire_count == 1) { 2722 mpte->wire_count = NPTEPG; 2723 pmap_fill_ptp(firstpte, newpte); 2724 } 2725 KASSERT((*firstpte & PG_FRAME) == (newpte & PG_FRAME), 2726 ("pmap_demote_pde: firstpte and newpte map different physical" 2727 " addresses")); 2728 2729 /* 2730 * If the mapping has changed attributes, update the page table 2731 * entries. 2732 */ 2733 if ((*firstpte & PG_PTE_PROMOTE) != (newpte & PG_PTE_PROMOTE)) 2734 pmap_fill_ptp(firstpte, newpte); 2735 2736 /* 2737 * Demote the mapping. This pmap is locked. The old PDE has 2738 * PG_A set. If the old PDE has PG_RW set, it also has PG_M 2739 * set. Thus, there is no danger of a race with another 2740 * processor changing the setting of PG_A and/or PG_M between 2741 * the read above and the store below. 2742 */ 2743 if (workaround_erratum383) 2744 pmap_update_pde(pmap, va, pde, newpde); 2745 else if (pmap == kernel_pmap) 2746 pmap_kenter_pde(va, newpde); 2747 else 2748 pde_store(pde, newpde); 2749 if (firstpte == PADDR2) 2750 mtx_unlock(&PMAP2mutex); 2751 2752 /* 2753 * Invalidate the recursive mapping of the page table page. 2754 */ 2755 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va)); 2756 2757 /* 2758 * Demote the pv entry. This depends on the earlier demotion 2759 * of the mapping. Specifically, the (re)creation of a per- 2760 * page pv entry might trigger the execution of pmap_collect(), 2761 * which might reclaim a newly (re)created per-page pv entry 2762 * and destroy the associated mapping. In order to destroy 2763 * the mapping, the PDE must have already changed from mapping 2764 * the 2mpage to referencing the page table page. 2765 */ 2766 if ((oldpde & PG_MANAGED) != 0) 2767 pmap_pv_demote_pde(pmap, va, oldpde & PG_PS_FRAME); 2768 2769 pmap_pde_demotions++; 2770 CTR2(KTR_PMAP, "pmap_demote_pde: success for va %#x" 2771 " in pmap %p", va, pmap); 2772 return (TRUE); 2773} 2774 2775/* 2776 * Removes a 2- or 4MB page mapping from the kernel pmap. 2777 */ 2778static void 2779pmap_remove_kernel_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va) 2780{ 2781 pd_entry_t newpde; 2782 vm_paddr_t mptepa; 2783 vm_page_t mpte; 2784 2785 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2786 mpte = pmap_lookup_pt_page(pmap, va); 2787 if (mpte == NULL) 2788 panic("pmap_remove_kernel_pde: Missing pt page."); 2789 2790 pmap_remove_pt_page(pmap, mpte); 2791 mptepa = VM_PAGE_TO_PHYS(mpte); 2792 newpde = mptepa | PG_M | PG_A | PG_RW | PG_V; 2793 2794 /* 2795 * Initialize the page table page. 2796 */ 2797 pagezero((void *)&KPTmap[i386_btop(trunc_4mpage(va))]); 2798 2799 /* 2800 * Remove the mapping. 2801 */ 2802 if (workaround_erratum383) 2803 pmap_update_pde(pmap, va, pde, newpde); 2804 else 2805 pmap_kenter_pde(va, newpde); 2806 2807 /* 2808 * Invalidate the recursive mapping of the page table page. 2809 */ 2810 pmap_invalidate_page(pmap, (vm_offset_t)vtopte(va)); 2811} 2812 2813/* 2814 * pmap_remove_pde: do the things to unmap a superpage in a process 2815 */ 2816static void 2817pmap_remove_pde(pmap_t pmap, pd_entry_t *pdq, vm_offset_t sva, 2818 struct spglist *free) 2819{ 2820 struct md_page *pvh; 2821 pd_entry_t oldpde; 2822 vm_offset_t eva, va; 2823 vm_page_t m, mpte; 2824 2825 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2826 KASSERT((sva & PDRMASK) == 0, 2827 ("pmap_remove_pde: sva is not 4mpage aligned")); 2828 oldpde = pte_load_clear(pdq); 2829 if (oldpde & PG_W) 2830 pmap->pm_stats.wired_count -= NBPDR / PAGE_SIZE; 2831 2832 /* 2833 * Machines that don't support invlpg, also don't support 2834 * PG_G. 2835 */ 2836 if (oldpde & PG_G) 2837 pmap_invalidate_page(kernel_pmap, sva); 2838 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 2839 if (oldpde & PG_MANAGED) { 2840 pvh = pa_to_pvh(oldpde & PG_PS_FRAME); 2841 pmap_pvh_free(pvh, pmap, sva); 2842 eva = sva + NBPDR; 2843 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME); 2844 va < eva; va += PAGE_SIZE, m++) { 2845 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2846 vm_page_dirty(m); 2847 if (oldpde & PG_A) 2848 vm_page_aflag_set(m, PGA_REFERENCED); 2849 if (TAILQ_EMPTY(&m->md.pv_list) && 2850 TAILQ_EMPTY(&pvh->pv_list)) 2851 vm_page_aflag_clear(m, PGA_WRITEABLE); 2852 } 2853 } 2854 if (pmap == kernel_pmap) { 2855 pmap_remove_kernel_pde(pmap, pdq, sva); 2856 } else { 2857 mpte = pmap_lookup_pt_page(pmap, sva); 2858 if (mpte != NULL) { 2859 pmap_remove_pt_page(pmap, mpte); 2860 pmap->pm_stats.resident_count--; 2861 KASSERT(mpte->wire_count == NPTEPG, 2862 ("pmap_remove_pde: pte page wire count error")); 2863 mpte->wire_count = 0; 2864 pmap_add_delayed_free_list(mpte, free, FALSE); 2865 atomic_subtract_int(&cnt.v_wire_count, 1); 2866 } 2867 } 2868} 2869 2870/* 2871 * pmap_remove_pte: do the things to unmap a page in a process 2872 */ 2873static int 2874pmap_remove_pte(pmap_t pmap, pt_entry_t *ptq, vm_offset_t va, 2875 struct spglist *free) 2876{ 2877 pt_entry_t oldpte; 2878 vm_page_t m; 2879 2880 rw_assert(&pvh_global_lock, RA_WLOCKED); 2881 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2882 oldpte = pte_load_clear(ptq); 2883 KASSERT(oldpte != 0, 2884 ("pmap_remove_pte: pmap %p va %x zero pte", pmap, va)); 2885 if (oldpte & PG_W) 2886 pmap->pm_stats.wired_count -= 1; 2887 /* 2888 * Machines that don't support invlpg, also don't support 2889 * PG_G. 2890 */ 2891 if (oldpte & PG_G) 2892 pmap_invalidate_page(kernel_pmap, va); 2893 pmap->pm_stats.resident_count -= 1; 2894 if (oldpte & PG_MANAGED) { 2895 m = PHYS_TO_VM_PAGE(oldpte & PG_FRAME); 2896 if ((oldpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 2897 vm_page_dirty(m); 2898 if (oldpte & PG_A) 2899 vm_page_aflag_set(m, PGA_REFERENCED); 2900 pmap_remove_entry(pmap, m, va); 2901 } 2902 return (pmap_unuse_pt(pmap, va, free)); 2903} 2904 2905/* 2906 * Remove a single page from a process address space 2907 */ 2908static void 2909pmap_remove_page(pmap_t pmap, vm_offset_t va, struct spglist *free) 2910{ 2911 pt_entry_t *pte; 2912 2913 rw_assert(&pvh_global_lock, RA_WLOCKED); 2914 KASSERT(curthread->td_pinned > 0, ("curthread not pinned")); 2915 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 2916 if ((pte = pmap_pte_quick(pmap, va)) == NULL || *pte == 0) 2917 return; 2918 pmap_remove_pte(pmap, pte, va, free); 2919 pmap_invalidate_page(pmap, va); 2920} 2921 2922/* 2923 * Remove the given range of addresses from the specified map. 2924 * 2925 * It is assumed that the start and end are properly 2926 * rounded to the page size. 2927 */ 2928void 2929pmap_remove(pmap_t pmap, vm_offset_t sva, vm_offset_t eva) 2930{ 2931 vm_offset_t pdnxt; 2932 pd_entry_t ptpaddr; 2933 pt_entry_t *pte; 2934 struct spglist free; 2935 int anyvalid; 2936 2937 /* 2938 * Perform an unsynchronized read. This is, however, safe. 2939 */ 2940 if (pmap->pm_stats.resident_count == 0) 2941 return; 2942 2943 anyvalid = 0; 2944 SLIST_INIT(&free); 2945 2946 rw_wlock(&pvh_global_lock); 2947 sched_pin(); 2948 PMAP_LOCK(pmap); 2949 2950 /* 2951 * special handling of removing one page. a very 2952 * common operation and easy to short circuit some 2953 * code. 2954 */ 2955 if ((sva + PAGE_SIZE == eva) && 2956 ((pmap->pm_pdir[(sva >> PDRSHIFT)] & PG_PS) == 0)) { 2957 pmap_remove_page(pmap, sva, &free); 2958 goto out; 2959 } 2960 2961 for (; sva < eva; sva = pdnxt) { 2962 u_int pdirindex; 2963 2964 /* 2965 * Calculate index for next page table. 2966 */ 2967 pdnxt = (sva + NBPDR) & ~PDRMASK; 2968 if (pdnxt < sva) 2969 pdnxt = eva; 2970 if (pmap->pm_stats.resident_count == 0) 2971 break; 2972 2973 pdirindex = sva >> PDRSHIFT; 2974 ptpaddr = pmap->pm_pdir[pdirindex]; 2975 2976 /* 2977 * Weed out invalid mappings. Note: we assume that the page 2978 * directory table is always allocated, and in kernel virtual. 2979 */ 2980 if (ptpaddr == 0) 2981 continue; 2982 2983 /* 2984 * Check for large page. 2985 */ 2986 if ((ptpaddr & PG_PS) != 0) { 2987 /* 2988 * Are we removing the entire large page? If not, 2989 * demote the mapping and fall through. 2990 */ 2991 if (sva + NBPDR == pdnxt && eva >= pdnxt) { 2992 /* 2993 * The TLB entry for a PG_G mapping is 2994 * invalidated by pmap_remove_pde(). 2995 */ 2996 if ((ptpaddr & PG_G) == 0) 2997 anyvalid = 1; 2998 pmap_remove_pde(pmap, 2999 &pmap->pm_pdir[pdirindex], sva, &free); 3000 continue; 3001 } else if (!pmap_demote_pde(pmap, 3002 &pmap->pm_pdir[pdirindex], sva)) { 3003 /* The large page mapping was destroyed. */ 3004 continue; 3005 } 3006 } 3007 3008 /* 3009 * Limit our scan to either the end of the va represented 3010 * by the current page table page, or to the end of the 3011 * range being removed. 3012 */ 3013 if (pdnxt > eva) 3014 pdnxt = eva; 3015 3016 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 3017 sva += PAGE_SIZE) { 3018 if (*pte == 0) 3019 continue; 3020 3021 /* 3022 * The TLB entry for a PG_G mapping is invalidated 3023 * by pmap_remove_pte(). 3024 */ 3025 if ((*pte & PG_G) == 0) 3026 anyvalid = 1; 3027 if (pmap_remove_pte(pmap, pte, sva, &free)) 3028 break; 3029 } 3030 } 3031out: 3032 sched_unpin(); 3033 if (anyvalid) 3034 pmap_invalidate_all(pmap); 3035 rw_wunlock(&pvh_global_lock); 3036 PMAP_UNLOCK(pmap); 3037 pmap_free_zero_pages(&free); 3038} 3039 3040/* 3041 * Routine: pmap_remove_all 3042 * Function: 3043 * Removes this physical page from 3044 * all physical maps in which it resides. 3045 * Reflects back modify bits to the pager. 3046 * 3047 * Notes: 3048 * Original versions of this routine were very 3049 * inefficient because they iteratively called 3050 * pmap_remove (slow...) 3051 */ 3052 3053void 3054pmap_remove_all(vm_page_t m) 3055{ 3056 struct md_page *pvh; 3057 pv_entry_t pv; 3058 pmap_t pmap; 3059 pt_entry_t *pte, tpte; 3060 pd_entry_t *pde; 3061 vm_offset_t va; 3062 struct spglist free; 3063 3064 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 3065 ("pmap_remove_all: page %p is not managed", m)); 3066 SLIST_INIT(&free); 3067 rw_wlock(&pvh_global_lock); 3068 sched_pin(); 3069 if ((m->flags & PG_FICTITIOUS) != 0) 3070 goto small_mappings; 3071 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 3072 while ((pv = TAILQ_FIRST(&pvh->pv_list)) != NULL) { 3073 va = pv->pv_va; 3074 pmap = PV_PMAP(pv); 3075 PMAP_LOCK(pmap); 3076 pde = pmap_pde(pmap, va); 3077 (void)pmap_demote_pde(pmap, pde, va); 3078 PMAP_UNLOCK(pmap); 3079 } 3080small_mappings: 3081 while ((pv = TAILQ_FIRST(&m->md.pv_list)) != NULL) { 3082 pmap = PV_PMAP(pv); 3083 PMAP_LOCK(pmap); 3084 pmap->pm_stats.resident_count--; 3085 pde = pmap_pde(pmap, pv->pv_va); 3086 KASSERT((*pde & PG_PS) == 0, ("pmap_remove_all: found" 3087 " a 4mpage in page %p's pv list", m)); 3088 pte = pmap_pte_quick(pmap, pv->pv_va); 3089 tpte = pte_load_clear(pte); 3090 KASSERT(tpte != 0, ("pmap_remove_all: pmap %p va %x zero pte", 3091 pmap, pv->pv_va)); 3092 if (tpte & PG_W) 3093 pmap->pm_stats.wired_count--; 3094 if (tpte & PG_A) 3095 vm_page_aflag_set(m, PGA_REFERENCED); 3096 3097 /* 3098 * Update the vm_page_t clean and reference bits. 3099 */ 3100 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 3101 vm_page_dirty(m); 3102 pmap_unuse_pt(pmap, pv->pv_va, &free); 3103 pmap_invalidate_page(pmap, pv->pv_va); 3104 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 3105 free_pv_entry(pmap, pv); 3106 PMAP_UNLOCK(pmap); 3107 } 3108 vm_page_aflag_clear(m, PGA_WRITEABLE); 3109 sched_unpin(); 3110 rw_wunlock(&pvh_global_lock); 3111 pmap_free_zero_pages(&free); 3112} 3113 3114/* 3115 * pmap_protect_pde: do the things to protect a 4mpage in a process 3116 */ 3117static boolean_t 3118pmap_protect_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t sva, vm_prot_t prot) 3119{ 3120 pd_entry_t newpde, oldpde; 3121 vm_offset_t eva, va; 3122 vm_page_t m; 3123 boolean_t anychanged; 3124 3125 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3126 KASSERT((sva & PDRMASK) == 0, 3127 ("pmap_protect_pde: sva is not 4mpage aligned")); 3128 anychanged = FALSE; 3129retry: 3130 oldpde = newpde = *pde; 3131 if (oldpde & PG_MANAGED) { 3132 eva = sva + NBPDR; 3133 for (va = sva, m = PHYS_TO_VM_PAGE(oldpde & PG_PS_FRAME); 3134 va < eva; va += PAGE_SIZE, m++) 3135 if ((oldpde & (PG_M | PG_RW)) == (PG_M | PG_RW)) 3136 vm_page_dirty(m); 3137 } 3138 if ((prot & VM_PROT_WRITE) == 0) 3139 newpde &= ~(PG_RW | PG_M); 3140#ifdef PAE 3141 if ((prot & VM_PROT_EXECUTE) == 0) 3142 newpde |= pg_nx; 3143#endif 3144 if (newpde != oldpde) { 3145 if (!pde_cmpset(pde, oldpde, newpde)) 3146 goto retry; 3147 if (oldpde & PG_G) 3148 pmap_invalidate_page(pmap, sva); 3149 else 3150 anychanged = TRUE; 3151 } 3152 return (anychanged); 3153} 3154 3155/* 3156 * Set the physical protection on the 3157 * specified range of this map as requested. 3158 */ 3159void 3160pmap_protect(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, vm_prot_t prot) 3161{ 3162 vm_offset_t pdnxt; 3163 pd_entry_t ptpaddr; 3164 pt_entry_t *pte; 3165 boolean_t anychanged, pv_lists_locked; 3166 3167 if ((prot & VM_PROT_READ) == VM_PROT_NONE) { 3168 pmap_remove(pmap, sva, eva); 3169 return; 3170 } 3171 3172#ifdef PAE 3173 if ((prot & (VM_PROT_WRITE|VM_PROT_EXECUTE)) == 3174 (VM_PROT_WRITE|VM_PROT_EXECUTE)) 3175 return; 3176#else 3177 if (prot & VM_PROT_WRITE) 3178 return; 3179#endif 3180 3181 if (pmap_is_current(pmap)) 3182 pv_lists_locked = FALSE; 3183 else { 3184 pv_lists_locked = TRUE; 3185resume: 3186 rw_wlock(&pvh_global_lock); 3187 sched_pin(); 3188 } 3189 anychanged = FALSE; 3190 3191 PMAP_LOCK(pmap); 3192 for (; sva < eva; sva = pdnxt) { 3193 pt_entry_t obits, pbits; 3194 u_int pdirindex; 3195 3196 pdnxt = (sva + NBPDR) & ~PDRMASK; 3197 if (pdnxt < sva) 3198 pdnxt = eva; 3199 3200 pdirindex = sva >> PDRSHIFT; 3201 ptpaddr = pmap->pm_pdir[pdirindex]; 3202 3203 /* 3204 * Weed out invalid mappings. Note: we assume that the page 3205 * directory table is always allocated, and in kernel virtual. 3206 */ 3207 if (ptpaddr == 0) 3208 continue; 3209 3210 /* 3211 * Check for large page. 3212 */ 3213 if ((ptpaddr & PG_PS) != 0) { 3214 /* 3215 * Are we protecting the entire large page? If not, 3216 * demote the mapping and fall through. 3217 */ 3218 if (sva + NBPDR == pdnxt && eva >= pdnxt) { 3219 /* 3220 * The TLB entry for a PG_G mapping is 3221 * invalidated by pmap_protect_pde(). 3222 */ 3223 if (pmap_protect_pde(pmap, 3224 &pmap->pm_pdir[pdirindex], sva, prot)) 3225 anychanged = TRUE; 3226 continue; 3227 } else { 3228 if (!pv_lists_locked) { 3229 pv_lists_locked = TRUE; 3230 if (!rw_try_wlock(&pvh_global_lock)) { 3231 if (anychanged) 3232 pmap_invalidate_all( 3233 pmap); 3234 PMAP_UNLOCK(pmap); 3235 goto resume; 3236 } 3237 sched_pin(); 3238 } 3239 if (!pmap_demote_pde(pmap, 3240 &pmap->pm_pdir[pdirindex], sva)) { 3241 /* 3242 * The large page mapping was 3243 * destroyed. 3244 */ 3245 continue; 3246 } 3247 } 3248 } 3249 3250 if (pdnxt > eva) 3251 pdnxt = eva; 3252 3253 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 3254 sva += PAGE_SIZE) { 3255 vm_page_t m; 3256 3257retry: 3258 /* 3259 * Regardless of whether a pte is 32 or 64 bits in 3260 * size, PG_RW, PG_A, and PG_M are among the least 3261 * significant 32 bits. 3262 */ 3263 obits = pbits = *pte; 3264 if ((pbits & PG_V) == 0) 3265 continue; 3266 3267 if ((prot & VM_PROT_WRITE) == 0) { 3268 if ((pbits & (PG_MANAGED | PG_M | PG_RW)) == 3269 (PG_MANAGED | PG_M | PG_RW)) { 3270 m = PHYS_TO_VM_PAGE(pbits & PG_FRAME); 3271 vm_page_dirty(m); 3272 } 3273 pbits &= ~(PG_RW | PG_M); 3274 } 3275#ifdef PAE 3276 if ((prot & VM_PROT_EXECUTE) == 0) 3277 pbits |= pg_nx; 3278#endif 3279 3280 if (pbits != obits) { 3281#ifdef PAE 3282 if (!atomic_cmpset_64(pte, obits, pbits)) 3283 goto retry; 3284#else 3285 if (!atomic_cmpset_int((u_int *)pte, obits, 3286 pbits)) 3287 goto retry; 3288#endif 3289 if (obits & PG_G) 3290 pmap_invalidate_page(pmap, sva); 3291 else 3292 anychanged = TRUE; 3293 } 3294 } 3295 } 3296 if (anychanged) 3297 pmap_invalidate_all(pmap); 3298 if (pv_lists_locked) { 3299 sched_unpin(); 3300 rw_wunlock(&pvh_global_lock); 3301 } 3302 PMAP_UNLOCK(pmap); 3303} 3304 3305/* 3306 * Tries to promote the 512 or 1024, contiguous 4KB page mappings that are 3307 * within a single page table page (PTP) to a single 2- or 4MB page mapping. 3308 * For promotion to occur, two conditions must be met: (1) the 4KB page 3309 * mappings must map aligned, contiguous physical memory and (2) the 4KB page 3310 * mappings must have identical characteristics. 3311 * 3312 * Managed (PG_MANAGED) mappings within the kernel address space are not 3313 * promoted. The reason is that kernel PDEs are replicated in each pmap but 3314 * pmap_clear_ptes() and pmap_ts_referenced() only read the PDE from the kernel 3315 * pmap. 3316 */ 3317static void 3318pmap_promote_pde(pmap_t pmap, pd_entry_t *pde, vm_offset_t va) 3319{ 3320 pd_entry_t newpde; 3321 pt_entry_t *firstpte, oldpte, pa, *pte; 3322 vm_offset_t oldpteva; 3323 vm_page_t mpte; 3324 3325 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3326 3327 /* 3328 * Examine the first PTE in the specified PTP. Abort if this PTE is 3329 * either invalid, unused, or does not map the first 4KB physical page 3330 * within a 2- or 4MB page. 3331 */ 3332 firstpte = pmap_pte_quick(pmap, trunc_4mpage(va)); 3333setpde: 3334 newpde = *firstpte; 3335 if ((newpde & ((PG_FRAME & PDRMASK) | PG_A | PG_V)) != (PG_A | PG_V)) { 3336 pmap_pde_p_failures++; 3337 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3338 " in pmap %p", va, pmap); 3339 return; 3340 } 3341 if ((*firstpte & PG_MANAGED) != 0 && pmap == kernel_pmap) { 3342 pmap_pde_p_failures++; 3343 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3344 " in pmap %p", va, pmap); 3345 return; 3346 } 3347 if ((newpde & (PG_M | PG_RW)) == PG_RW) { 3348 /* 3349 * When PG_M is already clear, PG_RW can be cleared without 3350 * a TLB invalidation. 3351 */ 3352 if (!atomic_cmpset_int((u_int *)firstpte, newpde, newpde & 3353 ~PG_RW)) 3354 goto setpde; 3355 newpde &= ~PG_RW; 3356 } 3357 3358 /* 3359 * Examine each of the other PTEs in the specified PTP. Abort if this 3360 * PTE maps an unexpected 4KB physical page or does not have identical 3361 * characteristics to the first PTE. 3362 */ 3363 pa = (newpde & (PG_PS_FRAME | PG_A | PG_V)) + NBPDR - PAGE_SIZE; 3364 for (pte = firstpte + NPTEPG - 1; pte > firstpte; pte--) { 3365setpte: 3366 oldpte = *pte; 3367 if ((oldpte & (PG_FRAME | PG_A | PG_V)) != pa) { 3368 pmap_pde_p_failures++; 3369 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3370 " in pmap %p", va, pmap); 3371 return; 3372 } 3373 if ((oldpte & (PG_M | PG_RW)) == PG_RW) { 3374 /* 3375 * When PG_M is already clear, PG_RW can be cleared 3376 * without a TLB invalidation. 3377 */ 3378 if (!atomic_cmpset_int((u_int *)pte, oldpte, 3379 oldpte & ~PG_RW)) 3380 goto setpte; 3381 oldpte &= ~PG_RW; 3382 oldpteva = (oldpte & PG_FRAME & PDRMASK) | 3383 (va & ~PDRMASK); 3384 CTR2(KTR_PMAP, "pmap_promote_pde: protect for va %#x" 3385 " in pmap %p", oldpteva, pmap); 3386 } 3387 if ((oldpte & PG_PTE_PROMOTE) != (newpde & PG_PTE_PROMOTE)) { 3388 pmap_pde_p_failures++; 3389 CTR2(KTR_PMAP, "pmap_promote_pde: failure for va %#x" 3390 " in pmap %p", va, pmap); 3391 return; 3392 } 3393 pa -= PAGE_SIZE; 3394 } 3395 3396 /* 3397 * Save the page table page in its current state until the PDE 3398 * mapping the superpage is demoted by pmap_demote_pde() or 3399 * destroyed by pmap_remove_pde(). 3400 */ 3401 mpte = PHYS_TO_VM_PAGE(*pde & PG_FRAME); 3402 KASSERT(mpte >= vm_page_array && 3403 mpte < &vm_page_array[vm_page_array_size], 3404 ("pmap_promote_pde: page table page is out of range")); 3405 KASSERT(mpte->pindex == va >> PDRSHIFT, 3406 ("pmap_promote_pde: page table page's pindex is wrong")); 3407 if (pmap_insert_pt_page(pmap, mpte)) { 3408 pmap_pde_p_failures++; 3409 CTR2(KTR_PMAP, 3410 "pmap_promote_pde: failure for va %#x in pmap %p", va, 3411 pmap); 3412 return; 3413 } 3414 3415 /* 3416 * Promote the pv entries. 3417 */ 3418 if ((newpde & PG_MANAGED) != 0) 3419 pmap_pv_promote_pde(pmap, va, newpde & PG_PS_FRAME); 3420 3421 /* 3422 * Propagate the PAT index to its proper position. 3423 */ 3424 if ((newpde & PG_PTE_PAT) != 0) 3425 newpde ^= PG_PDE_PAT | PG_PTE_PAT; 3426 3427 /* 3428 * Map the superpage. 3429 */ 3430 if (workaround_erratum383) 3431 pmap_update_pde(pmap, va, pde, PG_PS | newpde); 3432 else if (pmap == kernel_pmap) 3433 pmap_kenter_pde(va, PG_PS | newpde); 3434 else 3435 pde_store(pde, PG_PS | newpde); 3436 3437 pmap_pde_promotions++; 3438 CTR2(KTR_PMAP, "pmap_promote_pde: success for va %#x" 3439 " in pmap %p", va, pmap); 3440} 3441 3442/* 3443 * Insert the given physical page (p) at 3444 * the specified virtual address (v) in the 3445 * target physical map with the protection requested. 3446 * 3447 * If specified, the page will be wired down, meaning 3448 * that the related pte can not be reclaimed. 3449 * 3450 * NB: This is the only routine which MAY NOT lazy-evaluate 3451 * or lose information. That is, this routine must actually 3452 * insert this page into the given map NOW. 3453 */ 3454void 3455pmap_enter(pmap_t pmap, vm_offset_t va, vm_prot_t access, vm_page_t m, 3456 vm_prot_t prot, boolean_t wired) 3457{ 3458 pd_entry_t *pde; 3459 pt_entry_t *pte; 3460 pt_entry_t newpte, origpte; 3461 pv_entry_t pv; 3462 vm_paddr_t opa, pa; 3463 vm_page_t mpte, om; 3464 boolean_t invlva; 3465 3466 va = trunc_page(va); 3467 KASSERT(va <= VM_MAX_KERNEL_ADDRESS, ("pmap_enter: toobig")); 3468 KASSERT(va < UPT_MIN_ADDRESS || va >= UPT_MAX_ADDRESS, 3469 ("pmap_enter: invalid to pmap_enter page table pages (va: 0x%x)", 3470 va)); 3471 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m)) 3472 VM_OBJECT_ASSERT_WLOCKED(m->object); 3473 3474 mpte = NULL; 3475 3476 rw_wlock(&pvh_global_lock); 3477 PMAP_LOCK(pmap); 3478 sched_pin(); 3479 3480 /* 3481 * In the case that a page table page is not 3482 * resident, we are creating it here. 3483 */ 3484 if (va < VM_MAXUSER_ADDRESS) { 3485 mpte = pmap_allocpte(pmap, va, M_WAITOK); 3486 } 3487 3488 pde = pmap_pde(pmap, va); 3489 if ((*pde & PG_PS) != 0) 3490 panic("pmap_enter: attempted pmap_enter on 4MB page"); 3491 pte = pmap_pte_quick(pmap, va); 3492 3493 /* 3494 * Page Directory table entry not valid, we need a new PT page 3495 */ 3496 if (pte == NULL) { 3497 panic("pmap_enter: invalid page directory pdir=%#jx, va=%#x", 3498 (uintmax_t)pmap->pm_pdir[PTDPTDI], va); 3499 } 3500 3501 pa = VM_PAGE_TO_PHYS(m); 3502 om = NULL; 3503 origpte = *pte; 3504 opa = origpte & PG_FRAME; 3505 3506 /* 3507 * Mapping has not changed, must be protection or wiring change. 3508 */ 3509 if (origpte && (opa == pa)) { 3510 /* 3511 * Wiring change, just update stats. We don't worry about 3512 * wiring PT pages as they remain resident as long as there 3513 * are valid mappings in them. Hence, if a user page is wired, 3514 * the PT page will be also. 3515 */ 3516 if (wired && ((origpte & PG_W) == 0)) 3517 pmap->pm_stats.wired_count++; 3518 else if (!wired && (origpte & PG_W)) 3519 pmap->pm_stats.wired_count--; 3520 3521 /* 3522 * Remove extra pte reference 3523 */ 3524 if (mpte) 3525 mpte->wire_count--; 3526 3527 if (origpte & PG_MANAGED) { 3528 om = m; 3529 pa |= PG_MANAGED; 3530 } 3531 goto validate; 3532 } 3533 3534 pv = NULL; 3535 3536 /* 3537 * Mapping has changed, invalidate old range and fall through to 3538 * handle validating new mapping. 3539 */ 3540 if (opa) { 3541 if (origpte & PG_W) 3542 pmap->pm_stats.wired_count--; 3543 if (origpte & PG_MANAGED) { 3544 om = PHYS_TO_VM_PAGE(opa); 3545 pv = pmap_pvh_remove(&om->md, pmap, va); 3546 } 3547 if (mpte != NULL) { 3548 mpte->wire_count--; 3549 KASSERT(mpte->wire_count > 0, 3550 ("pmap_enter: missing reference to page table page," 3551 " va: 0x%x", va)); 3552 } 3553 } else 3554 pmap->pm_stats.resident_count++; 3555 3556 /* 3557 * Enter on the PV list if part of our managed memory. 3558 */ 3559 if ((m->oflags & VPO_UNMANAGED) == 0) { 3560 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva, 3561 ("pmap_enter: managed mapping within the clean submap")); 3562 if (pv == NULL) 3563 pv = get_pv_entry(pmap, FALSE); 3564 pv->pv_va = va; 3565 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 3566 pa |= PG_MANAGED; 3567 } else if (pv != NULL) 3568 free_pv_entry(pmap, pv); 3569 3570 /* 3571 * Increment counters 3572 */ 3573 if (wired) 3574 pmap->pm_stats.wired_count++; 3575 3576validate: 3577 /* 3578 * Now validate mapping with desired protection/wiring. 3579 */ 3580 newpte = (pt_entry_t)(pa | pmap_cache_bits(m->md.pat_mode, 0) | PG_V); 3581 if ((prot & VM_PROT_WRITE) != 0) { 3582 newpte |= PG_RW; 3583 if ((newpte & PG_MANAGED) != 0) 3584 vm_page_aflag_set(m, PGA_WRITEABLE); 3585 } 3586#ifdef PAE 3587 if ((prot & VM_PROT_EXECUTE) == 0) 3588 newpte |= pg_nx; 3589#endif 3590 if (wired) 3591 newpte |= PG_W; 3592 if (va < VM_MAXUSER_ADDRESS) 3593 newpte |= PG_U; 3594 if (pmap == kernel_pmap) 3595 newpte |= pgeflag; 3596 3597 /* 3598 * if the mapping or permission bits are different, we need 3599 * to update the pte. 3600 */ 3601 if ((origpte & ~(PG_M|PG_A)) != newpte) { 3602 newpte |= PG_A; 3603 if ((access & VM_PROT_WRITE) != 0) 3604 newpte |= PG_M; 3605 if (origpte & PG_V) { 3606 invlva = FALSE; 3607 origpte = pte_load_store(pte, newpte); 3608 if (origpte & PG_A) { 3609 if (origpte & PG_MANAGED) 3610 vm_page_aflag_set(om, PGA_REFERENCED); 3611 if (opa != VM_PAGE_TO_PHYS(m)) 3612 invlva = TRUE; 3613#ifdef PAE 3614 if ((origpte & PG_NX) == 0 && 3615 (newpte & PG_NX) != 0) 3616 invlva = TRUE; 3617#endif 3618 } 3619 if ((origpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 3620 if ((origpte & PG_MANAGED) != 0) 3621 vm_page_dirty(om); 3622 if ((prot & VM_PROT_WRITE) == 0) 3623 invlva = TRUE; 3624 } 3625 if ((origpte & PG_MANAGED) != 0 && 3626 TAILQ_EMPTY(&om->md.pv_list) && 3627 ((om->flags & PG_FICTITIOUS) != 0 || 3628 TAILQ_EMPTY(&pa_to_pvh(opa)->pv_list))) 3629 vm_page_aflag_clear(om, PGA_WRITEABLE); 3630 if (invlva) 3631 pmap_invalidate_page(pmap, va); 3632 } else 3633 pte_store(pte, newpte); 3634 } 3635 3636 /* 3637 * If both the page table page and the reservation are fully 3638 * populated, then attempt promotion. 3639 */ 3640 if ((mpte == NULL || mpte->wire_count == NPTEPG) && 3641 pg_ps_enabled && (m->flags & PG_FICTITIOUS) == 0 && 3642 vm_reserv_level_iffullpop(m) == 0) 3643 pmap_promote_pde(pmap, pde, va); 3644 3645 sched_unpin(); 3646 rw_wunlock(&pvh_global_lock); 3647 PMAP_UNLOCK(pmap); 3648} 3649 3650/* 3651 * Tries to create a 2- or 4MB page mapping. Returns TRUE if successful and 3652 * FALSE otherwise. Fails if (1) a page table page cannot be allocated without 3653 * blocking, (2) a mapping already exists at the specified virtual address, or 3654 * (3) a pv entry cannot be allocated without reclaiming another pv entry. 3655 */ 3656static boolean_t 3657pmap_enter_pde(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 3658{ 3659 pd_entry_t *pde, newpde; 3660 3661 rw_assert(&pvh_global_lock, RA_WLOCKED); 3662 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3663 pde = pmap_pde(pmap, va); 3664 if (*pde != 0) { 3665 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx" 3666 " in pmap %p", va, pmap); 3667 return (FALSE); 3668 } 3669 newpde = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 1) | 3670 PG_PS | PG_V; 3671 if ((m->oflags & VPO_UNMANAGED) == 0) { 3672 newpde |= PG_MANAGED; 3673 3674 /* 3675 * Abort this mapping if its PV entry could not be created. 3676 */ 3677 if (!pmap_pv_insert_pde(pmap, va, VM_PAGE_TO_PHYS(m))) { 3678 CTR2(KTR_PMAP, "pmap_enter_pde: failure for va %#lx" 3679 " in pmap %p", va, pmap); 3680 return (FALSE); 3681 } 3682 } 3683#ifdef PAE 3684 if ((prot & VM_PROT_EXECUTE) == 0) 3685 newpde |= pg_nx; 3686#endif 3687 if (va < VM_MAXUSER_ADDRESS) 3688 newpde |= PG_U; 3689 3690 /* 3691 * Increment counters. 3692 */ 3693 pmap->pm_stats.resident_count += NBPDR / PAGE_SIZE; 3694 3695 /* 3696 * Map the superpage. 3697 */ 3698 pde_store(pde, newpde); 3699 3700 pmap_pde_mappings++; 3701 CTR2(KTR_PMAP, "pmap_enter_pde: success for va %#lx" 3702 " in pmap %p", va, pmap); 3703 return (TRUE); 3704} 3705 3706/* 3707 * Maps a sequence of resident pages belonging to the same object. 3708 * The sequence begins with the given page m_start. This page is 3709 * mapped at the given virtual address start. Each subsequent page is 3710 * mapped at a virtual address that is offset from start by the same 3711 * amount as the page is offset from m_start within the object. The 3712 * last page in the sequence is the page with the largest offset from 3713 * m_start that can be mapped at a virtual address less than the given 3714 * virtual address end. Not every virtual page between start and end 3715 * is mapped; only those for which a resident page exists with the 3716 * corresponding offset from m_start are mapped. 3717 */ 3718void 3719pmap_enter_object(pmap_t pmap, vm_offset_t start, vm_offset_t end, 3720 vm_page_t m_start, vm_prot_t prot) 3721{ 3722 vm_offset_t va; 3723 vm_page_t m, mpte; 3724 vm_pindex_t diff, psize; 3725 3726 VM_OBJECT_ASSERT_LOCKED(m_start->object); 3727 3728 psize = atop(end - start); 3729 mpte = NULL; 3730 m = m_start; 3731 rw_wlock(&pvh_global_lock); 3732 PMAP_LOCK(pmap); 3733 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) { 3734 va = start + ptoa(diff); 3735 if ((va & PDRMASK) == 0 && va + NBPDR <= end && 3736 (VM_PAGE_TO_PHYS(m) & PDRMASK) == 0 && 3737 pg_ps_enabled && vm_reserv_level_iffullpop(m) == 0 && 3738 pmap_enter_pde(pmap, va, m, prot)) 3739 m = &m[NBPDR / PAGE_SIZE - 1]; 3740 else 3741 mpte = pmap_enter_quick_locked(pmap, va, m, prot, 3742 mpte); 3743 m = TAILQ_NEXT(m, listq); 3744 } 3745 rw_wunlock(&pvh_global_lock); 3746 PMAP_UNLOCK(pmap); 3747} 3748 3749/* 3750 * this code makes some *MAJOR* assumptions: 3751 * 1. Current pmap & pmap exists. 3752 * 2. Not wired. 3753 * 3. Read access. 3754 * 4. No page table pages. 3755 * but is *MUCH* faster than pmap_enter... 3756 */ 3757 3758void 3759pmap_enter_quick(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot) 3760{ 3761 3762 rw_wlock(&pvh_global_lock); 3763 PMAP_LOCK(pmap); 3764 (void)pmap_enter_quick_locked(pmap, va, m, prot, NULL); 3765 rw_wunlock(&pvh_global_lock); 3766 PMAP_UNLOCK(pmap); 3767} 3768 3769static vm_page_t 3770pmap_enter_quick_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, 3771 vm_prot_t prot, vm_page_t mpte) 3772{ 3773 pt_entry_t *pte; 3774 vm_paddr_t pa; 3775 struct spglist free; 3776 3777 KASSERT(va < kmi.clean_sva || va >= kmi.clean_eva || 3778 (m->oflags & VPO_UNMANAGED) != 0, 3779 ("pmap_enter_quick_locked: managed mapping within the clean submap")); 3780 rw_assert(&pvh_global_lock, RA_WLOCKED); 3781 PMAP_LOCK_ASSERT(pmap, MA_OWNED); 3782 3783 /* 3784 * In the case that a page table page is not 3785 * resident, we are creating it here. 3786 */ 3787 if (va < VM_MAXUSER_ADDRESS) { 3788 u_int ptepindex; 3789 pd_entry_t ptepa; 3790 3791 /* 3792 * Calculate pagetable page index 3793 */ 3794 ptepindex = va >> PDRSHIFT; 3795 if (mpte && (mpte->pindex == ptepindex)) { 3796 mpte->wire_count++; 3797 } else { 3798 /* 3799 * Get the page directory entry 3800 */ 3801 ptepa = pmap->pm_pdir[ptepindex]; 3802 3803 /* 3804 * If the page table page is mapped, we just increment 3805 * the hold count, and activate it. 3806 */ 3807 if (ptepa) { 3808 if (ptepa & PG_PS) 3809 return (NULL); 3810 mpte = PHYS_TO_VM_PAGE(ptepa & PG_FRAME); 3811 mpte->wire_count++; 3812 } else { 3813 mpte = _pmap_allocpte(pmap, ptepindex, 3814 M_NOWAIT); 3815 if (mpte == NULL) 3816 return (mpte); 3817 } 3818 } 3819 } else { 3820 mpte = NULL; 3821 } 3822 3823 /* 3824 * This call to vtopte makes the assumption that we are 3825 * entering the page into the current pmap. In order to support 3826 * quick entry into any pmap, one would likely use pmap_pte_quick. 3827 * But that isn't as quick as vtopte. 3828 */ 3829 pte = vtopte(va); 3830 if (*pte) { 3831 if (mpte != NULL) { 3832 mpte->wire_count--; 3833 mpte = NULL; 3834 } 3835 return (mpte); 3836 } 3837 3838 /* 3839 * Enter on the PV list if part of our managed memory. 3840 */ 3841 if ((m->oflags & VPO_UNMANAGED) == 0 && 3842 !pmap_try_insert_pv_entry(pmap, va, m)) { 3843 if (mpte != NULL) { 3844 SLIST_INIT(&free); 3845 if (pmap_unwire_ptp(pmap, mpte, &free)) { 3846 pmap_invalidate_page(pmap, va); 3847 pmap_free_zero_pages(&free); 3848 } 3849 3850 mpte = NULL; 3851 } 3852 return (mpte); 3853 } 3854 3855 /* 3856 * Increment counters 3857 */ 3858 pmap->pm_stats.resident_count++; 3859 3860 pa = VM_PAGE_TO_PHYS(m) | pmap_cache_bits(m->md.pat_mode, 0); 3861#ifdef PAE 3862 if ((prot & VM_PROT_EXECUTE) == 0) 3863 pa |= pg_nx; 3864#endif 3865 3866 /* 3867 * Now validate mapping with RO protection 3868 */ 3869 if ((m->oflags & VPO_UNMANAGED) != 0) 3870 pte_store(pte, pa | PG_V | PG_U); 3871 else 3872 pte_store(pte, pa | PG_V | PG_U | PG_MANAGED); 3873 return (mpte); 3874} 3875 3876/* 3877 * Make a temporary mapping for a physical address. This is only intended 3878 * to be used for panic dumps. 3879 */ 3880void * 3881pmap_kenter_temporary(vm_paddr_t pa, int i) 3882{ 3883 vm_offset_t va; 3884 3885 va = (vm_offset_t)crashdumpmap + (i * PAGE_SIZE); 3886 pmap_kenter(va, pa); 3887 invlpg(va); 3888 return ((void *)crashdumpmap); 3889} 3890 3891/* 3892 * This code maps large physical mmap regions into the 3893 * processor address space. Note that some shortcuts 3894 * are taken, but the code works. 3895 */ 3896void 3897pmap_object_init_pt(pmap_t pmap, vm_offset_t addr, vm_object_t object, 3898 vm_pindex_t pindex, vm_size_t size) 3899{ 3900 pd_entry_t *pde; 3901 vm_paddr_t pa, ptepa; 3902 vm_page_t p; 3903 int pat_mode; 3904 3905 VM_OBJECT_ASSERT_WLOCKED(object); 3906 KASSERT(object->type == OBJT_DEVICE || object->type == OBJT_SG, 3907 ("pmap_object_init_pt: non-device object")); 3908 if (pseflag && 3909 (addr & (NBPDR - 1)) == 0 && (size & (NBPDR - 1)) == 0) { 3910 if (!vm_object_populate(object, pindex, pindex + atop(size))) 3911 return; 3912 p = vm_page_lookup(object, pindex); 3913 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3914 ("pmap_object_init_pt: invalid page %p", p)); 3915 pat_mode = p->md.pat_mode; 3916 3917 /* 3918 * Abort the mapping if the first page is not physically 3919 * aligned to a 2/4MB page boundary. 3920 */ 3921 ptepa = VM_PAGE_TO_PHYS(p); 3922 if (ptepa & (NBPDR - 1)) 3923 return; 3924 3925 /* 3926 * Skip the first page. Abort the mapping if the rest of 3927 * the pages are not physically contiguous or have differing 3928 * memory attributes. 3929 */ 3930 p = TAILQ_NEXT(p, listq); 3931 for (pa = ptepa + PAGE_SIZE; pa < ptepa + size; 3932 pa += PAGE_SIZE) { 3933 KASSERT(p->valid == VM_PAGE_BITS_ALL, 3934 ("pmap_object_init_pt: invalid page %p", p)); 3935 if (pa != VM_PAGE_TO_PHYS(p) || 3936 pat_mode != p->md.pat_mode) 3937 return; 3938 p = TAILQ_NEXT(p, listq); 3939 } 3940 3941 /* 3942 * Map using 2/4MB pages. Since "ptepa" is 2/4M aligned and 3943 * "size" is a multiple of 2/4M, adding the PAT setting to 3944 * "pa" will not affect the termination of this loop. 3945 */ 3946 PMAP_LOCK(pmap); 3947 for (pa = ptepa | pmap_cache_bits(pat_mode, 1); pa < ptepa + 3948 size; pa += NBPDR) { 3949 pde = pmap_pde(pmap, addr); 3950 if (*pde == 0) { 3951 pde_store(pde, pa | PG_PS | PG_M | PG_A | 3952 PG_U | PG_RW | PG_V); 3953 pmap->pm_stats.resident_count += NBPDR / 3954 PAGE_SIZE; 3955 pmap_pde_mappings++; 3956 } 3957 /* Else continue on if the PDE is already valid. */ 3958 addr += NBPDR; 3959 } 3960 PMAP_UNLOCK(pmap); 3961 } 3962} 3963 3964/* 3965 * Routine: pmap_change_wiring 3966 * Function: Change the wiring attribute for a map/virtual-address 3967 * pair. 3968 * In/out conditions: 3969 * The mapping must already exist in the pmap. 3970 */ 3971void 3972pmap_change_wiring(pmap_t pmap, vm_offset_t va, boolean_t wired) 3973{ 3974 pd_entry_t *pde; 3975 pt_entry_t *pte; 3976 boolean_t are_queues_locked; 3977 3978 are_queues_locked = FALSE; 3979retry: 3980 PMAP_LOCK(pmap); 3981 pde = pmap_pde(pmap, va); 3982 if ((*pde & PG_PS) != 0) { 3983 if (!wired != ((*pde & PG_W) == 0)) { 3984 if (!are_queues_locked) { 3985 are_queues_locked = TRUE; 3986 if (!rw_try_wlock(&pvh_global_lock)) { 3987 PMAP_UNLOCK(pmap); 3988 rw_wlock(&pvh_global_lock); 3989 goto retry; 3990 } 3991 } 3992 if (!pmap_demote_pde(pmap, pde, va)) 3993 panic("pmap_change_wiring: demotion failed"); 3994 } else 3995 goto out; 3996 } 3997 pte = pmap_pte(pmap, va); 3998 3999 if (wired && !pmap_pte_w(pte)) 4000 pmap->pm_stats.wired_count++; 4001 else if (!wired && pmap_pte_w(pte)) 4002 pmap->pm_stats.wired_count--; 4003 4004 /* 4005 * Wiring is not a hardware characteristic so there is no need to 4006 * invalidate TLB. 4007 */ 4008 pmap_pte_set_w(pte, wired); 4009 pmap_pte_release(pte); 4010out: 4011 if (are_queues_locked) 4012 rw_wunlock(&pvh_global_lock); 4013 PMAP_UNLOCK(pmap); 4014} 4015 4016 4017 4018/* 4019 * Copy the range specified by src_addr/len 4020 * from the source map to the range dst_addr/len 4021 * in the destination map. 4022 * 4023 * This routine is only advisory and need not do anything. 4024 */ 4025 4026void 4027pmap_copy(pmap_t dst_pmap, pmap_t src_pmap, vm_offset_t dst_addr, vm_size_t len, 4028 vm_offset_t src_addr) 4029{ 4030 struct spglist free; 4031 vm_offset_t addr; 4032 vm_offset_t end_addr = src_addr + len; 4033 vm_offset_t pdnxt; 4034 4035 if (dst_addr != src_addr) 4036 return; 4037 4038 if (!pmap_is_current(src_pmap)) 4039 return; 4040 4041 rw_wlock(&pvh_global_lock); 4042 if (dst_pmap < src_pmap) { 4043 PMAP_LOCK(dst_pmap); 4044 PMAP_LOCK(src_pmap); 4045 } else { 4046 PMAP_LOCK(src_pmap); 4047 PMAP_LOCK(dst_pmap); 4048 } 4049 sched_pin(); 4050 for (addr = src_addr; addr < end_addr; addr = pdnxt) { 4051 pt_entry_t *src_pte, *dst_pte; 4052 vm_page_t dstmpte, srcmpte; 4053 pd_entry_t srcptepaddr; 4054 u_int ptepindex; 4055 4056 KASSERT(addr < UPT_MIN_ADDRESS, 4057 ("pmap_copy: invalid to pmap_copy page tables")); 4058 4059 pdnxt = (addr + NBPDR) & ~PDRMASK; 4060 if (pdnxt < addr) 4061 pdnxt = end_addr; 4062 ptepindex = addr >> PDRSHIFT; 4063 4064 srcptepaddr = src_pmap->pm_pdir[ptepindex]; 4065 if (srcptepaddr == 0) 4066 continue; 4067 4068 if (srcptepaddr & PG_PS) { 4069 if ((addr & PDRMASK) != 0 || addr + NBPDR > end_addr) 4070 continue; 4071 if (dst_pmap->pm_pdir[ptepindex] == 0 && 4072 ((srcptepaddr & PG_MANAGED) == 0 || 4073 pmap_pv_insert_pde(dst_pmap, addr, srcptepaddr & 4074 PG_PS_FRAME))) { 4075 dst_pmap->pm_pdir[ptepindex] = srcptepaddr & 4076 ~PG_W; 4077 dst_pmap->pm_stats.resident_count += 4078 NBPDR / PAGE_SIZE; 4079 } 4080 continue; 4081 } 4082 4083 srcmpte = PHYS_TO_VM_PAGE(srcptepaddr & PG_FRAME); 4084 KASSERT(srcmpte->wire_count > 0, 4085 ("pmap_copy: source page table page is unused")); 4086 4087 if (pdnxt > end_addr) 4088 pdnxt = end_addr; 4089 4090 src_pte = vtopte(addr); 4091 while (addr < pdnxt) { 4092 pt_entry_t ptetemp; 4093 ptetemp = *src_pte; 4094 /* 4095 * we only virtual copy managed pages 4096 */ 4097 if ((ptetemp & PG_MANAGED) != 0) { 4098 dstmpte = pmap_allocpte(dst_pmap, addr, 4099 M_NOWAIT); 4100 if (dstmpte == NULL) 4101 goto out; 4102 dst_pte = pmap_pte_quick(dst_pmap, addr); 4103 if (*dst_pte == 0 && 4104 pmap_try_insert_pv_entry(dst_pmap, addr, 4105 PHYS_TO_VM_PAGE(ptetemp & PG_FRAME))) { 4106 /* 4107 * Clear the wired, modified, and 4108 * accessed (referenced) bits 4109 * during the copy. 4110 */ 4111 *dst_pte = ptetemp & ~(PG_W | PG_M | 4112 PG_A); 4113 dst_pmap->pm_stats.resident_count++; 4114 } else { 4115 SLIST_INIT(&free); 4116 if (pmap_unwire_ptp(dst_pmap, dstmpte, 4117 &free)) { 4118 pmap_invalidate_page(dst_pmap, 4119 addr); 4120 pmap_free_zero_pages(&free); 4121 } 4122 goto out; 4123 } 4124 if (dstmpte->wire_count >= srcmpte->wire_count) 4125 break; 4126 } 4127 addr += PAGE_SIZE; 4128 src_pte++; 4129 } 4130 } 4131out: 4132 sched_unpin(); 4133 rw_wunlock(&pvh_global_lock); 4134 PMAP_UNLOCK(src_pmap); 4135 PMAP_UNLOCK(dst_pmap); 4136} 4137 4138static __inline void 4139pagezero(void *page) 4140{ 4141#if defined(I686_CPU) 4142 if (cpu_class == CPUCLASS_686) { 4143#if defined(CPU_ENABLE_SSE) 4144 if (cpu_feature & CPUID_SSE2) 4145 sse2_pagezero(page); 4146 else 4147#endif 4148 i686_pagezero(page); 4149 } else 4150#endif 4151 bzero(page, PAGE_SIZE); 4152} 4153 4154/* 4155 * pmap_zero_page zeros the specified hardware page by mapping 4156 * the page into KVM and using bzero to clear its contents. 4157 */ 4158void 4159pmap_zero_page(vm_page_t m) 4160{ 4161 struct sysmaps *sysmaps; 4162 4163 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 4164 mtx_lock(&sysmaps->lock); 4165 if (*sysmaps->CMAP2) 4166 panic("pmap_zero_page: CMAP2 busy"); 4167 sched_pin(); 4168 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M | 4169 pmap_cache_bits(m->md.pat_mode, 0); 4170 invlcaddr(sysmaps->CADDR2); 4171 pagezero(sysmaps->CADDR2); 4172 *sysmaps->CMAP2 = 0; 4173 sched_unpin(); 4174 mtx_unlock(&sysmaps->lock); 4175} 4176 4177/* 4178 * pmap_zero_page_area zeros the specified hardware page by mapping 4179 * the page into KVM and using bzero to clear its contents. 4180 * 4181 * off and size may not cover an area beyond a single hardware page. 4182 */ 4183void 4184pmap_zero_page_area(vm_page_t m, int off, int size) 4185{ 4186 struct sysmaps *sysmaps; 4187 4188 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 4189 mtx_lock(&sysmaps->lock); 4190 if (*sysmaps->CMAP2) 4191 panic("pmap_zero_page_area: CMAP2 busy"); 4192 sched_pin(); 4193 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M | 4194 pmap_cache_bits(m->md.pat_mode, 0); 4195 invlcaddr(sysmaps->CADDR2); 4196 if (off == 0 && size == PAGE_SIZE) 4197 pagezero(sysmaps->CADDR2); 4198 else 4199 bzero((char *)sysmaps->CADDR2 + off, size); 4200 *sysmaps->CMAP2 = 0; 4201 sched_unpin(); 4202 mtx_unlock(&sysmaps->lock); 4203} 4204 4205/* 4206 * pmap_zero_page_idle zeros the specified hardware page by mapping 4207 * the page into KVM and using bzero to clear its contents. This 4208 * is intended to be called from the vm_pagezero process only and 4209 * outside of Giant. 4210 */ 4211void 4212pmap_zero_page_idle(vm_page_t m) 4213{ 4214 4215 if (*CMAP3) 4216 panic("pmap_zero_page_idle: CMAP3 busy"); 4217 sched_pin(); 4218 *CMAP3 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | PG_A | PG_M | 4219 pmap_cache_bits(m->md.pat_mode, 0); 4220 invlcaddr(CADDR3); 4221 pagezero(CADDR3); 4222 *CMAP3 = 0; 4223 sched_unpin(); 4224} 4225 4226/* 4227 * pmap_copy_page copies the specified (machine independent) 4228 * page by mapping the page into virtual memory and using 4229 * bcopy to copy the page, one machine dependent page at a 4230 * time. 4231 */ 4232void 4233pmap_copy_page(vm_page_t src, vm_page_t dst) 4234{ 4235 struct sysmaps *sysmaps; 4236 4237 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 4238 mtx_lock(&sysmaps->lock); 4239 if (*sysmaps->CMAP1) 4240 panic("pmap_copy_page: CMAP1 busy"); 4241 if (*sysmaps->CMAP2) 4242 panic("pmap_copy_page: CMAP2 busy"); 4243 sched_pin(); 4244 invlpg((u_int)sysmaps->CADDR1); 4245 invlpg((u_int)sysmaps->CADDR2); 4246 *sysmaps->CMAP1 = PG_V | VM_PAGE_TO_PHYS(src) | PG_A | 4247 pmap_cache_bits(src->md.pat_mode, 0); 4248 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(dst) | PG_A | PG_M | 4249 pmap_cache_bits(dst->md.pat_mode, 0); 4250 bcopy(sysmaps->CADDR1, sysmaps->CADDR2, PAGE_SIZE); 4251 *sysmaps->CMAP1 = 0; 4252 *sysmaps->CMAP2 = 0; 4253 sched_unpin(); 4254 mtx_unlock(&sysmaps->lock); 4255} 4256 4257int unmapped_buf_allowed = 1; 4258 4259void 4260pmap_copy_pages(vm_page_t ma[], vm_offset_t a_offset, vm_page_t mb[], 4261 vm_offset_t b_offset, int xfersize) 4262{ 4263 struct sysmaps *sysmaps; 4264 vm_page_t a_pg, b_pg; 4265 char *a_cp, *b_cp; 4266 vm_offset_t a_pg_offset, b_pg_offset; 4267 int cnt; 4268 4269 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 4270 mtx_lock(&sysmaps->lock); 4271 if (*sysmaps->CMAP1 != 0) 4272 panic("pmap_copy_pages: CMAP1 busy"); 4273 if (*sysmaps->CMAP2 != 0) 4274 panic("pmap_copy_pages: CMAP2 busy"); 4275 sched_pin(); 4276 while (xfersize > 0) { 4277 invlpg((u_int)sysmaps->CADDR1); 4278 invlpg((u_int)sysmaps->CADDR2); 4279 a_pg = ma[a_offset >> PAGE_SHIFT]; 4280 a_pg_offset = a_offset & PAGE_MASK; 4281 cnt = min(xfersize, PAGE_SIZE - a_pg_offset); 4282 b_pg = mb[b_offset >> PAGE_SHIFT]; 4283 b_pg_offset = b_offset & PAGE_MASK; 4284 cnt = min(cnt, PAGE_SIZE - b_pg_offset); 4285 *sysmaps->CMAP1 = PG_V | VM_PAGE_TO_PHYS(a_pg) | PG_A | 4286 pmap_cache_bits(b_pg->md.pat_mode, 0); 4287 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(b_pg) | PG_A | 4288 PG_M | pmap_cache_bits(b_pg->md.pat_mode, 0); 4289 a_cp = sysmaps->CADDR1 + a_pg_offset; 4290 b_cp = sysmaps->CADDR2 + b_pg_offset; 4291 bcopy(a_cp, b_cp, cnt); 4292 a_offset += cnt; 4293 b_offset += cnt; 4294 xfersize -= cnt; 4295 } 4296 *sysmaps->CMAP1 = 0; 4297 *sysmaps->CMAP2 = 0; 4298 sched_unpin(); 4299 mtx_unlock(&sysmaps->lock); 4300} 4301 4302/* 4303 * Returns true if the pmap's pv is one of the first 4304 * 16 pvs linked to from this page. This count may 4305 * be changed upwards or downwards in the future; it 4306 * is only necessary that true be returned for a small 4307 * subset of pmaps for proper page aging. 4308 */ 4309boolean_t 4310pmap_page_exists_quick(pmap_t pmap, vm_page_t m) 4311{ 4312 struct md_page *pvh; 4313 pv_entry_t pv; 4314 int loops = 0; 4315 boolean_t rv; 4316 4317 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4318 ("pmap_page_exists_quick: page %p is not managed", m)); 4319 rv = FALSE; 4320 rw_wlock(&pvh_global_lock); 4321 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 4322 if (PV_PMAP(pv) == pmap) { 4323 rv = TRUE; 4324 break; 4325 } 4326 loops++; 4327 if (loops >= 16) 4328 break; 4329 } 4330 if (!rv && loops < 16 && (m->flags & PG_FICTITIOUS) == 0) { 4331 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4332 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 4333 if (PV_PMAP(pv) == pmap) { 4334 rv = TRUE; 4335 break; 4336 } 4337 loops++; 4338 if (loops >= 16) 4339 break; 4340 } 4341 } 4342 rw_wunlock(&pvh_global_lock); 4343 return (rv); 4344} 4345 4346/* 4347 * pmap_page_wired_mappings: 4348 * 4349 * Return the number of managed mappings to the given physical page 4350 * that are wired. 4351 */ 4352int 4353pmap_page_wired_mappings(vm_page_t m) 4354{ 4355 int count; 4356 4357 count = 0; 4358 if ((m->oflags & VPO_UNMANAGED) != 0) 4359 return (count); 4360 rw_wlock(&pvh_global_lock); 4361 count = pmap_pvh_wired_mappings(&m->md, count); 4362 if ((m->flags & PG_FICTITIOUS) == 0) { 4363 count = pmap_pvh_wired_mappings(pa_to_pvh(VM_PAGE_TO_PHYS(m)), 4364 count); 4365 } 4366 rw_wunlock(&pvh_global_lock); 4367 return (count); 4368} 4369 4370/* 4371 * pmap_pvh_wired_mappings: 4372 * 4373 * Return the updated number "count" of managed mappings that are wired. 4374 */ 4375static int 4376pmap_pvh_wired_mappings(struct md_page *pvh, int count) 4377{ 4378 pmap_t pmap; 4379 pt_entry_t *pte; 4380 pv_entry_t pv; 4381 4382 rw_assert(&pvh_global_lock, RA_WLOCKED); 4383 sched_pin(); 4384 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 4385 pmap = PV_PMAP(pv); 4386 PMAP_LOCK(pmap); 4387 pte = pmap_pte_quick(pmap, pv->pv_va); 4388 if ((*pte & PG_W) != 0) 4389 count++; 4390 PMAP_UNLOCK(pmap); 4391 } 4392 sched_unpin(); 4393 return (count); 4394} 4395 4396/* 4397 * Returns TRUE if the given page is mapped individually or as part of 4398 * a 4mpage. Otherwise, returns FALSE. 4399 */ 4400boolean_t 4401pmap_page_is_mapped(vm_page_t m) 4402{ 4403 boolean_t rv; 4404 4405 if ((m->oflags & VPO_UNMANAGED) != 0) 4406 return (FALSE); 4407 rw_wlock(&pvh_global_lock); 4408 rv = !TAILQ_EMPTY(&m->md.pv_list) || 4409 ((m->flags & PG_FICTITIOUS) == 0 && 4410 !TAILQ_EMPTY(&pa_to_pvh(VM_PAGE_TO_PHYS(m))->pv_list)); 4411 rw_wunlock(&pvh_global_lock); 4412 return (rv); 4413} 4414 4415/* 4416 * Remove all pages from specified address space 4417 * this aids process exit speeds. Also, this code 4418 * is special cased for current process only, but 4419 * can have the more generic (and slightly slower) 4420 * mode enabled. This is much faster than pmap_remove 4421 * in the case of running down an entire address space. 4422 */ 4423void 4424pmap_remove_pages(pmap_t pmap) 4425{ 4426 pt_entry_t *pte, tpte; 4427 vm_page_t m, mpte, mt; 4428 pv_entry_t pv; 4429 struct md_page *pvh; 4430 struct pv_chunk *pc, *npc; 4431 struct spglist free; 4432 int field, idx; 4433 int32_t bit; 4434 uint32_t inuse, bitmask; 4435 int allfree; 4436 4437 if (pmap != PCPU_GET(curpmap)) { 4438 printf("warning: pmap_remove_pages called with non-current pmap\n"); 4439 return; 4440 } 4441 SLIST_INIT(&free); 4442 rw_wlock(&pvh_global_lock); 4443 PMAP_LOCK(pmap); 4444 sched_pin(); 4445 TAILQ_FOREACH_SAFE(pc, &pmap->pm_pvchunk, pc_list, npc) { 4446 KASSERT(pc->pc_pmap == pmap, ("Wrong pmap %p %p", pmap, 4447 pc->pc_pmap)); 4448 allfree = 1; 4449 for (field = 0; field < _NPCM; field++) { 4450 inuse = ~pc->pc_map[field] & pc_freemask[field]; 4451 while (inuse != 0) { 4452 bit = bsfl(inuse); 4453 bitmask = 1UL << bit; 4454 idx = field * 32 + bit; 4455 pv = &pc->pc_pventry[idx]; 4456 inuse &= ~bitmask; 4457 4458 pte = pmap_pde(pmap, pv->pv_va); 4459 tpte = *pte; 4460 if ((tpte & PG_PS) == 0) { 4461 pte = vtopte(pv->pv_va); 4462 tpte = *pte & ~PG_PTE_PAT; 4463 } 4464 4465 if (tpte == 0) { 4466 printf( 4467 "TPTE at %p IS ZERO @ VA %08x\n", 4468 pte, pv->pv_va); 4469 panic("bad pte"); 4470 } 4471 4472/* 4473 * We cannot remove wired pages from a process' mapping at this time 4474 */ 4475 if (tpte & PG_W) { 4476 allfree = 0; 4477 continue; 4478 } 4479 4480 m = PHYS_TO_VM_PAGE(tpte & PG_FRAME); 4481 KASSERT(m->phys_addr == (tpte & PG_FRAME), 4482 ("vm_page_t %p phys_addr mismatch %016jx %016jx", 4483 m, (uintmax_t)m->phys_addr, 4484 (uintmax_t)tpte)); 4485 4486 KASSERT((m->flags & PG_FICTITIOUS) != 0 || 4487 m < &vm_page_array[vm_page_array_size], 4488 ("pmap_remove_pages: bad tpte %#jx", 4489 (uintmax_t)tpte)); 4490 4491 pte_clear(pte); 4492 4493 /* 4494 * Update the vm_page_t clean/reference bits. 4495 */ 4496 if ((tpte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 4497 if ((tpte & PG_PS) != 0) { 4498 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++) 4499 vm_page_dirty(mt); 4500 } else 4501 vm_page_dirty(m); 4502 } 4503 4504 /* Mark free */ 4505 PV_STAT(pv_entry_frees++); 4506 PV_STAT(pv_entry_spare++); 4507 pv_entry_count--; 4508 pc->pc_map[field] |= bitmask; 4509 if ((tpte & PG_PS) != 0) { 4510 pmap->pm_stats.resident_count -= NBPDR / PAGE_SIZE; 4511 pvh = pa_to_pvh(tpte & PG_PS_FRAME); 4512 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next); 4513 if (TAILQ_EMPTY(&pvh->pv_list)) { 4514 for (mt = m; mt < &m[NBPDR / PAGE_SIZE]; mt++) 4515 if (TAILQ_EMPTY(&mt->md.pv_list)) 4516 vm_page_aflag_clear(mt, PGA_WRITEABLE); 4517 } 4518 mpte = pmap_lookup_pt_page(pmap, pv->pv_va); 4519 if (mpte != NULL) { 4520 pmap_remove_pt_page(pmap, mpte); 4521 pmap->pm_stats.resident_count--; 4522 KASSERT(mpte->wire_count == NPTEPG, 4523 ("pmap_remove_pages: pte page wire count error")); 4524 mpte->wire_count = 0; 4525 pmap_add_delayed_free_list(mpte, &free, FALSE); 4526 atomic_subtract_int(&cnt.v_wire_count, 1); 4527 } 4528 } else { 4529 pmap->pm_stats.resident_count--; 4530 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 4531 if (TAILQ_EMPTY(&m->md.pv_list) && 4532 (m->flags & PG_FICTITIOUS) == 0) { 4533 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4534 if (TAILQ_EMPTY(&pvh->pv_list)) 4535 vm_page_aflag_clear(m, PGA_WRITEABLE); 4536 } 4537 pmap_unuse_pt(pmap, pv->pv_va, &free); 4538 } 4539 } 4540 } 4541 if (allfree) { 4542 TAILQ_REMOVE(&pmap->pm_pvchunk, pc, pc_list); 4543 free_pv_chunk(pc); 4544 } 4545 } 4546 sched_unpin(); 4547 pmap_invalidate_all(pmap); 4548 rw_wunlock(&pvh_global_lock); 4549 PMAP_UNLOCK(pmap); 4550 pmap_free_zero_pages(&free); 4551} 4552 4553/* 4554 * pmap_is_modified: 4555 * 4556 * Return whether or not the specified physical page was modified 4557 * in any physical maps. 4558 */ 4559boolean_t 4560pmap_is_modified(vm_page_t m) 4561{ 4562 boolean_t rv; 4563 4564 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4565 ("pmap_is_modified: page %p is not managed", m)); 4566 4567 /* 4568 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 4569 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE 4570 * is clear, no PTEs can have PG_M set. 4571 */ 4572 VM_OBJECT_ASSERT_WLOCKED(m->object); 4573 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 4574 return (FALSE); 4575 rw_wlock(&pvh_global_lock); 4576 rv = pmap_is_modified_pvh(&m->md) || 4577 ((m->flags & PG_FICTITIOUS) == 0 && 4578 pmap_is_modified_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m)))); 4579 rw_wunlock(&pvh_global_lock); 4580 return (rv); 4581} 4582 4583/* 4584 * Returns TRUE if any of the given mappings were used to modify 4585 * physical memory. Otherwise, returns FALSE. Both page and 2mpage 4586 * mappings are supported. 4587 */ 4588static boolean_t 4589pmap_is_modified_pvh(struct md_page *pvh) 4590{ 4591 pv_entry_t pv; 4592 pt_entry_t *pte; 4593 pmap_t pmap; 4594 boolean_t rv; 4595 4596 rw_assert(&pvh_global_lock, RA_WLOCKED); 4597 rv = FALSE; 4598 sched_pin(); 4599 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 4600 pmap = PV_PMAP(pv); 4601 PMAP_LOCK(pmap); 4602 pte = pmap_pte_quick(pmap, pv->pv_va); 4603 rv = (*pte & (PG_M | PG_RW)) == (PG_M | PG_RW); 4604 PMAP_UNLOCK(pmap); 4605 if (rv) 4606 break; 4607 } 4608 sched_unpin(); 4609 return (rv); 4610} 4611 4612/* 4613 * pmap_is_prefaultable: 4614 * 4615 * Return whether or not the specified virtual address is elgible 4616 * for prefault. 4617 */ 4618boolean_t 4619pmap_is_prefaultable(pmap_t pmap, vm_offset_t addr) 4620{ 4621 pd_entry_t *pde; 4622 pt_entry_t *pte; 4623 boolean_t rv; 4624 4625 rv = FALSE; 4626 PMAP_LOCK(pmap); 4627 pde = pmap_pde(pmap, addr); 4628 if (*pde != 0 && (*pde & PG_PS) == 0) { 4629 pte = vtopte(addr); 4630 rv = *pte == 0; 4631 } 4632 PMAP_UNLOCK(pmap); 4633 return (rv); 4634} 4635 4636/* 4637 * pmap_is_referenced: 4638 * 4639 * Return whether or not the specified physical page was referenced 4640 * in any physical maps. 4641 */ 4642boolean_t 4643pmap_is_referenced(vm_page_t m) 4644{ 4645 boolean_t rv; 4646 4647 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4648 ("pmap_is_referenced: page %p is not managed", m)); 4649 rw_wlock(&pvh_global_lock); 4650 rv = pmap_is_referenced_pvh(&m->md) || 4651 ((m->flags & PG_FICTITIOUS) == 0 && 4652 pmap_is_referenced_pvh(pa_to_pvh(VM_PAGE_TO_PHYS(m)))); 4653 rw_wunlock(&pvh_global_lock); 4654 return (rv); 4655} 4656 4657/* 4658 * Returns TRUE if any of the given mappings were referenced and FALSE 4659 * otherwise. Both page and 4mpage mappings are supported. 4660 */ 4661static boolean_t 4662pmap_is_referenced_pvh(struct md_page *pvh) 4663{ 4664 pv_entry_t pv; 4665 pt_entry_t *pte; 4666 pmap_t pmap; 4667 boolean_t rv; 4668 4669 rw_assert(&pvh_global_lock, RA_WLOCKED); 4670 rv = FALSE; 4671 sched_pin(); 4672 TAILQ_FOREACH(pv, &pvh->pv_list, pv_next) { 4673 pmap = PV_PMAP(pv); 4674 PMAP_LOCK(pmap); 4675 pte = pmap_pte_quick(pmap, pv->pv_va); 4676 rv = (*pte & (PG_A | PG_V)) == (PG_A | PG_V); 4677 PMAP_UNLOCK(pmap); 4678 if (rv) 4679 break; 4680 } 4681 sched_unpin(); 4682 return (rv); 4683} 4684 4685/* 4686 * Clear the write and modified bits in each of the given page's mappings. 4687 */ 4688void 4689pmap_remove_write(vm_page_t m) 4690{ 4691 struct md_page *pvh; 4692 pv_entry_t next_pv, pv; 4693 pmap_t pmap; 4694 pd_entry_t *pde; 4695 pt_entry_t oldpte, *pte; 4696 vm_offset_t va; 4697 4698 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4699 ("pmap_remove_write: page %p is not managed", m)); 4700 4701 /* 4702 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be 4703 * set by another thread while the object is locked. Thus, 4704 * if PGA_WRITEABLE is clear, no page table entries need updating. 4705 */ 4706 VM_OBJECT_ASSERT_WLOCKED(m->object); 4707 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0) 4708 return; 4709 rw_wlock(&pvh_global_lock); 4710 sched_pin(); 4711 if ((m->flags & PG_FICTITIOUS) != 0) 4712 goto small_mappings; 4713 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4714 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) { 4715 va = pv->pv_va; 4716 pmap = PV_PMAP(pv); 4717 PMAP_LOCK(pmap); 4718 pde = pmap_pde(pmap, va); 4719 if ((*pde & PG_RW) != 0) 4720 (void)pmap_demote_pde(pmap, pde, va); 4721 PMAP_UNLOCK(pmap); 4722 } 4723small_mappings: 4724 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 4725 pmap = PV_PMAP(pv); 4726 PMAP_LOCK(pmap); 4727 pde = pmap_pde(pmap, pv->pv_va); 4728 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_write: found" 4729 " a 4mpage in page %p's pv list", m)); 4730 pte = pmap_pte_quick(pmap, pv->pv_va); 4731retry: 4732 oldpte = *pte; 4733 if ((oldpte & PG_RW) != 0) { 4734 /* 4735 * Regardless of whether a pte is 32 or 64 bits 4736 * in size, PG_RW and PG_M are among the least 4737 * significant 32 bits. 4738 */ 4739 if (!atomic_cmpset_int((u_int *)pte, oldpte, 4740 oldpte & ~(PG_RW | PG_M))) 4741 goto retry; 4742 if ((oldpte & PG_M) != 0) 4743 vm_page_dirty(m); 4744 pmap_invalidate_page(pmap, pv->pv_va); 4745 } 4746 PMAP_UNLOCK(pmap); 4747 } 4748 vm_page_aflag_clear(m, PGA_WRITEABLE); 4749 sched_unpin(); 4750 rw_wunlock(&pvh_global_lock); 4751} 4752 4753#define PMAP_TS_REFERENCED_MAX 5 4754 4755/* 4756 * pmap_ts_referenced: 4757 * 4758 * Return a count of reference bits for a page, clearing those bits. 4759 * It is not necessary for every reference bit to be cleared, but it 4760 * is necessary that 0 only be returned when there are truly no 4761 * reference bits set. 4762 * 4763 * XXX: The exact number of bits to check and clear is a matter that 4764 * should be tested and standardized at some point in the future for 4765 * optimal aging of shared pages. 4766 */ 4767int 4768pmap_ts_referenced(vm_page_t m) 4769{ 4770 struct md_page *pvh; 4771 pv_entry_t pv, pvf; 4772 pmap_t pmap; 4773 pd_entry_t *pde; 4774 pt_entry_t *pte; 4775 vm_paddr_t pa; 4776 int rtval = 0; 4777 4778 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4779 ("pmap_ts_referenced: page %p is not managed", m)); 4780 pa = VM_PAGE_TO_PHYS(m); 4781 pvh = pa_to_pvh(pa); 4782 rw_wlock(&pvh_global_lock); 4783 sched_pin(); 4784 if ((m->flags & PG_FICTITIOUS) != 0 || 4785 (pvf = TAILQ_FIRST(&pvh->pv_list)) == NULL) 4786 goto small_mappings; 4787 pv = pvf; 4788 do { 4789 pmap = PV_PMAP(pv); 4790 PMAP_LOCK(pmap); 4791 pde = pmap_pde(pmap, pv->pv_va); 4792 if ((*pde & PG_A) != 0) { 4793 /* 4794 * Since this reference bit is shared by either 1024 4795 * or 512 4KB pages, it should not be cleared every 4796 * time it is tested. Apply a simple "hash" function 4797 * on the physical page number, the virtual superpage 4798 * number, and the pmap address to select one 4KB page 4799 * out of the 1024 or 512 on which testing the 4800 * reference bit will result in clearing that bit. 4801 * This function is designed to avoid the selection of 4802 * the same 4KB page for every 2- or 4MB page mapping. 4803 * 4804 * On demotion, a mapping that hasn't been referenced 4805 * is simply destroyed. To avoid the possibility of a 4806 * subsequent page fault on a demoted wired mapping, 4807 * always leave its reference bit set. Moreover, 4808 * since the superpage is wired, the current state of 4809 * its reference bit won't affect page replacement. 4810 */ 4811 if ((((pa >> PAGE_SHIFT) ^ (pv->pv_va >> PDRSHIFT) ^ 4812 (uintptr_t)pmap) & (NPTEPG - 1)) == 0 && 4813 (*pde & PG_W) == 0) { 4814 atomic_clear_int((u_int *)pde, PG_A); 4815 pmap_invalidate_page(pmap, pv->pv_va); 4816 } 4817 rtval++; 4818 } 4819 PMAP_UNLOCK(pmap); 4820 /* Rotate the PV list if it has more than one entry. */ 4821 if (TAILQ_NEXT(pv, pv_next) != NULL) { 4822 TAILQ_REMOVE(&pvh->pv_list, pv, pv_next); 4823 TAILQ_INSERT_TAIL(&pvh->pv_list, pv, pv_next); 4824 } 4825 if (rtval >= PMAP_TS_REFERENCED_MAX) 4826 goto out; 4827 } while ((pv = TAILQ_FIRST(&pvh->pv_list)) != pvf); 4828small_mappings: 4829 if ((pvf = TAILQ_FIRST(&m->md.pv_list)) == NULL) 4830 goto out; 4831 pv = pvf; 4832 do { 4833 pmap = PV_PMAP(pv); 4834 PMAP_LOCK(pmap); 4835 pde = pmap_pde(pmap, pv->pv_va); 4836 KASSERT((*pde & PG_PS) == 0, 4837 ("pmap_ts_referenced: found a 4mpage in page %p's pv list", 4838 m)); 4839 pte = pmap_pte_quick(pmap, pv->pv_va); 4840 if ((*pte & PG_A) != 0) { 4841 atomic_clear_int((u_int *)pte, PG_A); 4842 pmap_invalidate_page(pmap, pv->pv_va); 4843 rtval++; 4844 } 4845 PMAP_UNLOCK(pmap); 4846 /* Rotate the PV list if it has more than one entry. */ 4847 if (TAILQ_NEXT(pv, pv_next) != NULL) { 4848 TAILQ_REMOVE(&m->md.pv_list, pv, pv_next); 4849 TAILQ_INSERT_TAIL(&m->md.pv_list, pv, pv_next); 4850 } 4851 } while ((pv = TAILQ_FIRST(&m->md.pv_list)) != pvf && rtval < 4852 PMAP_TS_REFERENCED_MAX); 4853out: 4854 sched_unpin(); 4855 rw_wunlock(&pvh_global_lock); 4856 return (rtval); 4857} 4858 4859/* 4860 * Apply the given advice to the specified range of addresses within the 4861 * given pmap. Depending on the advice, clear the referenced and/or 4862 * modified flags in each mapping and set the mapped page's dirty field. 4863 */ 4864void 4865pmap_advise(pmap_t pmap, vm_offset_t sva, vm_offset_t eva, int advice) 4866{ 4867 pd_entry_t oldpde, *pde; 4868 pt_entry_t *pte; 4869 vm_offset_t pdnxt; 4870 vm_page_t m; 4871 boolean_t anychanged, pv_lists_locked; 4872 4873 if (advice != MADV_DONTNEED && advice != MADV_FREE) 4874 return; 4875 if (pmap_is_current(pmap)) 4876 pv_lists_locked = FALSE; 4877 else { 4878 pv_lists_locked = TRUE; 4879resume: 4880 rw_wlock(&pvh_global_lock); 4881 sched_pin(); 4882 } 4883 anychanged = FALSE; 4884 PMAP_LOCK(pmap); 4885 for (; sva < eva; sva = pdnxt) { 4886 pdnxt = (sva + NBPDR) & ~PDRMASK; 4887 if (pdnxt < sva) 4888 pdnxt = eva; 4889 pde = pmap_pde(pmap, sva); 4890 oldpde = *pde; 4891 if ((oldpde & PG_V) == 0) 4892 continue; 4893 else if ((oldpde & PG_PS) != 0) { 4894 if ((oldpde & PG_MANAGED) == 0) 4895 continue; 4896 if (!pv_lists_locked) { 4897 pv_lists_locked = TRUE; 4898 if (!rw_try_wlock(&pvh_global_lock)) { 4899 if (anychanged) 4900 pmap_invalidate_all(pmap); 4901 PMAP_UNLOCK(pmap); 4902 goto resume; 4903 } 4904 sched_pin(); 4905 } 4906 if (!pmap_demote_pde(pmap, pde, sva)) { 4907 /* 4908 * The large page mapping was destroyed. 4909 */ 4910 continue; 4911 } 4912 4913 /* 4914 * Unless the page mappings are wired, remove the 4915 * mapping to a single page so that a subsequent 4916 * access may repromote. Since the underlying page 4917 * table page is fully populated, this removal never 4918 * frees a page table page. 4919 */ 4920 if ((oldpde & PG_W) == 0) { 4921 pte = pmap_pte_quick(pmap, sva); 4922 KASSERT((*pte & PG_V) != 0, 4923 ("pmap_advise: invalid PTE")); 4924 pmap_remove_pte(pmap, pte, sva, NULL); 4925 anychanged = TRUE; 4926 } 4927 } 4928 if (pdnxt > eva) 4929 pdnxt = eva; 4930 for (pte = pmap_pte_quick(pmap, sva); sva != pdnxt; pte++, 4931 sva += PAGE_SIZE) { 4932 if ((*pte & (PG_MANAGED | PG_V)) != (PG_MANAGED | 4933 PG_V)) 4934 continue; 4935 else if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 4936 if (advice == MADV_DONTNEED) { 4937 /* 4938 * Future calls to pmap_is_modified() 4939 * can be avoided by making the page 4940 * dirty now. 4941 */ 4942 m = PHYS_TO_VM_PAGE(*pte & PG_FRAME); 4943 vm_page_dirty(m); 4944 } 4945 atomic_clear_int((u_int *)pte, PG_M | PG_A); 4946 } else if ((*pte & PG_A) != 0) 4947 atomic_clear_int((u_int *)pte, PG_A); 4948 else 4949 continue; 4950 if ((*pte & PG_G) != 0) 4951 pmap_invalidate_page(pmap, sva); 4952 else 4953 anychanged = TRUE; 4954 } 4955 } 4956 if (anychanged) 4957 pmap_invalidate_all(pmap); 4958 if (pv_lists_locked) { 4959 sched_unpin(); 4960 rw_wunlock(&pvh_global_lock); 4961 } 4962 PMAP_UNLOCK(pmap); 4963} 4964 4965/* 4966 * Clear the modify bits on the specified physical page. 4967 */ 4968void 4969pmap_clear_modify(vm_page_t m) 4970{ 4971 struct md_page *pvh; 4972 pv_entry_t next_pv, pv; 4973 pmap_t pmap; 4974 pd_entry_t oldpde, *pde; 4975 pt_entry_t oldpte, *pte; 4976 vm_offset_t va; 4977 4978 KASSERT((m->oflags & VPO_UNMANAGED) == 0, 4979 ("pmap_clear_modify: page %p is not managed", m)); 4980 VM_OBJECT_ASSERT_WLOCKED(m->object); 4981 KASSERT(!vm_page_xbusied(m), 4982 ("pmap_clear_modify: page %p is exclusive busied", m)); 4983 4984 /* 4985 * If the page is not PGA_WRITEABLE, then no PTEs can have PG_M set. 4986 * If the object containing the page is locked and the page is not 4987 * exclusive busied, then PGA_WRITEABLE cannot be concurrently set. 4988 */ 4989 if ((m->aflags & PGA_WRITEABLE) == 0) 4990 return; 4991 rw_wlock(&pvh_global_lock); 4992 sched_pin(); 4993 if ((m->flags & PG_FICTITIOUS) != 0) 4994 goto small_mappings; 4995 pvh = pa_to_pvh(VM_PAGE_TO_PHYS(m)); 4996 TAILQ_FOREACH_SAFE(pv, &pvh->pv_list, pv_next, next_pv) { 4997 va = pv->pv_va; 4998 pmap = PV_PMAP(pv); 4999 PMAP_LOCK(pmap); 5000 pde = pmap_pde(pmap, va); 5001 oldpde = *pde; 5002 if ((oldpde & PG_RW) != 0) { 5003 if (pmap_demote_pde(pmap, pde, va)) { 5004 if ((oldpde & PG_W) == 0) { 5005 /* 5006 * Write protect the mapping to a 5007 * single page so that a subsequent 5008 * write access may repromote. 5009 */ 5010 va += VM_PAGE_TO_PHYS(m) - (oldpde & 5011 PG_PS_FRAME); 5012 pte = pmap_pte_quick(pmap, va); 5013 oldpte = *pte; 5014 if ((oldpte & PG_V) != 0) { 5015 /* 5016 * Regardless of whether a pte is 32 or 64 bits 5017 * in size, PG_RW and PG_M are among the least 5018 * significant 32 bits. 5019 */ 5020 while (!atomic_cmpset_int((u_int *)pte, 5021 oldpte, 5022 oldpte & ~(PG_M | PG_RW))) 5023 oldpte = *pte; 5024 vm_page_dirty(m); 5025 pmap_invalidate_page(pmap, va); 5026 } 5027 } 5028 } 5029 } 5030 PMAP_UNLOCK(pmap); 5031 } 5032small_mappings: 5033 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 5034 pmap = PV_PMAP(pv); 5035 PMAP_LOCK(pmap); 5036 pde = pmap_pde(pmap, pv->pv_va); 5037 KASSERT((*pde & PG_PS) == 0, ("pmap_clear_modify: found" 5038 " a 4mpage in page %p's pv list", m)); 5039 pte = pmap_pte_quick(pmap, pv->pv_va); 5040 if ((*pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) { 5041 /* 5042 * Regardless of whether a pte is 32 or 64 bits 5043 * in size, PG_M is among the least significant 5044 * 32 bits. 5045 */ 5046 atomic_clear_int((u_int *)pte, PG_M); 5047 pmap_invalidate_page(pmap, pv->pv_va); 5048 } 5049 PMAP_UNLOCK(pmap); 5050 } 5051 sched_unpin(); 5052 rw_wunlock(&pvh_global_lock); 5053} 5054 5055/* 5056 * Miscellaneous support routines follow 5057 */ 5058 5059/* Adjust the cache mode for a 4KB page mapped via a PTE. */ 5060static __inline void 5061pmap_pte_attr(pt_entry_t *pte, int cache_bits) 5062{ 5063 u_int opte, npte; 5064 5065 /* 5066 * The cache mode bits are all in the low 32-bits of the 5067 * PTE, so we can just spin on updating the low 32-bits. 5068 */ 5069 do { 5070 opte = *(u_int *)pte; 5071 npte = opte & ~PG_PTE_CACHE; 5072 npte |= cache_bits; 5073 } while (npte != opte && !atomic_cmpset_int((u_int *)pte, opte, npte)); 5074} 5075 5076/* Adjust the cache mode for a 2/4MB page mapped via a PDE. */ 5077static __inline void 5078pmap_pde_attr(pd_entry_t *pde, int cache_bits) 5079{ 5080 u_int opde, npde; 5081 5082 /* 5083 * The cache mode bits are all in the low 32-bits of the 5084 * PDE, so we can just spin on updating the low 32-bits. 5085 */ 5086 do { 5087 opde = *(u_int *)pde; 5088 npde = opde & ~PG_PDE_CACHE; 5089 npde |= cache_bits; 5090 } while (npde != opde && !atomic_cmpset_int((u_int *)pde, opde, npde)); 5091} 5092 5093/* 5094 * Map a set of physical memory pages into the kernel virtual 5095 * address space. Return a pointer to where it is mapped. This 5096 * routine is intended to be used for mapping device memory, 5097 * NOT real memory. 5098 */ 5099void * 5100pmap_mapdev_attr(vm_paddr_t pa, vm_size_t size, int mode) 5101{ 5102 vm_offset_t va, offset; 5103 vm_size_t tmpsize; 5104 5105 offset = pa & PAGE_MASK; 5106 size = round_page(offset + size); 5107 pa = pa & PG_FRAME; 5108 5109 if (pa < KERNLOAD && pa + size <= KERNLOAD) 5110 va = KERNBASE + pa; 5111 else 5112 va = kva_alloc(size); 5113 if (!va) 5114 panic("pmap_mapdev: Couldn't alloc kernel virtual memory"); 5115 5116 for (tmpsize = 0; tmpsize < size; tmpsize += PAGE_SIZE) 5117 pmap_kenter_attr(va + tmpsize, pa + tmpsize, mode); 5118 pmap_invalidate_range(kernel_pmap, va, va + tmpsize); 5119 pmap_invalidate_cache_range(va, va + size); 5120 return ((void *)(va + offset)); 5121} 5122 5123void * 5124pmap_mapdev(vm_paddr_t pa, vm_size_t size) 5125{ 5126 5127 return (pmap_mapdev_attr(pa, size, PAT_UNCACHEABLE)); 5128} 5129 5130void * 5131pmap_mapbios(vm_paddr_t pa, vm_size_t size) 5132{ 5133 5134 return (pmap_mapdev_attr(pa, size, PAT_WRITE_BACK)); 5135} 5136 5137void 5138pmap_unmapdev(vm_offset_t va, vm_size_t size) 5139{ 5140 vm_offset_t base, offset; 5141 5142 if (va >= KERNBASE && va + size <= KERNBASE + KERNLOAD) 5143 return; 5144 base = trunc_page(va); 5145 offset = va & PAGE_MASK; 5146 size = round_page(offset + size); 5147 kva_free(base, size); 5148} 5149 5150/* 5151 * Sets the memory attribute for the specified page. 5152 */ 5153void 5154pmap_page_set_memattr(vm_page_t m, vm_memattr_t ma) 5155{ 5156 5157 m->md.pat_mode = ma; 5158 if ((m->flags & PG_FICTITIOUS) != 0) 5159 return; 5160 5161 /* 5162 * If "m" is a normal page, flush it from the cache. 5163 * See pmap_invalidate_cache_range(). 5164 * 5165 * First, try to find an existing mapping of the page by sf 5166 * buffer. sf_buf_invalidate_cache() modifies mapping and 5167 * flushes the cache. 5168 */ 5169 if (sf_buf_invalidate_cache(m)) 5170 return; 5171 5172 /* 5173 * If page is not mapped by sf buffer, but CPU does not 5174 * support self snoop, map the page transient and do 5175 * invalidation. In the worst case, whole cache is flushed by 5176 * pmap_invalidate_cache_range(). 5177 */ 5178 if ((cpu_feature & CPUID_SS) == 0) 5179 pmap_flush_page(m); 5180} 5181 5182static void 5183pmap_flush_page(vm_page_t m) 5184{ 5185 struct sysmaps *sysmaps; 5186 vm_offset_t sva, eva; 5187 5188 if ((cpu_feature & CPUID_CLFSH) != 0) { 5189 sysmaps = &sysmaps_pcpu[PCPU_GET(cpuid)]; 5190 mtx_lock(&sysmaps->lock); 5191 if (*sysmaps->CMAP2) 5192 panic("pmap_flush_page: CMAP2 busy"); 5193 sched_pin(); 5194 *sysmaps->CMAP2 = PG_V | PG_RW | VM_PAGE_TO_PHYS(m) | 5195 PG_A | PG_M | pmap_cache_bits(m->md.pat_mode, 0); 5196 invlcaddr(sysmaps->CADDR2); 5197 sva = (vm_offset_t)sysmaps->CADDR2; 5198 eva = sva + PAGE_SIZE; 5199 5200 /* 5201 * Use mfence despite the ordering implied by 5202 * mtx_{un,}lock() because clflush is not guaranteed 5203 * to be ordered by any other instruction. 5204 */ 5205 mfence(); 5206 for (; sva < eva; sva += cpu_clflush_line_size) 5207 clflush(sva); 5208 mfence(); 5209 *sysmaps->CMAP2 = 0; 5210 sched_unpin(); 5211 mtx_unlock(&sysmaps->lock); 5212 } else 5213 pmap_invalidate_cache(); 5214} 5215 5216/* 5217 * Changes the specified virtual address range's memory type to that given by 5218 * the parameter "mode". The specified virtual address range must be 5219 * completely contained within either the kernel map. 5220 * 5221 * Returns zero if the change completed successfully, and either EINVAL or 5222 * ENOMEM if the change failed. Specifically, EINVAL is returned if some part 5223 * of the virtual address range was not mapped, and ENOMEM is returned if 5224 * there was insufficient memory available to complete the change. 5225 */ 5226int 5227pmap_change_attr(vm_offset_t va, vm_size_t size, int mode) 5228{ 5229 vm_offset_t base, offset, tmpva; 5230 pd_entry_t *pde; 5231 pt_entry_t *pte; 5232 int cache_bits_pte, cache_bits_pde; 5233 boolean_t changed; 5234 5235 base = trunc_page(va); 5236 offset = va & PAGE_MASK; 5237 size = round_page(offset + size); 5238 5239 /* 5240 * Only supported on kernel virtual addresses above the recursive map. 5241 */ 5242 if (base < VM_MIN_KERNEL_ADDRESS) 5243 return (EINVAL); 5244 5245 cache_bits_pde = pmap_cache_bits(mode, 1); 5246 cache_bits_pte = pmap_cache_bits(mode, 0); 5247 changed = FALSE; 5248 5249 /* 5250 * Pages that aren't mapped aren't supported. Also break down 5251 * 2/4MB pages into 4KB pages if required. 5252 */ 5253 PMAP_LOCK(kernel_pmap); 5254 for (tmpva = base; tmpva < base + size; ) { 5255 pde = pmap_pde(kernel_pmap, tmpva); 5256 if (*pde == 0) { 5257 PMAP_UNLOCK(kernel_pmap); 5258 return (EINVAL); 5259 } 5260 if (*pde & PG_PS) { 5261 /* 5262 * If the current 2/4MB page already has 5263 * the required memory type, then we need not 5264 * demote this page. Just increment tmpva to 5265 * the next 2/4MB page frame. 5266 */ 5267 if ((*pde & PG_PDE_CACHE) == cache_bits_pde) { 5268 tmpva = trunc_4mpage(tmpva) + NBPDR; 5269 continue; 5270 } 5271 5272 /* 5273 * If the current offset aligns with a 2/4MB 5274 * page frame and there is at least 2/4MB left 5275 * within the range, then we need not break 5276 * down this page into 4KB pages. 5277 */ 5278 if ((tmpva & PDRMASK) == 0 && 5279 tmpva + PDRMASK < base + size) { 5280 tmpva += NBPDR; 5281 continue; 5282 } 5283 if (!pmap_demote_pde(kernel_pmap, pde, tmpva)) { 5284 PMAP_UNLOCK(kernel_pmap); 5285 return (ENOMEM); 5286 } 5287 } 5288 pte = vtopte(tmpva); 5289 if (*pte == 0) { 5290 PMAP_UNLOCK(kernel_pmap); 5291 return (EINVAL); 5292 } 5293 tmpva += PAGE_SIZE; 5294 } 5295 PMAP_UNLOCK(kernel_pmap); 5296 5297 /* 5298 * Ok, all the pages exist, so run through them updating their 5299 * cache mode if required. 5300 */ 5301 for (tmpva = base; tmpva < base + size; ) { 5302 pde = pmap_pde(kernel_pmap, tmpva); 5303 if (*pde & PG_PS) { 5304 if ((*pde & PG_PDE_CACHE) != cache_bits_pde) { 5305 pmap_pde_attr(pde, cache_bits_pde); 5306 changed = TRUE; 5307 } 5308 tmpva = trunc_4mpage(tmpva) + NBPDR; 5309 } else { 5310 pte = vtopte(tmpva); 5311 if ((*pte & PG_PTE_CACHE) != cache_bits_pte) { 5312 pmap_pte_attr(pte, cache_bits_pte); 5313 changed = TRUE; 5314 } 5315 tmpva += PAGE_SIZE; 5316 } 5317 } 5318 5319 /* 5320 * Flush CPU caches to make sure any data isn't cached that 5321 * shouldn't be, etc. 5322 */ 5323 if (changed) { 5324 pmap_invalidate_range(kernel_pmap, base, tmpva); 5325 pmap_invalidate_cache_range(base, tmpva); 5326 } 5327 return (0); 5328} 5329 5330/* 5331 * perform the pmap work for mincore 5332 */ 5333int 5334pmap_mincore(pmap_t pmap, vm_offset_t addr, vm_paddr_t *locked_pa) 5335{ 5336 pd_entry_t *pdep; 5337 pt_entry_t *ptep, pte; 5338 vm_paddr_t pa; 5339 int val; 5340 5341 PMAP_LOCK(pmap); 5342retry: 5343 pdep = pmap_pde(pmap, addr); 5344 if (*pdep != 0) { 5345 if (*pdep & PG_PS) { 5346 pte = *pdep; 5347 /* Compute the physical address of the 4KB page. */ 5348 pa = ((*pdep & PG_PS_FRAME) | (addr & PDRMASK)) & 5349 PG_FRAME; 5350 val = MINCORE_SUPER; 5351 } else { 5352 ptep = pmap_pte(pmap, addr); 5353 pte = *ptep; 5354 pmap_pte_release(ptep); 5355 pa = pte & PG_FRAME; 5356 val = 0; 5357 } 5358 } else { 5359 pte = 0; 5360 pa = 0; 5361 val = 0; 5362 } 5363 if ((pte & PG_V) != 0) { 5364 val |= MINCORE_INCORE; 5365 if ((pte & (PG_M | PG_RW)) == (PG_M | PG_RW)) 5366 val |= MINCORE_MODIFIED | MINCORE_MODIFIED_OTHER; 5367 if ((pte & PG_A) != 0) 5368 val |= MINCORE_REFERENCED | MINCORE_REFERENCED_OTHER; 5369 } 5370 if ((val & (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER)) != 5371 (MINCORE_MODIFIED_OTHER | MINCORE_REFERENCED_OTHER) && 5372 (pte & (PG_MANAGED | PG_V)) == (PG_MANAGED | PG_V)) { 5373 /* Ensure that "PHYS_TO_VM_PAGE(pa)->object" doesn't change. */ 5374 if (vm_page_pa_tryrelock(pmap, pa, locked_pa)) 5375 goto retry; 5376 } else 5377 PA_UNLOCK_COND(*locked_pa); 5378 PMAP_UNLOCK(pmap); 5379 return (val); 5380} 5381 5382void 5383pmap_activate(struct thread *td) 5384{ 5385 pmap_t pmap, oldpmap; 5386 u_int cpuid; 5387 u_int32_t cr3; 5388 5389 critical_enter(); 5390 pmap = vmspace_pmap(td->td_proc->p_vmspace); 5391 oldpmap = PCPU_GET(curpmap); 5392 cpuid = PCPU_GET(cpuid); 5393#if defined(SMP) 5394 CPU_CLR_ATOMIC(cpuid, &oldpmap->pm_active); 5395 CPU_SET_ATOMIC(cpuid, &pmap->pm_active); 5396#else 5397 CPU_CLR(cpuid, &oldpmap->pm_active); 5398 CPU_SET(cpuid, &pmap->pm_active); 5399#endif 5400#ifdef PAE 5401 cr3 = vtophys(pmap->pm_pdpt); 5402#else 5403 cr3 = vtophys(pmap->pm_pdir); 5404#endif 5405 /* 5406 * pmap_activate is for the current thread on the current cpu 5407 */ 5408 td->td_pcb->pcb_cr3 = cr3; 5409 load_cr3(cr3); 5410 PCPU_SET(curpmap, pmap); 5411 critical_exit(); 5412} 5413 5414void 5415pmap_sync_icache(pmap_t pm, vm_offset_t va, vm_size_t sz) 5416{ 5417} 5418 5419/* 5420 * Increase the starting virtual address of the given mapping if a 5421 * different alignment might result in more superpage mappings. 5422 */ 5423void 5424pmap_align_superpage(vm_object_t object, vm_ooffset_t offset, 5425 vm_offset_t *addr, vm_size_t size) 5426{ 5427 vm_offset_t superpage_offset; 5428 5429 if (size < NBPDR) 5430 return; 5431 if (object != NULL && (object->flags & OBJ_COLORED) != 0) 5432 offset += ptoa(object->pg_color); 5433 superpage_offset = offset & PDRMASK; 5434 if (size - ((NBPDR - superpage_offset) & PDRMASK) < NBPDR || 5435 (*addr & PDRMASK) == superpage_offset) 5436 return; 5437 if ((*addr & PDRMASK) < superpage_offset) 5438 *addr = (*addr & ~PDRMASK) + superpage_offset; 5439 else 5440 *addr = ((*addr + PDRMASK) & ~PDRMASK) + superpage_offset; 5441} 5442 5443 5444#if defined(PMAP_DEBUG) 5445pmap_pid_dump(int pid) 5446{ 5447 pmap_t pmap; 5448 struct proc *p; 5449 int npte = 0; 5450 int index; 5451 5452 sx_slock(&allproc_lock); 5453 FOREACH_PROC_IN_SYSTEM(p) { 5454 if (p->p_pid != pid) 5455 continue; 5456 5457 if (p->p_vmspace) { 5458 int i,j; 5459 index = 0; 5460 pmap = vmspace_pmap(p->p_vmspace); 5461 for (i = 0; i < NPDEPTD; i++) { 5462 pd_entry_t *pde; 5463 pt_entry_t *pte; 5464 vm_offset_t base = i << PDRSHIFT; 5465 5466 pde = &pmap->pm_pdir[i]; 5467 if (pde && pmap_pde_v(pde)) { 5468 for (j = 0; j < NPTEPG; j++) { 5469 vm_offset_t va = base + (j << PAGE_SHIFT); 5470 if (va >= (vm_offset_t) VM_MIN_KERNEL_ADDRESS) { 5471 if (index) { 5472 index = 0; 5473 printf("\n"); 5474 } 5475 sx_sunlock(&allproc_lock); 5476 return (npte); 5477 } 5478 pte = pmap_pte(pmap, va); 5479 if (pte && pmap_pte_v(pte)) { 5480 pt_entry_t pa; 5481 vm_page_t m; 5482 pa = *pte; 5483 m = PHYS_TO_VM_PAGE(pa & PG_FRAME); 5484 printf("va: 0x%x, pt: 0x%x, h: %d, w: %d, f: 0x%x", 5485 va, pa, m->hold_count, m->wire_count, m->flags); 5486 npte++; 5487 index++; 5488 if (index >= 2) { 5489 index = 0; 5490 printf("\n"); 5491 } else { 5492 printf(" "); 5493 } 5494 } 5495 } 5496 } 5497 } 5498 } 5499 } 5500 sx_sunlock(&allproc_lock); 5501 return (npte); 5502} 5503#endif 5504 5505#if defined(DEBUG) 5506 5507static void pads(pmap_t pm); 5508void pmap_pvdump(vm_paddr_t pa); 5509 5510/* print address space of pmap*/ 5511static void 5512pads(pmap_t pm) 5513{ 5514 int i, j; 5515 vm_paddr_t va; 5516 pt_entry_t *ptep; 5517 5518 if (pm == kernel_pmap) 5519 return; 5520 for (i = 0; i < NPDEPTD; i++) 5521 if (pm->pm_pdir[i]) 5522 for (j = 0; j < NPTEPG; j++) { 5523 va = (i << PDRSHIFT) + (j << PAGE_SHIFT); 5524 if (pm == kernel_pmap && va < KERNBASE) 5525 continue; 5526 if (pm != kernel_pmap && va > UPT_MAX_ADDRESS) 5527 continue; 5528 ptep = pmap_pte(pm, va); 5529 if (pmap_pte_v(ptep)) 5530 printf("%x:%x ", va, *ptep); 5531 }; 5532 5533} 5534 5535void 5536pmap_pvdump(vm_paddr_t pa) 5537{ 5538 pv_entry_t pv; 5539 pmap_t pmap; 5540 vm_page_t m; 5541 5542 printf("pa %x", pa); 5543 m = PHYS_TO_VM_PAGE(pa); 5544 TAILQ_FOREACH(pv, &m->md.pv_list, pv_next) { 5545 pmap = PV_PMAP(pv); 5546 printf(" -> pmap %p, va %x", (void *)pmap, pv->pv_va); 5547 pads(pmap); 5548 } 5549 printf(" "); 5550} 5551#endif 5552