mp_machdep.c revision 299062
1/*- 2 * Copyright (c) 1996, by Steve Passe 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. The name of the developer may NOT be used to endorse or promote products 11 * derived from this software without specific prior written permission. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 */ 25 26#include <sys/cdefs.h> 27__FBSDID("$FreeBSD: stable/10/sys/i386/i386/mp_machdep.c 299062 2016-05-04 11:53:30Z avg $"); 28 29#include "opt_apic.h" 30#include "opt_cpu.h" 31#include "opt_kstack_pages.h" 32#include "opt_pmap.h" 33#include "opt_sched.h" 34#include "opt_smp.h" 35 36#if !defined(lint) 37#if !defined(SMP) 38#error How did you get here? 39#endif 40 41#ifndef DEV_APIC 42#error The apic device is required for SMP, add "device apic" to your config file. 43#endif 44#if defined(CPU_DISABLE_CMPXCHG) && !defined(COMPILING_LINT) 45#error SMP not supported with CPU_DISABLE_CMPXCHG 46#endif 47#endif /* not lint */ 48 49#include <sys/param.h> 50#include <sys/systm.h> 51#include <sys/bus.h> 52#include <sys/cons.h> /* cngetc() */ 53#include <sys/cpuset.h> 54#ifdef GPROF 55#include <sys/gmon.h> 56#endif 57#include <sys/kernel.h> 58#include <sys/ktr.h> 59#include <sys/lock.h> 60#include <sys/malloc.h> 61#include <sys/memrange.h> 62#include <sys/mutex.h> 63#include <sys/pcpu.h> 64#include <sys/proc.h> 65#include <sys/sched.h> 66#include <sys/smp.h> 67#include <sys/sysctl.h> 68 69#include <vm/vm.h> 70#include <vm/vm_param.h> 71#include <vm/pmap.h> 72#include <vm/vm_kern.h> 73#include <vm/vm_extern.h> 74 75#include <x86/apicreg.h> 76#include <machine/clock.h> 77#include <machine/cputypes.h> 78#include <x86/mca.h> 79#include <machine/md_var.h> 80#include <machine/pcb.h> 81#include <machine/psl.h> 82#include <machine/smp.h> 83#include <machine/specialreg.h> 84#include <machine/cpu.h> 85 86#define WARMBOOT_TARGET 0 87#define WARMBOOT_OFF (KERNBASE + 0x0467) 88#define WARMBOOT_SEG (KERNBASE + 0x0469) 89 90#define CMOS_REG (0x70) 91#define CMOS_DATA (0x71) 92#define BIOS_RESET (0x0f) 93#define BIOS_WARM (0x0a) 94 95/* 96 * this code MUST be enabled here and in mpboot.s. 97 * it follows the very early stages of AP boot by placing values in CMOS ram. 98 * it NORMALLY will never be needed and thus the primitive method for enabling. 99 * 100#define CHECK_POINTS 101 */ 102 103#if defined(CHECK_POINTS) && !defined(PC98) 104#define CHECK_READ(A) (outb(CMOS_REG, (A)), inb(CMOS_DATA)) 105#define CHECK_WRITE(A,D) (outb(CMOS_REG, (A)), outb(CMOS_DATA, (D))) 106 107#define CHECK_INIT(D); \ 108 CHECK_WRITE(0x34, (D)); \ 109 CHECK_WRITE(0x35, (D)); \ 110 CHECK_WRITE(0x36, (D)); \ 111 CHECK_WRITE(0x37, (D)); \ 112 CHECK_WRITE(0x38, (D)); \ 113 CHECK_WRITE(0x39, (D)); 114 115#define CHECK_PRINT(S); \ 116 printf("%s: %d, %d, %d, %d, %d, %d\n", \ 117 (S), \ 118 CHECK_READ(0x34), \ 119 CHECK_READ(0x35), \ 120 CHECK_READ(0x36), \ 121 CHECK_READ(0x37), \ 122 CHECK_READ(0x38), \ 123 CHECK_READ(0x39)); 124 125#else /* CHECK_POINTS */ 126 127#define CHECK_INIT(D) 128#define CHECK_PRINT(S) 129#define CHECK_WRITE(A, D) 130 131#endif /* CHECK_POINTS */ 132 133/* lock region used by kernel profiling */ 134int mcount_lock; 135 136int mp_naps; /* # of Applications processors */ 137int boot_cpu_id = -1; /* designated BSP */ 138 139extern struct pcpu __pcpu[]; 140 141/* AP uses this during bootstrap. Do not staticize. */ 142char *bootSTK; 143static int bootAP; 144 145/* Free these after use */ 146void *bootstacks[MAXCPU]; 147static void *dpcpu; 148 149struct pcb stoppcbs[MAXCPU]; 150struct susppcb **susppcbs; 151 152/* Variables needed for SMP tlb shootdown. */ 153vm_offset_t smp_tlb_addr1; 154vm_offset_t smp_tlb_addr2; 155volatile int smp_tlb_wait; 156 157#ifdef COUNT_IPIS 158/* Interrupt counts. */ 159static u_long *ipi_preempt_counts[MAXCPU]; 160static u_long *ipi_ast_counts[MAXCPU]; 161u_long *ipi_invltlb_counts[MAXCPU]; 162u_long *ipi_invlrng_counts[MAXCPU]; 163u_long *ipi_invlpg_counts[MAXCPU]; 164u_long *ipi_invlcache_counts[MAXCPU]; 165u_long *ipi_rendezvous_counts[MAXCPU]; 166u_long *ipi_lazypmap_counts[MAXCPU]; 167static u_long *ipi_hardclock_counts[MAXCPU]; 168#endif 169 170/* Default cpu_ops implementation. */ 171struct cpu_ops cpu_ops = { 172 .ipi_vectored = lapic_ipi_vectored 173}; 174 175/* 176 * Local data and functions. 177 */ 178 179static volatile cpuset_t ipi_nmi_pending; 180 181/* used to hold the AP's until we are ready to release them */ 182static struct mtx ap_boot_mtx; 183 184/* Set to 1 once we're ready to let the APs out of the pen. */ 185static volatile int aps_ready = 0; 186 187/* 188 * Store data from cpu_add() until later in the boot when we actually setup 189 * the APs. 190 */ 191struct cpu_info { 192 int cpu_present:1; 193 int cpu_bsp:1; 194 int cpu_disabled:1; 195 int cpu_hyperthread:1; 196} static cpu_info[MAX_APIC_ID + 1]; 197int cpu_apic_ids[MAXCPU]; 198int apic_cpuids[MAX_APIC_ID + 1]; 199 200/* Holds pending bitmap based IPIs per CPU */ 201volatile u_int cpu_ipi_pending[MAXCPU]; 202 203static u_int boot_address; 204static int cpu_logical; /* logical cpus per core */ 205static int cpu_cores; /* cores per package */ 206 207static void assign_cpu_ids(void); 208static void install_ap_tramp(void); 209static void set_interrupt_apic_ids(void); 210static int start_all_aps(void); 211static int start_ap(int apic_id); 212static void release_aps(void *dummy); 213 214static u_int hyperthreading_cpus; /* logical cpus sharing L1 cache */ 215static int hyperthreading_allowed = 1; 216 217static void 218mem_range_AP_init(void) 219{ 220 if (mem_range_softc.mr_op && mem_range_softc.mr_op->initAP) 221 mem_range_softc.mr_op->initAP(&mem_range_softc); 222} 223 224static void 225topo_probe_amd(void) 226{ 227 int core_id_bits; 228 int id; 229 230 /* AMD processors do not support HTT. */ 231 cpu_logical = 1; 232 233 if ((amd_feature2 & AMDID2_CMP) == 0) { 234 cpu_cores = 1; 235 return; 236 } 237 238 core_id_bits = (cpu_procinfo2 & AMDID_COREID_SIZE) >> 239 AMDID_COREID_SIZE_SHIFT; 240 if (core_id_bits == 0) { 241 cpu_cores = (cpu_procinfo2 & AMDID_CMP_CORES) + 1; 242 return; 243 } 244 245 /* Fam 10h and newer should get here. */ 246 for (id = 0; id <= MAX_APIC_ID; id++) { 247 /* Check logical CPU availability. */ 248 if (!cpu_info[id].cpu_present || cpu_info[id].cpu_disabled) 249 continue; 250 /* Check if logical CPU has the same package ID. */ 251 if ((id >> core_id_bits) != (boot_cpu_id >> core_id_bits)) 252 continue; 253 cpu_cores++; 254 } 255} 256 257/* 258 * Round up to the next power of two, if necessary, and then 259 * take log2. 260 * Returns -1 if argument is zero. 261 */ 262static __inline int 263mask_width(u_int x) 264{ 265 266 return (fls(x << (1 - powerof2(x))) - 1); 267} 268 269static void 270topo_probe_0x4(void) 271{ 272 u_int p[4]; 273 int pkg_id_bits; 274 int core_id_bits; 275 int max_cores; 276 int max_logical; 277 int id; 278 279 /* Both zero and one here mean one logical processor per package. */ 280 max_logical = (cpu_feature & CPUID_HTT) != 0 ? 281 (cpu_procinfo & CPUID_HTT_CORES) >> 16 : 1; 282 if (max_logical <= 1) 283 return; 284 285 /* 286 * Because of uniformity assumption we examine only 287 * those logical processors that belong to the same 288 * package as BSP. Further, we count number of 289 * logical processors that belong to the same core 290 * as BSP thus deducing number of threads per core. 291 */ 292 if (cpu_high >= 0x4) { 293 cpuid_count(0x04, 0, p); 294 max_cores = ((p[0] >> 26) & 0x3f) + 1; 295 } else 296 max_cores = 1; 297 core_id_bits = mask_width(max_logical/max_cores); 298 if (core_id_bits < 0) 299 return; 300 pkg_id_bits = core_id_bits + mask_width(max_cores); 301 302 for (id = 0; id <= MAX_APIC_ID; id++) { 303 /* Check logical CPU availability. */ 304 if (!cpu_info[id].cpu_present || cpu_info[id].cpu_disabled) 305 continue; 306 /* Check if logical CPU has the same package ID. */ 307 if ((id >> pkg_id_bits) != (boot_cpu_id >> pkg_id_bits)) 308 continue; 309 cpu_cores++; 310 /* Check if logical CPU has the same package and core IDs. */ 311 if ((id >> core_id_bits) == (boot_cpu_id >> core_id_bits)) 312 cpu_logical++; 313 } 314 315 KASSERT(cpu_cores >= 1 && cpu_logical >= 1, 316 ("topo_probe_0x4 couldn't find BSP")); 317 318 cpu_cores /= cpu_logical; 319 hyperthreading_cpus = cpu_logical; 320} 321 322static void 323topo_probe_0xb(void) 324{ 325 u_int p[4]; 326 int bits; 327 int cnt; 328 int i; 329 int logical; 330 int type; 331 int x; 332 333 /* We only support three levels for now. */ 334 for (i = 0; i < 3; i++) { 335 cpuid_count(0x0b, i, p); 336 337 /* Fall back if CPU leaf 11 doesn't really exist. */ 338 if (i == 0 && p[1] == 0) { 339 topo_probe_0x4(); 340 return; 341 } 342 343 bits = p[0] & 0x1f; 344 logical = p[1] &= 0xffff; 345 type = (p[2] >> 8) & 0xff; 346 if (type == 0 || logical == 0) 347 break; 348 /* 349 * Because of uniformity assumption we examine only 350 * those logical processors that belong to the same 351 * package as BSP. 352 */ 353 for (cnt = 0, x = 0; x <= MAX_APIC_ID; x++) { 354 if (!cpu_info[x].cpu_present || 355 cpu_info[x].cpu_disabled) 356 continue; 357 if (x >> bits == boot_cpu_id >> bits) 358 cnt++; 359 } 360 if (type == CPUID_TYPE_SMT) 361 cpu_logical = cnt; 362 else if (type == CPUID_TYPE_CORE) 363 cpu_cores = cnt; 364 } 365 if (cpu_logical == 0) 366 cpu_logical = 1; 367 cpu_cores /= cpu_logical; 368} 369 370/* 371 * Both topology discovery code and code that consumes topology 372 * information assume top-down uniformity of the topology. 373 * That is, all physical packages must be identical and each 374 * core in a package must have the same number of threads. 375 * Topology information is queried only on BSP, on which this 376 * code runs and for which it can query CPUID information. 377 * Then topology is extrapolated on all packages using the 378 * uniformity assumption. 379 */ 380static void 381topo_probe(void) 382{ 383 static int cpu_topo_probed = 0; 384 385 if (cpu_topo_probed) 386 return; 387 388 CPU_ZERO(&logical_cpus_mask); 389 if (mp_ncpus <= 1) 390 cpu_cores = cpu_logical = 1; 391 else if (cpu_vendor_id == CPU_VENDOR_AMD) 392 topo_probe_amd(); 393 else if (cpu_vendor_id == CPU_VENDOR_INTEL) { 394 /* 395 * See Intel(R) 64 Architecture Processor 396 * Topology Enumeration article for details. 397 * 398 * Note that 0x1 <= cpu_high < 4 case should be 399 * compatible with topo_probe_0x4() logic when 400 * CPUID.1:EBX[23:16] > 0 (cpu_cores will be 1) 401 * or it should trigger the fallback otherwise. 402 */ 403 if (cpu_high >= 0xb) 404 topo_probe_0xb(); 405 else if (cpu_high >= 0x1) 406 topo_probe_0x4(); 407 } 408 409 /* 410 * Fallback: assume each logical CPU is in separate 411 * physical package. That is, no multi-core, no SMT. 412 */ 413 if (cpu_cores == 0 || cpu_logical == 0) 414 cpu_cores = cpu_logical = 1; 415 cpu_topo_probed = 1; 416} 417 418struct cpu_group * 419cpu_topo(void) 420{ 421 int cg_flags; 422 423 /* 424 * Determine whether any threading flags are 425 * necessry. 426 */ 427 topo_probe(); 428 if (cpu_logical > 1 && hyperthreading_cpus) 429 cg_flags = CG_FLAG_HTT; 430 else if (cpu_logical > 1) 431 cg_flags = CG_FLAG_SMT; 432 else 433 cg_flags = 0; 434 if (mp_ncpus % (cpu_cores * cpu_logical) != 0) { 435 printf("WARNING: Non-uniform processors.\n"); 436 printf("WARNING: Using suboptimal topology.\n"); 437 return (smp_topo_none()); 438 } 439 /* 440 * No multi-core or hyper-threaded. 441 */ 442 if (cpu_logical * cpu_cores == 1) 443 return (smp_topo_none()); 444 /* 445 * Only HTT no multi-core. 446 */ 447 if (cpu_logical > 1 && cpu_cores == 1) 448 return (smp_topo_1level(CG_SHARE_L1, cpu_logical, cg_flags)); 449 /* 450 * Only multi-core no HTT. 451 */ 452 if (cpu_cores > 1 && cpu_logical == 1) 453 return (smp_topo_1level(CG_SHARE_L2, cpu_cores, cg_flags)); 454 /* 455 * Both HTT and multi-core. 456 */ 457 return (smp_topo_2level(CG_SHARE_L2, cpu_cores, 458 CG_SHARE_L1, cpu_logical, cg_flags)); 459} 460 461 462/* 463 * Calculate usable address in base memory for AP trampoline code. 464 */ 465u_int 466mp_bootaddress(u_int basemem) 467{ 468 469 boot_address = trunc_page(basemem); /* round down to 4k boundary */ 470 if ((basemem - boot_address) < bootMP_size) 471 boot_address -= PAGE_SIZE; /* not enough, lower by 4k */ 472 473 return boot_address; 474} 475 476void 477cpu_add(u_int apic_id, char boot_cpu) 478{ 479 480 if (apic_id > MAX_APIC_ID) { 481 panic("SMP: APIC ID %d too high", apic_id); 482 return; 483 } 484 KASSERT(cpu_info[apic_id].cpu_present == 0, ("CPU %d added twice", 485 apic_id)); 486 cpu_info[apic_id].cpu_present = 1; 487 if (boot_cpu) { 488 KASSERT(boot_cpu_id == -1, 489 ("CPU %d claims to be BSP, but CPU %d already is", apic_id, 490 boot_cpu_id)); 491 boot_cpu_id = apic_id; 492 cpu_info[apic_id].cpu_bsp = 1; 493 } 494 if (mp_ncpus < MAXCPU) { 495 mp_ncpus++; 496 mp_maxid = mp_ncpus - 1; 497 } 498 if (bootverbose) 499 printf("SMP: Added CPU %d (%s)\n", apic_id, boot_cpu ? "BSP" : 500 "AP"); 501} 502 503void 504cpu_mp_setmaxid(void) 505{ 506 507 /* 508 * mp_maxid should be already set by calls to cpu_add(). 509 * Just sanity check its value here. 510 */ 511 if (mp_ncpus == 0) 512 KASSERT(mp_maxid == 0, 513 ("%s: mp_ncpus is zero, but mp_maxid is not", __func__)); 514 else if (mp_ncpus == 1) 515 mp_maxid = 0; 516 else 517 KASSERT(mp_maxid >= mp_ncpus - 1, 518 ("%s: counters out of sync: max %d, count %d", __func__, 519 mp_maxid, mp_ncpus)); 520} 521 522int 523cpu_mp_probe(void) 524{ 525 526 /* 527 * Always record BSP in CPU map so that the mbuf init code works 528 * correctly. 529 */ 530 CPU_SETOF(0, &all_cpus); 531 if (mp_ncpus == 0) { 532 /* 533 * No CPUs were found, so this must be a UP system. Setup 534 * the variables to represent a system with a single CPU 535 * with an id of 0. 536 */ 537 mp_ncpus = 1; 538 return (0); 539 } 540 541 /* At least one CPU was found. */ 542 if (mp_ncpus == 1) { 543 /* 544 * One CPU was found, so this must be a UP system with 545 * an I/O APIC. 546 */ 547 mp_maxid = 0; 548 return (0); 549 } 550 551 /* At least two CPUs were found. */ 552 return (1); 553} 554 555/* 556 * Initialize the IPI handlers and start up the AP's. 557 */ 558void 559cpu_mp_start(void) 560{ 561 int i; 562 563 /* Initialize the logical ID to APIC ID table. */ 564 for (i = 0; i < MAXCPU; i++) { 565 cpu_apic_ids[i] = -1; 566 cpu_ipi_pending[i] = 0; 567 } 568 569 /* Install an inter-CPU IPI for TLB invalidation */ 570 setidt(IPI_INVLTLB, IDTVEC(invltlb), 571 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 572 setidt(IPI_INVLPG, IDTVEC(invlpg), 573 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 574 setidt(IPI_INVLRNG, IDTVEC(invlrng), 575 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 576 577 /* Install an inter-CPU IPI for cache invalidation. */ 578 setidt(IPI_INVLCACHE, IDTVEC(invlcache), 579 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 580 581 /* Install an inter-CPU IPI for lazy pmap release */ 582 setidt(IPI_LAZYPMAP, IDTVEC(lazypmap), 583 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 584 585 /* Install an inter-CPU IPI for all-CPU rendezvous */ 586 setidt(IPI_RENDEZVOUS, IDTVEC(rendezvous), 587 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 588 589 /* Install generic inter-CPU IPI handler */ 590 setidt(IPI_BITMAP_VECTOR, IDTVEC(ipi_intr_bitmap_handler), 591 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 592 593 /* Install an inter-CPU IPI for CPU stop/restart */ 594 setidt(IPI_STOP, IDTVEC(cpustop), 595 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 596 597 /* Install an inter-CPU IPI for CPU suspend/resume */ 598 setidt(IPI_SUSPEND, IDTVEC(cpususpend), 599 SDT_SYS386IGT, SEL_KPL, GSEL(GCODE_SEL, SEL_KPL)); 600 601 /* Set boot_cpu_id if needed. */ 602 if (boot_cpu_id == -1) { 603 boot_cpu_id = PCPU_GET(apic_id); 604 cpu_info[boot_cpu_id].cpu_bsp = 1; 605 } else 606 KASSERT(boot_cpu_id == PCPU_GET(apic_id), 607 ("BSP's APIC ID doesn't match boot_cpu_id")); 608 609 /* Probe logical/physical core configuration. */ 610 topo_probe(); 611 612 assign_cpu_ids(); 613 614 /* Start each Application Processor */ 615 start_all_aps(); 616 617 set_interrupt_apic_ids(); 618} 619 620 621/* 622 * Print various information about the SMP system hardware and setup. 623 */ 624void 625cpu_mp_announce(void) 626{ 627 const char *hyperthread; 628 int i; 629 630 printf("FreeBSD/SMP: %d package(s) x %d core(s)", 631 mp_ncpus / (cpu_cores * cpu_logical), cpu_cores); 632 if (hyperthreading_cpus > 1) 633 printf(" x %d HTT threads", cpu_logical); 634 else if (cpu_logical > 1) 635 printf(" x %d SMT threads", cpu_logical); 636 printf("\n"); 637 638 /* List active CPUs first. */ 639 printf(" cpu0 (BSP): APIC ID: %2d\n", boot_cpu_id); 640 for (i = 1; i < mp_ncpus; i++) { 641 if (cpu_info[cpu_apic_ids[i]].cpu_hyperthread) 642 hyperthread = "/HT"; 643 else 644 hyperthread = ""; 645 printf(" cpu%d (AP%s): APIC ID: %2d\n", i, hyperthread, 646 cpu_apic_ids[i]); 647 } 648 649 /* List disabled CPUs last. */ 650 for (i = 0; i <= MAX_APIC_ID; i++) { 651 if (!cpu_info[i].cpu_present || !cpu_info[i].cpu_disabled) 652 continue; 653 if (cpu_info[i].cpu_hyperthread) 654 hyperthread = "/HT"; 655 else 656 hyperthread = ""; 657 printf(" cpu (AP%s): APIC ID: %2d (disabled)\n", hyperthread, 658 i); 659 } 660} 661 662/* 663 * AP CPU's call this to initialize themselves. 664 */ 665void 666init_secondary(void) 667{ 668 struct pcpu *pc; 669 vm_offset_t addr; 670 int gsel_tss; 671 int x, myid; 672 u_int cpuid, cr0; 673 674 /* bootAP is set in start_ap() to our ID. */ 675 myid = bootAP; 676 677 /* Get per-cpu data */ 678 pc = &__pcpu[myid]; 679 680 /* prime data page for it to use */ 681 pcpu_init(pc, myid, sizeof(struct pcpu)); 682 dpcpu_init(dpcpu, myid); 683 pc->pc_apic_id = cpu_apic_ids[myid]; 684 pc->pc_prvspace = pc; 685 pc->pc_curthread = 0; 686 687 fix_cpuid(); 688 689 gdt_segs[GPRIV_SEL].ssd_base = (int) pc; 690 gdt_segs[GPROC0_SEL].ssd_base = (int) &pc->pc_common_tss; 691 692 for (x = 0; x < NGDT; x++) { 693 ssdtosd(&gdt_segs[x], &gdt[myid * NGDT + x].sd); 694 } 695 696 r_gdt.rd_limit = NGDT * sizeof(gdt[0]) - 1; 697 r_gdt.rd_base = (int) &gdt[myid * NGDT]; 698 lgdt(&r_gdt); /* does magic intra-segment return */ 699 700 lidt(&r_idt); 701 702 lldt(_default_ldt); 703 PCPU_SET(currentldt, _default_ldt); 704 705 gsel_tss = GSEL(GPROC0_SEL, SEL_KPL); 706 gdt[myid * NGDT + GPROC0_SEL].sd.sd_type = SDT_SYS386TSS; 707 PCPU_SET(common_tss.tss_esp0, 0); /* not used until after switch */ 708 PCPU_SET(common_tss.tss_ss0, GSEL(GDATA_SEL, SEL_KPL)); 709 PCPU_SET(common_tss.tss_ioopt, (sizeof (struct i386tss)) << 16); 710 PCPU_SET(tss_gdt, &gdt[myid * NGDT + GPROC0_SEL].sd); 711 PCPU_SET(common_tssd, *PCPU_GET(tss_gdt)); 712 ltr(gsel_tss); 713 714 PCPU_SET(fsgs_gdt, &gdt[myid * NGDT + GUFS_SEL].sd); 715 716 /* 717 * Set to a known state: 718 * Set by mpboot.s: CR0_PG, CR0_PE 719 * Set by cpu_setregs: CR0_NE, CR0_MP, CR0_TS, CR0_WP, CR0_AM 720 */ 721 cr0 = rcr0(); 722 cr0 &= ~(CR0_CD | CR0_NW | CR0_EM); 723 load_cr0(cr0); 724 CHECK_WRITE(0x38, 5); 725 726 /* Disable local APIC just to be sure. */ 727 lapic_disable(); 728 729 /* signal our startup to the BSP. */ 730 mp_naps++; 731 CHECK_WRITE(0x39, 6); 732 733 /* Spin until the BSP releases the AP's. */ 734 while (!aps_ready) 735 ia32_pause(); 736 737 /* BSP may have changed PTD while we were waiting */ 738 invltlb(); 739 for (addr = 0; addr < NKPT * NBPDR - 1; addr += PAGE_SIZE) 740 invlpg(addr); 741 742#if defined(I586_CPU) && !defined(NO_F00F_HACK) 743 lidt(&r_idt); 744#endif 745 746 /* Initialize the PAT MSR if present. */ 747 pmap_init_pat(); 748 749 /* set up CPU registers and state */ 750 cpu_setregs(); 751 752 /* set up SSE/NX */ 753 initializecpu(); 754 755 /* set up FPU state on the AP */ 756 npxinit(false); 757 758 if (cpu_ops.cpu_init) 759 cpu_ops.cpu_init(); 760 761 /* A quick check from sanity claus */ 762 cpuid = PCPU_GET(cpuid); 763 if (PCPU_GET(apic_id) != lapic_id()) { 764 printf("SMP: cpuid = %d\n", cpuid); 765 printf("SMP: actual apic_id = %d\n", lapic_id()); 766 printf("SMP: correct apic_id = %d\n", PCPU_GET(apic_id)); 767 panic("cpuid mismatch! boom!!"); 768 } 769 770 /* Initialize curthread. */ 771 KASSERT(PCPU_GET(idlethread) != NULL, ("no idle thread")); 772 PCPU_SET(curthread, PCPU_GET(idlethread)); 773 774 mca_init(); 775 776 mtx_lock_spin(&ap_boot_mtx); 777 778 /* Init local apic for irq's */ 779 lapic_setup(1); 780 781 /* Set memory range attributes for this CPU to match the BSP */ 782 mem_range_AP_init(); 783 784 smp_cpus++; 785 786 CTR1(KTR_SMP, "SMP: AP CPU #%d Launched", cpuid); 787 printf("SMP: AP CPU #%d Launched!\n", cpuid); 788 789 /* Determine if we are a logical CPU. */ 790 /* XXX Calculation depends on cpu_logical being a power of 2, e.g. 2 */ 791 if (cpu_logical > 1 && PCPU_GET(apic_id) % cpu_logical != 0) 792 CPU_SET(cpuid, &logical_cpus_mask); 793 794 if (bootverbose) 795 lapic_dump("AP"); 796 797 if (smp_cpus == mp_ncpus) { 798 /* enable IPI's, tlb shootdown, freezes etc */ 799 atomic_store_rel_int(&smp_started, 1); 800 } 801 802 mtx_unlock_spin(&ap_boot_mtx); 803 804 /* Wait until all the AP's are up. */ 805 while (smp_started == 0) 806 ia32_pause(); 807 808 /* Start per-CPU event timers. */ 809 cpu_initclocks_ap(); 810 811 /* Enter the scheduler. */ 812 sched_throw(NULL); 813 814 panic("scheduler returned us to %s", __func__); 815 /* NOTREACHED */ 816} 817 818/******************************************************************* 819 * local functions and data 820 */ 821 822/* 823 * We tell the I/O APIC code about all the CPUs we want to receive 824 * interrupts. If we don't want certain CPUs to receive IRQs we 825 * can simply not tell the I/O APIC code about them in this function. 826 * We also do not tell it about the BSP since it tells itself about 827 * the BSP internally to work with UP kernels and on UP machines. 828 */ 829static void 830set_interrupt_apic_ids(void) 831{ 832 u_int i, apic_id; 833 834 for (i = 0; i < MAXCPU; i++) { 835 apic_id = cpu_apic_ids[i]; 836 if (apic_id == -1) 837 continue; 838 if (cpu_info[apic_id].cpu_bsp) 839 continue; 840 if (cpu_info[apic_id].cpu_disabled) 841 continue; 842 843 /* Don't let hyperthreads service interrupts. */ 844 if (hyperthreading_cpus > 1 && 845 apic_id % hyperthreading_cpus != 0) 846 continue; 847 848 intr_add_cpu(i); 849 } 850} 851 852/* 853 * Assign logical CPU IDs to local APICs. 854 */ 855static void 856assign_cpu_ids(void) 857{ 858 u_int i; 859 860 TUNABLE_INT_FETCH("machdep.hyperthreading_allowed", 861 &hyperthreading_allowed); 862 863 /* Check for explicitly disabled CPUs. */ 864 for (i = 0; i <= MAX_APIC_ID; i++) { 865 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp) 866 continue; 867 868 if (hyperthreading_cpus > 1 && i % hyperthreading_cpus != 0) { 869 cpu_info[i].cpu_hyperthread = 1; 870 871 /* 872 * Don't use HT CPU if it has been disabled by a 873 * tunable. 874 */ 875 if (hyperthreading_allowed == 0) { 876 cpu_info[i].cpu_disabled = 1; 877 continue; 878 } 879 } 880 881 /* Don't use this CPU if it has been disabled by a tunable. */ 882 if (resource_disabled("lapic", i)) { 883 cpu_info[i].cpu_disabled = 1; 884 continue; 885 } 886 } 887 888 if (hyperthreading_allowed == 0 && hyperthreading_cpus > 1) { 889 hyperthreading_cpus = 0; 890 cpu_logical = 1; 891 } 892 893 /* 894 * Assign CPU IDs to local APIC IDs and disable any CPUs 895 * beyond MAXCPU. CPU 0 is always assigned to the BSP. 896 * 897 * To minimize confusion for userland, we attempt to number 898 * CPUs such that all threads and cores in a package are 899 * grouped together. For now we assume that the BSP is always 900 * the first thread in a package and just start adding APs 901 * starting with the BSP's APIC ID. 902 */ 903 mp_ncpus = 1; 904 cpu_apic_ids[0] = boot_cpu_id; 905 apic_cpuids[boot_cpu_id] = 0; 906 for (i = boot_cpu_id + 1; i != boot_cpu_id; 907 i == MAX_APIC_ID ? i = 0 : i++) { 908 if (!cpu_info[i].cpu_present || cpu_info[i].cpu_bsp || 909 cpu_info[i].cpu_disabled) 910 continue; 911 912 if (mp_ncpus < MAXCPU) { 913 cpu_apic_ids[mp_ncpus] = i; 914 apic_cpuids[i] = mp_ncpus; 915 mp_ncpus++; 916 } else 917 cpu_info[i].cpu_disabled = 1; 918 } 919 KASSERT(mp_maxid >= mp_ncpus - 1, 920 ("%s: counters out of sync: max %d, count %d", __func__, mp_maxid, 921 mp_ncpus)); 922} 923 924/* 925 * start each AP in our list 926 */ 927/* Lowest 1MB is already mapped: don't touch*/ 928#define TMPMAP_START 1 929static int 930start_all_aps(void) 931{ 932#ifndef PC98 933 u_char mpbiosreason; 934#endif 935 u_int32_t mpbioswarmvec; 936 int apic_id, cpu, i; 937 938 mtx_init(&ap_boot_mtx, "ap boot", NULL, MTX_SPIN); 939 940 /* install the AP 1st level boot code */ 941 install_ap_tramp(); 942 943 /* save the current value of the warm-start vector */ 944 mpbioswarmvec = *((u_int32_t *) WARMBOOT_OFF); 945#ifndef PC98 946 outb(CMOS_REG, BIOS_RESET); 947 mpbiosreason = inb(CMOS_DATA); 948#endif 949 950 /* set up temporary P==V mapping for AP boot */ 951 /* XXX this is a hack, we should boot the AP on its own stack/PTD */ 952 for (i = TMPMAP_START; i < NKPT; i++) 953 PTD[i] = PTD[KPTDI + i]; 954 invltlb(); 955 956 /* start each AP */ 957 for (cpu = 1; cpu < mp_ncpus; cpu++) { 958 apic_id = cpu_apic_ids[cpu]; 959 960 /* allocate and set up a boot stack data page */ 961 bootstacks[cpu] = 962 (char *)kmem_malloc(kernel_arena, KSTACK_PAGES * PAGE_SIZE, 963 M_WAITOK | M_ZERO); 964 dpcpu = (void *)kmem_malloc(kernel_arena, DPCPU_SIZE, 965 M_WAITOK | M_ZERO); 966 /* setup a vector to our boot code */ 967 *((volatile u_short *) WARMBOOT_OFF) = WARMBOOT_TARGET; 968 *((volatile u_short *) WARMBOOT_SEG) = (boot_address >> 4); 969#ifndef PC98 970 outb(CMOS_REG, BIOS_RESET); 971 outb(CMOS_DATA, BIOS_WARM); /* 'warm-start' */ 972#endif 973 974 bootSTK = (char *)bootstacks[cpu] + KSTACK_PAGES * PAGE_SIZE - 4; 975 bootAP = cpu; 976 977 /* attempt to start the Application Processor */ 978 CHECK_INIT(99); /* setup checkpoints */ 979 if (!start_ap(apic_id)) { 980 printf("AP #%d (PHY# %d) failed!\n", cpu, apic_id); 981 CHECK_PRINT("trace"); /* show checkpoints */ 982 /* better panic as the AP may be running loose */ 983 printf("panic y/n? [y] "); 984 if (cngetc() != 'n') 985 panic("bye-bye"); 986 } 987 CHECK_PRINT("trace"); /* show checkpoints */ 988 989 CPU_SET(cpu, &all_cpus); /* record AP in CPU map */ 990 } 991 992 /* restore the warmstart vector */ 993 *(u_int32_t *) WARMBOOT_OFF = mpbioswarmvec; 994 995#ifndef PC98 996 outb(CMOS_REG, BIOS_RESET); 997 outb(CMOS_DATA, mpbiosreason); 998#endif 999 1000 /* Undo V==P hack from above */ 1001 for (i = TMPMAP_START; i < NKPT; i++) 1002 PTD[i] = 0; 1003 pmap_invalidate_range(kernel_pmap, 0, NKPT * NBPDR - 1); 1004 1005 /* number of APs actually started */ 1006 return mp_naps; 1007} 1008 1009/* 1010 * load the 1st level AP boot code into base memory. 1011 */ 1012 1013/* targets for relocation */ 1014extern void bigJump(void); 1015extern void bootCodeSeg(void); 1016extern void bootDataSeg(void); 1017extern void MPentry(void); 1018extern u_int MP_GDT; 1019extern u_int mp_gdtbase; 1020 1021static void 1022install_ap_tramp(void) 1023{ 1024 int x; 1025 int size = *(int *) ((u_long) & bootMP_size); 1026 vm_offset_t va = boot_address + KERNBASE; 1027 u_char *src = (u_char *) ((u_long) bootMP); 1028 u_char *dst = (u_char *) va; 1029 u_int boot_base = (u_int) bootMP; 1030 u_int8_t *dst8; 1031 u_int16_t *dst16; 1032 u_int32_t *dst32; 1033 1034 KASSERT (size <= PAGE_SIZE, 1035 ("'size' do not fit into PAGE_SIZE, as expected.")); 1036 pmap_kenter(va, boot_address); 1037 pmap_invalidate_page (kernel_pmap, va); 1038 for (x = 0; x < size; ++x) 1039 *dst++ = *src++; 1040 1041 /* 1042 * modify addresses in code we just moved to basemem. unfortunately we 1043 * need fairly detailed info about mpboot.s for this to work. changes 1044 * to mpboot.s might require changes here. 1045 */ 1046 1047 /* boot code is located in KERNEL space */ 1048 dst = (u_char *) va; 1049 1050 /* modify the lgdt arg */ 1051 dst32 = (u_int32_t *) (dst + ((u_int) & mp_gdtbase - boot_base)); 1052 *dst32 = boot_address + ((u_int) & MP_GDT - boot_base); 1053 1054 /* modify the ljmp target for MPentry() */ 1055 dst32 = (u_int32_t *) (dst + ((u_int) bigJump - boot_base) + 1); 1056 *dst32 = ((u_int) MPentry - KERNBASE); 1057 1058 /* modify the target for boot code segment */ 1059 dst16 = (u_int16_t *) (dst + ((u_int) bootCodeSeg - boot_base)); 1060 dst8 = (u_int8_t *) (dst16 + 1); 1061 *dst16 = (u_int) boot_address & 0xffff; 1062 *dst8 = ((u_int) boot_address >> 16) & 0xff; 1063 1064 /* modify the target for boot data segment */ 1065 dst16 = (u_int16_t *) (dst + ((u_int) bootDataSeg - boot_base)); 1066 dst8 = (u_int8_t *) (dst16 + 1); 1067 *dst16 = (u_int) boot_address & 0xffff; 1068 *dst8 = ((u_int) boot_address >> 16) & 0xff; 1069} 1070 1071/* 1072 * This function starts the AP (application processor) identified 1073 * by the APIC ID 'physicalCpu'. It does quite a "song and dance" 1074 * to accomplish this. This is necessary because of the nuances 1075 * of the different hardware we might encounter. It isn't pretty, 1076 * but it seems to work. 1077 */ 1078static int 1079start_ap(int apic_id) 1080{ 1081 int vector, ms; 1082 int cpus; 1083 1084 /* calculate the vector */ 1085 vector = (boot_address >> 12) & 0xff; 1086 1087 /* used as a watchpoint to signal AP startup */ 1088 cpus = mp_naps; 1089 1090 ipi_startup(apic_id, vector); 1091 1092 /* Wait up to 5 seconds for it to start. */ 1093 for (ms = 0; ms < 5000; ms++) { 1094 if (mp_naps > cpus) 1095 return 1; /* return SUCCESS */ 1096 DELAY(1000); 1097 } 1098 return 0; /* return FAILURE */ 1099} 1100 1101#ifdef COUNT_XINVLTLB_HITS 1102u_int xhits_gbl[MAXCPU]; 1103u_int xhits_pg[MAXCPU]; 1104u_int xhits_rng[MAXCPU]; 1105static SYSCTL_NODE(_debug, OID_AUTO, xhits, CTLFLAG_RW, 0, ""); 1106SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, global, CTLFLAG_RW, &xhits_gbl, 1107 sizeof(xhits_gbl), "IU", ""); 1108SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, page, CTLFLAG_RW, &xhits_pg, 1109 sizeof(xhits_pg), "IU", ""); 1110SYSCTL_OPAQUE(_debug_xhits, OID_AUTO, range, CTLFLAG_RW, &xhits_rng, 1111 sizeof(xhits_rng), "IU", ""); 1112 1113u_int ipi_global; 1114u_int ipi_page; 1115u_int ipi_range; 1116u_int ipi_range_size; 1117SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_global, CTLFLAG_RW, &ipi_global, 0, ""); 1118SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_page, CTLFLAG_RW, &ipi_page, 0, ""); 1119SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range, CTLFLAG_RW, &ipi_range, 0, ""); 1120SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_range_size, CTLFLAG_RW, &ipi_range_size, 1121 0, ""); 1122 1123u_int ipi_masked_global; 1124u_int ipi_masked_page; 1125u_int ipi_masked_range; 1126u_int ipi_masked_range_size; 1127SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_global, CTLFLAG_RW, 1128 &ipi_masked_global, 0, ""); 1129SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_page, CTLFLAG_RW, 1130 &ipi_masked_page, 0, ""); 1131SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range, CTLFLAG_RW, 1132 &ipi_masked_range, 0, ""); 1133SYSCTL_INT(_debug_xhits, OID_AUTO, ipi_masked_range_size, CTLFLAG_RW, 1134 &ipi_masked_range_size, 0, ""); 1135#endif /* COUNT_XINVLTLB_HITS */ 1136 1137/* 1138 * Init and startup IPI. 1139 */ 1140void 1141ipi_startup(int apic_id, int vector) 1142{ 1143 1144 /* 1145 * This attempts to follow the algorithm described in the 1146 * Intel Multiprocessor Specification v1.4 in section B.4. 1147 * For each IPI, we allow the local APIC ~20us to deliver the 1148 * IPI. If that times out, we panic. 1149 */ 1150 1151 /* 1152 * first we do an INIT IPI: this INIT IPI might be run, resetting 1153 * and running the target CPU. OR this INIT IPI might be latched (P5 1154 * bug), CPU waiting for STARTUP IPI. OR this INIT IPI might be 1155 * ignored. 1156 */ 1157 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_LEVEL | 1158 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, apic_id); 1159 lapic_ipi_wait(100); 1160 1161 /* Explicitly deassert the INIT IPI. */ 1162 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_LEVEL | 1163 APIC_LEVEL_DEASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_INIT, 1164 apic_id); 1165 1166 DELAY(10000); /* wait ~10mS */ 1167 1168 /* 1169 * next we do a STARTUP IPI: the previous INIT IPI might still be 1170 * latched, (P5 bug) this 1st STARTUP would then terminate 1171 * immediately, and the previously started INIT IPI would continue. OR 1172 * the previous INIT IPI has already run. and this STARTUP IPI will 1173 * run. OR the previous INIT IPI was ignored. and this STARTUP IPI 1174 * will run. 1175 */ 1176 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 1177 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | 1178 vector, apic_id); 1179 if (!lapic_ipi_wait(100)) 1180 panic("Failed to deliver first STARTUP IPI to APIC %d", 1181 apic_id); 1182 DELAY(200); /* wait ~200uS */ 1183 1184 /* 1185 * finally we do a 2nd STARTUP IPI: this 2nd STARTUP IPI should run IF 1186 * the previous STARTUP IPI was cancelled by a latched INIT IPI. OR 1187 * this STARTUP IPI will be ignored, as only ONE STARTUP IPI is 1188 * recognized after hardware RESET or INIT IPI. 1189 */ 1190 lapic_ipi_raw(APIC_DEST_DESTFLD | APIC_TRIGMOD_EDGE | 1191 APIC_LEVEL_ASSERT | APIC_DESTMODE_PHY | APIC_DELMODE_STARTUP | 1192 vector, apic_id); 1193 if (!lapic_ipi_wait(100)) 1194 panic("Failed to deliver second STARTUP IPI to APIC %d", 1195 apic_id); 1196 1197 DELAY(200); /* wait ~200uS */ 1198} 1199 1200/* 1201 * Send an IPI to specified CPU handling the bitmap logic. 1202 */ 1203static void 1204ipi_send_cpu(int cpu, u_int ipi) 1205{ 1206 u_int bitmap, old_pending, new_pending; 1207 1208 KASSERT(cpu_apic_ids[cpu] != -1, ("IPI to non-existent CPU %d", cpu)); 1209 1210 if (IPI_IS_BITMAPED(ipi)) { 1211 bitmap = 1 << ipi; 1212 ipi = IPI_BITMAP_VECTOR; 1213 do { 1214 old_pending = cpu_ipi_pending[cpu]; 1215 new_pending = old_pending | bitmap; 1216 } while (!atomic_cmpset_int(&cpu_ipi_pending[cpu], 1217 old_pending, new_pending)); 1218 if (old_pending) 1219 return; 1220 } 1221 cpu_ops.ipi_vectored(ipi, cpu_apic_ids[cpu]); 1222} 1223 1224/* 1225 * Flush the TLB on all other CPU's 1226 */ 1227static void 1228smp_tlb_shootdown(u_int vector, vm_offset_t addr1, vm_offset_t addr2) 1229{ 1230 u_int ncpu; 1231 1232 ncpu = mp_ncpus - 1; /* does not shootdown self */ 1233 if (ncpu < 1) 1234 return; /* no other cpus */ 1235 if (!(read_eflags() & PSL_I)) 1236 panic("%s: interrupts disabled", __func__); 1237 mtx_lock_spin(&smp_ipi_mtx); 1238 smp_tlb_addr1 = addr1; 1239 smp_tlb_addr2 = addr2; 1240 atomic_store_rel_int(&smp_tlb_wait, 0); 1241 ipi_all_but_self(vector); 1242 while (smp_tlb_wait < ncpu) 1243 ia32_pause(); 1244 mtx_unlock_spin(&smp_ipi_mtx); 1245} 1246 1247static void 1248smp_targeted_tlb_shootdown(cpuset_t mask, u_int vector, vm_offset_t addr1, vm_offset_t addr2) 1249{ 1250 int cpu, ncpu, othercpus; 1251 1252 othercpus = mp_ncpus - 1; 1253 if (CPU_ISFULLSET(&mask)) { 1254 if (othercpus < 1) 1255 return; 1256 } else { 1257 CPU_CLR(PCPU_GET(cpuid), &mask); 1258 if (CPU_EMPTY(&mask)) 1259 return; 1260 } 1261 if (!(read_eflags() & PSL_I)) 1262 panic("%s: interrupts disabled", __func__); 1263 mtx_lock_spin(&smp_ipi_mtx); 1264 smp_tlb_addr1 = addr1; 1265 smp_tlb_addr2 = addr2; 1266 atomic_store_rel_int(&smp_tlb_wait, 0); 1267 if (CPU_ISFULLSET(&mask)) { 1268 ncpu = othercpus; 1269 ipi_all_but_self(vector); 1270 } else { 1271 ncpu = 0; 1272 while ((cpu = CPU_FFS(&mask)) != 0) { 1273 cpu--; 1274 CPU_CLR(cpu, &mask); 1275 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, 1276 vector); 1277 ipi_send_cpu(cpu, vector); 1278 ncpu++; 1279 } 1280 } 1281 while (smp_tlb_wait < ncpu) 1282 ia32_pause(); 1283 mtx_unlock_spin(&smp_ipi_mtx); 1284} 1285 1286void 1287smp_cache_flush(void) 1288{ 1289 1290 if (smp_started) 1291 smp_tlb_shootdown(IPI_INVLCACHE, 0, 0); 1292} 1293 1294void 1295smp_invltlb(void) 1296{ 1297 1298 if (smp_started) { 1299 smp_tlb_shootdown(IPI_INVLTLB, 0, 0); 1300#ifdef COUNT_XINVLTLB_HITS 1301 ipi_global++; 1302#endif 1303 } 1304} 1305 1306void 1307smp_invlpg(vm_offset_t addr) 1308{ 1309 1310 if (smp_started) { 1311 smp_tlb_shootdown(IPI_INVLPG, addr, 0); 1312#ifdef COUNT_XINVLTLB_HITS 1313 ipi_page++; 1314#endif 1315 } 1316} 1317 1318void 1319smp_invlpg_range(vm_offset_t addr1, vm_offset_t addr2) 1320{ 1321 1322 if (smp_started) { 1323 smp_tlb_shootdown(IPI_INVLRNG, addr1, addr2); 1324#ifdef COUNT_XINVLTLB_HITS 1325 ipi_range++; 1326 ipi_range_size += (addr2 - addr1) / PAGE_SIZE; 1327#endif 1328 } 1329} 1330 1331void 1332smp_masked_invltlb(cpuset_t mask) 1333{ 1334 1335 if (smp_started) { 1336 smp_targeted_tlb_shootdown(mask, IPI_INVLTLB, 0, 0); 1337#ifdef COUNT_XINVLTLB_HITS 1338 ipi_masked_global++; 1339#endif 1340 } 1341} 1342 1343void 1344smp_masked_invlpg(cpuset_t mask, vm_offset_t addr) 1345{ 1346 1347 if (smp_started) { 1348 smp_targeted_tlb_shootdown(mask, IPI_INVLPG, addr, 0); 1349#ifdef COUNT_XINVLTLB_HITS 1350 ipi_masked_page++; 1351#endif 1352 } 1353} 1354 1355void 1356smp_masked_invlpg_range(cpuset_t mask, vm_offset_t addr1, vm_offset_t addr2) 1357{ 1358 1359 if (smp_started) { 1360 smp_targeted_tlb_shootdown(mask, IPI_INVLRNG, addr1, addr2); 1361#ifdef COUNT_XINVLTLB_HITS 1362 ipi_masked_range++; 1363 ipi_masked_range_size += (addr2 - addr1) / PAGE_SIZE; 1364#endif 1365 } 1366} 1367 1368void 1369ipi_bitmap_handler(struct trapframe frame) 1370{ 1371 struct trapframe *oldframe; 1372 struct thread *td; 1373 int cpu = PCPU_GET(cpuid); 1374 u_int ipi_bitmap; 1375 1376 critical_enter(); 1377 td = curthread; 1378 td->td_intr_nesting_level++; 1379 oldframe = td->td_intr_frame; 1380 td->td_intr_frame = &frame; 1381 ipi_bitmap = atomic_readandclear_int(&cpu_ipi_pending[cpu]); 1382 if (ipi_bitmap & (1 << IPI_PREEMPT)) { 1383#ifdef COUNT_IPIS 1384 (*ipi_preempt_counts[cpu])++; 1385#endif 1386 sched_preempt(td); 1387 } 1388 if (ipi_bitmap & (1 << IPI_AST)) { 1389#ifdef COUNT_IPIS 1390 (*ipi_ast_counts[cpu])++; 1391#endif 1392 /* Nothing to do for AST */ 1393 } 1394 if (ipi_bitmap & (1 << IPI_HARDCLOCK)) { 1395#ifdef COUNT_IPIS 1396 (*ipi_hardclock_counts[cpu])++; 1397#endif 1398 hardclockintr(); 1399 } 1400 td->td_intr_frame = oldframe; 1401 td->td_intr_nesting_level--; 1402 critical_exit(); 1403} 1404 1405/* 1406 * send an IPI to a set of cpus. 1407 */ 1408void 1409ipi_selected(cpuset_t cpus, u_int ipi) 1410{ 1411 int cpu; 1412 1413 /* 1414 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit 1415 * of help in order to understand what is the source. 1416 * Set the mask of receiving CPUs for this purpose. 1417 */ 1418 if (ipi == IPI_STOP_HARD) 1419 CPU_OR_ATOMIC(&ipi_nmi_pending, &cpus); 1420 1421 while ((cpu = CPU_FFS(&cpus)) != 0) { 1422 cpu--; 1423 CPU_CLR(cpu, &cpus); 1424 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi); 1425 ipi_send_cpu(cpu, ipi); 1426 } 1427} 1428 1429/* 1430 * send an IPI to a specific CPU. 1431 */ 1432void 1433ipi_cpu(int cpu, u_int ipi) 1434{ 1435 1436 /* 1437 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit 1438 * of help in order to understand what is the source. 1439 * Set the mask of receiving CPUs for this purpose. 1440 */ 1441 if (ipi == IPI_STOP_HARD) 1442 CPU_SET_ATOMIC(cpu, &ipi_nmi_pending); 1443 1444 CTR3(KTR_SMP, "%s: cpu: %d ipi: %x", __func__, cpu, ipi); 1445 ipi_send_cpu(cpu, ipi); 1446} 1447 1448/* 1449 * send an IPI to all CPUs EXCEPT myself 1450 */ 1451void 1452ipi_all_but_self(u_int ipi) 1453{ 1454 cpuset_t other_cpus; 1455 1456 other_cpus = all_cpus; 1457 CPU_CLR(PCPU_GET(cpuid), &other_cpus); 1458 if (IPI_IS_BITMAPED(ipi)) { 1459 ipi_selected(other_cpus, ipi); 1460 return; 1461 } 1462 1463 /* 1464 * IPI_STOP_HARD maps to a NMI and the trap handler needs a bit 1465 * of help in order to understand what is the source. 1466 * Set the mask of receiving CPUs for this purpose. 1467 */ 1468 if (ipi == IPI_STOP_HARD) 1469 CPU_OR_ATOMIC(&ipi_nmi_pending, &other_cpus); 1470 1471 CTR2(KTR_SMP, "%s: ipi: %x", __func__, ipi); 1472 cpu_ops.ipi_vectored(ipi, APIC_IPI_DEST_OTHERS); 1473} 1474 1475int 1476ipi_nmi_handler() 1477{ 1478 u_int cpuid; 1479 1480 /* 1481 * As long as there is not a simple way to know about a NMI's 1482 * source, if the bitmask for the current CPU is present in 1483 * the global pending bitword an IPI_STOP_HARD has been issued 1484 * and should be handled. 1485 */ 1486 cpuid = PCPU_GET(cpuid); 1487 if (!CPU_ISSET(cpuid, &ipi_nmi_pending)) 1488 return (1); 1489 1490 CPU_CLR_ATOMIC(cpuid, &ipi_nmi_pending); 1491 cpustop_handler(); 1492 return (0); 1493} 1494 1495/* 1496 * Handle an IPI_STOP by saving our current context and spinning until we 1497 * are resumed. 1498 */ 1499void 1500cpustop_handler(void) 1501{ 1502 u_int cpu; 1503 1504 cpu = PCPU_GET(cpuid); 1505 1506 savectx(&stoppcbs[cpu]); 1507 1508 /* Indicate that we are stopped */ 1509 CPU_SET_ATOMIC(cpu, &stopped_cpus); 1510 1511 /* Wait for restart */ 1512 while (!CPU_ISSET(cpu, &started_cpus)) 1513 ia32_pause(); 1514 1515 CPU_CLR_ATOMIC(cpu, &started_cpus); 1516 CPU_CLR_ATOMIC(cpu, &stopped_cpus); 1517 1518 if (cpu == 0 && cpustop_restartfunc != NULL) { 1519 cpustop_restartfunc(); 1520 cpustop_restartfunc = NULL; 1521 } 1522} 1523 1524/* 1525 * Handle an IPI_SUSPEND by saving our current context and spinning until we 1526 * are resumed. 1527 */ 1528void 1529cpususpend_handler(void) 1530{ 1531 u_int cpu; 1532 1533 mtx_assert(&smp_ipi_mtx, MA_NOTOWNED); 1534 1535 cpu = PCPU_GET(cpuid); 1536 if (savectx(&susppcbs[cpu]->sp_pcb)) { 1537 npxsuspend(susppcbs[cpu]->sp_fpususpend); 1538 wbinvd(); 1539 CPU_SET_ATOMIC(cpu, &suspended_cpus); 1540 } else { 1541 npxresume(susppcbs[cpu]->sp_fpususpend); 1542 pmap_init_pat(); 1543 initializecpu(); 1544 PCPU_SET(switchtime, 0); 1545 PCPU_SET(switchticks, ticks); 1546 1547 /* Indicate that we are resumed */ 1548 CPU_CLR_ATOMIC(cpu, &suspended_cpus); 1549 } 1550 1551 /* Wait for resume */ 1552 while (!CPU_ISSET(cpu, &started_cpus)) 1553 ia32_pause(); 1554 1555 if (cpu_ops.cpu_resume) 1556 cpu_ops.cpu_resume(); 1557 1558 /* Resume MCA and local APIC */ 1559 mca_resume(); 1560 lapic_setup(0); 1561 1562 /* Indicate that we are resumed */ 1563 CPU_CLR_ATOMIC(cpu, &suspended_cpus); 1564 CPU_CLR_ATOMIC(cpu, &started_cpus); 1565} 1566 1567/* 1568 * Handlers for TLB related IPIs 1569 */ 1570void 1571invltlb_handler(void) 1572{ 1573 uint64_t cr3; 1574#ifdef COUNT_XINVLTLB_HITS 1575 xhits_gbl[PCPU_GET(cpuid)]++; 1576#endif /* COUNT_XINVLTLB_HITS */ 1577#ifdef COUNT_IPIS 1578 (*ipi_invltlb_counts[PCPU_GET(cpuid)])++; 1579#endif /* COUNT_IPIS */ 1580 1581 cr3 = rcr3(); 1582 load_cr3(cr3); 1583 atomic_add_int(&smp_tlb_wait, 1); 1584} 1585 1586void 1587invlpg_handler(void) 1588{ 1589#ifdef COUNT_XINVLTLB_HITS 1590 xhits_pg[PCPU_GET(cpuid)]++; 1591#endif /* COUNT_XINVLTLB_HITS */ 1592#ifdef COUNT_IPIS 1593 (*ipi_invlpg_counts[PCPU_GET(cpuid)])++; 1594#endif /* COUNT_IPIS */ 1595 1596 invlpg(smp_tlb_addr1); 1597 1598 atomic_add_int(&smp_tlb_wait, 1); 1599} 1600 1601void 1602invlrng_handler(void) 1603{ 1604 vm_offset_t addr; 1605#ifdef COUNT_XINVLTLB_HITS 1606 xhits_rng[PCPU_GET(cpuid)]++; 1607#endif /* COUNT_XINVLTLB_HITS */ 1608#ifdef COUNT_IPIS 1609 (*ipi_invlrng_counts[PCPU_GET(cpuid)])++; 1610#endif /* COUNT_IPIS */ 1611 1612 addr = smp_tlb_addr1; 1613 do { 1614 invlpg(addr); 1615 addr += PAGE_SIZE; 1616 } while (addr < smp_tlb_addr2); 1617 1618 atomic_add_int(&smp_tlb_wait, 1); 1619} 1620 1621void 1622invlcache_handler(void) 1623{ 1624#ifdef COUNT_IPIS 1625 (*ipi_invlcache_counts[PCPU_GET(cpuid)])++; 1626#endif /* COUNT_IPIS */ 1627 1628 wbinvd(); 1629 atomic_add_int(&smp_tlb_wait, 1); 1630} 1631 1632/* 1633 * This is called once the rest of the system is up and running and we're 1634 * ready to let the AP's out of the pen. 1635 */ 1636static void 1637release_aps(void *dummy __unused) 1638{ 1639 1640 if (mp_ncpus == 1) 1641 return; 1642 atomic_store_rel_int(&aps_ready, 1); 1643 while (smp_started == 0) 1644 ia32_pause(); 1645} 1646SYSINIT(start_aps, SI_SUB_SMP, SI_ORDER_FIRST, release_aps, NULL); 1647 1648#ifdef COUNT_IPIS 1649/* 1650 * Setup interrupt counters for IPI handlers. 1651 */ 1652static void 1653mp_ipi_intrcnt(void *dummy) 1654{ 1655 char buf[64]; 1656 int i; 1657 1658 CPU_FOREACH(i) { 1659 snprintf(buf, sizeof(buf), "cpu%d:invltlb", i); 1660 intrcnt_add(buf, &ipi_invltlb_counts[i]); 1661 snprintf(buf, sizeof(buf), "cpu%d:invlrng", i); 1662 intrcnt_add(buf, &ipi_invlrng_counts[i]); 1663 snprintf(buf, sizeof(buf), "cpu%d:invlpg", i); 1664 intrcnt_add(buf, &ipi_invlpg_counts[i]); 1665 snprintf(buf, sizeof(buf), "cpu%d:invlcache", i); 1666 intrcnt_add(buf, &ipi_invlcache_counts[i]); 1667 snprintf(buf, sizeof(buf), "cpu%d:preempt", i); 1668 intrcnt_add(buf, &ipi_preempt_counts[i]); 1669 snprintf(buf, sizeof(buf), "cpu%d:ast", i); 1670 intrcnt_add(buf, &ipi_ast_counts[i]); 1671 snprintf(buf, sizeof(buf), "cpu%d:rendezvous", i); 1672 intrcnt_add(buf, &ipi_rendezvous_counts[i]); 1673 snprintf(buf, sizeof(buf), "cpu%d:lazypmap", i); 1674 intrcnt_add(buf, &ipi_lazypmap_counts[i]); 1675 snprintf(buf, sizeof(buf), "cpu%d:hardclock", i); 1676 intrcnt_add(buf, &ipi_hardclock_counts[i]); 1677 } 1678} 1679SYSINIT(mp_ipi_intrcnt, SI_SUB_INTR, SI_ORDER_MIDDLE, mp_ipi_intrcnt, NULL); 1680#endif 1681