initcpu.c revision 277374
1/*- 2 * Copyright (c) KATO Takenori, 1997, 1998. 3 * 4 * All rights reserved. Unpublished rights reserved under the copyright 5 * laws of Japan. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer as 13 * the first lines of this file unmodified. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: stable/10/sys/i386/i386/initcpu.c 277374 2015-01-19 10:52:55Z kib $"); 32 33#include "opt_cpu.h" 34 35#include <sys/param.h> 36#include <sys/kernel.h> 37#include <sys/systm.h> 38#include <sys/sysctl.h> 39 40#include <machine/cputypes.h> 41#include <machine/md_var.h> 42#include <machine/specialreg.h> 43 44#include <vm/vm.h> 45#include <vm/pmap.h> 46 47#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU) 48#define CPU_ENABLE_SSE 49#endif 50 51#ifdef I486_CPU 52static void init_5x86(void); 53static void init_bluelightning(void); 54static void init_486dlc(void); 55static void init_cy486dx(void); 56#ifdef CPU_I486_ON_386 57static void init_i486_on_386(void); 58#endif 59static void init_6x86(void); 60#endif /* I486_CPU */ 61 62#if defined(I586_CPU) && defined(CPU_WT_ALLOC) 63static void enable_K5_wt_alloc(void); 64static void enable_K6_wt_alloc(void); 65static void enable_K6_2_wt_alloc(void); 66#endif 67 68#ifdef I686_CPU 69static void init_6x86MX(void); 70static void init_ppro(void); 71static void init_mendocino(void); 72#endif 73 74static int hw_instruction_sse; 75SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD, 76 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU"); 77/* 78 * -1: automatic (default) 79 * 0: keep enable CLFLUSH 80 * 1: force disable CLFLUSH 81 */ 82static int hw_clflush_disable = -1; 83 84int cpu; /* Are we 386, 386sx, 486, etc? */ 85u_int cpu_feature; /* Feature flags */ 86u_int cpu_feature2; /* Feature flags */ 87u_int amd_feature; /* AMD feature flags */ 88u_int amd_feature2; /* AMD feature flags */ 89u_int amd_pminfo; /* AMD advanced power management info */ 90u_int via_feature_rng; /* VIA RNG features */ 91u_int via_feature_xcrypt; /* VIA ACE features */ 92u_int cpu_high; /* Highest arg to CPUID */ 93u_int cpu_exthigh; /* Highest arg to extended CPUID */ 94u_int cpu_id; /* Stepping ID */ 95u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */ 96u_int cpu_procinfo2; /* Multicore info */ 97char cpu_vendor[20]; /* CPU Origin code */ 98u_int cpu_vendor_id; /* CPU vendor ID */ 99#ifdef CPU_ENABLE_SSE 100u_int cpu_fxsr; /* SSE enabled */ 101u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */ 102#endif 103u_int cpu_clflush_line_size = 32; 104u_int cpu_stdext_feature; 105u_int cpu_max_ext_state_size; 106u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */ 107u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */ 108u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */ 109u_int cyrix_did; /* Device ID of Cyrix CPU */ 110u_int cpu_maxphyaddr; /* Max phys addr width in bits */ 111 112SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD, 113 &via_feature_rng, 0, "VIA RNG feature available in CPU"); 114SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD, 115 &via_feature_xcrypt, 0, "VIA xcrypt feature available in CPU"); 116 117#ifdef I486_CPU 118/* 119 * IBM Blue Lightning 120 */ 121static void 122init_bluelightning(void) 123{ 124 register_t saveintr; 125 126#if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE) 127 need_post_dma_flush = 1; 128#endif 129 130 saveintr = intr_disable(); 131 132 load_cr0(rcr0() | CR0_CD | CR0_NW); 133 invd(); 134 135#ifdef CPU_BLUELIGHTNING_FPU_OP_CACHE 136 wrmsr(0x1000, 0x9c92LL); /* FP operand can be cacheable on Cyrix FPU */ 137#else 138 wrmsr(0x1000, 0x1c92LL); /* Intel FPU */ 139#endif 140 /* Enables 13MB and 0-640KB cache. */ 141 wrmsr(0x1001, (0xd0LL << 32) | 0x3ff); 142#ifdef CPU_BLUELIGHTNING_3X 143 wrmsr(0x1002, 0x04000000LL); /* Enables triple-clock mode. */ 144#else 145 wrmsr(0x1002, 0x03000000LL); /* Enables double-clock mode. */ 146#endif 147 148 /* Enable caching in CR0. */ 149 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 150 invd(); 151 intr_restore(saveintr); 152} 153 154/* 155 * Cyrix 486SLC/DLC/SR/DR series 156 */ 157static void 158init_486dlc(void) 159{ 160 register_t saveintr; 161 u_char ccr0; 162 163 saveintr = intr_disable(); 164 invd(); 165 166 ccr0 = read_cyrix_reg(CCR0); 167#ifndef CYRIX_CACHE_WORKS 168 ccr0 |= CCR0_NC1 | CCR0_BARB; 169 write_cyrix_reg(CCR0, ccr0); 170 invd(); 171#else 172 ccr0 &= ~CCR0_NC0; 173#ifndef CYRIX_CACHE_REALLY_WORKS 174 ccr0 |= CCR0_NC1 | CCR0_BARB; 175#else 176 ccr0 |= CCR0_NC1; 177#endif 178#ifdef CPU_DIRECT_MAPPED_CACHE 179 ccr0 |= CCR0_CO; /* Direct mapped mode. */ 180#endif 181 write_cyrix_reg(CCR0, ccr0); 182 183 /* Clear non-cacheable region. */ 184 write_cyrix_reg(NCR1+2, NCR_SIZE_0K); 185 write_cyrix_reg(NCR2+2, NCR_SIZE_0K); 186 write_cyrix_reg(NCR3+2, NCR_SIZE_0K); 187 write_cyrix_reg(NCR4+2, NCR_SIZE_0K); 188 189 write_cyrix_reg(0, 0); /* dummy write */ 190 191 /* Enable caching in CR0. */ 192 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 193 invd(); 194#endif /* !CYRIX_CACHE_WORKS */ 195 intr_restore(saveintr); 196} 197 198 199/* 200 * Cyrix 486S/DX series 201 */ 202static void 203init_cy486dx(void) 204{ 205 register_t saveintr; 206 u_char ccr2; 207 208 saveintr = intr_disable(); 209 invd(); 210 211 ccr2 = read_cyrix_reg(CCR2); 212#ifdef CPU_SUSP_HLT 213 ccr2 |= CCR2_SUSP_HLT; 214#endif 215 216#ifdef PC98 217 /* Enables WB cache interface pin and Lock NW bit in CR0. */ 218 ccr2 |= CCR2_WB | CCR2_LOCK_NW; 219 /* Unlock NW bit in CR0. */ 220 write_cyrix_reg(CCR2, ccr2 & ~CCR2_LOCK_NW); 221 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */ 222#endif 223 224 write_cyrix_reg(CCR2, ccr2); 225 intr_restore(saveintr); 226} 227 228 229/* 230 * Cyrix 5x86 231 */ 232static void 233init_5x86(void) 234{ 235 register_t saveintr; 236 u_char ccr2, ccr3, ccr4, pcr0; 237 238 saveintr = intr_disable(); 239 240 load_cr0(rcr0() | CR0_CD | CR0_NW); 241 wbinvd(); 242 243 (void)read_cyrix_reg(CCR3); /* dummy */ 244 245 /* Initialize CCR2. */ 246 ccr2 = read_cyrix_reg(CCR2); 247 ccr2 |= CCR2_WB; 248#ifdef CPU_SUSP_HLT 249 ccr2 |= CCR2_SUSP_HLT; 250#else 251 ccr2 &= ~CCR2_SUSP_HLT; 252#endif 253 ccr2 |= CCR2_WT1; 254 write_cyrix_reg(CCR2, ccr2); 255 256 /* Initialize CCR4. */ 257 ccr3 = read_cyrix_reg(CCR3); 258 write_cyrix_reg(CCR3, CCR3_MAPEN0); 259 260 ccr4 = read_cyrix_reg(CCR4); 261 ccr4 |= CCR4_DTE; 262 ccr4 |= CCR4_MEM; 263#ifdef CPU_FASTER_5X86_FPU 264 ccr4 |= CCR4_FASTFPE; 265#else 266 ccr4 &= ~CCR4_FASTFPE; 267#endif 268 ccr4 &= ~CCR4_IOMASK; 269 /******************************************************************** 270 * WARNING: The "BIOS Writers Guide" mentions that I/O recovery time 271 * should be 0 for errata fix. 272 ********************************************************************/ 273#ifdef CPU_IORT 274 ccr4 |= CPU_IORT & CCR4_IOMASK; 275#endif 276 write_cyrix_reg(CCR4, ccr4); 277 278 /* Initialize PCR0. */ 279 /**************************************************************** 280 * WARNING: RSTK_EN and LOOP_EN could make your system unstable. 281 * BTB_EN might make your system unstable. 282 ****************************************************************/ 283 pcr0 = read_cyrix_reg(PCR0); 284#ifdef CPU_RSTK_EN 285 pcr0 |= PCR0_RSTK; 286#else 287 pcr0 &= ~PCR0_RSTK; 288#endif 289#ifdef CPU_BTB_EN 290 pcr0 |= PCR0_BTB; 291#else 292 pcr0 &= ~PCR0_BTB; 293#endif 294#ifdef CPU_LOOP_EN 295 pcr0 |= PCR0_LOOP; 296#else 297 pcr0 &= ~PCR0_LOOP; 298#endif 299 300 /**************************************************************** 301 * WARNING: if you use a memory mapped I/O device, don't use 302 * DISABLE_5X86_LSSER option, which may reorder memory mapped 303 * I/O access. 304 * IF YOUR MOTHERBOARD HAS PCI BUS, DON'T DISABLE LSSER. 305 ****************************************************************/ 306#ifdef CPU_DISABLE_5X86_LSSER 307 pcr0 &= ~PCR0_LSSER; 308#else 309 pcr0 |= PCR0_LSSER; 310#endif 311 write_cyrix_reg(PCR0, pcr0); 312 313 /* Restore CCR3. */ 314 write_cyrix_reg(CCR3, ccr3); 315 316 (void)read_cyrix_reg(0x80); /* dummy */ 317 318 /* Unlock NW bit in CR0. */ 319 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW); 320 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */ 321 /* Lock NW bit in CR0. */ 322 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW); 323 324 intr_restore(saveintr); 325} 326 327#ifdef CPU_I486_ON_386 328/* 329 * There are i486 based upgrade products for i386 machines. 330 * In this case, BIOS doesn't enable CPU cache. 331 */ 332static void 333init_i486_on_386(void) 334{ 335 register_t saveintr; 336 337#if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE) 338 need_post_dma_flush = 1; 339#endif 340 341 saveintr = intr_disable(); 342 343 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0, NW = 0 */ 344 345 intr_restore(saveintr); 346} 347#endif 348 349/* 350 * Cyrix 6x86 351 * 352 * XXX - What should I do here? Please let me know. 353 */ 354static void 355init_6x86(void) 356{ 357 register_t saveintr; 358 u_char ccr3, ccr4; 359 360 saveintr = intr_disable(); 361 362 load_cr0(rcr0() | CR0_CD | CR0_NW); 363 wbinvd(); 364 365 /* Initialize CCR0. */ 366 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1); 367 368 /* Initialize CCR1. */ 369#ifdef CPU_CYRIX_NO_LOCK 370 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK); 371#else 372 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK); 373#endif 374 375 /* Initialize CCR2. */ 376#ifdef CPU_SUSP_HLT 377 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT); 378#else 379 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT); 380#endif 381 382 ccr3 = read_cyrix_reg(CCR3); 383 write_cyrix_reg(CCR3, CCR3_MAPEN0); 384 385 /* Initialize CCR4. */ 386 ccr4 = read_cyrix_reg(CCR4); 387 ccr4 |= CCR4_DTE; 388 ccr4 &= ~CCR4_IOMASK; 389#ifdef CPU_IORT 390 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK)); 391#else 392 write_cyrix_reg(CCR4, ccr4 | 7); 393#endif 394 395 /* Initialize CCR5. */ 396#ifdef CPU_WT_ALLOC 397 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC); 398#endif 399 400 /* Restore CCR3. */ 401 write_cyrix_reg(CCR3, ccr3); 402 403 /* Unlock NW bit in CR0. */ 404 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW); 405 406 /* 407 * Earlier revision of the 6x86 CPU could crash the system if 408 * L1 cache is in write-back mode. 409 */ 410 if ((cyrix_did & 0xff00) > 0x1600) 411 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 412 else { 413 /* Revision 2.6 and lower. */ 414#ifdef CYRIX_CACHE_REALLY_WORKS 415 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 416#else 417 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0 and NW = 1 */ 418#endif 419 } 420 421 /* Lock NW bit in CR0. */ 422 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW); 423 424 intr_restore(saveintr); 425} 426#endif /* I486_CPU */ 427 428#ifdef I586_CPU 429/* 430 * Rise mP6 431 */ 432static void 433init_rise(void) 434{ 435 436 /* 437 * The CMPXCHG8B instruction is always available but hidden. 438 */ 439 cpu_feature |= CPUID_CX8; 440} 441 442/* 443 * IDT WinChip C6/2/2A/2B/3 444 * 445 * http://www.centtech.com/winchip_bios_writers_guide_v4_0.pdf 446 */ 447static void 448init_winchip(void) 449{ 450 u_int regs[4]; 451 uint64_t fcr; 452 453 fcr = rdmsr(0x0107); 454 455 /* 456 * Set ECX8, DSMC, DTLOCK/EDCTLB, EMMX, and ERETSTK and clear DPDC. 457 */ 458 fcr |= (1 << 1) | (1 << 7) | (1 << 8) | (1 << 9) | (1 << 16); 459 fcr &= ~(1ULL << 11); 460 461 /* 462 * Additionally, set EBRPRED, E2MMX and EAMD3D for WinChip 2 and 3. 463 */ 464 if (CPUID_TO_MODEL(cpu_id) >= 8) 465 fcr |= (1 << 12) | (1 << 19) | (1 << 20); 466 467 wrmsr(0x0107, fcr); 468 do_cpuid(1, regs); 469 cpu_feature = regs[3]; 470} 471#endif 472 473#ifdef I686_CPU 474/* 475 * Cyrix 6x86MX (code-named M2) 476 * 477 * XXX - What should I do here? Please let me know. 478 */ 479static void 480init_6x86MX(void) 481{ 482 register_t saveintr; 483 u_char ccr3, ccr4; 484 485 saveintr = intr_disable(); 486 487 load_cr0(rcr0() | CR0_CD | CR0_NW); 488 wbinvd(); 489 490 /* Initialize CCR0. */ 491 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1); 492 493 /* Initialize CCR1. */ 494#ifdef CPU_CYRIX_NO_LOCK 495 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK); 496#else 497 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK); 498#endif 499 500 /* Initialize CCR2. */ 501#ifdef CPU_SUSP_HLT 502 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT); 503#else 504 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT); 505#endif 506 507 ccr3 = read_cyrix_reg(CCR3); 508 write_cyrix_reg(CCR3, CCR3_MAPEN0); 509 510 /* Initialize CCR4. */ 511 ccr4 = read_cyrix_reg(CCR4); 512 ccr4 &= ~CCR4_IOMASK; 513#ifdef CPU_IORT 514 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK)); 515#else 516 write_cyrix_reg(CCR4, ccr4 | 7); 517#endif 518 519 /* Initialize CCR5. */ 520#ifdef CPU_WT_ALLOC 521 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC); 522#endif 523 524 /* Restore CCR3. */ 525 write_cyrix_reg(CCR3, ccr3); 526 527 /* Unlock NW bit in CR0. */ 528 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW); 529 530 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 531 532 /* Lock NW bit in CR0. */ 533 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW); 534 535 intr_restore(saveintr); 536} 537 538static int ppro_apic_used = -1; 539 540static void 541init_ppro(void) 542{ 543 u_int64_t apicbase; 544 545 /* 546 * Local APIC should be disabled if it is not going to be used. 547 */ 548 if (ppro_apic_used != 1) { 549 apicbase = rdmsr(MSR_APICBASE); 550 apicbase &= ~APICBASE_ENABLED; 551 wrmsr(MSR_APICBASE, apicbase); 552 ppro_apic_used = 0; 553 } 554} 555 556/* 557 * If the local APIC is going to be used after being disabled above, 558 * re-enable it and don't disable it in the future. 559 */ 560void 561ppro_reenable_apic(void) 562{ 563 u_int64_t apicbase; 564 565 if (ppro_apic_used == 0) { 566 apicbase = rdmsr(MSR_APICBASE); 567 apicbase |= APICBASE_ENABLED; 568 wrmsr(MSR_APICBASE, apicbase); 569 ppro_apic_used = 1; 570 } 571} 572 573/* 574 * Initialize BBL_CR_CTL3 (Control register 3: used to configure the 575 * L2 cache). 576 */ 577static void 578init_mendocino(void) 579{ 580#ifdef CPU_PPRO2CELERON 581 register_t saveintr; 582 u_int64_t bbl_cr_ctl3; 583 584 saveintr = intr_disable(); 585 586 load_cr0(rcr0() | CR0_CD | CR0_NW); 587 wbinvd(); 588 589 bbl_cr_ctl3 = rdmsr(MSR_BBL_CR_CTL3); 590 591 /* If the L2 cache is configured, do nothing. */ 592 if (!(bbl_cr_ctl3 & 1)) { 593 bbl_cr_ctl3 = 0x134052bLL; 594 595 /* Set L2 Cache Latency (Default: 5). */ 596#ifdef CPU_CELERON_L2_LATENCY 597#if CPU_L2_LATENCY > 15 598#error invalid CPU_L2_LATENCY. 599#endif 600 bbl_cr_ctl3 |= CPU_L2_LATENCY << 1; 601#else 602 bbl_cr_ctl3 |= 5 << 1; 603#endif 604 wrmsr(MSR_BBL_CR_CTL3, bbl_cr_ctl3); 605 } 606 607 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); 608 intr_restore(saveintr); 609#endif /* CPU_PPRO2CELERON */ 610} 611 612/* 613 * Initialize special VIA features 614 */ 615static void 616init_via(void) 617{ 618 u_int regs[4], val; 619 uint64_t fcr; 620 621 /* 622 * Explicitly enable CX8 and PGE on C3. 623 * 624 * http://www.via.com.tw/download/mainboards/6/13/VIA_C3_EBGA%20datasheet110.pdf 625 */ 626 if (CPUID_TO_MODEL(cpu_id) <= 9) 627 fcr = (1 << 1) | (1 << 7); 628 else 629 fcr = 0; 630 631 /* 632 * Check extended CPUID for PadLock features. 633 * 634 * http://www.via.com.tw/en/downloads/whitepapers/initiatives/padlock/programming_guide.pdf 635 */ 636 do_cpuid(0xc0000000, regs); 637 if (regs[0] >= 0xc0000001) { 638 do_cpuid(0xc0000001, regs); 639 val = regs[3]; 640 } else 641 val = 0; 642 643 /* Enable RNG if present. */ 644 if ((val & VIA_CPUID_HAS_RNG) != 0) { 645 via_feature_rng = VIA_HAS_RNG; 646 wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG); 647 } 648 649 /* Enable PadLock if present. */ 650 if ((val & VIA_CPUID_HAS_ACE) != 0) 651 via_feature_xcrypt |= VIA_HAS_AES; 652 if ((val & VIA_CPUID_HAS_ACE2) != 0) 653 via_feature_xcrypt |= VIA_HAS_AESCTR; 654 if ((val & VIA_CPUID_HAS_PHE) != 0) 655 via_feature_xcrypt |= VIA_HAS_SHA; 656 if ((val & VIA_CPUID_HAS_PMM) != 0) 657 via_feature_xcrypt |= VIA_HAS_MM; 658 if (via_feature_xcrypt != 0) 659 fcr |= 1 << 28; 660 661 wrmsr(0x1107, rdmsr(0x1107) | fcr); 662} 663 664#endif /* I686_CPU */ 665 666#if defined(I586_CPU) || defined(I686_CPU) 667static void 668init_transmeta(void) 669{ 670 u_int regs[0]; 671 672 /* Expose all hidden features. */ 673 wrmsr(0x80860004, rdmsr(0x80860004) | ~0UL); 674 do_cpuid(1, regs); 675 cpu_feature = regs[3]; 676} 677#endif 678 679extern int elf32_nxstack; 680 681void 682initializecpu(void) 683{ 684 685 switch (cpu) { 686#ifdef I486_CPU 687 case CPU_BLUE: 688 init_bluelightning(); 689 break; 690 case CPU_486DLC: 691 init_486dlc(); 692 break; 693 case CPU_CY486DX: 694 init_cy486dx(); 695 break; 696 case CPU_M1SC: 697 init_5x86(); 698 break; 699#ifdef CPU_I486_ON_386 700 case CPU_486: 701 init_i486_on_386(); 702 break; 703#endif 704 case CPU_M1: 705 init_6x86(); 706 break; 707#endif /* I486_CPU */ 708#ifdef I586_CPU 709 case CPU_586: 710 switch (cpu_vendor_id) { 711 case CPU_VENDOR_AMD: 712#ifdef CPU_WT_ALLOC 713 if (((cpu_id & 0x0f0) > 0) && 714 ((cpu_id & 0x0f0) < 0x60) && 715 ((cpu_id & 0x00f) > 3)) 716 enable_K5_wt_alloc(); 717 else if (((cpu_id & 0x0f0) > 0x80) || 718 (((cpu_id & 0x0f0) == 0x80) && 719 (cpu_id & 0x00f) > 0x07)) 720 enable_K6_2_wt_alloc(); 721 else if ((cpu_id & 0x0f0) > 0x50) 722 enable_K6_wt_alloc(); 723#endif 724 if ((cpu_id & 0xf0) == 0xa0) 725 /* 726 * Make sure the TSC runs through 727 * suspension, otherwise we can't use 728 * it as timecounter 729 */ 730 wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL); 731 break; 732 case CPU_VENDOR_CENTAUR: 733 init_winchip(); 734 break; 735 case CPU_VENDOR_TRANSMETA: 736 init_transmeta(); 737 break; 738 case CPU_VENDOR_RISE: 739 init_rise(); 740 break; 741 } 742 break; 743#endif 744#ifdef I686_CPU 745 case CPU_M2: 746 init_6x86MX(); 747 break; 748 case CPU_686: 749 switch (cpu_vendor_id) { 750 case CPU_VENDOR_INTEL: 751 switch (cpu_id & 0xff0) { 752 case 0x610: 753 init_ppro(); 754 break; 755 case 0x660: 756 init_mendocino(); 757 break; 758 } 759 break; 760#ifdef CPU_ATHLON_SSE_HACK 761 case CPU_VENDOR_AMD: 762 /* 763 * Sometimes the BIOS doesn't enable SSE instructions. 764 * According to AMD document 20734, the mobile 765 * Duron, the (mobile) Athlon 4 and the Athlon MP 766 * support SSE. These correspond to cpu_id 0x66X 767 * or 0x67X. 768 */ 769 if ((cpu_feature & CPUID_XMM) == 0 && 770 ((cpu_id & ~0xf) == 0x660 || 771 (cpu_id & ~0xf) == 0x670 || 772 (cpu_id & ~0xf) == 0x680)) { 773 u_int regs[4]; 774 wrmsr(MSR_HWCR, rdmsr(MSR_HWCR) & ~0x08000); 775 do_cpuid(1, regs); 776 cpu_feature = regs[3]; 777 } 778 break; 779#endif 780 case CPU_VENDOR_CENTAUR: 781 init_via(); 782 break; 783 case CPU_VENDOR_TRANSMETA: 784 init_transmeta(); 785 break; 786 } 787#ifdef PAE 788 if ((amd_feature & AMDID_NX) != 0) { 789 uint64_t msr; 790 791 msr = rdmsr(MSR_EFER) | EFER_NXE; 792 wrmsr(MSR_EFER, msr); 793 pg_nx = PG_NX; 794 elf32_nxstack = 1; 795 } 796#endif 797 break; 798#endif 799 default: 800 break; 801 } 802#if defined(CPU_ENABLE_SSE) 803 if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) { 804 load_cr4(rcr4() | CR4_FXSR | CR4_XMM); 805 cpu_fxsr = hw_instruction_sse = 1; 806 } 807#endif 808} 809 810void 811initializecpucache(void) 812{ 813 814 /* 815 * CPUID with %eax = 1, %ebx returns 816 * Bits 15-8: CLFLUSH line size 817 * (Value * 8 = cache line size in bytes) 818 */ 819 if ((cpu_feature & CPUID_CLFSH) != 0) 820 cpu_clflush_line_size = ((cpu_procinfo >> 8) & 0xff) * 8; 821 /* 822 * XXXKIB: (temporary) hack to work around traps generated 823 * when CLFLUSHing APIC register window under virtualization 824 * environments. These environments tend to disable the 825 * CPUID_SS feature even though the native CPU supports it. 826 */ 827 TUNABLE_INT_FETCH("hw.clflush_disable", &hw_clflush_disable); 828 if (vm_guest != VM_GUEST_NO && hw_clflush_disable == -1) 829 cpu_feature &= ~CPUID_CLFSH; 830 /* 831 * Allow to disable CLFLUSH feature manually by 832 * hw.clflush_disable tunable. 833 */ 834 if (hw_clflush_disable == 1) 835 cpu_feature &= ~CPUID_CLFSH; 836 837#if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE) 838 /* 839 * OS should flush L1 cache by itself because no PC-98 supports 840 * non-Intel CPUs. Use wbinvd instruction before DMA transfer 841 * when need_pre_dma_flush = 1, use invd instruction after DMA 842 * transfer when need_post_dma_flush = 1. If your CPU upgrade 843 * product supports hardware cache control, you can add the 844 * CPU_UPGRADE_HW_CACHE option in your kernel configuration file. 845 * This option eliminates unneeded cache flush instruction(s). 846 */ 847 if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 848 switch (cpu) { 849#ifdef I486_CPU 850 case CPU_486DLC: 851 need_post_dma_flush = 1; 852 break; 853 case CPU_M1SC: 854 need_pre_dma_flush = 1; 855 break; 856 case CPU_CY486DX: 857 need_pre_dma_flush = 1; 858#ifdef CPU_I486_ON_386 859 need_post_dma_flush = 1; 860#endif 861 break; 862#endif 863 default: 864 break; 865 } 866 } else if (cpu_vendor_id == CPU_VENDOR_AMD) { 867 switch (cpu_id & 0xFF0) { 868 case 0x470: /* Enhanced Am486DX2 WB */ 869 case 0x490: /* Enhanced Am486DX4 WB */ 870 case 0x4F0: /* Am5x86 WB */ 871 need_pre_dma_flush = 1; 872 break; 873 } 874 } else if (cpu_vendor_id == CPU_VENDOR_IBM) { 875 need_post_dma_flush = 1; 876 } else { 877#ifdef CPU_I486_ON_386 878 need_pre_dma_flush = 1; 879#endif 880 } 881#endif /* PC98 && !CPU_UPGRADE_HW_CACHE */ 882} 883 884#if defined(I586_CPU) && defined(CPU_WT_ALLOC) 885/* 886 * Enable write allocate feature of AMD processors. 887 * Following two functions require the Maxmem variable being set. 888 */ 889static void 890enable_K5_wt_alloc(void) 891{ 892 u_int64_t msr; 893 register_t saveintr; 894 895 /* 896 * Write allocate is supported only on models 1, 2, and 3, with 897 * a stepping of 4 or greater. 898 */ 899 if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) { 900 saveintr = intr_disable(); 901 msr = rdmsr(0x83); /* HWCR */ 902 wrmsr(0x83, msr & !(0x10)); 903 904 /* 905 * We have to tell the chip where the top of memory is, 906 * since video cards could have frame bufferes there, 907 * memory-mapped I/O could be there, etc. 908 */ 909 if(Maxmem > 0) 910 msr = Maxmem / 16; 911 else 912 msr = 0; 913 msr |= AMD_WT_ALLOC_TME | AMD_WT_ALLOC_FRE; 914#ifdef PC98 915 if (!(inb(0x43b) & 4)) { 916 wrmsr(0x86, 0x0ff00f0); 917 msr |= AMD_WT_ALLOC_PRE; 918 } 919#else 920 /* 921 * There is no way to know wheter 15-16M hole exists or not. 922 * Therefore, we disable write allocate for this range. 923 */ 924 wrmsr(0x86, 0x0ff00f0); 925 msr |= AMD_WT_ALLOC_PRE; 926#endif 927 wrmsr(0x85, msr); 928 929 msr=rdmsr(0x83); 930 wrmsr(0x83, msr|0x10); /* enable write allocate */ 931 intr_restore(saveintr); 932 } 933} 934 935static void 936enable_K6_wt_alloc(void) 937{ 938 quad_t size; 939 u_int64_t whcr; 940 register_t saveintr; 941 942 saveintr = intr_disable(); 943 wbinvd(); 944 945#ifdef CPU_DISABLE_CACHE 946 /* 947 * Certain K6-2 box becomes unstable when write allocation is 948 * enabled. 949 */ 950 /* 951 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12), 952 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported. 953 * All other bits in TR12 have no effect on the processer's operation. 954 * The I/O Trap Restart function (bit 9 of TR12) is always enabled 955 * on the AMD-K6. 956 */ 957 wrmsr(0x0000000e, (u_int64_t)0x0008); 958#endif 959 /* Don't assume that memory size is aligned with 4M. */ 960 if (Maxmem > 0) 961 size = ((Maxmem >> 8) + 3) >> 2; 962 else 963 size = 0; 964 965 /* Limit is 508M bytes. */ 966 if (size > 0x7f) 967 size = 0x7f; 968 whcr = (rdmsr(0xc0000082) & ~(0x7fLL << 1)) | (size << 1); 969 970#if defined(PC98) || defined(NO_MEMORY_HOLE) 971 if (whcr & (0x7fLL << 1)) { 972#ifdef PC98 973 /* 974 * If bit 2 of port 0x43b is 0, disable wrte allocate for the 975 * 15-16M range. 976 */ 977 if (!(inb(0x43b) & 4)) 978 whcr &= ~0x0001LL; 979 else 980#endif 981 whcr |= 0x0001LL; 982 } 983#else 984 /* 985 * There is no way to know wheter 15-16M hole exists or not. 986 * Therefore, we disable write allocate for this range. 987 */ 988 whcr &= ~0x0001LL; 989#endif 990 wrmsr(0x0c0000082, whcr); 991 992 intr_restore(saveintr); 993} 994 995static void 996enable_K6_2_wt_alloc(void) 997{ 998 quad_t size; 999 u_int64_t whcr; 1000 register_t saveintr; 1001 1002 saveintr = intr_disable(); 1003 wbinvd(); 1004 1005#ifdef CPU_DISABLE_CACHE 1006 /* 1007 * Certain K6-2 box becomes unstable when write allocation is 1008 * enabled. 1009 */ 1010 /* 1011 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12), 1012 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported. 1013 * All other bits in TR12 have no effect on the processer's operation. 1014 * The I/O Trap Restart function (bit 9 of TR12) is always enabled 1015 * on the AMD-K6. 1016 */ 1017 wrmsr(0x0000000e, (u_int64_t)0x0008); 1018#endif 1019 /* Don't assume that memory size is aligned with 4M. */ 1020 if (Maxmem > 0) 1021 size = ((Maxmem >> 8) + 3) >> 2; 1022 else 1023 size = 0; 1024 1025 /* Limit is 4092M bytes. */ 1026 if (size > 0x3fff) 1027 size = 0x3ff; 1028 whcr = (rdmsr(0xc0000082) & ~(0x3ffLL << 22)) | (size << 22); 1029 1030#if defined(PC98) || defined(NO_MEMORY_HOLE) 1031 if (whcr & (0x3ffLL << 22)) { 1032#ifdef PC98 1033 /* 1034 * If bit 2 of port 0x43b is 0, disable wrte allocate for the 1035 * 15-16M range. 1036 */ 1037 if (!(inb(0x43b) & 4)) 1038 whcr &= ~(1LL << 16); 1039 else 1040#endif 1041 whcr |= 1LL << 16; 1042 } 1043#else 1044 /* 1045 * There is no way to know wheter 15-16M hole exists or not. 1046 * Therefore, we disable write allocate for this range. 1047 */ 1048 whcr &= ~(1LL << 16); 1049#endif 1050 wrmsr(0x0c0000082, whcr); 1051 1052 intr_restore(saveintr); 1053} 1054#endif /* I585_CPU && CPU_WT_ALLOC */ 1055 1056#include "opt_ddb.h" 1057#ifdef DDB 1058#include <ddb/ddb.h> 1059 1060DB_SHOW_COMMAND(cyrixreg, cyrixreg) 1061{ 1062 register_t saveintr; 1063 u_int cr0; 1064 u_char ccr1, ccr2, ccr3; 1065 u_char ccr0 = 0, ccr4 = 0, ccr5 = 0, pcr0 = 0; 1066 1067 cr0 = rcr0(); 1068 if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 1069 saveintr = intr_disable(); 1070 1071 1072 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) { 1073 ccr0 = read_cyrix_reg(CCR0); 1074 } 1075 ccr1 = read_cyrix_reg(CCR1); 1076 ccr2 = read_cyrix_reg(CCR2); 1077 ccr3 = read_cyrix_reg(CCR3); 1078 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) { 1079 write_cyrix_reg(CCR3, CCR3_MAPEN0); 1080 ccr4 = read_cyrix_reg(CCR4); 1081 if ((cpu == CPU_M1) || (cpu == CPU_M2)) 1082 ccr5 = read_cyrix_reg(CCR5); 1083 else 1084 pcr0 = read_cyrix_reg(PCR0); 1085 write_cyrix_reg(CCR3, ccr3); /* Restore CCR3. */ 1086 } 1087 intr_restore(saveintr); 1088 1089 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) 1090 printf("CCR0=%x, ", (u_int)ccr0); 1091 1092 printf("CCR1=%x, CCR2=%x, CCR3=%x", 1093 (u_int)ccr1, (u_int)ccr2, (u_int)ccr3); 1094 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) { 1095 printf(", CCR4=%x, ", (u_int)ccr4); 1096 if (cpu == CPU_M1SC) 1097 printf("PCR0=%x\n", pcr0); 1098 else 1099 printf("CCR5=%x\n", ccr5); 1100 } 1101 } 1102 printf("CR0=%x\n", cr0); 1103} 1104#endif /* DDB */ 1105