initcpu.c revision 276084
1/*- 2 * Copyright (c) KATO Takenori, 1997, 1998. 3 * 4 * All rights reserved. Unpublished rights reserved under the copyright 5 * laws of Japan. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer as 13 * the first lines of this file unmodified. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: stable/10/sys/i386/i386/initcpu.c 276084 2014-12-22 21:32:39Z jhb $"); 32 33#include "opt_cpu.h" 34 35#include <sys/param.h> 36#include <sys/kernel.h> 37#include <sys/systm.h> 38#include <sys/sysctl.h> 39 40#include <machine/cputypes.h> 41#include <machine/md_var.h> 42#include <machine/specialreg.h> 43 44#include <vm/vm.h> 45#include <vm/pmap.h> 46 47#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU) 48#define CPU_ENABLE_SSE 49#endif 50 51#ifdef I486_CPU 52static void init_5x86(void); 53static void init_bluelightning(void); 54static void init_486dlc(void); 55static void init_cy486dx(void); 56#ifdef CPU_I486_ON_386 57static void init_i486_on_386(void); 58#endif 59static void init_6x86(void); 60#endif /* I486_CPU */ 61 62#if defined(I586_CPU) && defined(CPU_WT_ALLOC) 63static void enable_K5_wt_alloc(void); 64static void enable_K6_wt_alloc(void); 65static void enable_K6_2_wt_alloc(void); 66#endif 67 68#ifdef I686_CPU 69static void init_6x86MX(void); 70static void init_ppro(void); 71static void init_mendocino(void); 72#endif 73 74static int hw_instruction_sse; 75SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD, 76 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU"); 77/* 78 * -1: automatic (default) 79 * 0: keep enable CLFLUSH 80 * 1: force disable CLFLUSH 81 */ 82static int hw_clflush_disable = -1; 83 84int cpu; /* Are we 386, 386sx, 486, etc? */ 85u_int cpu_feature; /* Feature flags */ 86u_int cpu_feature2; /* Feature flags */ 87u_int amd_feature; /* AMD feature flags */ 88u_int amd_feature2; /* AMD feature flags */ 89u_int amd_pminfo; /* AMD advanced power management info */ 90u_int via_feature_rng; /* VIA RNG features */ 91u_int via_feature_xcrypt; /* VIA ACE features */ 92u_int cpu_high; /* Highest arg to CPUID */ 93u_int cpu_exthigh; /* Highest arg to extended CPUID */ 94u_int cpu_id; /* Stepping ID */ 95u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */ 96u_int cpu_procinfo2; /* Multicore info */ 97char cpu_vendor[20]; /* CPU Origin code */ 98u_int cpu_vendor_id; /* CPU vendor ID */ 99#ifdef CPU_ENABLE_SSE 100u_int cpu_fxsr; /* SSE enabled */ 101u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */ 102#endif 103u_int cpu_clflush_line_size = 32; 104u_int cpu_stdext_feature; 105u_int cpu_max_ext_state_size; 106u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */ 107u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */ 108u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */ 109u_int cyrix_did; /* Device ID of Cyrix CPU */ 110 111SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD, 112 &via_feature_rng, 0, "VIA RNG feature available in CPU"); 113SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD, 114 &via_feature_xcrypt, 0, "VIA xcrypt feature available in CPU"); 115 116#ifdef I486_CPU 117/* 118 * IBM Blue Lightning 119 */ 120static void 121init_bluelightning(void) 122{ 123 register_t saveintr; 124 125#if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE) 126 need_post_dma_flush = 1; 127#endif 128 129 saveintr = intr_disable(); 130 131 load_cr0(rcr0() | CR0_CD | CR0_NW); 132 invd(); 133 134#ifdef CPU_BLUELIGHTNING_FPU_OP_CACHE 135 wrmsr(0x1000, 0x9c92LL); /* FP operand can be cacheable on Cyrix FPU */ 136#else 137 wrmsr(0x1000, 0x1c92LL); /* Intel FPU */ 138#endif 139 /* Enables 13MB and 0-640KB cache. */ 140 wrmsr(0x1001, (0xd0LL << 32) | 0x3ff); 141#ifdef CPU_BLUELIGHTNING_3X 142 wrmsr(0x1002, 0x04000000LL); /* Enables triple-clock mode. */ 143#else 144 wrmsr(0x1002, 0x03000000LL); /* Enables double-clock mode. */ 145#endif 146 147 /* Enable caching in CR0. */ 148 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 149 invd(); 150 intr_restore(saveintr); 151} 152 153/* 154 * Cyrix 486SLC/DLC/SR/DR series 155 */ 156static void 157init_486dlc(void) 158{ 159 register_t saveintr; 160 u_char ccr0; 161 162 saveintr = intr_disable(); 163 invd(); 164 165 ccr0 = read_cyrix_reg(CCR0); 166#ifndef CYRIX_CACHE_WORKS 167 ccr0 |= CCR0_NC1 | CCR0_BARB; 168 write_cyrix_reg(CCR0, ccr0); 169 invd(); 170#else 171 ccr0 &= ~CCR0_NC0; 172#ifndef CYRIX_CACHE_REALLY_WORKS 173 ccr0 |= CCR0_NC1 | CCR0_BARB; 174#else 175 ccr0 |= CCR0_NC1; 176#endif 177#ifdef CPU_DIRECT_MAPPED_CACHE 178 ccr0 |= CCR0_CO; /* Direct mapped mode. */ 179#endif 180 write_cyrix_reg(CCR0, ccr0); 181 182 /* Clear non-cacheable region. */ 183 write_cyrix_reg(NCR1+2, NCR_SIZE_0K); 184 write_cyrix_reg(NCR2+2, NCR_SIZE_0K); 185 write_cyrix_reg(NCR3+2, NCR_SIZE_0K); 186 write_cyrix_reg(NCR4+2, NCR_SIZE_0K); 187 188 write_cyrix_reg(0, 0); /* dummy write */ 189 190 /* Enable caching in CR0. */ 191 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 192 invd(); 193#endif /* !CYRIX_CACHE_WORKS */ 194 intr_restore(saveintr); 195} 196 197 198/* 199 * Cyrix 486S/DX series 200 */ 201static void 202init_cy486dx(void) 203{ 204 register_t saveintr; 205 u_char ccr2; 206 207 saveintr = intr_disable(); 208 invd(); 209 210 ccr2 = read_cyrix_reg(CCR2); 211#ifdef CPU_SUSP_HLT 212 ccr2 |= CCR2_SUSP_HLT; 213#endif 214 215#ifdef PC98 216 /* Enables WB cache interface pin and Lock NW bit in CR0. */ 217 ccr2 |= CCR2_WB | CCR2_LOCK_NW; 218 /* Unlock NW bit in CR0. */ 219 write_cyrix_reg(CCR2, ccr2 & ~CCR2_LOCK_NW); 220 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */ 221#endif 222 223 write_cyrix_reg(CCR2, ccr2); 224 intr_restore(saveintr); 225} 226 227 228/* 229 * Cyrix 5x86 230 */ 231static void 232init_5x86(void) 233{ 234 register_t saveintr; 235 u_char ccr2, ccr3, ccr4, pcr0; 236 237 saveintr = intr_disable(); 238 239 load_cr0(rcr0() | CR0_CD | CR0_NW); 240 wbinvd(); 241 242 (void)read_cyrix_reg(CCR3); /* dummy */ 243 244 /* Initialize CCR2. */ 245 ccr2 = read_cyrix_reg(CCR2); 246 ccr2 |= CCR2_WB; 247#ifdef CPU_SUSP_HLT 248 ccr2 |= CCR2_SUSP_HLT; 249#else 250 ccr2 &= ~CCR2_SUSP_HLT; 251#endif 252 ccr2 |= CCR2_WT1; 253 write_cyrix_reg(CCR2, ccr2); 254 255 /* Initialize CCR4. */ 256 ccr3 = read_cyrix_reg(CCR3); 257 write_cyrix_reg(CCR3, CCR3_MAPEN0); 258 259 ccr4 = read_cyrix_reg(CCR4); 260 ccr4 |= CCR4_DTE; 261 ccr4 |= CCR4_MEM; 262#ifdef CPU_FASTER_5X86_FPU 263 ccr4 |= CCR4_FASTFPE; 264#else 265 ccr4 &= ~CCR4_FASTFPE; 266#endif 267 ccr4 &= ~CCR4_IOMASK; 268 /******************************************************************** 269 * WARNING: The "BIOS Writers Guide" mentions that I/O recovery time 270 * should be 0 for errata fix. 271 ********************************************************************/ 272#ifdef CPU_IORT 273 ccr4 |= CPU_IORT & CCR4_IOMASK; 274#endif 275 write_cyrix_reg(CCR4, ccr4); 276 277 /* Initialize PCR0. */ 278 /**************************************************************** 279 * WARNING: RSTK_EN and LOOP_EN could make your system unstable. 280 * BTB_EN might make your system unstable. 281 ****************************************************************/ 282 pcr0 = read_cyrix_reg(PCR0); 283#ifdef CPU_RSTK_EN 284 pcr0 |= PCR0_RSTK; 285#else 286 pcr0 &= ~PCR0_RSTK; 287#endif 288#ifdef CPU_BTB_EN 289 pcr0 |= PCR0_BTB; 290#else 291 pcr0 &= ~PCR0_BTB; 292#endif 293#ifdef CPU_LOOP_EN 294 pcr0 |= PCR0_LOOP; 295#else 296 pcr0 &= ~PCR0_LOOP; 297#endif 298 299 /**************************************************************** 300 * WARNING: if you use a memory mapped I/O device, don't use 301 * DISABLE_5X86_LSSER option, which may reorder memory mapped 302 * I/O access. 303 * IF YOUR MOTHERBOARD HAS PCI BUS, DON'T DISABLE LSSER. 304 ****************************************************************/ 305#ifdef CPU_DISABLE_5X86_LSSER 306 pcr0 &= ~PCR0_LSSER; 307#else 308 pcr0 |= PCR0_LSSER; 309#endif 310 write_cyrix_reg(PCR0, pcr0); 311 312 /* Restore CCR3. */ 313 write_cyrix_reg(CCR3, ccr3); 314 315 (void)read_cyrix_reg(0x80); /* dummy */ 316 317 /* Unlock NW bit in CR0. */ 318 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW); 319 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */ 320 /* Lock NW bit in CR0. */ 321 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW); 322 323 intr_restore(saveintr); 324} 325 326#ifdef CPU_I486_ON_386 327/* 328 * There are i486 based upgrade products for i386 machines. 329 * In this case, BIOS doesn't enable CPU cache. 330 */ 331static void 332init_i486_on_386(void) 333{ 334 register_t saveintr; 335 336#if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE) 337 need_post_dma_flush = 1; 338#endif 339 340 saveintr = intr_disable(); 341 342 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0, NW = 0 */ 343 344 intr_restore(saveintr); 345} 346#endif 347 348/* 349 * Cyrix 6x86 350 * 351 * XXX - What should I do here? Please let me know. 352 */ 353static void 354init_6x86(void) 355{ 356 register_t saveintr; 357 u_char ccr3, ccr4; 358 359 saveintr = intr_disable(); 360 361 load_cr0(rcr0() | CR0_CD | CR0_NW); 362 wbinvd(); 363 364 /* Initialize CCR0. */ 365 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1); 366 367 /* Initialize CCR1. */ 368#ifdef CPU_CYRIX_NO_LOCK 369 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK); 370#else 371 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK); 372#endif 373 374 /* Initialize CCR2. */ 375#ifdef CPU_SUSP_HLT 376 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT); 377#else 378 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT); 379#endif 380 381 ccr3 = read_cyrix_reg(CCR3); 382 write_cyrix_reg(CCR3, CCR3_MAPEN0); 383 384 /* Initialize CCR4. */ 385 ccr4 = read_cyrix_reg(CCR4); 386 ccr4 |= CCR4_DTE; 387 ccr4 &= ~CCR4_IOMASK; 388#ifdef CPU_IORT 389 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK)); 390#else 391 write_cyrix_reg(CCR4, ccr4 | 7); 392#endif 393 394 /* Initialize CCR5. */ 395#ifdef CPU_WT_ALLOC 396 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC); 397#endif 398 399 /* Restore CCR3. */ 400 write_cyrix_reg(CCR3, ccr3); 401 402 /* Unlock NW bit in CR0. */ 403 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW); 404 405 /* 406 * Earlier revision of the 6x86 CPU could crash the system if 407 * L1 cache is in write-back mode. 408 */ 409 if ((cyrix_did & 0xff00) > 0x1600) 410 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 411 else { 412 /* Revision 2.6 and lower. */ 413#ifdef CYRIX_CACHE_REALLY_WORKS 414 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 415#else 416 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0 and NW = 1 */ 417#endif 418 } 419 420 /* Lock NW bit in CR0. */ 421 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW); 422 423 intr_restore(saveintr); 424} 425#endif /* I486_CPU */ 426 427#ifdef I586_CPU 428/* 429 * Rise mP6 430 */ 431static void 432init_rise(void) 433{ 434 435 /* 436 * The CMPXCHG8B instruction is always available but hidden. 437 */ 438 cpu_feature |= CPUID_CX8; 439} 440 441/* 442 * IDT WinChip C6/2/2A/2B/3 443 * 444 * http://www.centtech.com/winchip_bios_writers_guide_v4_0.pdf 445 */ 446static void 447init_winchip(void) 448{ 449 u_int regs[4]; 450 uint64_t fcr; 451 452 fcr = rdmsr(0x0107); 453 454 /* 455 * Set ECX8, DSMC, DTLOCK/EDCTLB, EMMX, and ERETSTK and clear DPDC. 456 */ 457 fcr |= (1 << 1) | (1 << 7) | (1 << 8) | (1 << 9) | (1 << 16); 458 fcr &= ~(1ULL << 11); 459 460 /* 461 * Additionally, set EBRPRED, E2MMX and EAMD3D for WinChip 2 and 3. 462 */ 463 if (CPUID_TO_MODEL(cpu_id) >= 8) 464 fcr |= (1 << 12) | (1 << 19) | (1 << 20); 465 466 wrmsr(0x0107, fcr); 467 do_cpuid(1, regs); 468 cpu_feature = regs[3]; 469} 470#endif 471 472#ifdef I686_CPU 473/* 474 * Cyrix 6x86MX (code-named M2) 475 * 476 * XXX - What should I do here? Please let me know. 477 */ 478static void 479init_6x86MX(void) 480{ 481 register_t saveintr; 482 u_char ccr3, ccr4; 483 484 saveintr = intr_disable(); 485 486 load_cr0(rcr0() | CR0_CD | CR0_NW); 487 wbinvd(); 488 489 /* Initialize CCR0. */ 490 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1); 491 492 /* Initialize CCR1. */ 493#ifdef CPU_CYRIX_NO_LOCK 494 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK); 495#else 496 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK); 497#endif 498 499 /* Initialize CCR2. */ 500#ifdef CPU_SUSP_HLT 501 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT); 502#else 503 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT); 504#endif 505 506 ccr3 = read_cyrix_reg(CCR3); 507 write_cyrix_reg(CCR3, CCR3_MAPEN0); 508 509 /* Initialize CCR4. */ 510 ccr4 = read_cyrix_reg(CCR4); 511 ccr4 &= ~CCR4_IOMASK; 512#ifdef CPU_IORT 513 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK)); 514#else 515 write_cyrix_reg(CCR4, ccr4 | 7); 516#endif 517 518 /* Initialize CCR5. */ 519#ifdef CPU_WT_ALLOC 520 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC); 521#endif 522 523 /* Restore CCR3. */ 524 write_cyrix_reg(CCR3, ccr3); 525 526 /* Unlock NW bit in CR0. */ 527 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW); 528 529 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 530 531 /* Lock NW bit in CR0. */ 532 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW); 533 534 intr_restore(saveintr); 535} 536 537static int ppro_apic_used = -1; 538 539static void 540init_ppro(void) 541{ 542 u_int64_t apicbase; 543 544 /* 545 * Local APIC should be disabled if it is not going to be used. 546 */ 547 if (ppro_apic_used != 1) { 548 apicbase = rdmsr(MSR_APICBASE); 549 apicbase &= ~APICBASE_ENABLED; 550 wrmsr(MSR_APICBASE, apicbase); 551 ppro_apic_used = 0; 552 } 553} 554 555/* 556 * If the local APIC is going to be used after being disabled above, 557 * re-enable it and don't disable it in the future. 558 */ 559void 560ppro_reenable_apic(void) 561{ 562 u_int64_t apicbase; 563 564 if (ppro_apic_used == 0) { 565 apicbase = rdmsr(MSR_APICBASE); 566 apicbase |= APICBASE_ENABLED; 567 wrmsr(MSR_APICBASE, apicbase); 568 ppro_apic_used = 1; 569 } 570} 571 572/* 573 * Initialize BBL_CR_CTL3 (Control register 3: used to configure the 574 * L2 cache). 575 */ 576static void 577init_mendocino(void) 578{ 579#ifdef CPU_PPRO2CELERON 580 register_t saveintr; 581 u_int64_t bbl_cr_ctl3; 582 583 saveintr = intr_disable(); 584 585 load_cr0(rcr0() | CR0_CD | CR0_NW); 586 wbinvd(); 587 588 bbl_cr_ctl3 = rdmsr(MSR_BBL_CR_CTL3); 589 590 /* If the L2 cache is configured, do nothing. */ 591 if (!(bbl_cr_ctl3 & 1)) { 592 bbl_cr_ctl3 = 0x134052bLL; 593 594 /* Set L2 Cache Latency (Default: 5). */ 595#ifdef CPU_CELERON_L2_LATENCY 596#if CPU_L2_LATENCY > 15 597#error invalid CPU_L2_LATENCY. 598#endif 599 bbl_cr_ctl3 |= CPU_L2_LATENCY << 1; 600#else 601 bbl_cr_ctl3 |= 5 << 1; 602#endif 603 wrmsr(MSR_BBL_CR_CTL3, bbl_cr_ctl3); 604 } 605 606 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); 607 intr_restore(saveintr); 608#endif /* CPU_PPRO2CELERON */ 609} 610 611/* 612 * Initialize special VIA features 613 */ 614static void 615init_via(void) 616{ 617 u_int regs[4], val; 618 uint64_t fcr; 619 620 /* 621 * Explicitly enable CX8 and PGE on C3. 622 * 623 * http://www.via.com.tw/download/mainboards/6/13/VIA_C3_EBGA%20datasheet110.pdf 624 */ 625 if (CPUID_TO_MODEL(cpu_id) <= 9) 626 fcr = (1 << 1) | (1 << 7); 627 else 628 fcr = 0; 629 630 /* 631 * Check extended CPUID for PadLock features. 632 * 633 * http://www.via.com.tw/en/downloads/whitepapers/initiatives/padlock/programming_guide.pdf 634 */ 635 do_cpuid(0xc0000000, regs); 636 if (regs[0] >= 0xc0000001) { 637 do_cpuid(0xc0000001, regs); 638 val = regs[3]; 639 } else 640 val = 0; 641 642 /* Enable RNG if present. */ 643 if ((val & VIA_CPUID_HAS_RNG) != 0) { 644 via_feature_rng = VIA_HAS_RNG; 645 wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG); 646 } 647 648 /* Enable PadLock if present. */ 649 if ((val & VIA_CPUID_HAS_ACE) != 0) 650 via_feature_xcrypt |= VIA_HAS_AES; 651 if ((val & VIA_CPUID_HAS_ACE2) != 0) 652 via_feature_xcrypt |= VIA_HAS_AESCTR; 653 if ((val & VIA_CPUID_HAS_PHE) != 0) 654 via_feature_xcrypt |= VIA_HAS_SHA; 655 if ((val & VIA_CPUID_HAS_PMM) != 0) 656 via_feature_xcrypt |= VIA_HAS_MM; 657 if (via_feature_xcrypt != 0) 658 fcr |= 1 << 28; 659 660 wrmsr(0x1107, rdmsr(0x1107) | fcr); 661} 662 663#endif /* I686_CPU */ 664 665#if defined(I586_CPU) || defined(I686_CPU) 666static void 667init_transmeta(void) 668{ 669 u_int regs[0]; 670 671 /* Expose all hidden features. */ 672 wrmsr(0x80860004, rdmsr(0x80860004) | ~0UL); 673 do_cpuid(1, regs); 674 cpu_feature = regs[3]; 675} 676#endif 677 678extern int elf32_nxstack; 679 680void 681initializecpu(void) 682{ 683 684 switch (cpu) { 685#ifdef I486_CPU 686 case CPU_BLUE: 687 init_bluelightning(); 688 break; 689 case CPU_486DLC: 690 init_486dlc(); 691 break; 692 case CPU_CY486DX: 693 init_cy486dx(); 694 break; 695 case CPU_M1SC: 696 init_5x86(); 697 break; 698#ifdef CPU_I486_ON_386 699 case CPU_486: 700 init_i486_on_386(); 701 break; 702#endif 703 case CPU_M1: 704 init_6x86(); 705 break; 706#endif /* I486_CPU */ 707#ifdef I586_CPU 708 case CPU_586: 709 switch (cpu_vendor_id) { 710 case CPU_VENDOR_AMD: 711#ifdef CPU_WT_ALLOC 712 if (((cpu_id & 0x0f0) > 0) && 713 ((cpu_id & 0x0f0) < 0x60) && 714 ((cpu_id & 0x00f) > 3)) 715 enable_K5_wt_alloc(); 716 else if (((cpu_id & 0x0f0) > 0x80) || 717 (((cpu_id & 0x0f0) == 0x80) && 718 (cpu_id & 0x00f) > 0x07)) 719 enable_K6_2_wt_alloc(); 720 else if ((cpu_id & 0x0f0) > 0x50) 721 enable_K6_wt_alloc(); 722#endif 723 if ((cpu_id & 0xf0) == 0xa0) 724 /* 725 * Make sure the TSC runs through 726 * suspension, otherwise we can't use 727 * it as timecounter 728 */ 729 wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL); 730 break; 731 case CPU_VENDOR_CENTAUR: 732 init_winchip(); 733 break; 734 case CPU_VENDOR_TRANSMETA: 735 init_transmeta(); 736 break; 737 case CPU_VENDOR_RISE: 738 init_rise(); 739 break; 740 } 741 break; 742#endif 743#ifdef I686_CPU 744 case CPU_M2: 745 init_6x86MX(); 746 break; 747 case CPU_686: 748 switch (cpu_vendor_id) { 749 case CPU_VENDOR_INTEL: 750 switch (cpu_id & 0xff0) { 751 case 0x610: 752 init_ppro(); 753 break; 754 case 0x660: 755 init_mendocino(); 756 break; 757 } 758 break; 759#ifdef CPU_ATHLON_SSE_HACK 760 case CPU_VENDOR_AMD: 761 /* 762 * Sometimes the BIOS doesn't enable SSE instructions. 763 * According to AMD document 20734, the mobile 764 * Duron, the (mobile) Athlon 4 and the Athlon MP 765 * support SSE. These correspond to cpu_id 0x66X 766 * or 0x67X. 767 */ 768 if ((cpu_feature & CPUID_XMM) == 0 && 769 ((cpu_id & ~0xf) == 0x660 || 770 (cpu_id & ~0xf) == 0x670 || 771 (cpu_id & ~0xf) == 0x680)) { 772 u_int regs[4]; 773 wrmsr(MSR_HWCR, rdmsr(MSR_HWCR) & ~0x08000); 774 do_cpuid(1, regs); 775 cpu_feature = regs[3]; 776 } 777 break; 778#endif 779 case CPU_VENDOR_CENTAUR: 780 init_via(); 781 break; 782 case CPU_VENDOR_TRANSMETA: 783 init_transmeta(); 784 break; 785 } 786#ifdef PAE 787 if ((amd_feature & AMDID_NX) != 0) { 788 uint64_t msr; 789 790 msr = rdmsr(MSR_EFER) | EFER_NXE; 791 wrmsr(MSR_EFER, msr); 792 pg_nx = PG_NX; 793 elf32_nxstack = 1; 794 } 795#endif 796 break; 797#endif 798 default: 799 break; 800 } 801#if defined(CPU_ENABLE_SSE) 802 if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) { 803 load_cr4(rcr4() | CR4_FXSR | CR4_XMM); 804 cpu_fxsr = hw_instruction_sse = 1; 805 } 806#endif 807} 808 809void 810initializecpucache(void) 811{ 812 813 /* 814 * CPUID with %eax = 1, %ebx returns 815 * Bits 15-8: CLFLUSH line size 816 * (Value * 8 = cache line size in bytes) 817 */ 818 if ((cpu_feature & CPUID_CLFSH) != 0) 819 cpu_clflush_line_size = ((cpu_procinfo >> 8) & 0xff) * 8; 820 /* 821 * XXXKIB: (temporary) hack to work around traps generated 822 * when CLFLUSHing APIC register window under virtualization 823 * environments. These environments tend to disable the 824 * CPUID_SS feature even though the native CPU supports it. 825 */ 826 TUNABLE_INT_FETCH("hw.clflush_disable", &hw_clflush_disable); 827 if (vm_guest != VM_GUEST_NO && hw_clflush_disable == -1) 828 cpu_feature &= ~CPUID_CLFSH; 829 /* 830 * Allow to disable CLFLUSH feature manually by 831 * hw.clflush_disable tunable. 832 */ 833 if (hw_clflush_disable == 1) 834 cpu_feature &= ~CPUID_CLFSH; 835 836#if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE) 837 /* 838 * OS should flush L1 cache by itself because no PC-98 supports 839 * non-Intel CPUs. Use wbinvd instruction before DMA transfer 840 * when need_pre_dma_flush = 1, use invd instruction after DMA 841 * transfer when need_post_dma_flush = 1. If your CPU upgrade 842 * product supports hardware cache control, you can add the 843 * CPU_UPGRADE_HW_CACHE option in your kernel configuration file. 844 * This option eliminates unneeded cache flush instruction(s). 845 */ 846 if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 847 switch (cpu) { 848#ifdef I486_CPU 849 case CPU_486DLC: 850 need_post_dma_flush = 1; 851 break; 852 case CPU_M1SC: 853 need_pre_dma_flush = 1; 854 break; 855 case CPU_CY486DX: 856 need_pre_dma_flush = 1; 857#ifdef CPU_I486_ON_386 858 need_post_dma_flush = 1; 859#endif 860 break; 861#endif 862 default: 863 break; 864 } 865 } else if (cpu_vendor_id == CPU_VENDOR_AMD) { 866 switch (cpu_id & 0xFF0) { 867 case 0x470: /* Enhanced Am486DX2 WB */ 868 case 0x490: /* Enhanced Am486DX4 WB */ 869 case 0x4F0: /* Am5x86 WB */ 870 need_pre_dma_flush = 1; 871 break; 872 } 873 } else if (cpu_vendor_id == CPU_VENDOR_IBM) { 874 need_post_dma_flush = 1; 875 } else { 876#ifdef CPU_I486_ON_386 877 need_pre_dma_flush = 1; 878#endif 879 } 880#endif /* PC98 && !CPU_UPGRADE_HW_CACHE */ 881} 882 883#if defined(I586_CPU) && defined(CPU_WT_ALLOC) 884/* 885 * Enable write allocate feature of AMD processors. 886 * Following two functions require the Maxmem variable being set. 887 */ 888static void 889enable_K5_wt_alloc(void) 890{ 891 u_int64_t msr; 892 register_t saveintr; 893 894 /* 895 * Write allocate is supported only on models 1, 2, and 3, with 896 * a stepping of 4 or greater. 897 */ 898 if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) { 899 saveintr = intr_disable(); 900 msr = rdmsr(0x83); /* HWCR */ 901 wrmsr(0x83, msr & !(0x10)); 902 903 /* 904 * We have to tell the chip where the top of memory is, 905 * since video cards could have frame bufferes there, 906 * memory-mapped I/O could be there, etc. 907 */ 908 if(Maxmem > 0) 909 msr = Maxmem / 16; 910 else 911 msr = 0; 912 msr |= AMD_WT_ALLOC_TME | AMD_WT_ALLOC_FRE; 913#ifdef PC98 914 if (!(inb(0x43b) & 4)) { 915 wrmsr(0x86, 0x0ff00f0); 916 msr |= AMD_WT_ALLOC_PRE; 917 } 918#else 919 /* 920 * There is no way to know wheter 15-16M hole exists or not. 921 * Therefore, we disable write allocate for this range. 922 */ 923 wrmsr(0x86, 0x0ff00f0); 924 msr |= AMD_WT_ALLOC_PRE; 925#endif 926 wrmsr(0x85, msr); 927 928 msr=rdmsr(0x83); 929 wrmsr(0x83, msr|0x10); /* enable write allocate */ 930 intr_restore(saveintr); 931 } 932} 933 934static void 935enable_K6_wt_alloc(void) 936{ 937 quad_t size; 938 u_int64_t whcr; 939 register_t saveintr; 940 941 saveintr = intr_disable(); 942 wbinvd(); 943 944#ifdef CPU_DISABLE_CACHE 945 /* 946 * Certain K6-2 box becomes unstable when write allocation is 947 * enabled. 948 */ 949 /* 950 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12), 951 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported. 952 * All other bits in TR12 have no effect on the processer's operation. 953 * The I/O Trap Restart function (bit 9 of TR12) is always enabled 954 * on the AMD-K6. 955 */ 956 wrmsr(0x0000000e, (u_int64_t)0x0008); 957#endif 958 /* Don't assume that memory size is aligned with 4M. */ 959 if (Maxmem > 0) 960 size = ((Maxmem >> 8) + 3) >> 2; 961 else 962 size = 0; 963 964 /* Limit is 508M bytes. */ 965 if (size > 0x7f) 966 size = 0x7f; 967 whcr = (rdmsr(0xc0000082) & ~(0x7fLL << 1)) | (size << 1); 968 969#if defined(PC98) || defined(NO_MEMORY_HOLE) 970 if (whcr & (0x7fLL << 1)) { 971#ifdef PC98 972 /* 973 * If bit 2 of port 0x43b is 0, disable wrte allocate for the 974 * 15-16M range. 975 */ 976 if (!(inb(0x43b) & 4)) 977 whcr &= ~0x0001LL; 978 else 979#endif 980 whcr |= 0x0001LL; 981 } 982#else 983 /* 984 * There is no way to know wheter 15-16M hole exists or not. 985 * Therefore, we disable write allocate for this range. 986 */ 987 whcr &= ~0x0001LL; 988#endif 989 wrmsr(0x0c0000082, whcr); 990 991 intr_restore(saveintr); 992} 993 994static void 995enable_K6_2_wt_alloc(void) 996{ 997 quad_t size; 998 u_int64_t whcr; 999 register_t saveintr; 1000 1001 saveintr = intr_disable(); 1002 wbinvd(); 1003 1004#ifdef CPU_DISABLE_CACHE 1005 /* 1006 * Certain K6-2 box becomes unstable when write allocation is 1007 * enabled. 1008 */ 1009 /* 1010 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12), 1011 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported. 1012 * All other bits in TR12 have no effect on the processer's operation. 1013 * The I/O Trap Restart function (bit 9 of TR12) is always enabled 1014 * on the AMD-K6. 1015 */ 1016 wrmsr(0x0000000e, (u_int64_t)0x0008); 1017#endif 1018 /* Don't assume that memory size is aligned with 4M. */ 1019 if (Maxmem > 0) 1020 size = ((Maxmem >> 8) + 3) >> 2; 1021 else 1022 size = 0; 1023 1024 /* Limit is 4092M bytes. */ 1025 if (size > 0x3fff) 1026 size = 0x3ff; 1027 whcr = (rdmsr(0xc0000082) & ~(0x3ffLL << 22)) | (size << 22); 1028 1029#if defined(PC98) || defined(NO_MEMORY_HOLE) 1030 if (whcr & (0x3ffLL << 22)) { 1031#ifdef PC98 1032 /* 1033 * If bit 2 of port 0x43b is 0, disable wrte allocate for the 1034 * 15-16M range. 1035 */ 1036 if (!(inb(0x43b) & 4)) 1037 whcr &= ~(1LL << 16); 1038 else 1039#endif 1040 whcr |= 1LL << 16; 1041 } 1042#else 1043 /* 1044 * There is no way to know wheter 15-16M hole exists or not. 1045 * Therefore, we disable write allocate for this range. 1046 */ 1047 whcr &= ~(1LL << 16); 1048#endif 1049 wrmsr(0x0c0000082, whcr); 1050 1051 intr_restore(saveintr); 1052} 1053#endif /* I585_CPU && CPU_WT_ALLOC */ 1054 1055#include "opt_ddb.h" 1056#ifdef DDB 1057#include <ddb/ddb.h> 1058 1059DB_SHOW_COMMAND(cyrixreg, cyrixreg) 1060{ 1061 register_t saveintr; 1062 u_int cr0; 1063 u_char ccr1, ccr2, ccr3; 1064 u_char ccr0 = 0, ccr4 = 0, ccr5 = 0, pcr0 = 0; 1065 1066 cr0 = rcr0(); 1067 if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 1068 saveintr = intr_disable(); 1069 1070 1071 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) { 1072 ccr0 = read_cyrix_reg(CCR0); 1073 } 1074 ccr1 = read_cyrix_reg(CCR1); 1075 ccr2 = read_cyrix_reg(CCR2); 1076 ccr3 = read_cyrix_reg(CCR3); 1077 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) { 1078 write_cyrix_reg(CCR3, CCR3_MAPEN0); 1079 ccr4 = read_cyrix_reg(CCR4); 1080 if ((cpu == CPU_M1) || (cpu == CPU_M2)) 1081 ccr5 = read_cyrix_reg(CCR5); 1082 else 1083 pcr0 = read_cyrix_reg(PCR0); 1084 write_cyrix_reg(CCR3, ccr3); /* Restore CCR3. */ 1085 } 1086 intr_restore(saveintr); 1087 1088 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) 1089 printf("CCR0=%x, ", (u_int)ccr0); 1090 1091 printf("CCR1=%x, CCR2=%x, CCR3=%x", 1092 (u_int)ccr1, (u_int)ccr2, (u_int)ccr3); 1093 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) { 1094 printf(", CCR4=%x, ", (u_int)ccr4); 1095 if (cpu == CPU_M1SC) 1096 printf("PCR0=%x\n", pcr0); 1097 else 1098 printf("CCR5=%x\n", ccr5); 1099 } 1100 } 1101 printf("CR0=%x\n", cr0); 1102} 1103#endif /* DDB */ 1104