initcpu.c revision 276076
1/*- 2 * Copyright (c) KATO Takenori, 1997, 1998. 3 * 4 * All rights reserved. Unpublished rights reserved under the copyright 5 * laws of Japan. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer as 13 * the first lines of this file unmodified. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: stable/10/sys/i386/i386/initcpu.c 276076 2014-12-22 19:53:55Z jhb $"); 32 33#include "opt_cpu.h" 34 35#include <sys/param.h> 36#include <sys/kernel.h> 37#include <sys/systm.h> 38#include <sys/sysctl.h> 39 40#include <machine/cputypes.h> 41#include <machine/md_var.h> 42#include <machine/specialreg.h> 43 44#include <vm/vm.h> 45#include <vm/pmap.h> 46 47#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU) 48#define CPU_ENABLE_SSE 49#endif 50 51#ifdef I486_CPU 52static void init_5x86(void); 53static void init_bluelightning(void); 54static void init_486dlc(void); 55static void init_cy486dx(void); 56#ifdef CPU_I486_ON_386 57static void init_i486_on_386(void); 58#endif 59static void init_6x86(void); 60#endif /* I486_CPU */ 61 62#if defined(I586_CPU) && defined(CPU_WT_ALLOC) 63static void enable_K5_wt_alloc(void); 64static void enable_K6_wt_alloc(void); 65static void enable_K6_2_wt_alloc(void); 66#endif 67 68#ifdef I686_CPU 69static void init_6x86MX(void); 70static void init_ppro(void); 71static void init_mendocino(void); 72#endif 73 74static int hw_instruction_sse; 75SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD, 76 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU"); 77/* 78 * -1: automatic (default) 79 * 0: keep enable CLFLUSH 80 * 1: force disable CLFLUSH 81 */ 82static int hw_clflush_disable = -1; 83 84int cpu; /* Are we 386, 386sx, 486, etc? */ 85u_int cpu_feature; /* Feature flags */ 86u_int cpu_feature2; /* Feature flags */ 87u_int amd_feature; /* AMD feature flags */ 88u_int amd_feature2; /* AMD feature flags */ 89u_int amd_pminfo; /* AMD advanced power management info */ 90u_int via_feature_rng; /* VIA RNG features */ 91u_int via_feature_xcrypt; /* VIA ACE features */ 92u_int cpu_high; /* Highest arg to CPUID */ 93u_int cpu_exthigh; /* Highest arg to extended CPUID */ 94u_int cpu_id; /* Stepping ID */ 95u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */ 96u_int cpu_procinfo2; /* Multicore info */ 97char cpu_vendor[20]; /* CPU Origin code */ 98u_int cpu_vendor_id; /* CPU vendor ID */ 99#ifdef CPU_ENABLE_SSE 100u_int cpu_fxsr; /* SSE enabled */ 101u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */ 102#endif 103u_int cpu_clflush_line_size = 32; 104u_int cpu_stdext_feature; 105u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */ 106u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */ 107u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */ 108u_int cyrix_did; /* Device ID of Cyrix CPU */ 109 110SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD, 111 &via_feature_rng, 0, "VIA RNG feature available in CPU"); 112SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD, 113 &via_feature_xcrypt, 0, "VIA xcrypt feature available in CPU"); 114 115#ifdef I486_CPU 116/* 117 * IBM Blue Lightning 118 */ 119static void 120init_bluelightning(void) 121{ 122 register_t saveintr; 123 124#if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE) 125 need_post_dma_flush = 1; 126#endif 127 128 saveintr = intr_disable(); 129 130 load_cr0(rcr0() | CR0_CD | CR0_NW); 131 invd(); 132 133#ifdef CPU_BLUELIGHTNING_FPU_OP_CACHE 134 wrmsr(0x1000, 0x9c92LL); /* FP operand can be cacheable on Cyrix FPU */ 135#else 136 wrmsr(0x1000, 0x1c92LL); /* Intel FPU */ 137#endif 138 /* Enables 13MB and 0-640KB cache. */ 139 wrmsr(0x1001, (0xd0LL << 32) | 0x3ff); 140#ifdef CPU_BLUELIGHTNING_3X 141 wrmsr(0x1002, 0x04000000LL); /* Enables triple-clock mode. */ 142#else 143 wrmsr(0x1002, 0x03000000LL); /* Enables double-clock mode. */ 144#endif 145 146 /* Enable caching in CR0. */ 147 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 148 invd(); 149 intr_restore(saveintr); 150} 151 152/* 153 * Cyrix 486SLC/DLC/SR/DR series 154 */ 155static void 156init_486dlc(void) 157{ 158 register_t saveintr; 159 u_char ccr0; 160 161 saveintr = intr_disable(); 162 invd(); 163 164 ccr0 = read_cyrix_reg(CCR0); 165#ifndef CYRIX_CACHE_WORKS 166 ccr0 |= CCR0_NC1 | CCR0_BARB; 167 write_cyrix_reg(CCR0, ccr0); 168 invd(); 169#else 170 ccr0 &= ~CCR0_NC0; 171#ifndef CYRIX_CACHE_REALLY_WORKS 172 ccr0 |= CCR0_NC1 | CCR0_BARB; 173#else 174 ccr0 |= CCR0_NC1; 175#endif 176#ifdef CPU_DIRECT_MAPPED_CACHE 177 ccr0 |= CCR0_CO; /* Direct mapped mode. */ 178#endif 179 write_cyrix_reg(CCR0, ccr0); 180 181 /* Clear non-cacheable region. */ 182 write_cyrix_reg(NCR1+2, NCR_SIZE_0K); 183 write_cyrix_reg(NCR2+2, NCR_SIZE_0K); 184 write_cyrix_reg(NCR3+2, NCR_SIZE_0K); 185 write_cyrix_reg(NCR4+2, NCR_SIZE_0K); 186 187 write_cyrix_reg(0, 0); /* dummy write */ 188 189 /* Enable caching in CR0. */ 190 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 191 invd(); 192#endif /* !CYRIX_CACHE_WORKS */ 193 intr_restore(saveintr); 194} 195 196 197/* 198 * Cyrix 486S/DX series 199 */ 200static void 201init_cy486dx(void) 202{ 203 register_t saveintr; 204 u_char ccr2; 205 206 saveintr = intr_disable(); 207 invd(); 208 209 ccr2 = read_cyrix_reg(CCR2); 210#ifdef CPU_SUSP_HLT 211 ccr2 |= CCR2_SUSP_HLT; 212#endif 213 214#ifdef PC98 215 /* Enables WB cache interface pin and Lock NW bit in CR0. */ 216 ccr2 |= CCR2_WB | CCR2_LOCK_NW; 217 /* Unlock NW bit in CR0. */ 218 write_cyrix_reg(CCR2, ccr2 & ~CCR2_LOCK_NW); 219 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */ 220#endif 221 222 write_cyrix_reg(CCR2, ccr2); 223 intr_restore(saveintr); 224} 225 226 227/* 228 * Cyrix 5x86 229 */ 230static void 231init_5x86(void) 232{ 233 register_t saveintr; 234 u_char ccr2, ccr3, ccr4, pcr0; 235 236 saveintr = intr_disable(); 237 238 load_cr0(rcr0() | CR0_CD | CR0_NW); 239 wbinvd(); 240 241 (void)read_cyrix_reg(CCR3); /* dummy */ 242 243 /* Initialize CCR2. */ 244 ccr2 = read_cyrix_reg(CCR2); 245 ccr2 |= CCR2_WB; 246#ifdef CPU_SUSP_HLT 247 ccr2 |= CCR2_SUSP_HLT; 248#else 249 ccr2 &= ~CCR2_SUSP_HLT; 250#endif 251 ccr2 |= CCR2_WT1; 252 write_cyrix_reg(CCR2, ccr2); 253 254 /* Initialize CCR4. */ 255 ccr3 = read_cyrix_reg(CCR3); 256 write_cyrix_reg(CCR3, CCR3_MAPEN0); 257 258 ccr4 = read_cyrix_reg(CCR4); 259 ccr4 |= CCR4_DTE; 260 ccr4 |= CCR4_MEM; 261#ifdef CPU_FASTER_5X86_FPU 262 ccr4 |= CCR4_FASTFPE; 263#else 264 ccr4 &= ~CCR4_FASTFPE; 265#endif 266 ccr4 &= ~CCR4_IOMASK; 267 /******************************************************************** 268 * WARNING: The "BIOS Writers Guide" mentions that I/O recovery time 269 * should be 0 for errata fix. 270 ********************************************************************/ 271#ifdef CPU_IORT 272 ccr4 |= CPU_IORT & CCR4_IOMASK; 273#endif 274 write_cyrix_reg(CCR4, ccr4); 275 276 /* Initialize PCR0. */ 277 /**************************************************************** 278 * WARNING: RSTK_EN and LOOP_EN could make your system unstable. 279 * BTB_EN might make your system unstable. 280 ****************************************************************/ 281 pcr0 = read_cyrix_reg(PCR0); 282#ifdef CPU_RSTK_EN 283 pcr0 |= PCR0_RSTK; 284#else 285 pcr0 &= ~PCR0_RSTK; 286#endif 287#ifdef CPU_BTB_EN 288 pcr0 |= PCR0_BTB; 289#else 290 pcr0 &= ~PCR0_BTB; 291#endif 292#ifdef CPU_LOOP_EN 293 pcr0 |= PCR0_LOOP; 294#else 295 pcr0 &= ~PCR0_LOOP; 296#endif 297 298 /**************************************************************** 299 * WARNING: if you use a memory mapped I/O device, don't use 300 * DISABLE_5X86_LSSER option, which may reorder memory mapped 301 * I/O access. 302 * IF YOUR MOTHERBOARD HAS PCI BUS, DON'T DISABLE LSSER. 303 ****************************************************************/ 304#ifdef CPU_DISABLE_5X86_LSSER 305 pcr0 &= ~PCR0_LSSER; 306#else 307 pcr0 |= PCR0_LSSER; 308#endif 309 write_cyrix_reg(PCR0, pcr0); 310 311 /* Restore CCR3. */ 312 write_cyrix_reg(CCR3, ccr3); 313 314 (void)read_cyrix_reg(0x80); /* dummy */ 315 316 /* Unlock NW bit in CR0. */ 317 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW); 318 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */ 319 /* Lock NW bit in CR0. */ 320 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW); 321 322 intr_restore(saveintr); 323} 324 325#ifdef CPU_I486_ON_386 326/* 327 * There are i486 based upgrade products for i386 machines. 328 * In this case, BIOS doesn't enable CPU cache. 329 */ 330static void 331init_i486_on_386(void) 332{ 333 register_t saveintr; 334 335#if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE) 336 need_post_dma_flush = 1; 337#endif 338 339 saveintr = intr_disable(); 340 341 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0, NW = 0 */ 342 343 intr_restore(saveintr); 344} 345#endif 346 347/* 348 * Cyrix 6x86 349 * 350 * XXX - What should I do here? Please let me know. 351 */ 352static void 353init_6x86(void) 354{ 355 register_t saveintr; 356 u_char ccr3, ccr4; 357 358 saveintr = intr_disable(); 359 360 load_cr0(rcr0() | CR0_CD | CR0_NW); 361 wbinvd(); 362 363 /* Initialize CCR0. */ 364 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1); 365 366 /* Initialize CCR1. */ 367#ifdef CPU_CYRIX_NO_LOCK 368 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK); 369#else 370 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK); 371#endif 372 373 /* Initialize CCR2. */ 374#ifdef CPU_SUSP_HLT 375 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT); 376#else 377 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT); 378#endif 379 380 ccr3 = read_cyrix_reg(CCR3); 381 write_cyrix_reg(CCR3, CCR3_MAPEN0); 382 383 /* Initialize CCR4. */ 384 ccr4 = read_cyrix_reg(CCR4); 385 ccr4 |= CCR4_DTE; 386 ccr4 &= ~CCR4_IOMASK; 387#ifdef CPU_IORT 388 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK)); 389#else 390 write_cyrix_reg(CCR4, ccr4 | 7); 391#endif 392 393 /* Initialize CCR5. */ 394#ifdef CPU_WT_ALLOC 395 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC); 396#endif 397 398 /* Restore CCR3. */ 399 write_cyrix_reg(CCR3, ccr3); 400 401 /* Unlock NW bit in CR0. */ 402 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW); 403 404 /* 405 * Earlier revision of the 6x86 CPU could crash the system if 406 * L1 cache is in write-back mode. 407 */ 408 if ((cyrix_did & 0xff00) > 0x1600) 409 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 410 else { 411 /* Revision 2.6 and lower. */ 412#ifdef CYRIX_CACHE_REALLY_WORKS 413 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 414#else 415 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0 and NW = 1 */ 416#endif 417 } 418 419 /* Lock NW bit in CR0. */ 420 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW); 421 422 intr_restore(saveintr); 423} 424#endif /* I486_CPU */ 425 426#ifdef I586_CPU 427/* 428 * Rise mP6 429 */ 430static void 431init_rise(void) 432{ 433 434 /* 435 * The CMPXCHG8B instruction is always available but hidden. 436 */ 437 cpu_feature |= CPUID_CX8; 438} 439 440/* 441 * IDT WinChip C6/2/2A/2B/3 442 * 443 * http://www.centtech.com/winchip_bios_writers_guide_v4_0.pdf 444 */ 445static void 446init_winchip(void) 447{ 448 u_int regs[4]; 449 uint64_t fcr; 450 451 fcr = rdmsr(0x0107); 452 453 /* 454 * Set ECX8, DSMC, DTLOCK/EDCTLB, EMMX, and ERETSTK and clear DPDC. 455 */ 456 fcr |= (1 << 1) | (1 << 7) | (1 << 8) | (1 << 9) | (1 << 16); 457 fcr &= ~(1ULL << 11); 458 459 /* 460 * Additionally, set EBRPRED, E2MMX and EAMD3D for WinChip 2 and 3. 461 */ 462 if (CPUID_TO_MODEL(cpu_id) >= 8) 463 fcr |= (1 << 12) | (1 << 19) | (1 << 20); 464 465 wrmsr(0x0107, fcr); 466 do_cpuid(1, regs); 467 cpu_feature = regs[3]; 468} 469#endif 470 471#ifdef I686_CPU 472/* 473 * Cyrix 6x86MX (code-named M2) 474 * 475 * XXX - What should I do here? Please let me know. 476 */ 477static void 478init_6x86MX(void) 479{ 480 register_t saveintr; 481 u_char ccr3, ccr4; 482 483 saveintr = intr_disable(); 484 485 load_cr0(rcr0() | CR0_CD | CR0_NW); 486 wbinvd(); 487 488 /* Initialize CCR0. */ 489 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1); 490 491 /* Initialize CCR1. */ 492#ifdef CPU_CYRIX_NO_LOCK 493 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK); 494#else 495 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK); 496#endif 497 498 /* Initialize CCR2. */ 499#ifdef CPU_SUSP_HLT 500 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT); 501#else 502 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT); 503#endif 504 505 ccr3 = read_cyrix_reg(CCR3); 506 write_cyrix_reg(CCR3, CCR3_MAPEN0); 507 508 /* Initialize CCR4. */ 509 ccr4 = read_cyrix_reg(CCR4); 510 ccr4 &= ~CCR4_IOMASK; 511#ifdef CPU_IORT 512 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK)); 513#else 514 write_cyrix_reg(CCR4, ccr4 | 7); 515#endif 516 517 /* Initialize CCR5. */ 518#ifdef CPU_WT_ALLOC 519 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC); 520#endif 521 522 /* Restore CCR3. */ 523 write_cyrix_reg(CCR3, ccr3); 524 525 /* Unlock NW bit in CR0. */ 526 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW); 527 528 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 529 530 /* Lock NW bit in CR0. */ 531 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW); 532 533 intr_restore(saveintr); 534} 535 536static int ppro_apic_used = -1; 537 538static void 539init_ppro(void) 540{ 541 u_int64_t apicbase; 542 543 /* 544 * Local APIC should be disabled if it is not going to be used. 545 */ 546 if (ppro_apic_used != 1) { 547 apicbase = rdmsr(MSR_APICBASE); 548 apicbase &= ~APICBASE_ENABLED; 549 wrmsr(MSR_APICBASE, apicbase); 550 ppro_apic_used = 0; 551 } 552} 553 554/* 555 * If the local APIC is going to be used after being disabled above, 556 * re-enable it and don't disable it in the future. 557 */ 558void 559ppro_reenable_apic(void) 560{ 561 u_int64_t apicbase; 562 563 if (ppro_apic_used == 0) { 564 apicbase = rdmsr(MSR_APICBASE); 565 apicbase |= APICBASE_ENABLED; 566 wrmsr(MSR_APICBASE, apicbase); 567 ppro_apic_used = 1; 568 } 569} 570 571/* 572 * Initialize BBL_CR_CTL3 (Control register 3: used to configure the 573 * L2 cache). 574 */ 575static void 576init_mendocino(void) 577{ 578#ifdef CPU_PPRO2CELERON 579 register_t saveintr; 580 u_int64_t bbl_cr_ctl3; 581 582 saveintr = intr_disable(); 583 584 load_cr0(rcr0() | CR0_CD | CR0_NW); 585 wbinvd(); 586 587 bbl_cr_ctl3 = rdmsr(MSR_BBL_CR_CTL3); 588 589 /* If the L2 cache is configured, do nothing. */ 590 if (!(bbl_cr_ctl3 & 1)) { 591 bbl_cr_ctl3 = 0x134052bLL; 592 593 /* Set L2 Cache Latency (Default: 5). */ 594#ifdef CPU_CELERON_L2_LATENCY 595#if CPU_L2_LATENCY > 15 596#error invalid CPU_L2_LATENCY. 597#endif 598 bbl_cr_ctl3 |= CPU_L2_LATENCY << 1; 599#else 600 bbl_cr_ctl3 |= 5 << 1; 601#endif 602 wrmsr(MSR_BBL_CR_CTL3, bbl_cr_ctl3); 603 } 604 605 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); 606 intr_restore(saveintr); 607#endif /* CPU_PPRO2CELERON */ 608} 609 610/* 611 * Initialize special VIA features 612 */ 613static void 614init_via(void) 615{ 616 u_int regs[4], val; 617 uint64_t fcr; 618 619 /* 620 * Explicitly enable CX8 and PGE on C3. 621 * 622 * http://www.via.com.tw/download/mainboards/6/13/VIA_C3_EBGA%20datasheet110.pdf 623 */ 624 if (CPUID_TO_MODEL(cpu_id) <= 9) 625 fcr = (1 << 1) | (1 << 7); 626 else 627 fcr = 0; 628 629 /* 630 * Check extended CPUID for PadLock features. 631 * 632 * http://www.via.com.tw/en/downloads/whitepapers/initiatives/padlock/programming_guide.pdf 633 */ 634 do_cpuid(0xc0000000, regs); 635 if (regs[0] >= 0xc0000001) { 636 do_cpuid(0xc0000001, regs); 637 val = regs[3]; 638 } else 639 val = 0; 640 641 /* Enable RNG if present. */ 642 if ((val & VIA_CPUID_HAS_RNG) != 0) { 643 via_feature_rng = VIA_HAS_RNG; 644 wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG); 645 } 646 647 /* Enable PadLock if present. */ 648 if ((val & VIA_CPUID_HAS_ACE) != 0) 649 via_feature_xcrypt |= VIA_HAS_AES; 650 if ((val & VIA_CPUID_HAS_ACE2) != 0) 651 via_feature_xcrypt |= VIA_HAS_AESCTR; 652 if ((val & VIA_CPUID_HAS_PHE) != 0) 653 via_feature_xcrypt |= VIA_HAS_SHA; 654 if ((val & VIA_CPUID_HAS_PMM) != 0) 655 via_feature_xcrypt |= VIA_HAS_MM; 656 if (via_feature_xcrypt != 0) 657 fcr |= 1 << 28; 658 659 wrmsr(0x1107, rdmsr(0x1107) | fcr); 660} 661 662#endif /* I686_CPU */ 663 664#if defined(I586_CPU) || defined(I686_CPU) 665static void 666init_transmeta(void) 667{ 668 u_int regs[0]; 669 670 /* Expose all hidden features. */ 671 wrmsr(0x80860004, rdmsr(0x80860004) | ~0UL); 672 do_cpuid(1, regs); 673 cpu_feature = regs[3]; 674} 675#endif 676 677extern int elf32_nxstack; 678 679void 680initializecpu(void) 681{ 682 683 switch (cpu) { 684#ifdef I486_CPU 685 case CPU_BLUE: 686 init_bluelightning(); 687 break; 688 case CPU_486DLC: 689 init_486dlc(); 690 break; 691 case CPU_CY486DX: 692 init_cy486dx(); 693 break; 694 case CPU_M1SC: 695 init_5x86(); 696 break; 697#ifdef CPU_I486_ON_386 698 case CPU_486: 699 init_i486_on_386(); 700 break; 701#endif 702 case CPU_M1: 703 init_6x86(); 704 break; 705#endif /* I486_CPU */ 706#ifdef I586_CPU 707 case CPU_586: 708 switch (cpu_vendor_id) { 709 case CPU_VENDOR_AMD: 710#ifdef CPU_WT_ALLOC 711 if (((cpu_id & 0x0f0) > 0) && 712 ((cpu_id & 0x0f0) < 0x60) && 713 ((cpu_id & 0x00f) > 3)) 714 enable_K5_wt_alloc(); 715 else if (((cpu_id & 0x0f0) > 0x80) || 716 (((cpu_id & 0x0f0) == 0x80) && 717 (cpu_id & 0x00f) > 0x07)) 718 enable_K6_2_wt_alloc(); 719 else if ((cpu_id & 0x0f0) > 0x50) 720 enable_K6_wt_alloc(); 721#endif 722 if ((cpu_id & 0xf0) == 0xa0) 723 /* 724 * Make sure the TSC runs through 725 * suspension, otherwise we can't use 726 * it as timecounter 727 */ 728 wrmsr(0x1900, rdmsr(0x1900) | 0x20ULL); 729 break; 730 case CPU_VENDOR_CENTAUR: 731 init_winchip(); 732 break; 733 case CPU_VENDOR_TRANSMETA: 734 init_transmeta(); 735 break; 736 case CPU_VENDOR_RISE: 737 init_rise(); 738 break; 739 } 740 break; 741#endif 742#ifdef I686_CPU 743 case CPU_M2: 744 init_6x86MX(); 745 break; 746 case CPU_686: 747 switch (cpu_vendor_id) { 748 case CPU_VENDOR_INTEL: 749 switch (cpu_id & 0xff0) { 750 case 0x610: 751 init_ppro(); 752 break; 753 case 0x660: 754 init_mendocino(); 755 break; 756 } 757 break; 758#ifdef CPU_ATHLON_SSE_HACK 759 case CPU_VENDOR_AMD: 760 /* 761 * Sometimes the BIOS doesn't enable SSE instructions. 762 * According to AMD document 20734, the mobile 763 * Duron, the (mobile) Athlon 4 and the Athlon MP 764 * support SSE. These correspond to cpu_id 0x66X 765 * or 0x67X. 766 */ 767 if ((cpu_feature & CPUID_XMM) == 0 && 768 ((cpu_id & ~0xf) == 0x660 || 769 (cpu_id & ~0xf) == 0x670 || 770 (cpu_id & ~0xf) == 0x680)) { 771 u_int regs[4]; 772 wrmsr(MSR_HWCR, rdmsr(MSR_HWCR) & ~0x08000); 773 do_cpuid(1, regs); 774 cpu_feature = regs[3]; 775 } 776 break; 777#endif 778 case CPU_VENDOR_CENTAUR: 779 init_via(); 780 break; 781 case CPU_VENDOR_TRANSMETA: 782 init_transmeta(); 783 break; 784 } 785#ifdef PAE 786 if ((amd_feature & AMDID_NX) != 0) { 787 uint64_t msr; 788 789 msr = rdmsr(MSR_EFER) | EFER_NXE; 790 wrmsr(MSR_EFER, msr); 791 pg_nx = PG_NX; 792 elf32_nxstack = 1; 793 } 794#endif 795 break; 796#endif 797 default: 798 break; 799 } 800#if defined(CPU_ENABLE_SSE) 801 if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) { 802 load_cr4(rcr4() | CR4_FXSR | CR4_XMM); 803 cpu_fxsr = hw_instruction_sse = 1; 804 } 805#endif 806} 807 808void 809initializecpucache(void) 810{ 811 812 /* 813 * CPUID with %eax = 1, %ebx returns 814 * Bits 15-8: CLFLUSH line size 815 * (Value * 8 = cache line size in bytes) 816 */ 817 if ((cpu_feature & CPUID_CLFSH) != 0) 818 cpu_clflush_line_size = ((cpu_procinfo >> 8) & 0xff) * 8; 819 /* 820 * XXXKIB: (temporary) hack to work around traps generated 821 * when CLFLUSHing APIC register window under virtualization 822 * environments. These environments tend to disable the 823 * CPUID_SS feature even though the native CPU supports it. 824 */ 825 TUNABLE_INT_FETCH("hw.clflush_disable", &hw_clflush_disable); 826 if (vm_guest != VM_GUEST_NO && hw_clflush_disable == -1) 827 cpu_feature &= ~CPUID_CLFSH; 828 /* 829 * Allow to disable CLFLUSH feature manually by 830 * hw.clflush_disable tunable. 831 */ 832 if (hw_clflush_disable == 1) 833 cpu_feature &= ~CPUID_CLFSH; 834 835#if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE) 836 /* 837 * OS should flush L1 cache by itself because no PC-98 supports 838 * non-Intel CPUs. Use wbinvd instruction before DMA transfer 839 * when need_pre_dma_flush = 1, use invd instruction after DMA 840 * transfer when need_post_dma_flush = 1. If your CPU upgrade 841 * product supports hardware cache control, you can add the 842 * CPU_UPGRADE_HW_CACHE option in your kernel configuration file. 843 * This option eliminates unneeded cache flush instruction(s). 844 */ 845 if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 846 switch (cpu) { 847#ifdef I486_CPU 848 case CPU_486DLC: 849 need_post_dma_flush = 1; 850 break; 851 case CPU_M1SC: 852 need_pre_dma_flush = 1; 853 break; 854 case CPU_CY486DX: 855 need_pre_dma_flush = 1; 856#ifdef CPU_I486_ON_386 857 need_post_dma_flush = 1; 858#endif 859 break; 860#endif 861 default: 862 break; 863 } 864 } else if (cpu_vendor_id == CPU_VENDOR_AMD) { 865 switch (cpu_id & 0xFF0) { 866 case 0x470: /* Enhanced Am486DX2 WB */ 867 case 0x490: /* Enhanced Am486DX4 WB */ 868 case 0x4F0: /* Am5x86 WB */ 869 need_pre_dma_flush = 1; 870 break; 871 } 872 } else if (cpu_vendor_id == CPU_VENDOR_IBM) { 873 need_post_dma_flush = 1; 874 } else { 875#ifdef CPU_I486_ON_386 876 need_pre_dma_flush = 1; 877#endif 878 } 879#endif /* PC98 && !CPU_UPGRADE_HW_CACHE */ 880} 881 882#if defined(I586_CPU) && defined(CPU_WT_ALLOC) 883/* 884 * Enable write allocate feature of AMD processors. 885 * Following two functions require the Maxmem variable being set. 886 */ 887static void 888enable_K5_wt_alloc(void) 889{ 890 u_int64_t msr; 891 register_t saveintr; 892 893 /* 894 * Write allocate is supported only on models 1, 2, and 3, with 895 * a stepping of 4 or greater. 896 */ 897 if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) { 898 saveintr = intr_disable(); 899 msr = rdmsr(0x83); /* HWCR */ 900 wrmsr(0x83, msr & !(0x10)); 901 902 /* 903 * We have to tell the chip where the top of memory is, 904 * since video cards could have frame bufferes there, 905 * memory-mapped I/O could be there, etc. 906 */ 907 if(Maxmem > 0) 908 msr = Maxmem / 16; 909 else 910 msr = 0; 911 msr |= AMD_WT_ALLOC_TME | AMD_WT_ALLOC_FRE; 912#ifdef PC98 913 if (!(inb(0x43b) & 4)) { 914 wrmsr(0x86, 0x0ff00f0); 915 msr |= AMD_WT_ALLOC_PRE; 916 } 917#else 918 /* 919 * There is no way to know wheter 15-16M hole exists or not. 920 * Therefore, we disable write allocate for this range. 921 */ 922 wrmsr(0x86, 0x0ff00f0); 923 msr |= AMD_WT_ALLOC_PRE; 924#endif 925 wrmsr(0x85, msr); 926 927 msr=rdmsr(0x83); 928 wrmsr(0x83, msr|0x10); /* enable write allocate */ 929 intr_restore(saveintr); 930 } 931} 932 933static void 934enable_K6_wt_alloc(void) 935{ 936 quad_t size; 937 u_int64_t whcr; 938 register_t saveintr; 939 940 saveintr = intr_disable(); 941 wbinvd(); 942 943#ifdef CPU_DISABLE_CACHE 944 /* 945 * Certain K6-2 box becomes unstable when write allocation is 946 * enabled. 947 */ 948 /* 949 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12), 950 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported. 951 * All other bits in TR12 have no effect on the processer's operation. 952 * The I/O Trap Restart function (bit 9 of TR12) is always enabled 953 * on the AMD-K6. 954 */ 955 wrmsr(0x0000000e, (u_int64_t)0x0008); 956#endif 957 /* Don't assume that memory size is aligned with 4M. */ 958 if (Maxmem > 0) 959 size = ((Maxmem >> 8) + 3) >> 2; 960 else 961 size = 0; 962 963 /* Limit is 508M bytes. */ 964 if (size > 0x7f) 965 size = 0x7f; 966 whcr = (rdmsr(0xc0000082) & ~(0x7fLL << 1)) | (size << 1); 967 968#if defined(PC98) || defined(NO_MEMORY_HOLE) 969 if (whcr & (0x7fLL << 1)) { 970#ifdef PC98 971 /* 972 * If bit 2 of port 0x43b is 0, disable wrte allocate for the 973 * 15-16M range. 974 */ 975 if (!(inb(0x43b) & 4)) 976 whcr &= ~0x0001LL; 977 else 978#endif 979 whcr |= 0x0001LL; 980 } 981#else 982 /* 983 * There is no way to know wheter 15-16M hole exists or not. 984 * Therefore, we disable write allocate for this range. 985 */ 986 whcr &= ~0x0001LL; 987#endif 988 wrmsr(0x0c0000082, whcr); 989 990 intr_restore(saveintr); 991} 992 993static void 994enable_K6_2_wt_alloc(void) 995{ 996 quad_t size; 997 u_int64_t whcr; 998 register_t saveintr; 999 1000 saveintr = intr_disable(); 1001 wbinvd(); 1002 1003#ifdef CPU_DISABLE_CACHE 1004 /* 1005 * Certain K6-2 box becomes unstable when write allocation is 1006 * enabled. 1007 */ 1008 /* 1009 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12), 1010 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported. 1011 * All other bits in TR12 have no effect on the processer's operation. 1012 * The I/O Trap Restart function (bit 9 of TR12) is always enabled 1013 * on the AMD-K6. 1014 */ 1015 wrmsr(0x0000000e, (u_int64_t)0x0008); 1016#endif 1017 /* Don't assume that memory size is aligned with 4M. */ 1018 if (Maxmem > 0) 1019 size = ((Maxmem >> 8) + 3) >> 2; 1020 else 1021 size = 0; 1022 1023 /* Limit is 4092M bytes. */ 1024 if (size > 0x3fff) 1025 size = 0x3ff; 1026 whcr = (rdmsr(0xc0000082) & ~(0x3ffLL << 22)) | (size << 22); 1027 1028#if defined(PC98) || defined(NO_MEMORY_HOLE) 1029 if (whcr & (0x3ffLL << 22)) { 1030#ifdef PC98 1031 /* 1032 * If bit 2 of port 0x43b is 0, disable wrte allocate for the 1033 * 15-16M range. 1034 */ 1035 if (!(inb(0x43b) & 4)) 1036 whcr &= ~(1LL << 16); 1037 else 1038#endif 1039 whcr |= 1LL << 16; 1040 } 1041#else 1042 /* 1043 * There is no way to know wheter 15-16M hole exists or not. 1044 * Therefore, we disable write allocate for this range. 1045 */ 1046 whcr &= ~(1LL << 16); 1047#endif 1048 wrmsr(0x0c0000082, whcr); 1049 1050 intr_restore(saveintr); 1051} 1052#endif /* I585_CPU && CPU_WT_ALLOC */ 1053 1054#include "opt_ddb.h" 1055#ifdef DDB 1056#include <ddb/ddb.h> 1057 1058DB_SHOW_COMMAND(cyrixreg, cyrixreg) 1059{ 1060 register_t saveintr; 1061 u_int cr0; 1062 u_char ccr1, ccr2, ccr3; 1063 u_char ccr0 = 0, ccr4 = 0, ccr5 = 0, pcr0 = 0; 1064 1065 cr0 = rcr0(); 1066 if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 1067 saveintr = intr_disable(); 1068 1069 1070 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) { 1071 ccr0 = read_cyrix_reg(CCR0); 1072 } 1073 ccr1 = read_cyrix_reg(CCR1); 1074 ccr2 = read_cyrix_reg(CCR2); 1075 ccr3 = read_cyrix_reg(CCR3); 1076 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) { 1077 write_cyrix_reg(CCR3, CCR3_MAPEN0); 1078 ccr4 = read_cyrix_reg(CCR4); 1079 if ((cpu == CPU_M1) || (cpu == CPU_M2)) 1080 ccr5 = read_cyrix_reg(CCR5); 1081 else 1082 pcr0 = read_cyrix_reg(PCR0); 1083 write_cyrix_reg(CCR3, ccr3); /* Restore CCR3. */ 1084 } 1085 intr_restore(saveintr); 1086 1087 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) 1088 printf("CCR0=%x, ", (u_int)ccr0); 1089 1090 printf("CCR1=%x, CCR2=%x, CCR3=%x", 1091 (u_int)ccr1, (u_int)ccr2, (u_int)ccr3); 1092 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) { 1093 printf(", CCR4=%x, ", (u_int)ccr4); 1094 if (cpu == CPU_M1SC) 1095 printf("PCR0=%x\n", pcr0); 1096 else 1097 printf("CCR5=%x\n", ccr5); 1098 } 1099 } 1100 printf("CR0=%x\n", cr0); 1101} 1102#endif /* DDB */ 1103