initcpu.c revision 276070
1/*- 2 * Copyright (c) KATO Takenori, 1997, 1998. 3 * 4 * All rights reserved. Unpublished rights reserved under the copyright 5 * laws of Japan. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer as 13 * the first lines of this file unmodified. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: stable/10/sys/i386/i386/initcpu.c 276070 2014-12-22 18:40:59Z jhb $"); 32 33#include "opt_cpu.h" 34 35#include <sys/param.h> 36#include <sys/kernel.h> 37#include <sys/systm.h> 38#include <sys/sysctl.h> 39 40#include <machine/cputypes.h> 41#include <machine/md_var.h> 42#include <machine/specialreg.h> 43 44#include <vm/vm.h> 45#include <vm/pmap.h> 46 47#if !defined(CPU_DISABLE_SSE) && defined(I686_CPU) 48#define CPU_ENABLE_SSE 49#endif 50 51#ifdef I486_CPU 52static void init_5x86(void); 53static void init_bluelightning(void); 54static void init_486dlc(void); 55static void init_cy486dx(void); 56#ifdef CPU_I486_ON_386 57static void init_i486_on_386(void); 58#endif 59static void init_6x86(void); 60#endif /* I486_CPU */ 61 62#ifdef I686_CPU 63static void init_6x86MX(void); 64static void init_ppro(void); 65static void init_mendocino(void); 66#endif 67 68static int hw_instruction_sse; 69SYSCTL_INT(_hw, OID_AUTO, instruction_sse, CTLFLAG_RD, 70 &hw_instruction_sse, 0, "SIMD/MMX2 instructions available in CPU"); 71/* 72 * -1: automatic (default) 73 * 0: keep enable CLFLUSH 74 * 1: force disable CLFLUSH 75 */ 76static int hw_clflush_disable = -1; 77 78int cpu; /* Are we 386, 386sx, 486, etc? */ 79u_int cpu_feature; /* Feature flags */ 80u_int cpu_feature2; /* Feature flags */ 81u_int amd_feature; /* AMD feature flags */ 82u_int amd_feature2; /* AMD feature flags */ 83u_int amd_pminfo; /* AMD advanced power management info */ 84u_int via_feature_rng; /* VIA RNG features */ 85u_int via_feature_xcrypt; /* VIA ACE features */ 86u_int cpu_high; /* Highest arg to CPUID */ 87u_int cpu_exthigh; /* Highest arg to extended CPUID */ 88u_int cpu_id; /* Stepping ID */ 89u_int cpu_procinfo; /* HyperThreading Info / Brand Index / CLFUSH */ 90u_int cpu_procinfo2; /* Multicore info */ 91char cpu_vendor[20]; /* CPU Origin code */ 92u_int cpu_vendor_id; /* CPU vendor ID */ 93#ifdef CPU_ENABLE_SSE 94u_int cpu_fxsr; /* SSE enabled */ 95u_int cpu_mxcsr_mask; /* Valid bits in mxcsr */ 96#endif 97u_int cpu_clflush_line_size = 32; 98u_int cpu_stdext_feature; 99u_int cpu_mon_mwait_flags; /* MONITOR/MWAIT flags (CPUID.05H.ECX) */ 100u_int cpu_mon_min_size; /* MONITOR minimum range size, bytes */ 101u_int cpu_mon_max_size; /* MONITOR minimum range size, bytes */ 102u_int cyrix_did; /* Device ID of Cyrix CPU */ 103 104SYSCTL_UINT(_hw, OID_AUTO, via_feature_rng, CTLFLAG_RD, 105 &via_feature_rng, 0, "VIA RNG feature available in CPU"); 106SYSCTL_UINT(_hw, OID_AUTO, via_feature_xcrypt, CTLFLAG_RD, 107 &via_feature_xcrypt, 0, "VIA xcrypt feature available in CPU"); 108 109#ifdef I486_CPU 110/* 111 * IBM Blue Lightning 112 */ 113static void 114init_bluelightning(void) 115{ 116 register_t saveintr; 117 118#if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE) 119 need_post_dma_flush = 1; 120#endif 121 122 saveintr = intr_disable(); 123 124 load_cr0(rcr0() | CR0_CD | CR0_NW); 125 invd(); 126 127#ifdef CPU_BLUELIGHTNING_FPU_OP_CACHE 128 wrmsr(0x1000, 0x9c92LL); /* FP operand can be cacheable on Cyrix FPU */ 129#else 130 wrmsr(0x1000, 0x1c92LL); /* Intel FPU */ 131#endif 132 /* Enables 13MB and 0-640KB cache. */ 133 wrmsr(0x1001, (0xd0LL << 32) | 0x3ff); 134#ifdef CPU_BLUELIGHTNING_3X 135 wrmsr(0x1002, 0x04000000LL); /* Enables triple-clock mode. */ 136#else 137 wrmsr(0x1002, 0x03000000LL); /* Enables double-clock mode. */ 138#endif 139 140 /* Enable caching in CR0. */ 141 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 142 invd(); 143 intr_restore(saveintr); 144} 145 146/* 147 * Cyrix 486SLC/DLC/SR/DR series 148 */ 149static void 150init_486dlc(void) 151{ 152 register_t saveintr; 153 u_char ccr0; 154 155 saveintr = intr_disable(); 156 invd(); 157 158 ccr0 = read_cyrix_reg(CCR0); 159#ifndef CYRIX_CACHE_WORKS 160 ccr0 |= CCR0_NC1 | CCR0_BARB; 161 write_cyrix_reg(CCR0, ccr0); 162 invd(); 163#else 164 ccr0 &= ~CCR0_NC0; 165#ifndef CYRIX_CACHE_REALLY_WORKS 166 ccr0 |= CCR0_NC1 | CCR0_BARB; 167#else 168 ccr0 |= CCR0_NC1; 169#endif 170#ifdef CPU_DIRECT_MAPPED_CACHE 171 ccr0 |= CCR0_CO; /* Direct mapped mode. */ 172#endif 173 write_cyrix_reg(CCR0, ccr0); 174 175 /* Clear non-cacheable region. */ 176 write_cyrix_reg(NCR1+2, NCR_SIZE_0K); 177 write_cyrix_reg(NCR2+2, NCR_SIZE_0K); 178 write_cyrix_reg(NCR3+2, NCR_SIZE_0K); 179 write_cyrix_reg(NCR4+2, NCR_SIZE_0K); 180 181 write_cyrix_reg(0, 0); /* dummy write */ 182 183 /* Enable caching in CR0. */ 184 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 185 invd(); 186#endif /* !CYRIX_CACHE_WORKS */ 187 intr_restore(saveintr); 188} 189 190 191/* 192 * Cyrix 486S/DX series 193 */ 194static void 195init_cy486dx(void) 196{ 197 register_t saveintr; 198 u_char ccr2; 199 200 saveintr = intr_disable(); 201 invd(); 202 203 ccr2 = read_cyrix_reg(CCR2); 204#ifdef CPU_SUSP_HLT 205 ccr2 |= CCR2_SUSP_HLT; 206#endif 207 208#ifdef PC98 209 /* Enables WB cache interface pin and Lock NW bit in CR0. */ 210 ccr2 |= CCR2_WB | CCR2_LOCK_NW; 211 /* Unlock NW bit in CR0. */ 212 write_cyrix_reg(CCR2, ccr2 & ~CCR2_LOCK_NW); 213 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */ 214#endif 215 216 write_cyrix_reg(CCR2, ccr2); 217 intr_restore(saveintr); 218} 219 220 221/* 222 * Cyrix 5x86 223 */ 224static void 225init_5x86(void) 226{ 227 register_t saveintr; 228 u_char ccr2, ccr3, ccr4, pcr0; 229 230 saveintr = intr_disable(); 231 232 load_cr0(rcr0() | CR0_CD | CR0_NW); 233 wbinvd(); 234 235 (void)read_cyrix_reg(CCR3); /* dummy */ 236 237 /* Initialize CCR2. */ 238 ccr2 = read_cyrix_reg(CCR2); 239 ccr2 |= CCR2_WB; 240#ifdef CPU_SUSP_HLT 241 ccr2 |= CCR2_SUSP_HLT; 242#else 243 ccr2 &= ~CCR2_SUSP_HLT; 244#endif 245 ccr2 |= CCR2_WT1; 246 write_cyrix_reg(CCR2, ccr2); 247 248 /* Initialize CCR4. */ 249 ccr3 = read_cyrix_reg(CCR3); 250 write_cyrix_reg(CCR3, CCR3_MAPEN0); 251 252 ccr4 = read_cyrix_reg(CCR4); 253 ccr4 |= CCR4_DTE; 254 ccr4 |= CCR4_MEM; 255#ifdef CPU_FASTER_5X86_FPU 256 ccr4 |= CCR4_FASTFPE; 257#else 258 ccr4 &= ~CCR4_FASTFPE; 259#endif 260 ccr4 &= ~CCR4_IOMASK; 261 /******************************************************************** 262 * WARNING: The "BIOS Writers Guide" mentions that I/O recovery time 263 * should be 0 for errata fix. 264 ********************************************************************/ 265#ifdef CPU_IORT 266 ccr4 |= CPU_IORT & CCR4_IOMASK; 267#endif 268 write_cyrix_reg(CCR4, ccr4); 269 270 /* Initialize PCR0. */ 271 /**************************************************************** 272 * WARNING: RSTK_EN and LOOP_EN could make your system unstable. 273 * BTB_EN might make your system unstable. 274 ****************************************************************/ 275 pcr0 = read_cyrix_reg(PCR0); 276#ifdef CPU_RSTK_EN 277 pcr0 |= PCR0_RSTK; 278#else 279 pcr0 &= ~PCR0_RSTK; 280#endif 281#ifdef CPU_BTB_EN 282 pcr0 |= PCR0_BTB; 283#else 284 pcr0 &= ~PCR0_BTB; 285#endif 286#ifdef CPU_LOOP_EN 287 pcr0 |= PCR0_LOOP; 288#else 289 pcr0 &= ~PCR0_LOOP; 290#endif 291 292 /**************************************************************** 293 * WARNING: if you use a memory mapped I/O device, don't use 294 * DISABLE_5X86_LSSER option, which may reorder memory mapped 295 * I/O access. 296 * IF YOUR MOTHERBOARD HAS PCI BUS, DON'T DISABLE LSSER. 297 ****************************************************************/ 298#ifdef CPU_DISABLE_5X86_LSSER 299 pcr0 &= ~PCR0_LSSER; 300#else 301 pcr0 |= PCR0_LSSER; 302#endif 303 write_cyrix_reg(PCR0, pcr0); 304 305 /* Restore CCR3. */ 306 write_cyrix_reg(CCR3, ccr3); 307 308 (void)read_cyrix_reg(0x80); /* dummy */ 309 310 /* Unlock NW bit in CR0. */ 311 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW); 312 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0, NW = 1 */ 313 /* Lock NW bit in CR0. */ 314 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW); 315 316 intr_restore(saveintr); 317} 318 319#ifdef CPU_I486_ON_386 320/* 321 * There are i486 based upgrade products for i386 machines. 322 * In this case, BIOS doesn't enable CPU cache. 323 */ 324static void 325init_i486_on_386(void) 326{ 327 register_t saveintr; 328 329#if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE) 330 need_post_dma_flush = 1; 331#endif 332 333 saveintr = intr_disable(); 334 335 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0, NW = 0 */ 336 337 intr_restore(saveintr); 338} 339#endif 340 341/* 342 * Cyrix 6x86 343 * 344 * XXX - What should I do here? Please let me know. 345 */ 346static void 347init_6x86(void) 348{ 349 register_t saveintr; 350 u_char ccr3, ccr4; 351 352 saveintr = intr_disable(); 353 354 load_cr0(rcr0() | CR0_CD | CR0_NW); 355 wbinvd(); 356 357 /* Initialize CCR0. */ 358 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1); 359 360 /* Initialize CCR1. */ 361#ifdef CPU_CYRIX_NO_LOCK 362 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK); 363#else 364 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK); 365#endif 366 367 /* Initialize CCR2. */ 368#ifdef CPU_SUSP_HLT 369 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT); 370#else 371 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT); 372#endif 373 374 ccr3 = read_cyrix_reg(CCR3); 375 write_cyrix_reg(CCR3, CCR3_MAPEN0); 376 377 /* Initialize CCR4. */ 378 ccr4 = read_cyrix_reg(CCR4); 379 ccr4 |= CCR4_DTE; 380 ccr4 &= ~CCR4_IOMASK; 381#ifdef CPU_IORT 382 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK)); 383#else 384 write_cyrix_reg(CCR4, ccr4 | 7); 385#endif 386 387 /* Initialize CCR5. */ 388#ifdef CPU_WT_ALLOC 389 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC); 390#endif 391 392 /* Restore CCR3. */ 393 write_cyrix_reg(CCR3, ccr3); 394 395 /* Unlock NW bit in CR0. */ 396 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW); 397 398 /* 399 * Earlier revision of the 6x86 CPU could crash the system if 400 * L1 cache is in write-back mode. 401 */ 402 if ((cyrix_did & 0xff00) > 0x1600) 403 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 404 else { 405 /* Revision 2.6 and lower. */ 406#ifdef CYRIX_CACHE_REALLY_WORKS 407 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 408#else 409 load_cr0((rcr0() & ~CR0_CD) | CR0_NW); /* CD = 0 and NW = 1 */ 410#endif 411 } 412 413 /* Lock NW bit in CR0. */ 414 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW); 415 416 intr_restore(saveintr); 417} 418#endif /* I486_CPU */ 419 420#ifdef I586_CPU 421/* 422 * Rise mP6 423 */ 424static void 425init_rise(void) 426{ 427 428 /* 429 * The CMPXCHG8B instruction is always available but hidden. 430 */ 431 cpu_feature |= CPUID_CX8; 432} 433 434/* 435 * IDT WinChip C6/2/2A/2B/3 436 * 437 * http://www.centtech.com/winchip_bios_writers_guide_v4_0.pdf 438 */ 439static void 440init_winchip(void) 441{ 442 u_int regs[4]; 443 uint64_t fcr; 444 445 fcr = rdmsr(0x0107); 446 447 /* 448 * Set ECX8, DSMC, DTLOCK/EDCTLB, EMMX, and ERETSTK and clear DPDC. 449 */ 450 fcr |= (1 << 1) | (1 << 7) | (1 << 8) | (1 << 9) | (1 << 16); 451 fcr &= ~(1ULL << 11); 452 453 /* 454 * Additioanlly, set EBRPRED, E2MMX and EAMD3D for WinChip 2 and 3. 455 */ 456 if (CPUID_TO_MODEL(cpu_id) >= 8) 457 fcr |= (1 << 12) | (1 << 19) | (1 << 20); 458 459 wrmsr(0x0107, fcr); 460 do_cpuid(1, regs); 461 cpu_feature = regs[3]; 462} 463#endif 464 465#ifdef I686_CPU 466/* 467 * Cyrix 6x86MX (code-named M2) 468 * 469 * XXX - What should I do here? Please let me know. 470 */ 471static void 472init_6x86MX(void) 473{ 474 register_t saveintr; 475 u_char ccr3, ccr4; 476 477 saveintr = intr_disable(); 478 479 load_cr0(rcr0() | CR0_CD | CR0_NW); 480 wbinvd(); 481 482 /* Initialize CCR0. */ 483 write_cyrix_reg(CCR0, read_cyrix_reg(CCR0) | CCR0_NC1); 484 485 /* Initialize CCR1. */ 486#ifdef CPU_CYRIX_NO_LOCK 487 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) | CCR1_NO_LOCK); 488#else 489 write_cyrix_reg(CCR1, read_cyrix_reg(CCR1) & ~CCR1_NO_LOCK); 490#endif 491 492 /* Initialize CCR2. */ 493#ifdef CPU_SUSP_HLT 494 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_SUSP_HLT); 495#else 496 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_SUSP_HLT); 497#endif 498 499 ccr3 = read_cyrix_reg(CCR3); 500 write_cyrix_reg(CCR3, CCR3_MAPEN0); 501 502 /* Initialize CCR4. */ 503 ccr4 = read_cyrix_reg(CCR4); 504 ccr4 &= ~CCR4_IOMASK; 505#ifdef CPU_IORT 506 write_cyrix_reg(CCR4, ccr4 | (CPU_IORT & CCR4_IOMASK)); 507#else 508 write_cyrix_reg(CCR4, ccr4 | 7); 509#endif 510 511 /* Initialize CCR5. */ 512#ifdef CPU_WT_ALLOC 513 write_cyrix_reg(CCR5, read_cyrix_reg(CCR5) | CCR5_WT_ALLOC); 514#endif 515 516 /* Restore CCR3. */ 517 write_cyrix_reg(CCR3, ccr3); 518 519 /* Unlock NW bit in CR0. */ 520 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) & ~CCR2_LOCK_NW); 521 522 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); /* CD = 0 and NW = 0 */ 523 524 /* Lock NW bit in CR0. */ 525 write_cyrix_reg(CCR2, read_cyrix_reg(CCR2) | CCR2_LOCK_NW); 526 527 intr_restore(saveintr); 528} 529 530static void 531init_ppro(void) 532{ 533 u_int64_t apicbase; 534 535 /* 536 * Local APIC should be disabled if it is not going to be used. 537 */ 538 apicbase = rdmsr(MSR_APICBASE); 539 apicbase &= ~APICBASE_ENABLED; 540 wrmsr(MSR_APICBASE, apicbase); 541} 542 543/* 544 * Initialize BBL_CR_CTL3 (Control register 3: used to configure the 545 * L2 cache). 546 */ 547static void 548init_mendocino(void) 549{ 550#ifdef CPU_PPRO2CELERON 551 register_t saveintr; 552 u_int64_t bbl_cr_ctl3; 553 554 saveintr = intr_disable(); 555 556 load_cr0(rcr0() | CR0_CD | CR0_NW); 557 wbinvd(); 558 559 bbl_cr_ctl3 = rdmsr(MSR_BBL_CR_CTL3); 560 561 /* If the L2 cache is configured, do nothing. */ 562 if (!(bbl_cr_ctl3 & 1)) { 563 bbl_cr_ctl3 = 0x134052bLL; 564 565 /* Set L2 Cache Latency (Default: 5). */ 566#ifdef CPU_CELERON_L2_LATENCY 567#if CPU_L2_LATENCY > 15 568#error invalid CPU_L2_LATENCY. 569#endif 570 bbl_cr_ctl3 |= CPU_L2_LATENCY << 1; 571#else 572 bbl_cr_ctl3 |= 5 << 1; 573#endif 574 wrmsr(MSR_BBL_CR_CTL3, bbl_cr_ctl3); 575 } 576 577 load_cr0(rcr0() & ~(CR0_CD | CR0_NW)); 578 intr_restore(saveintr); 579#endif /* CPU_PPRO2CELERON */ 580} 581 582/* 583 * Initialize special VIA features 584 */ 585static void 586init_via(void) 587{ 588 u_int regs[4], val; 589 uint64_t fcr; 590 591 /* 592 * Explicitly enable CX8 and PGE on C3. 593 * 594 * http://www.via.com.tw/download/mainboards/6/13/VIA_C3_EBGA%20datasheet110.pdf 595 */ 596 if (CPUID_TO_MODEL(cpu_id) <= 9) 597 fcr = (1 << 1) | (1 << 7); 598 else 599 fcr = 0; 600 601 /* 602 * Check extended CPUID for PadLock features. 603 * 604 * http://www.via.com.tw/en/downloads/whitepapers/initiatives/padlock/programming_guide.pdf 605 */ 606 do_cpuid(0xc0000000, regs); 607 if (regs[0] >= 0xc0000001) { 608 do_cpuid(0xc0000001, regs); 609 val = regs[3]; 610 } else 611 val = 0; 612 613 /* Enable RNG if present. */ 614 if ((val & VIA_CPUID_HAS_RNG) != 0) { 615 via_feature_rng = VIA_HAS_RNG; 616 wrmsr(0x110B, rdmsr(0x110B) | VIA_CPUID_DO_RNG); 617 } 618 619 /* Enable PadLock if present. */ 620 if ((val & VIA_CPUID_HAS_ACE) != 0) 621 via_feature_xcrypt |= VIA_HAS_AES; 622 if ((val & VIA_CPUID_HAS_ACE2) != 0) 623 via_feature_xcrypt |= VIA_HAS_AESCTR; 624 if ((val & VIA_CPUID_HAS_PHE) != 0) 625 via_feature_xcrypt |= VIA_HAS_SHA; 626 if ((val & VIA_CPUID_HAS_PMM) != 0) 627 via_feature_xcrypt |= VIA_HAS_MM; 628 if (via_feature_xcrypt != 0) 629 fcr |= 1 << 28; 630 631 wrmsr(0x1107, rdmsr(0x1107) | fcr); 632} 633 634#endif /* I686_CPU */ 635 636#if defined(I586_CPU) || defined(I686_CPU) 637static void 638init_transmeta(void) 639{ 640 u_int regs[0]; 641 642 /* Expose all hidden features. */ 643 wrmsr(0x80860004, rdmsr(0x80860004) | ~0UL); 644 do_cpuid(1, regs); 645 cpu_feature = regs[3]; 646} 647#endif 648 649/* 650 * Initialize CR4 (Control register 4) to enable SSE instructions. 651 */ 652void 653enable_sse(void) 654{ 655#if defined(CPU_ENABLE_SSE) 656 if ((cpu_feature & CPUID_XMM) && (cpu_feature & CPUID_FXSR)) { 657 load_cr4(rcr4() | CR4_FXSR | CR4_XMM); 658 cpu_fxsr = hw_instruction_sse = 1; 659 } 660#endif 661} 662 663extern int elf32_nxstack; 664 665void 666initializecpu(void) 667{ 668 669 switch (cpu) { 670#ifdef I486_CPU 671 case CPU_BLUE: 672 init_bluelightning(); 673 break; 674 case CPU_486DLC: 675 init_486dlc(); 676 break; 677 case CPU_CY486DX: 678 init_cy486dx(); 679 break; 680 case CPU_M1SC: 681 init_5x86(); 682 break; 683#ifdef CPU_I486_ON_386 684 case CPU_486: 685 init_i486_on_386(); 686 break; 687#endif 688 case CPU_M1: 689 init_6x86(); 690 break; 691#endif /* I486_CPU */ 692#ifdef I586_CPU 693 case CPU_586: 694 switch (cpu_vendor_id) { 695 case CPU_VENDOR_CENTAUR: 696 init_winchip(); 697 break; 698 case CPU_VENDOR_TRANSMETA: 699 init_transmeta(); 700 break; 701 case CPU_VENDOR_RISE: 702 init_rise(); 703 break; 704 } 705 break; 706#endif 707#ifdef I686_CPU 708 case CPU_M2: 709 init_6x86MX(); 710 break; 711 case CPU_686: 712 switch (cpu_vendor_id) { 713 case CPU_VENDOR_INTEL: 714 switch (cpu_id & 0xff0) { 715 case 0x610: 716 init_ppro(); 717 break; 718 case 0x660: 719 init_mendocino(); 720 break; 721 } 722 break; 723#ifdef CPU_ATHLON_SSE_HACK 724 case CPU_VENDOR_AMD: 725 /* 726 * Sometimes the BIOS doesn't enable SSE instructions. 727 * According to AMD document 20734, the mobile 728 * Duron, the (mobile) Athlon 4 and the Athlon MP 729 * support SSE. These correspond to cpu_id 0x66X 730 * or 0x67X. 731 */ 732 if ((cpu_feature & CPUID_XMM) == 0 && 733 ((cpu_id & ~0xf) == 0x660 || 734 (cpu_id & ~0xf) == 0x670 || 735 (cpu_id & ~0xf) == 0x680)) { 736 u_int regs[4]; 737 wrmsr(MSR_HWCR, rdmsr(MSR_HWCR) & ~0x08000); 738 do_cpuid(1, regs); 739 cpu_feature = regs[3]; 740 } 741 break; 742#endif 743 case CPU_VENDOR_CENTAUR: 744 init_via(); 745 break; 746 case CPU_VENDOR_TRANSMETA: 747 init_transmeta(); 748 break; 749 } 750#ifdef PAE 751 if ((amd_feature & AMDID_NX) != 0) { 752 uint64_t msr; 753 754 msr = rdmsr(MSR_EFER) | EFER_NXE; 755 wrmsr(MSR_EFER, msr); 756 pg_nx = PG_NX; 757 elf32_nxstack = 1; 758 } 759#endif 760 break; 761#endif 762 default: 763 break; 764 } 765 enable_sse(); 766 767 /* 768 * CPUID with %eax = 1, %ebx returns 769 * Bits 15-8: CLFLUSH line size 770 * (Value * 8 = cache line size in bytes) 771 */ 772 if ((cpu_feature & CPUID_CLFSH) != 0) 773 cpu_clflush_line_size = ((cpu_procinfo >> 8) & 0xff) * 8; 774 /* 775 * XXXKIB: (temporary) hack to work around traps generated 776 * when CLFLUSHing APIC register window under virtualization 777 * environments. These environments tend to disable the 778 * CPUID_SS feature even though the native CPU supports it. 779 */ 780 TUNABLE_INT_FETCH("hw.clflush_disable", &hw_clflush_disable); 781 if (vm_guest != VM_GUEST_NO && hw_clflush_disable == -1) 782 cpu_feature &= ~CPUID_CLFSH; 783 /* 784 * Allow to disable CLFLUSH feature manually by 785 * hw.clflush_disable tunable. 786 */ 787 if (hw_clflush_disable == 1) 788 cpu_feature &= ~CPUID_CLFSH; 789 790#if defined(PC98) && !defined(CPU_UPGRADE_HW_CACHE) 791 /* 792 * OS should flush L1 cache by itself because no PC-98 supports 793 * non-Intel CPUs. Use wbinvd instruction before DMA transfer 794 * when need_pre_dma_flush = 1, use invd instruction after DMA 795 * transfer when need_post_dma_flush = 1. If your CPU upgrade 796 * product supports hardware cache control, you can add the 797 * CPU_UPGRADE_HW_CACHE option in your kernel configuration file. 798 * This option eliminates unneeded cache flush instruction(s). 799 */ 800 if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 801 switch (cpu) { 802#ifdef I486_CPU 803 case CPU_486DLC: 804 need_post_dma_flush = 1; 805 break; 806 case CPU_M1SC: 807 need_pre_dma_flush = 1; 808 break; 809 case CPU_CY486DX: 810 need_pre_dma_flush = 1; 811#ifdef CPU_I486_ON_386 812 need_post_dma_flush = 1; 813#endif 814 break; 815#endif 816 default: 817 break; 818 } 819 } else if (cpu_vendor_id == CPU_VENDOR_AMD) { 820 switch (cpu_id & 0xFF0) { 821 case 0x470: /* Enhanced Am486DX2 WB */ 822 case 0x490: /* Enhanced Am486DX4 WB */ 823 case 0x4F0: /* Am5x86 WB */ 824 need_pre_dma_flush = 1; 825 break; 826 } 827 } else if (cpu_vendor_id == CPU_VENDOR_IBM) { 828 need_post_dma_flush = 1; 829 } else { 830#ifdef CPU_I486_ON_386 831 need_pre_dma_flush = 1; 832#endif 833 } 834#endif /* PC98 && !CPU_UPGRADE_HW_CACHE */ 835} 836 837#if defined(I586_CPU) && defined(CPU_WT_ALLOC) 838/* 839 * Enable write allocate feature of AMD processors. 840 * Following two functions require the Maxmem variable being set. 841 */ 842void 843enable_K5_wt_alloc(void) 844{ 845 u_int64_t msr; 846 register_t saveintr; 847 848 /* 849 * Write allocate is supported only on models 1, 2, and 3, with 850 * a stepping of 4 or greater. 851 */ 852 if (((cpu_id & 0xf0) > 0) && ((cpu_id & 0x0f) > 3)) { 853 saveintr = intr_disable(); 854 msr = rdmsr(0x83); /* HWCR */ 855 wrmsr(0x83, msr & !(0x10)); 856 857 /* 858 * We have to tell the chip where the top of memory is, 859 * since video cards could have frame bufferes there, 860 * memory-mapped I/O could be there, etc. 861 */ 862 if(Maxmem > 0) 863 msr = Maxmem / 16; 864 else 865 msr = 0; 866 msr |= AMD_WT_ALLOC_TME | AMD_WT_ALLOC_FRE; 867#ifdef PC98 868 if (!(inb(0x43b) & 4)) { 869 wrmsr(0x86, 0x0ff00f0); 870 msr |= AMD_WT_ALLOC_PRE; 871 } 872#else 873 /* 874 * There is no way to know wheter 15-16M hole exists or not. 875 * Therefore, we disable write allocate for this range. 876 */ 877 wrmsr(0x86, 0x0ff00f0); 878 msr |= AMD_WT_ALLOC_PRE; 879#endif 880 wrmsr(0x85, msr); 881 882 msr=rdmsr(0x83); 883 wrmsr(0x83, msr|0x10); /* enable write allocate */ 884 intr_restore(saveintr); 885 } 886} 887 888void 889enable_K6_wt_alloc(void) 890{ 891 quad_t size; 892 u_int64_t whcr; 893 register_t saveintr; 894 895 saveintr = intr_disable(); 896 wbinvd(); 897 898#ifdef CPU_DISABLE_CACHE 899 /* 900 * Certain K6-2 box becomes unstable when write allocation is 901 * enabled. 902 */ 903 /* 904 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12), 905 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported. 906 * All other bits in TR12 have no effect on the processer's operation. 907 * The I/O Trap Restart function (bit 9 of TR12) is always enabled 908 * on the AMD-K6. 909 */ 910 wrmsr(0x0000000e, (u_int64_t)0x0008); 911#endif 912 /* Don't assume that memory size is aligned with 4M. */ 913 if (Maxmem > 0) 914 size = ((Maxmem >> 8) + 3) >> 2; 915 else 916 size = 0; 917 918 /* Limit is 508M bytes. */ 919 if (size > 0x7f) 920 size = 0x7f; 921 whcr = (rdmsr(0xc0000082) & ~(0x7fLL << 1)) | (size << 1); 922 923#if defined(PC98) || defined(NO_MEMORY_HOLE) 924 if (whcr & (0x7fLL << 1)) { 925#ifdef PC98 926 /* 927 * If bit 2 of port 0x43b is 0, disable wrte allocate for the 928 * 15-16M range. 929 */ 930 if (!(inb(0x43b) & 4)) 931 whcr &= ~0x0001LL; 932 else 933#endif 934 whcr |= 0x0001LL; 935 } 936#else 937 /* 938 * There is no way to know wheter 15-16M hole exists or not. 939 * Therefore, we disable write allocate for this range. 940 */ 941 whcr &= ~0x0001LL; 942#endif 943 wrmsr(0x0c0000082, whcr); 944 945 intr_restore(saveintr); 946} 947 948void 949enable_K6_2_wt_alloc(void) 950{ 951 quad_t size; 952 u_int64_t whcr; 953 register_t saveintr; 954 955 saveintr = intr_disable(); 956 wbinvd(); 957 958#ifdef CPU_DISABLE_CACHE 959 /* 960 * Certain K6-2 box becomes unstable when write allocation is 961 * enabled. 962 */ 963 /* 964 * The AMD-K6 processer provides the 64-bit Test Register 12(TR12), 965 * but only the Cache Inhibit(CI) (bit 3 of TR12) is suppported. 966 * All other bits in TR12 have no effect on the processer's operation. 967 * The I/O Trap Restart function (bit 9 of TR12) is always enabled 968 * on the AMD-K6. 969 */ 970 wrmsr(0x0000000e, (u_int64_t)0x0008); 971#endif 972 /* Don't assume that memory size is aligned with 4M. */ 973 if (Maxmem > 0) 974 size = ((Maxmem >> 8) + 3) >> 2; 975 else 976 size = 0; 977 978 /* Limit is 4092M bytes. */ 979 if (size > 0x3fff) 980 size = 0x3ff; 981 whcr = (rdmsr(0xc0000082) & ~(0x3ffLL << 22)) | (size << 22); 982 983#if defined(PC98) || defined(NO_MEMORY_HOLE) 984 if (whcr & (0x3ffLL << 22)) { 985#ifdef PC98 986 /* 987 * If bit 2 of port 0x43b is 0, disable wrte allocate for the 988 * 15-16M range. 989 */ 990 if (!(inb(0x43b) & 4)) 991 whcr &= ~(1LL << 16); 992 else 993#endif 994 whcr |= 1LL << 16; 995 } 996#else 997 /* 998 * There is no way to know wheter 15-16M hole exists or not. 999 * Therefore, we disable write allocate for this range. 1000 */ 1001 whcr &= ~(1LL << 16); 1002#endif 1003 wrmsr(0x0c0000082, whcr); 1004 1005 intr_restore(saveintr); 1006} 1007#endif /* I585_CPU && CPU_WT_ALLOC */ 1008 1009#include "opt_ddb.h" 1010#ifdef DDB 1011#include <ddb/ddb.h> 1012 1013DB_SHOW_COMMAND(cyrixreg, cyrixreg) 1014{ 1015 register_t saveintr; 1016 u_int cr0; 1017 u_char ccr1, ccr2, ccr3; 1018 u_char ccr0 = 0, ccr4 = 0, ccr5 = 0, pcr0 = 0; 1019 1020 cr0 = rcr0(); 1021 if (cpu_vendor_id == CPU_VENDOR_CYRIX) { 1022 saveintr = intr_disable(); 1023 1024 1025 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) { 1026 ccr0 = read_cyrix_reg(CCR0); 1027 } 1028 ccr1 = read_cyrix_reg(CCR1); 1029 ccr2 = read_cyrix_reg(CCR2); 1030 ccr3 = read_cyrix_reg(CCR3); 1031 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) { 1032 write_cyrix_reg(CCR3, CCR3_MAPEN0); 1033 ccr4 = read_cyrix_reg(CCR4); 1034 if ((cpu == CPU_M1) || (cpu == CPU_M2)) 1035 ccr5 = read_cyrix_reg(CCR5); 1036 else 1037 pcr0 = read_cyrix_reg(PCR0); 1038 write_cyrix_reg(CCR3, ccr3); /* Restore CCR3. */ 1039 } 1040 intr_restore(saveintr); 1041 1042 if ((cpu != CPU_M1SC) && (cpu != CPU_CY486DX)) 1043 printf("CCR0=%x, ", (u_int)ccr0); 1044 1045 printf("CCR1=%x, CCR2=%x, CCR3=%x", 1046 (u_int)ccr1, (u_int)ccr2, (u_int)ccr3); 1047 if ((cpu == CPU_M1SC) || (cpu == CPU_M1) || (cpu == CPU_M2)) { 1048 printf(", CCR4=%x, ", (u_int)ccr4); 1049 if (cpu == CPU_M1SC) 1050 printf("PCR0=%x\n", pcr0); 1051 else 1052 printf("CCR5=%x\n", ccr5); 1053 } 1054 } 1055 printf("CR0=%x\n", cr0); 1056} 1057#endif /* DDB */ 1058