s5pv210.h revision 273712
1/* 2 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 3 * Author: Mateusz Krawczuk <m.krawczuk@partner.samsung.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * Device Tree binding constants for Samsung S5PV210 clock controller. 10 */ 11 12#ifndef _DT_BINDINGS_CLOCK_S5PV210_H 13#define _DT_BINDINGS_CLOCK_S5PV210_H 14 15/* Core clocks. */ 16#define FIN_PLL 1 17#define FOUT_APLL 2 18#define FOUT_MPLL 3 19#define FOUT_EPLL 4 20#define FOUT_VPLL 5 21 22/* Muxes. */ 23#define MOUT_FLASH 6 24#define MOUT_PSYS 7 25#define MOUT_DSYS 8 26#define MOUT_MSYS 9 27#define MOUT_VPLL 10 28#define MOUT_EPLL 11 29#define MOUT_MPLL 12 30#define MOUT_APLL 13 31#define MOUT_VPLLSRC 14 32#define MOUT_CSIS 15 33#define MOUT_FIMD 16 34#define MOUT_CAM1 17 35#define MOUT_CAM0 18 36#define MOUT_DAC 19 37#define MOUT_MIXER 20 38#define MOUT_HDMI 21 39#define MOUT_G2D 22 40#define MOUT_MFC 23 41#define MOUT_G3D 24 42#define MOUT_FIMC2 25 43#define MOUT_FIMC1 26 44#define MOUT_FIMC0 27 45#define MOUT_UART3 28 46#define MOUT_UART2 29 47#define MOUT_UART1 30 48#define MOUT_UART0 31 49#define MOUT_MMC3 32 50#define MOUT_MMC2 33 51#define MOUT_MMC1 34 52#define MOUT_MMC0 35 53#define MOUT_PWM 36 54#define MOUT_SPI0 37 55#define MOUT_SPI1 38 56#define MOUT_DMC0 39 57#define MOUT_PWI 40 58#define MOUT_HPM 41 59#define MOUT_SPDIF 42 60#define MOUT_AUDIO2 43 61#define MOUT_AUDIO1 44 62#define MOUT_AUDIO0 45 63 64/* Dividers. */ 65#define DOUT_PCLKP 46 66#define DOUT_HCLKP 47 67#define DOUT_PCLKD 48 68#define DOUT_HCLKD 49 69#define DOUT_PCLKM 50 70#define DOUT_HCLKM 51 71#define DOUT_A2M 52 72#define DOUT_APLL 53 73#define DOUT_CSIS 54 74#define DOUT_FIMD 55 75#define DOUT_CAM1 56 76#define DOUT_CAM0 57 77#define DOUT_TBLK 58 78#define DOUT_G2D 59 79#define DOUT_MFC 60 80#define DOUT_G3D 61 81#define DOUT_FIMC2 62 82#define DOUT_FIMC1 63 83#define DOUT_FIMC0 64 84#define DOUT_UART3 65 85#define DOUT_UART2 66 86#define DOUT_UART1 67 87#define DOUT_UART0 68 88#define DOUT_MMC3 69 89#define DOUT_MMC2 70 90#define DOUT_MMC1 71 91#define DOUT_MMC0 72 92#define DOUT_PWM 73 93#define DOUT_SPI1 74 94#define DOUT_SPI0 75 95#define DOUT_DMC0 76 96#define DOUT_PWI 77 97#define DOUT_HPM 78 98#define DOUT_COPY 79 99#define DOUT_FLASH 80 100#define DOUT_AUDIO2 81 101#define DOUT_AUDIO1 82 102#define DOUT_AUDIO0 83 103#define DOUT_DPM 84 104#define DOUT_DVSEM 85 105 106/* Gates */ 107#define SCLK_FIMC 86 108#define CLK_CSIS 87 109#define CLK_ROTATOR 88 110#define CLK_FIMC2 89 111#define CLK_FIMC1 90 112#define CLK_FIMC0 91 113#define CLK_MFC 92 114#define CLK_G2D 93 115#define CLK_G3D 94 116#define CLK_IMEM 95 117#define CLK_PDMA1 96 118#define CLK_PDMA0 97 119#define CLK_MDMA 98 120#define CLK_DMC1 99 121#define CLK_DMC0 100 122#define CLK_NFCON 101 123#define CLK_SROMC 102 124#define CLK_CFCON 103 125#define CLK_NANDXL 104 126#define CLK_USB_HOST 105 127#define CLK_USB_OTG 106 128#define CLK_HDMI 107 129#define CLK_TVENC 108 130#define CLK_MIXER 109 131#define CLK_VP 110 132#define CLK_DSIM 111 133#define CLK_FIMD 112 134#define CLK_TZIC3 113 135#define CLK_TZIC2 114 136#define CLK_TZIC1 115 137#define CLK_TZIC0 116 138#define CLK_VIC3 117 139#define CLK_VIC2 118 140#define CLK_VIC1 119 141#define CLK_VIC0 120 142#define CLK_TSI 121 143#define CLK_HSMMC3 122 144#define CLK_HSMMC2 123 145#define CLK_HSMMC1 124 146#define CLK_HSMMC0 125 147#define CLK_JTAG 126 148#define CLK_MODEMIF 127 149#define CLK_CORESIGHT 128 150#define CLK_SDM 129 151#define CLK_SECSS 130 152#define CLK_PCM2 131 153#define CLK_PCM1 132 154#define CLK_PCM0 133 155#define CLK_SYSCON 134 156#define CLK_GPIO 135 157#define CLK_TSADC 136 158#define CLK_PWM 137 159#define CLK_WDT 138 160#define CLK_KEYIF 139 161#define CLK_UART3 140 162#define CLK_UART2 141 163#define CLK_UART1 142 164#define CLK_UART0 143 165#define CLK_SYSTIMER 144 166#define CLK_RTC 145 167#define CLK_SPI1 146 168#define CLK_SPI0 147 169#define CLK_I2C_HDMI_PHY 148 170#define CLK_I2C1 149 171#define CLK_I2C2 150 172#define CLK_I2C0 151 173#define CLK_I2S1 152 174#define CLK_I2S2 153 175#define CLK_I2S0 154 176#define CLK_AC97 155 177#define CLK_SPDIF 156 178#define CLK_TZPC3 157 179#define CLK_TZPC2 158 180#define CLK_TZPC1 159 181#define CLK_TZPC0 160 182#define CLK_SECKEY 161 183#define CLK_IEM_APC 162 184#define CLK_IEM_IEC 163 185#define CLK_CHIPID 164 186#define CLK_JPEG 163 187 188/* Special clocks*/ 189#define SCLK_PWI 164 190#define SCLK_SPDIF 165 191#define SCLK_AUDIO2 166 192#define SCLK_AUDIO1 167 193#define SCLK_AUDIO0 168 194#define SCLK_PWM 169 195#define SCLK_SPI1 170 196#define SCLK_SPI0 171 197#define SCLK_UART3 172 198#define SCLK_UART2 173 199#define SCLK_UART1 174 200#define SCLK_UART0 175 201#define SCLK_MMC3 176 202#define SCLK_MMC2 177 203#define SCLK_MMC1 178 204#define SCLK_MMC0 179 205#define SCLK_FINVPLL 180 206#define SCLK_CSIS 181 207#define SCLK_FIMD 182 208#define SCLK_CAM1 183 209#define SCLK_CAM0 184 210#define SCLK_DAC 185 211#define SCLK_MIXER 186 212#define SCLK_HDMI 187 213#define SCLK_FIMC2 188 214#define SCLK_FIMC1 189 215#define SCLK_FIMC0 190 216#define SCLK_HDMI27M 191 217#define SCLK_HDMIPHY 192 218#define SCLK_USBPHY0 193 219#define SCLK_USBPHY1 194 220 221/* S5P6442-specific clocks */ 222#define MOUT_D0SYNC 195 223#define MOUT_D1SYNC 196 224#define DOUT_MIXER 197 225#define CLK_ETB 198 226#define CLK_ETM 199 227 228/* CLKOUT */ 229#define FOUT_APLL_CLKOUT 200 230#define FOUT_MPLL_CLKOUT 201 231#define DOUT_APLL_CLKOUT 202 232#define MOUT_CLKSEL 203 233#define DOUT_CLKOUT 204 234#define MOUT_CLKOUT 205 235 236/* Total number of clocks. */ 237#define NR_CLKS 206 238 239#endif /* _DT_BINDINGS_CLOCK_S5PV210_H */ 240