exynos5250.h revision 284090
1/* 2 * Copyright (c) 2013 Samsung Electronics Co., Ltd. 3 * Author: Andrzej Hajda <a.hajda@samsung.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * Device Tree binding constants for Exynos5250 clock controller. 10*/ 11 12#ifndef _DT_BINDINGS_CLOCK_EXYNOS_5250_H 13#define _DT_BINDINGS_CLOCK_EXYNOS_5250_H 14 15/* core clocks */ 16#define CLK_FIN_PLL 1 17#define CLK_FOUT_APLL 2 18#define CLK_FOUT_MPLL 3 19#define CLK_FOUT_BPLL 4 20#define CLK_FOUT_GPLL 5 21#define CLK_FOUT_CPLL 6 22#define CLK_FOUT_EPLL 7 23#define CLK_FOUT_VPLL 8 24 25/* gate for special clocks (sclk) */ 26#define CLK_SCLK_CAM_BAYER 128 27#define CLK_SCLK_CAM0 129 28#define CLK_SCLK_CAM1 130 29#define CLK_SCLK_GSCL_WA 131 30#define CLK_SCLK_GSCL_WB 132 31#define CLK_SCLK_FIMD1 133 32#define CLK_SCLK_MIPI1 134 33#define CLK_SCLK_DP 135 34#define CLK_SCLK_HDMI 136 35#define CLK_SCLK_PIXEL 137 36#define CLK_SCLK_AUDIO0 138 37#define CLK_SCLK_MMC0 139 38#define CLK_SCLK_MMC1 140 39#define CLK_SCLK_MMC2 141 40#define CLK_SCLK_MMC3 142 41#define CLK_SCLK_SATA 143 42#define CLK_SCLK_USB3 144 43#define CLK_SCLK_JPEG 145 44#define CLK_SCLK_UART0 146 45#define CLK_SCLK_UART1 147 46#define CLK_SCLK_UART2 148 47#define CLK_SCLK_UART3 149 48#define CLK_SCLK_PWM 150 49#define CLK_SCLK_AUDIO1 151 50#define CLK_SCLK_AUDIO2 152 51#define CLK_SCLK_SPDIF 153 52#define CLK_SCLK_SPI0 154 53#define CLK_SCLK_SPI1 155 54#define CLK_SCLK_SPI2 156 55#define CLK_DIV_I2S1 157 56#define CLK_DIV_I2S2 158 57#define CLK_SCLK_HDMIPHY 159 58#define CLK_DIV_PCM0 160 59 60/* gate clocks */ 61#define CLK_GSCL0 256 62#define CLK_GSCL1 257 63#define CLK_GSCL2 258 64#define CLK_GSCL3 259 65#define CLK_GSCL_WA 260 66#define CLK_GSCL_WB 261 67#define CLK_SMMU_GSCL0 262 68#define CLK_SMMU_GSCL1 263 69#define CLK_SMMU_GSCL2 264 70#define CLK_SMMU_GSCL3 265 71#define CLK_MFC 266 72#define CLK_SMMU_MFCL 267 73#define CLK_SMMU_MFCR 268 74#define CLK_ROTATOR 269 75#define CLK_JPEG 270 76#define CLK_MDMA1 271 77#define CLK_SMMU_ROTATOR 272 78#define CLK_SMMU_JPEG 273 79#define CLK_SMMU_MDMA1 274 80#define CLK_PDMA0 275 81#define CLK_PDMA1 276 82#define CLK_SATA 277 83#define CLK_USBOTG 278 84#define CLK_MIPI_HSI 279 85#define CLK_SDMMC0 280 86#define CLK_SDMMC1 281 87#define CLK_SDMMC2 282 88#define CLK_SDMMC3 283 89#define CLK_SROMC 284 90#define CLK_USB2 285 91#define CLK_USB3 286 92#define CLK_SATA_PHYCTRL 287 93#define CLK_SATA_PHYI2C 288 94#define CLK_UART0 289 95#define CLK_UART1 290 96#define CLK_UART2 291 97#define CLK_UART3 292 98#define CLK_UART4 293 99#define CLK_I2C0 294 100#define CLK_I2C1 295 101#define CLK_I2C2 296 102#define CLK_I2C3 297 103#define CLK_I2C4 298 104#define CLK_I2C5 299 105#define CLK_I2C6 300 106#define CLK_I2C7 301 107#define CLK_I2C_HDMI 302 108#define CLK_ADC 303 109#define CLK_SPI0 304 110#define CLK_SPI1 305 111#define CLK_SPI2 306 112#define CLK_I2S1 307 113#define CLK_I2S2 308 114#define CLK_PCM1 309 115#define CLK_PCM2 310 116#define CLK_PWM 311 117#define CLK_SPDIF 312 118#define CLK_AC97 313 119#define CLK_HSI2C0 314 120#define CLK_HSI2C1 315 121#define CLK_HSI2C2 316 122#define CLK_HSI2C3 317 123#define CLK_CHIPID 318 124#define CLK_SYSREG 319 125#define CLK_PMU 320 126#define CLK_CMU_TOP 321 127#define CLK_CMU_CORE 322 128#define CLK_CMU_MEM 323 129#define CLK_TZPC0 324 130#define CLK_TZPC1 325 131#define CLK_TZPC2 326 132#define CLK_TZPC3 327 133#define CLK_TZPC4 328 134#define CLK_TZPC5 329 135#define CLK_TZPC6 330 136#define CLK_TZPC7 331 137#define CLK_TZPC8 332 138#define CLK_TZPC9 333 139#define CLK_HDMI_CEC 334 140#define CLK_MCT 335 141#define CLK_WDT 336 142#define CLK_RTC 337 143#define CLK_TMU 338 144#define CLK_FIMD1 339 145#define CLK_MIE1 340 146#define CLK_DSIM0 341 147#define CLK_DP 342 148#define CLK_MIXER 343 149#define CLK_HDMI 344 150#define CLK_G2D 345 151#define CLK_MDMA0 346 152#define CLK_SMMU_MDMA0 347 153#define CLK_SSS 348 154#define CLK_G3D 349 155#define CLK_SMMU_TV 350 156#define CLK_SMMU_FIMD1 351 157#define CLK_SMMU_2D 352 158#define CLK_SMMU_FIMC_ISP 353 159#define CLK_SMMU_FIMC_DRC 354 160#define CLK_SMMU_FIMC_SCC 355 161#define CLK_SMMU_FIMC_SCP 356 162#define CLK_SMMU_FIMC_FD 357 163#define CLK_SMMU_FIMC_MCU 358 164#define CLK_SMMU_FIMC_ODC 359 165#define CLK_SMMU_FIMC_DIS0 360 166#define CLK_SMMU_FIMC_DIS1 361 167#define CLK_SMMU_FIMC_3DNR 362 168#define CLK_SMMU_FIMC_LITE0 363 169#define CLK_SMMU_FIMC_LITE1 364 170#define CLK_CAMIF_TOP 365 171 172/* mux clocks */ 173#define CLK_MOUT_HDMI 1024 174#define CLK_MOUT_GPLL 1025 175 176/* must be greater than maximal clock id */ 177#define CLK_NR_CLKS 1026 178 179#endif /* _DT_BINDINGS_CLOCK_EXYNOS_5250_H */ 180