zynq-7000.dtsi revision 284090 
1/*
2 *  Copyright (C) 2011 - 2014 Xilinx
3 *
4 * This software is licensed under the terms of the GNU General Public
5 * License version 2, as published by the Free Software Foundation, and
6 * may be copied, distributed, and modified under those terms.
7 *
8 * This program is distributed in the hope that it will be useful,
9 * but WITHOUT ANY WARRANTY; without even the implied warranty of
10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
11 * GNU General Public License for more details.
12 */
13/include/ "skeleton.dtsi"
14
15/ {
16	compatible = "xlnx,zynq-7000";
17
18	cpus {
19		#address-cells = <1>;
20		#size-cells = <0>;
21
22		cpu@0 {
23			compatible = "arm,cortex-a9";
24			device_type = "cpu";
25			reg = <0>;
26			clocks = <&clkc 3>;
27			clock-latency = <1000>;
28			cpu0-supply = <&regulator_vccpint>;
29			operating-points = <
30				/* kHz    uV */
31				666667  1000000
32				333334  1000000
33			>;
34		};
35
36		cpu@1 {
37			compatible = "arm,cortex-a9";
38			device_type = "cpu";
39			reg = <1>;
40			clocks = <&clkc 3>;
41		};
42	};
43
44	pmu {
45		compatible = "arm,cortex-a9-pmu";
46		interrupts = <0 5 4>, <0 6 4>;
47		interrupt-parent = <&intc>;
48		reg = < 0xf8891000 0x1000 0xf8893000 0x1000 >;
49	};
50
51	regulator_vccpint: fixedregulator@0 {
52		compatible = "regulator-fixed";
53		regulator-name = "VCCPINT";
54		regulator-min-microvolt = <1000000>;
55		regulator-max-microvolt = <1000000>;
56		regulator-boot-on;
57		regulator-always-on;
58	};
59
60	amba {
61		compatible = "simple-bus";
62		#address-cells = <1>;
63		#size-cells = <1>;
64		interrupt-parent = <&intc>;
65		ranges;
66
67		adc: adc@f8007100 {
68			compatible = "xlnx,zynq-xadc-1.00.a";
69			reg = <0xf8007100 0x20>;
70			interrupts = <0 7 4>;
71			interrupt-parent = <&intc>;
72			clocks = <&clkc 12>;
73		};
74
75		can0: can@e0008000 {
76			compatible = "xlnx,zynq-can-1.0";
77			status = "disabled";
78			clocks = <&clkc 19>, <&clkc 36>;
79			clock-names = "can_clk", "pclk";
80			reg = <0xe0008000 0x1000>;
81			interrupts = <0 28 4>;
82			interrupt-parent = <&intc>;
83			tx-fifo-depth = <0x40>;
84			rx-fifo-depth = <0x40>;
85		};
86
87		can1: can@e0009000 {
88			compatible = "xlnx,zynq-can-1.0";
89			status = "disabled";
90			clocks = <&clkc 20>, <&clkc 37>;
91			clock-names = "can_clk", "pclk";
92			reg = <0xe0009000 0x1000>;
93			interrupts = <0 51 4>;
94			interrupt-parent = <&intc>;
95			tx-fifo-depth = <0x40>;
96			rx-fifo-depth = <0x40>;
97		};
98
99		gpio0: gpio@e000a000 {
100			compatible = "xlnx,zynq-gpio-1.0";
101			#gpio-cells = <2>;
102			clocks = <&clkc 42>;
103			gpio-controller;
104			interrupt-parent = <&intc>;
105			interrupts = <0 20 4>;
106			reg = <0xe000a000 0x1000>;
107		};
108
109		i2c0: i2c@e0004000 {
110			compatible = "cdns,i2c-r1p10";
111			status = "disabled";
112			clocks = <&clkc 38>;
113			interrupt-parent = <&intc>;
114			interrupts = <0 25 4>;
115			reg = <0xe0004000 0x1000>;
116			#address-cells = <1>;
117			#size-cells = <0>;
118		};
119
120		i2c1: i2c@e0005000 {
121			compatible = "cdns,i2c-r1p10";
122			status = "disabled";
123			clocks = <&clkc 39>;
124			interrupt-parent = <&intc>;
125			interrupts = <0 48 4>;
126			reg = <0xe0005000 0x1000>;
127			#address-cells = <1>;
128			#size-cells = <0>;
129		};
130
131		intc: interrupt-controller@f8f01000 {
132			compatible = "arm,cortex-a9-gic";
133			#interrupt-cells = <3>;
134			interrupt-controller;
135			reg = <0xF8F01000 0x1000>,
136			      <0xF8F00100 0x100>;
137		};
138
139		L2: cache-controller@f8f02000 {
140			compatible = "arm,pl310-cache";
141			reg = <0xF8F02000 0x1000>;
142			arm,data-latency = <3 2 2>;
143			arm,tag-latency = <2 2 2>;
144			cache-unified;
145			cache-level = <2>;
146		};
147
148		mc: memory-controller@f8006000 {
149			compatible = "xlnx,zynq-ddrc-a05";
150			reg = <0xf8006000 0x1000>;
151		};
152
153		uart0: serial@e0000000 {
154			compatible = "xlnx,xuartps", "cdns,uart-r1p8";
155			status = "disabled";
156			clocks = <&clkc 23>, <&clkc 40>;
157			clock-names = "uart_clk", "pclk";
158			reg = <0xE0000000 0x1000>;
159			interrupts = <0 27 4>;
160		};
161
162		uart1: serial@e0001000 {
163			compatible = "xlnx,xuartps", "cdns,uart-r1p8";
164			status = "disabled";
165			clocks = <&clkc 24>, <&clkc 41>;
166			clock-names = "uart_clk", "pclk";
167			reg = <0xE0001000 0x1000>;
168			interrupts = <0 50 4>;
169		};
170
171		spi0: spi@e0006000 {
172			compatible = "xlnx,zynq-spi-r1p6";
173			reg = <0xe0006000 0x1000>;
174			status = "disabled";
175			interrupt-parent = <&intc>;
176			interrupts = <0 26 4>;
177			clocks = <&clkc 25>, <&clkc 34>;
178			clock-names = "ref_clk", "pclk";
179			#address-cells = <1>;
180			#size-cells = <0>;
181		};
182
183		spi1: spi@e0007000 {
184			compatible = "xlnx,zynq-spi-r1p6";
185			reg = <0xe0007000 0x1000>;
186			status = "disabled";
187			interrupt-parent = <&intc>;
188			interrupts = <0 49 4>;
189			clocks = <&clkc 26>, <&clkc 35>;
190			clock-names = "ref_clk", "pclk";
191			#address-cells = <1>;
192			#size-cells = <0>;
193		};
194
195		gem0: ethernet@e000b000 {
196			compatible = "cdns,gem";
197			reg = <0xe000b000 0x1000>;
198			status = "disabled";
199			interrupts = <0 22 4>;
200			clocks = <&clkc 30>, <&clkc 30>, <&clkc 13>;
201			clock-names = "pclk", "hclk", "tx_clk";
202			#address-cells = <1>;
203			#size-cells = <0>;
204		};
205
206		gem1: ethernet@e000c000 {
207			compatible = "cdns,gem";
208			reg = <0xe000c000 0x1000>;
209			status = "disabled";
210			interrupts = <0 45 4>;
211			clocks = <&clkc 31>, <&clkc 31>, <&clkc 14>;
212			clock-names = "pclk", "hclk", "tx_clk";
213			#address-cells = <1>;
214			#size-cells = <0>;
215		};
216
217		sdhci0: sdhci@e0100000 {
218			compatible = "arasan,sdhci-8.9a";
219			status = "disabled";
220			clock-names = "clk_xin", "clk_ahb";
221			clocks = <&clkc 21>, <&clkc 32>;
222			interrupt-parent = <&intc>;
223			interrupts = <0 24 4>;
224			reg = <0xe0100000 0x1000>;
225		};
226
227		sdhci1: sdhci@e0101000 {
228			compatible = "arasan,sdhci-8.9a";
229			status = "disabled";
230			clock-names = "clk_xin", "clk_ahb";
231			clocks = <&clkc 22>, <&clkc 33>;
232			interrupt-parent = <&intc>;
233			interrupts = <0 47 4>;
234			reg = <0xe0101000 0x1000>;
235		};
236
237		slcr: slcr@f8000000 {
238			#address-cells = <1>;
239			#size-cells = <1>;
240			compatible = "xlnx,zynq-slcr", "syscon", "simple-bus";
241			reg = <0xF8000000 0x1000>;
242			ranges;
243			clkc: clkc@100 {
244				#clock-cells = <1>;
245				compatible = "xlnx,ps7-clkc";
246				fclk-enable = <0>;
247				clock-output-names = "armpll", "ddrpll", "iopll", "cpu_6or4x",
248						"cpu_3or2x", "cpu_2x", "cpu_1x", "ddr2x", "ddr3x",
249						"dci", "lqspi", "smc", "pcap", "gem0", "gem1",
250						"fclk0", "fclk1", "fclk2", "fclk3", "can0", "can1",
251						"sdio0", "sdio1", "uart0", "uart1", "spi0", "spi1",
252						"dma", "usb0_aper", "usb1_aper", "gem0_aper",
253						"gem1_aper", "sdio0_aper", "sdio1_aper",
254						"spi0_aper", "spi1_aper", "can0_aper", "can1_aper",
255						"i2c0_aper", "i2c1_aper", "uart0_aper", "uart1_aper",
256						"gpio_aper", "lqspi_aper", "smc_aper", "swdt",
257						"dbg_trc", "dbg_apb";
258				reg = <0x100 0x100>;
259			};
260
261			pinctrl0: pinctrl@700 {
262				compatible = "xlnx,pinctrl-zynq";
263				reg = <0x700 0x200>;
264				syscon = <&slcr>;
265			};
266		};
267
268		dmac_s: dmac@f8003000 {
269			compatible = "arm,pl330", "arm,primecell";
270			reg = <0xf8003000 0x1000>;
271			interrupt-parent = <&intc>;
272			interrupt-names = "abort", "dma0", "dma1", "dma2", "dma3",
273				"dma4", "dma5", "dma6", "dma7";
274			interrupts = <0 13 4>,
275			             <0 14 4>, <0 15 4>,
276			             <0 16 4>, <0 17 4>,
277			             <0 40 4>, <0 41 4>,
278			             <0 42 4>, <0 43 4>;
279			#dma-cells = <1>;
280			#dma-channels = <8>;
281			#dma-requests = <4>;
282			clocks = <&clkc 27>;
283			clock-names = "apb_pclk";
284		};
285
286		devcfg: devcfg@f8007000 {
287			compatible = "xlnx,zynq-devcfg-1.0";
288			reg = <0xf8007000 0x100>;
289		};
290
291		global_timer: timer@f8f00200 {
292			compatible = "arm,cortex-a9-global-timer";
293			reg = <0xf8f00200 0x20>;
294			interrupts = <1 11 0x301>;
295			interrupt-parent = <&intc>;
296			clocks = <&clkc 4>;
297		};
298
299		ttc0: timer@f8001000 {
300			interrupt-parent = <&intc>;
301			interrupts = <0 10 4>, <0 11 4>, <0 12 4>;
302			compatible = "cdns,ttc";
303			clocks = <&clkc 6>;
304			reg = <0xF8001000 0x1000>;
305		};
306
307		ttc1: timer@f8002000 {
308			interrupt-parent = <&intc>;
309			interrupts = <0 37 4>, <0 38 4>, <0 39 4>;
310			compatible = "cdns,ttc";
311			clocks = <&clkc 6>;
312			reg = <0xF8002000 0x1000>;
313		};
314
315		scutimer: timer@f8f00600 {
316			interrupt-parent = <&intc>;
317			interrupts = <1 13 0x301>;
318			compatible = "arm,cortex-a9-twd-timer";
319			reg = <0xf8f00600 0x20>;
320			clocks = <&clkc 4>;
321		};
322
323		usb0: usb@e0002000 {
324			compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
325			status = "disabled";
326			clocks = <&clkc 28>;
327			interrupt-parent = <&intc>;
328			interrupts = <0 21 4>;
329			reg = <0xe0002000 0x1000>;
330			phy_type = "ulpi";
331		};
332
333		usb1: usb@e0003000 {
334			compatible = "xlnx,zynq-usb-2.20a", "chipidea,usb2";
335			status = "disabled";
336			clocks = <&clkc 29>;
337			interrupt-parent = <&intc>;
338			interrupts = <0 44 4>;
339			reg = <0xe0003000 0x1000>;
340			phy_type = "ulpi";
341		};
342
343		watchdog0: watchdog@f8005000 {
344			clocks = <&clkc 45>;
345			compatible = "cdns,wdt-r1p2";
346			interrupt-parent = <&intc>;
347			interrupts = <0 9 1>;
348			reg = <0xf8005000 0x1000>;
349			timeout-sec = <10>;
350		};
351	};
352};
353