versatile-pb.dts revision 284090 
1145519Sdarrenr#include <versatile-ab.dts>
2145510Sdarrenr
3170268Sdarrenr/ {
4170268Sdarrenr	model = "ARM Versatile PB";
5170268Sdarrenr	compatible = "arm,versatile-pb";
6170268Sdarrenr
7170268Sdarrenr	amba {
8145510Sdarrenr		gpio2: gpio@101e6000 {
9145510Sdarrenr			compatible = "arm,pl061", "arm,primecell";
10145510Sdarrenr			reg = <0x101e6000 0x1000>;
11145510Sdarrenr			interrupts = <8>;
12145510Sdarrenr			gpio-controller;
13145510Sdarrenr			#gpio-cells = <2>;
14145510Sdarrenr			interrupt-controller;
15145510Sdarrenr			#interrupt-cells = <2>;
16145510Sdarrenr			clocks = <&pclk>;
17145510Sdarrenr			clock-names = "apb_pclk";
18145510Sdarrenr		};
19145510Sdarrenr
20145510Sdarrenr		gpio3: gpio@101e7000 {
21145510Sdarrenr			compatible = "arm,pl061", "arm,primecell";
22145510Sdarrenr			reg = <0x101e7000 0x1000>;
23145510Sdarrenr			interrupts = <9>;
24145510Sdarrenr			gpio-controller;
25145510Sdarrenr			#gpio-cells = <2>;
26145510Sdarrenr			interrupt-controller;
27145510Sdarrenr			#interrupt-cells = <2>;
28145510Sdarrenr			clocks = <&pclk>;
29145510Sdarrenr			clock-names = "apb_pclk";
30145510Sdarrenr		};
31145510Sdarrenr
32145510Sdarrenr		pci-controller@10001000 {
33145510Sdarrenr			compatible = "arm,versatile-pci";
34145510Sdarrenr			device_type = "pci";
35145510Sdarrenr			reg = <0x10001000 0x1000
36145510Sdarrenr			       0x41000000 0x10000
37145510Sdarrenr			       0x42000000 0x100000>;
38145510Sdarrenr			bus-range = <0 0xff>;
39145510Sdarrenr			#address-cells = <3>;
40145510Sdarrenr			#size-cells = <2>;
41145510Sdarrenr			#interrupt-cells = <1>;
42145510Sdarrenr
43145510Sdarrenr			ranges = <0x01000000 0 0x00000000 0x43000000 0 0x00010000   /* downstream I/O */
44145510Sdarrenr				  0x02000000 0 0x50000000 0x50000000 0 0x10000000   /* non-prefetchable memory */
45145510Sdarrenr				  0x42000000 0 0x60000000 0x60000000 0 0x10000000>; /* prefetchable memory */
46145510Sdarrenr
47145510Sdarrenr			interrupt-map-mask = <0x1800 0 0 7>;
48145510Sdarrenr			interrupt-map = <0x1800 0 0 1 &sic 28
49145510Sdarrenr					 0x1800 0 0 2 &sic 29
50145510Sdarrenr					 0x1800 0 0 3 &sic 30
51145510Sdarrenr					 0x1800 0 0 4 &sic 27
52145510Sdarrenr
53145510Sdarrenr					 0x1000 0 0 1 &sic 27
54145510Sdarrenr					 0x1000 0 0 2 &sic 28
55145510Sdarrenr					 0x1000 0 0 3 &sic 29
56145510Sdarrenr					 0x1000 0 0 4 &sic 30
57145510Sdarrenr
58145510Sdarrenr					 0x0800 0 0 1 &sic 30
59145510Sdarrenr					 0x0800 0 0 2 &sic 27
60145510Sdarrenr					 0x0800 0 0 3 &sic 28
61					 0x0800 0 0 4 &sic 29
62
63					 0x0000 0 0 1 &sic 29
64					 0x0000 0 0 2 &sic 30
65					 0x0000 0 0 3 &sic 27
66					 0x0000 0 0 4 &sic 28>;
67		};
68
69		fpga {
70			uart@9000 {
71				compatible = "arm,pl011", "arm,primecell";
72				reg = <0x9000 0x1000>;
73				interrupt-parent = <&sic>;
74				interrupts = <6>;
75				clocks = <&xtal24mhz>, <&pclk>;
76				clock-names = "uartclk", "apb_pclk";
77			};
78			sci@a000 {
79				compatible = "arm,primecell";
80				reg = <0xa000 0x1000>;
81				interrupt-parent = <&sic>;
82				interrupts = <5>;
83				clocks = <&xtal24mhz>;
84				clock-names = "apb_pclk";
85			};
86			mmc@b000 {
87				compatible = "arm,pl180", "arm,primecell";
88				reg = <0xb000 0x1000>;
89				interrupts-extended = <&vic 23 &sic 2>;
90				clocks = <&xtal24mhz>, <&pclk>;
91				clock-names = "mclk", "apb_pclk";
92			};
93		};
94	};
95};
96