sun5i-a13.dtsi revision 284090 
1/*
2 * Copyright 2012 Maxime Ripard
3 *
4 * Maxime Ripard <maxime.ripard@free-electrons.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14#include "skeleton.dtsi"
15
16#include <dt-bindings/thermal/thermal.h>
17
18#include <dt-bindings/dma/sun4i-a10.h>
19#include <dt-bindings/pinctrl/sun4i-a10.h>
20
21/ {
22	interrupt-parent = <&intc>;
23
24	chosen {
25		#address-cells = <1>;
26		#size-cells = <1>;
27		ranges;
28
29		framebuffer@0 {
30			compatible = "allwinner,simple-framebuffer",
31				     "simple-framebuffer";
32			allwinner,pipeline = "de_be0-lcd0";
33			clocks = <&pll5 1>, <&ahb_gates 36>, <&ahb_gates 44>;
34			status = "disabled";
35		};
36	};
37
38	cpus {
39		#address-cells = <1>;
40		#size-cells = <0>;
41
42		cpu0: cpu@0 {
43			device_type = "cpu";
44			compatible = "arm,cortex-a8";
45			reg = <0x0>;
46			clocks = <&cpu>;
47			clock-latency = <244144>; /* 8 32k periods */
48			operating-points = <
49				/* kHz    uV */
50				1104000	1500000
51				1008000 1400000
52				912000  1350000
53				864000  1300000
54				624000  1200000
55				576000  1200000
56				432000  1200000
57				>;
58			#cooling-cells = <2>;
59			cooling-min-level = <0>;
60			cooling-max-level = <6>;
61		};
62	};
63
64	thermal-zones {
65		cpu_thermal {
66			/* milliseconds */
67			polling-delay-passive = <250>;
68			polling-delay = <1000>;
69			thermal-sensors = <&rtp>;
70
71			cooling-maps {
72				map0 {
73					trip = <&cpu_alert0>;
74					cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
75				};
76			};
77
78			trips {
79				cpu_alert0: cpu_alert0 {
80					/* milliCelsius */
81					temperature = <850000>;
82					hysteresis = <2000>;
83					type = "passive";
84				};
85
86				cpu_crit: cpu_crit {
87					/* milliCelsius */
88					temperature = <100000>;
89					hysteresis = <2000>;
90					type = "critical";
91				};
92			};
93		};
94	};
95
96	memory {
97		reg = <0x40000000 0x20000000>;
98	};
99
100	clocks {
101		#address-cells = <1>;
102		#size-cells = <1>;
103		ranges;
104
105		/*
106		 * This is a dummy clock, to be used as placeholder on
107		 * other mux clocks when a specific parent clock is not
108		 * yet implemented. It should be dropped when the driver
109		 * is complete.
110		 */
111		dummy: dummy {
112			#clock-cells = <0>;
113			compatible = "fixed-clock";
114			clock-frequency = <0>;
115		};
116
117		osc24M: clk@01c20050 {
118			#clock-cells = <0>;
119			compatible = "allwinner,sun4i-a10-osc-clk";
120			reg = <0x01c20050 0x4>;
121			clock-frequency = <24000000>;
122			clock-output-names = "osc24M";
123		};
124
125		osc32k: clk@0 {
126			#clock-cells = <0>;
127			compatible = "fixed-clock";
128			clock-frequency = <32768>;
129			clock-output-names = "osc32k";
130		};
131
132		pll1: clk@01c20000 {
133			#clock-cells = <0>;
134			compatible = "allwinner,sun4i-a10-pll1-clk";
135			reg = <0x01c20000 0x4>;
136			clocks = <&osc24M>;
137			clock-output-names = "pll1";
138		};
139
140		pll4: clk@01c20018 {
141			#clock-cells = <0>;
142			compatible = "allwinner,sun4i-a10-pll1-clk";
143			reg = <0x01c20018 0x4>;
144			clocks = <&osc24M>;
145			clock-output-names = "pll4";
146		};
147
148		pll5: clk@01c20020 {
149			#clock-cells = <1>;
150			compatible = "allwinner,sun4i-a10-pll5-clk";
151			reg = <0x01c20020 0x4>;
152			clocks = <&osc24M>;
153			clock-output-names = "pll5_ddr", "pll5_other";
154		};
155
156		pll6: clk@01c20028 {
157			#clock-cells = <1>;
158			compatible = "allwinner,sun4i-a10-pll6-clk";
159			reg = <0x01c20028 0x4>;
160			clocks = <&osc24M>;
161			clock-output-names = "pll6_sata", "pll6_other", "pll6";
162		};
163
164		/* dummy is 200M */
165		cpu: cpu@01c20054 {
166			#clock-cells = <0>;
167			compatible = "allwinner,sun4i-a10-cpu-clk";
168			reg = <0x01c20054 0x4>;
169			clocks = <&osc32k>, <&osc24M>, <&pll1>, <&dummy>;
170			clock-output-names = "cpu";
171		};
172
173		axi: axi@01c20054 {
174			#clock-cells = <0>;
175			compatible = "allwinner,sun4i-a10-axi-clk";
176			reg = <0x01c20054 0x4>;
177			clocks = <&cpu>;
178			clock-output-names = "axi";
179		};
180
181		axi_gates: clk@01c2005c {
182			#clock-cells = <1>;
183			compatible = "allwinner,sun4i-a10-axi-gates-clk";
184			reg = <0x01c2005c 0x4>;
185			clocks = <&axi>;
186			clock-output-names = "axi_dram";
187		};
188
189		ahb: ahb@01c20054 {
190			#clock-cells = <0>;
191			compatible = "allwinner,sun4i-a10-ahb-clk";
192			reg = <0x01c20054 0x4>;
193			clocks = <&axi>;
194			clock-output-names = "ahb";
195		};
196
197		ahb_gates: clk@01c20060 {
198			#clock-cells = <1>;
199			compatible = "allwinner,sun5i-a13-ahb-gates-clk";
200			reg = <0x01c20060 0x8>;
201			clocks = <&ahb>;
202			clock-output-names = "ahb_usbotg", "ahb_ehci", "ahb_ohci",
203				"ahb_ss", "ahb_dma", "ahb_bist", "ahb_mmc0",
204				"ahb_mmc1", "ahb_mmc2", "ahb_nand", "ahb_sdram",
205				"ahb_spi0", "ahb_spi1", "ahb_spi2", "ahb_stimer",
206				"ahb_ve", "ahb_lcd", "ahb_csi", "ahb_de_be",
207				"ahb_de_fe", "ahb_iep", "ahb_mali400";
208		};
209
210		apb0: apb0@01c20054 {
211			#clock-cells = <0>;
212			compatible = "allwinner,sun4i-a10-apb0-clk";
213			reg = <0x01c20054 0x4>;
214			clocks = <&ahb>;
215			clock-output-names = "apb0";
216		};
217
218		apb0_gates: clk@01c20068 {
219			#clock-cells = <1>;
220			compatible = "allwinner,sun5i-a13-apb0-gates-clk";
221			reg = <0x01c20068 0x4>;
222			clocks = <&apb0>;
223			clock-output-names = "apb0_codec", "apb0_pio", "apb0_ir";
224		};
225
226		apb1: clk@01c20058 {
227			#clock-cells = <0>;
228			compatible = "allwinner,sun4i-a10-apb1-clk";
229			reg = <0x01c20058 0x4>;
230			clocks = <&osc24M>, <&pll6 1>, <&osc32k>;
231			clock-output-names = "apb1";
232		};
233
234		apb1_gates: clk@01c2006c {
235			#clock-cells = <1>;
236			compatible = "allwinner,sun5i-a13-apb1-gates-clk";
237			reg = <0x01c2006c 0x4>;
238			clocks = <&apb1>;
239			clock-output-names = "apb1_i2c0", "apb1_i2c1",
240				"apb1_i2c2", "apb1_uart1", "apb1_uart3";
241		};
242
243		nand_clk: clk@01c20080 {
244			#clock-cells = <0>;
245			compatible = "allwinner,sun4i-a10-mod0-clk";
246			reg = <0x01c20080 0x4>;
247			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
248			clock-output-names = "nand";
249		};
250
251		ms_clk: clk@01c20084 {
252			#clock-cells = <0>;
253			compatible = "allwinner,sun4i-a10-mod0-clk";
254			reg = <0x01c20084 0x4>;
255			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
256			clock-output-names = "ms";
257		};
258
259		mmc0_clk: clk@01c20088 {
260			#clock-cells = <1>;
261			compatible = "allwinner,sun4i-a10-mmc-clk";
262			reg = <0x01c20088 0x4>;
263			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
264			clock-output-names = "mmc0",
265					     "mmc0_output",
266					     "mmc0_sample";
267		};
268
269		mmc1_clk: clk@01c2008c {
270			#clock-cells = <1>;
271			compatible = "allwinner,sun4i-a10-mmc-clk";
272			reg = <0x01c2008c 0x4>;
273			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
274			clock-output-names = "mmc1",
275					     "mmc1_output",
276					     "mmc1_sample";
277		};
278
279		mmc2_clk: clk@01c20090 {
280			#clock-cells = <1>;
281			compatible = "allwinner,sun4i-a10-mmc-clk";
282			reg = <0x01c20090 0x4>;
283			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
284			clock-output-names = "mmc2",
285					     "mmc2_output",
286					     "mmc2_sample";
287		};
288
289		ts_clk: clk@01c20098 {
290			#clock-cells = <0>;
291			compatible = "allwinner,sun4i-a10-mod0-clk";
292			reg = <0x01c20098 0x4>;
293			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
294			clock-output-names = "ts";
295		};
296
297		ss_clk: clk@01c2009c {
298			#clock-cells = <0>;
299			compatible = "allwinner,sun4i-a10-mod0-clk";
300			reg = <0x01c2009c 0x4>;
301			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
302			clock-output-names = "ss";
303		};
304
305		spi0_clk: clk@01c200a0 {
306			#clock-cells = <0>;
307			compatible = "allwinner,sun4i-a10-mod0-clk";
308			reg = <0x01c200a0 0x4>;
309			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
310			clock-output-names = "spi0";
311		};
312
313		spi1_clk: clk@01c200a4 {
314			#clock-cells = <0>;
315			compatible = "allwinner,sun4i-a10-mod0-clk";
316			reg = <0x01c200a4 0x4>;
317			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
318			clock-output-names = "spi1";
319		};
320
321		spi2_clk: clk@01c200a8 {
322			#clock-cells = <0>;
323			compatible = "allwinner,sun4i-a10-mod0-clk";
324			reg = <0x01c200a8 0x4>;
325			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
326			clock-output-names = "spi2";
327		};
328
329		ir0_clk: clk@01c200b0 {
330			#clock-cells = <0>;
331			compatible = "allwinner,sun4i-a10-mod0-clk";
332			reg = <0x01c200b0 0x4>;
333			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
334			clock-output-names = "ir0";
335		};
336
337		usb_clk: clk@01c200cc {
338			#clock-cells = <1>;
339		        #reset-cells = <1>;
340			compatible = "allwinner,sun5i-a13-usb-clk";
341			reg = <0x01c200cc 0x4>;
342			clocks = <&pll6 1>;
343			clock-output-names = "usb_ohci0", "usb_phy";
344		};
345
346		mbus_clk: clk@01c2015c {
347			#clock-cells = <0>;
348			compatible = "allwinner,sun5i-a13-mbus-clk";
349			reg = <0x01c2015c 0x4>;
350			clocks = <&osc24M>, <&pll6 1>, <&pll5 1>;
351			clock-output-names = "mbus";
352		};
353	};
354
355	soc@01c00000 {
356		compatible = "simple-bus";
357		#address-cells = <1>;
358		#size-cells = <1>;
359		ranges;
360
361		dma: dma-controller@01c02000 {
362			compatible = "allwinner,sun4i-a10-dma";
363			reg = <0x01c02000 0x1000>;
364			interrupts = <27>;
365			clocks = <&ahb_gates 6>;
366			#dma-cells = <2>;
367		};
368
369		spi0: spi@01c05000 {
370			compatible = "allwinner,sun4i-a10-spi";
371			reg = <0x01c05000 0x1000>;
372			interrupts = <10>;
373			clocks = <&ahb_gates 20>, <&spi0_clk>;
374			clock-names = "ahb", "mod";
375			dmas = <&dma SUN4I_DMA_DEDICATED 27>,
376			       <&dma SUN4I_DMA_DEDICATED 26>;
377			dma-names = "rx", "tx";
378			status = "disabled";
379			#address-cells = <1>;
380			#size-cells = <0>;
381		};
382
383		spi1: spi@01c06000 {
384			compatible = "allwinner,sun4i-a10-spi";
385			reg = <0x01c06000 0x1000>;
386			interrupts = <11>;
387			clocks = <&ahb_gates 21>, <&spi1_clk>;
388			clock-names = "ahb", "mod";
389			dmas = <&dma SUN4I_DMA_DEDICATED 9>,
390			       <&dma SUN4I_DMA_DEDICATED 8>;
391			dma-names = "rx", "tx";
392			status = "disabled";
393			#address-cells = <1>;
394			#size-cells = <0>;
395		};
396
397		mmc0: mmc@01c0f000 {
398			compatible = "allwinner,sun5i-a13-mmc";
399			reg = <0x01c0f000 0x1000>;
400			clocks = <&ahb_gates 8>,
401				 <&mmc0_clk 0>,
402				 <&mmc0_clk 1>,
403				 <&mmc0_clk 2>;
404			clock-names = "ahb",
405				      "mmc",
406				      "output",
407				      "sample";
408			interrupts = <32>;
409			status = "disabled";
410		};
411
412		mmc2: mmc@01c11000 {
413			compatible = "allwinner,sun5i-a13-mmc";
414			reg = <0x01c11000 0x1000>;
415			clocks = <&ahb_gates 10>,
416				 <&mmc2_clk 0>,
417				 <&mmc2_clk 1>,
418				 <&mmc2_clk 2>;
419			clock-names = "ahb",
420				      "mmc",
421				      "output",
422				      "sample";
423			interrupts = <34>;
424			status = "disabled";
425		};
426
427		usbphy: phy@01c13400 {
428			#phy-cells = <1>;
429			compatible = "allwinner,sun5i-a13-usb-phy";
430			reg = <0x01c13400 0x10 0x01c14800 0x4>;
431			reg-names = "phy_ctrl", "pmu1";
432			clocks = <&usb_clk 8>;
433			clock-names = "usb_phy";
434			resets = <&usb_clk 0>, <&usb_clk 1>;
435			reset-names = "usb0_reset", "usb1_reset";
436			status = "disabled";
437		};
438
439		ehci0: usb@01c14000 {
440			compatible = "allwinner,sun5i-a13-ehci", "generic-ehci";
441			reg = <0x01c14000 0x100>;
442			interrupts = <39>;
443			clocks = <&ahb_gates 1>;
444			phys = <&usbphy 1>;
445			phy-names = "usb";
446			status = "disabled";
447		};
448
449		ohci0: usb@01c14400 {
450			compatible = "allwinner,sun5i-a13-ohci", "generic-ohci";
451			reg = <0x01c14400 0x100>;
452			interrupts = <40>;
453			clocks = <&usb_clk 6>, <&ahb_gates 2>;
454			phys = <&usbphy 1>;
455			phy-names = "usb";
456			status = "disabled";
457		};
458
459		spi2: spi@01c17000 {
460			compatible = "allwinner,sun4i-a10-spi";
461			reg = <0x01c17000 0x1000>;
462			interrupts = <12>;
463			clocks = <&ahb_gates 22>, <&spi2_clk>;
464			clock-names = "ahb", "mod";
465			dmas = <&dma SUN4I_DMA_DEDICATED 29>,
466			       <&dma SUN4I_DMA_DEDICATED 28>;
467			dma-names = "rx", "tx";
468			status = "disabled";
469			#address-cells = <1>;
470			#size-cells = <0>;
471		};
472
473		intc: interrupt-controller@01c20400 {
474			compatible = "allwinner,sun4i-a10-ic";
475			reg = <0x01c20400 0x400>;
476			interrupt-controller;
477			#interrupt-cells = <1>;
478		};
479
480		pio: pinctrl@01c20800 {
481			compatible = "allwinner,sun5i-a13-pinctrl";
482			reg = <0x01c20800 0x400>;
483			interrupts = <28>;
484			clocks = <&apb0_gates 5>;
485			gpio-controller;
486			interrupt-controller;
487			#interrupt-cells = <2>;
488			#size-cells = <0>;
489			#gpio-cells = <3>;
490
491			uart1_pins_a: uart1@0 {
492				allwinner,pins = "PE10", "PE11";
493				allwinner,function = "uart1";
494				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
495				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
496			};
497
498			uart1_pins_b: uart1@1 {
499				allwinner,pins = "PG3", "PG4";
500				allwinner,function = "uart1";
501				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
502				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
503			};
504
505			i2c0_pins_a: i2c0@0 {
506				allwinner,pins = "PB0", "PB1";
507				allwinner,function = "i2c0";
508				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
509				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
510			};
511
512			i2c1_pins_a: i2c1@0 {
513				allwinner,pins = "PB15", "PB16";
514				allwinner,function = "i2c1";
515				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
516				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
517			};
518
519			i2c2_pins_a: i2c2@0 {
520				allwinner,pins = "PB17", "PB18";
521				allwinner,function = "i2c2";
522				allwinner,drive = <SUN4I_PINCTRL_10_MA>;
523				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
524			};
525
526			mmc0_pins_a: mmc0@0 {
527				allwinner,pins = "PF0","PF1","PF2","PF3","PF4","PF5";
528				allwinner,function = "mmc0";
529				allwinner,drive = <SUN4I_PINCTRL_30_MA>;
530				allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
531			};
532		};
533
534		timer@01c20c00 {
535			compatible = "allwinner,sun4i-a10-timer";
536			reg = <0x01c20c00 0x90>;
537			interrupts = <22>;
538			clocks = <&osc24M>;
539		};
540
541		wdt: watchdog@01c20c90 {
542			compatible = "allwinner,sun4i-a10-wdt";
543			reg = <0x01c20c90 0x10>;
544		};
545
546		lradc: lradc@01c22800 {
547			compatible = "allwinner,sun4i-a10-lradc-keys";
548			reg = <0x01c22800 0x100>;
549			interrupts = <31>;
550			status = "disabled";
551		};
552
553		sid: eeprom@01c23800 {
554			compatible = "allwinner,sun4i-a10-sid";
555			reg = <0x01c23800 0x10>;
556		};
557
558		rtp: rtp@01c25000 {
559			compatible = "allwinner,sun4i-a10-ts";
560			reg = <0x01c25000 0x100>;
561			interrupts = <29>;
562			#thermal-sensor-cells = <0>;
563		};
564
565		uart1: serial@01c28400 {
566			compatible = "snps,dw-apb-uart";
567			reg = <0x01c28400 0x400>;
568			interrupts = <2>;
569			reg-shift = <2>;
570			reg-io-width = <4>;
571			clocks = <&apb1_gates 17>;
572			status = "disabled";
573		};
574
575		uart3: serial@01c28c00 {
576			compatible = "snps,dw-apb-uart";
577			reg = <0x01c28c00 0x400>;
578			interrupts = <4>;
579			reg-shift = <2>;
580			reg-io-width = <4>;
581			clocks = <&apb1_gates 19>;
582			status = "disabled";
583		};
584
585		i2c0: i2c@01c2ac00 {
586			compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
587			reg = <0x01c2ac00 0x400>;
588			interrupts = <7>;
589			clocks = <&apb1_gates 0>;
590			status = "disabled";
591			#address-cells = <1>;
592			#size-cells = <0>;
593		};
594
595		i2c1: i2c@01c2b000 {
596			compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
597			reg = <0x01c2b000 0x400>;
598			interrupts = <8>;
599			clocks = <&apb1_gates 1>;
600			status = "disabled";
601			#address-cells = <1>;
602			#size-cells = <0>;
603		};
604
605		i2c2: i2c@01c2b400 {
606			compatible = "allwinner,sun5i-a13-i2c", "allwinner,sun4i-a10-i2c";
607			reg = <0x01c2b400 0x400>;
608			interrupts = <9>;
609			clocks = <&apb1_gates 2>;
610			status = "disabled";
611			#address-cells = <1>;
612			#size-cells = <0>;
613		};
614
615		timer@01c60000 {
616			compatible = "allwinner,sun5i-a13-hstimer";
617			reg = <0x01c60000 0x1000>;
618			interrupts = <82>, <83>;
619			clocks = <&ahb_gates 28>;
620		};
621	};
622};
623