stih407.dtsi revision 284090
167754Smsmith/* 267754Smsmith * Copyright (C) 2015 STMicroelectronics Limited. 377424Smsmith * Author: Gabriel Fernandez <gabriel.fernandez@linaro.org> 467754Smsmith * 567754Smsmith * This program is free software; you can redistribute it and/or modify 667754Smsmith * it under the terms of the GNU General Public License version 2 as 7217365Sjkim * publishhed by the Free Software Foundation. 8306536Sjkim */ 970243Smsmith#include "stih407-clock.dtsi" 1067754Smsmith#include "stih407-family.dtsi" 11217365Sjkim/ { 12217365Sjkim soc { 13217365Sjkim /* Display */ 14217365Sjkim vtg_main: sti-vtg-main@8d02800 { 15217365Sjkim compatible = "st,vtg"; 16217365Sjkim reg = <0x8d02800 0x200>; 17217365Sjkim interrupts = <GIC_SPI 108 IRQ_TYPE_NONE>; 18217365Sjkim }; 19217365Sjkim 20217365Sjkim vtg_aux: sti-vtg-aux@8d00200 { 21217365Sjkim compatible = "st,vtg"; 22217365Sjkim reg = <0x8d00200 0x100>; 23217365Sjkim interrupts = <GIC_SPI 109 IRQ_TYPE_NONE>; 24217365Sjkim }; 2567754Smsmith 26217365Sjkim sti-display-subsystem { 27217365Sjkim compatible = "st,sti-display-subsystem"; 28217365Sjkim #address-cells = <1>; 2967754Smsmith #size-cells = <1>; 30217365Sjkim 31217365Sjkim assigned-clocks = <&clk_s_d2_quadfs 0>, 32217365Sjkim <&clk_s_d2_quadfs 0>, 33217365Sjkim <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, 34217365Sjkim <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, 35217365Sjkim <&clk_s_d2_flexgen CLK_PIX_GDP1>, 36217365Sjkim <&clk_s_d2_flexgen CLK_PIX_GDP2>, 37217365Sjkim <&clk_s_d2_flexgen CLK_PIX_GDP3>, 38217365Sjkim <&clk_s_d2_flexgen CLK_PIX_GDP4>; 39217365Sjkim 40217365Sjkim assigned-clock-parents = <0>, 41217365Sjkim <0>, 42217365Sjkim <&clk_s_d2_quadfs 0>, 4367754Smsmith <&clk_s_d2_quadfs 0>, 44193341Sjkim <&clk_s_d2_quadfs 0>, 45193341Sjkim <&clk_s_d2_quadfs 0>, 46193341Sjkim <&clk_s_d2_quadfs 0>, 4767754Smsmith <&clk_s_d2_quadfs 0>; 4867754Smsmith 4977424Smsmith assigned-clock-rates = <297000000>, <297000000>; 5091116Smsmith 5167754Smsmith ranges; 52151937Sjkim 5367754Smsmith sti-compositor@9d11000 { 54151937Sjkim compatible = "st,stih407-compositor"; 55151937Sjkim reg = <0x9d11000 0x1000>; 56151937Sjkim 57151937Sjkim clock-names = "compo_main", 58151937Sjkim "compo_aux", 59151937Sjkim "pix_main", 60151937Sjkim "pix_aux", 61151937Sjkim "pix_gdp1", 62151937Sjkim "pix_gdp2", 63151937Sjkim "pix_gdp3", 64151937Sjkim "pix_gdp4", 65151937Sjkim "main_parent", 66151937Sjkim "aux_parent"; 67151937Sjkim 68151937Sjkim clocks = <&clk_s_c0_flexgen CLK_COMPO_DVP>, 69151937Sjkim <&clk_s_c0_flexgen CLK_COMPO_DVP>, 70151937Sjkim <&clk_s_d2_flexgen CLK_PIX_MAIN_DISP>, 71151937Sjkim <&clk_s_d2_flexgen CLK_PIX_AUX_DISP>, 72151937Sjkim <&clk_s_d2_flexgen CLK_PIX_GDP1>, 73151937Sjkim <&clk_s_d2_flexgen CLK_PIX_GDP2>, 74151937Sjkim <&clk_s_d2_flexgen CLK_PIX_GDP3>, 75151937Sjkim <&clk_s_d2_flexgen CLK_PIX_GDP4>, 76151937Sjkim <&clk_s_d2_quadfs 0>, 77151937Sjkim <&clk_s_d2_quadfs 1>; 78151937Sjkim 79151937Sjkim reset-names = "compo-main", "compo-aux"; 80193267Sjkim resets = <&softreset STIH407_COMPO_SOFTRESET>, 81193267Sjkim <&softreset STIH407_COMPO_SOFTRESET>; 82193267Sjkim st,vtg = <&vtg_main>, <&vtg_aux>; 83193267Sjkim }; 84193267Sjkim 85151937Sjkim sti-tvout@8d08000 { 86151937Sjkim compatible = "st,stih407-tvout"; 87151937Sjkim reg = <0x8d08000 0x1000>; 88151937Sjkim reg-names = "tvout-reg"; 89151937Sjkim reset-names = "tvout"; 90151937Sjkim resets = <&softreset STIH407_HDTVOUT_SOFTRESET>; 91151937Sjkim #address-cells = <1>; 92151937Sjkim #size-cells = <1>; 93151937Sjkim assigned-clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, 94151937Sjkim <&clk_s_d2_flexgen CLK_TMDS_HDMI>, 95151937Sjkim <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, 96151937Sjkim <&clk_s_d0_flexgen CLK_PCM_0>, 97151937Sjkim <&clk_s_d2_flexgen CLK_PIX_HDDAC>, 98151937Sjkim <&clk_s_d2_flexgen CLK_HDDAC>; 99151937Sjkim 100151937Sjkim assigned-clock-parents = <&clk_s_d2_quadfs 0>, 101151937Sjkim <&clk_tmdsout_hdmi>, 102151937Sjkim <&clk_s_d2_quadfs 0>, 10373561Smsmith <&clk_s_d0_quadfs 0>, 10467754Smsmith <&clk_s_d2_quadfs 0>, 10577424Smsmith <&clk_s_d2_quadfs 0>; 10667754Smsmith ranges; 107151937Sjkim 108151937Sjkim sti-hdmi@8d04000 { 109151937Sjkim compatible = "st,stih407-hdmi"; 110151937Sjkim reg = <0x8d04000 0x1000>; 111151937Sjkim reg-names = "hdmi-reg"; 11267754Smsmith interrupts = <GIC_SPI 106 IRQ_TYPE_NONE>; 11373561Smsmith interrupt-names = "irq"; 11467754Smsmith clock-names = "pix", 115151937Sjkim "tmds", 116151937Sjkim "phy", 11767754Smsmith "audio", 118151937Sjkim "main_parent", 119151937Sjkim "aux_parent"; 12067754Smsmith 12167754Smsmith clocks = <&clk_s_d2_flexgen CLK_PIX_HDMI>, 12267754Smsmith <&clk_s_d2_flexgen CLK_TMDS_HDMI>, 12369450Smsmith <&clk_s_d2_flexgen CLK_REF_HDMIPHY>, 12477424Smsmith <&clk_s_d0_flexgen CLK_PCM_0>, 12573561Smsmith <&clk_s_d2_quadfs 0>, 12673561Smsmith <&clk_s_d2_quadfs 1>; 12767754Smsmith 12891116Smsmith hdmi,hpd-gpio = <&pio5 3>; 12967754Smsmith reset-names = "hdmi"; 13073561Smsmith resets = <&softreset STIH407_HDMI_TX_PHY_SOFTRESET>; 13167754Smsmith ddc = <&hdmiddc>; 13267754Smsmith 133167802Sjkim }; 13467754Smsmith 13567754Smsmith sti-hda@8d02000 { 13691116Smsmith compatible = "st,stih407-hda"; 13791116Smsmith reg = <0x8d02000 0x400>, <0x92b0120 0x4>; 13867754Smsmith reg-names = "hda-reg", "video-dacs-ctrl"; 13967754Smsmith clock-names = "pix", 14099679Siwasaki "hddac", 14167754Smsmith "main_parent", 14273561Smsmith "aux_parent"; 14367754Smsmith clocks = <&clk_s_d2_flexgen CLK_PIX_HDDAC>, 14467754Smsmith <&clk_s_d2_flexgen CLK_HDDAC>, 14567754Smsmith <&clk_s_d2_quadfs 0>, 14667754Smsmith <&clk_s_d2_quadfs 1>; 14767754Smsmith }; 14867754Smsmith }; 149306536Sjkim }; 15067754Smsmith }; 15167754Smsmith}; 15267754Smsmith