ste-nomadik-stn8815.dtsi revision 284090
1/* 2 * Device Tree for the ST-Ericsson Nomadik 8815 STn8815 SoC 3 */ 4 5#include <dt-bindings/gpio/gpio.h> 6#include "skeleton.dtsi" 7 8/ { 9 #address-cells = <1>; 10 #size-cells = <1>; 11 12 memory { 13 reg = <0x00000000 0x04000000>, 14 <0x08000000 0x04000000>; 15 }; 16 17 L2: l2-cache { 18 compatible = "arm,l210-cache"; 19 reg = <0x10210000 0x1000>; 20 interrupt-parent = <&vica>; 21 interrupts = <30>; 22 cache-unified; 23 cache-level = <2>; 24 }; 25 26 mtu0: mtu@101e2000 { 27 /* Nomadik system timer */ 28 compatible = "st,nomadik-mtu"; 29 reg = <0x101e2000 0x1000>; 30 interrupt-parent = <&vica>; 31 interrupts = <4>; 32 clocks = <&timclk>, <&pclk>; 33 clock-names = "timclk", "apb_pclk"; 34 }; 35 36 mtu1: mtu@101e3000 { 37 /* Secondary timer */ 38 reg = <0x101e3000 0x1000>; 39 interrupt-parent = <&vica>; 40 interrupts = <5>; 41 clocks = <&timclk>, <&pclk>; 42 clock-names = "timclk", "apb_pclk"; 43 }; 44 45 gpio0: gpio@101e4000 { 46 compatible = "st,nomadik-gpio"; 47 reg = <0x101e4000 0x80>; 48 interrupt-parent = <&vica>; 49 interrupts = <6>; 50 interrupt-controller; 51 #interrupt-cells = <2>; 52 gpio-controller; 53 #gpio-cells = <2>; 54 gpio-bank = <0>; 55 clocks = <&pclk>; 56 }; 57 58 gpio1: gpio@101e5000 { 59 compatible = "st,nomadik-gpio"; 60 reg = <0x101e5000 0x80>; 61 interrupt-parent = <&vica>; 62 interrupts = <7>; 63 interrupt-controller; 64 #interrupt-cells = <2>; 65 gpio-controller; 66 #gpio-cells = <2>; 67 gpio-bank = <1>; 68 clocks = <&pclk>; 69 }; 70 71 gpio2: gpio@101e6000 { 72 compatible = "st,nomadik-gpio"; 73 reg = <0x101e6000 0x80>; 74 interrupt-parent = <&vica>; 75 interrupts = <8>; 76 interrupt-controller; 77 #interrupt-cells = <2>; 78 gpio-controller; 79 #gpio-cells = <2>; 80 gpio-bank = <2>; 81 clocks = <&pclk>; 82 }; 83 84 gpio3: gpio@101e7000 { 85 compatible = "st,nomadik-gpio"; 86 reg = <0x101e7000 0x80>; 87 interrupt-parent = <&vica>; 88 interrupts = <9>; 89 interrupt-controller; 90 #interrupt-cells = <2>; 91 gpio-controller; 92 #gpio-cells = <2>; 93 gpio-bank = <3>; 94 clocks = <&pclk>; 95 }; 96 97 pinctrl { 98 compatible = "stericsson,stn8815-pinctrl"; 99 /* Pin configurations */ 100 uart0 { 101 uart0_default_mux: uart0_mux { 102 u0_default_mux { 103 function = "u0"; 104 groups = "u0_a_1"; 105 }; 106 }; 107 }; 108 uart1 { 109 uart1_default_mux: uart1_mux { 110 u1_default_mux { 111 function = "u1"; 112 groups = "u1_a_1"; 113 }; 114 }; 115 }; 116 mmcsd { 117 mmcsd_default_mux: mmcsd_mux { 118 mmcsd_default_mux { 119 function = "mmcsd"; 120 groups = "mmcsd_a_1", "mmcsd_b_1"; 121 }; 122 }; 123 mmcsd_default_mode: mmcsd_default { 124 mmcsd_default_cfg1 { 125 /* MCCLK */ 126 pins = "GPIO8_B10"; 127 ste,output = <0>; 128 }; 129 mmcsd_default_cfg2 { 130 /* MCCMDDIR, MCDAT0DIR, MCDAT31DIR, MCDATDIR2 */ 131 pins = "GPIO10_C11", "GPIO15_A12", 132 "GPIO16_C13", "GPIO23_D15"; 133 ste,output = <1>; 134 }; 135 mmcsd_default_cfg3 { 136 /* MCCMD, MCDAT3-0, MCMSFBCLK */ 137 pins = "GPIO9_A10", "GPIO11_B11", 138 "GPIO12_A11", "GPIO13_C12", 139 "GPIO14_B12", "GPIO24_C15"; 140 ste,input = <1>; 141 }; 142 }; 143 }; 144 i2c0 { 145 i2c0_default_mux: i2c0_mux { 146 i2c0_default_mux { 147 function = "i2c0"; 148 groups = "i2c0_a_1"; 149 }; 150 }; 151 i2c0_default_mode: i2c0_default { 152 i2c0_default_cfg { 153 pins = "GPIO62_D3", "GPIO63_D2"; 154 ste,input = <0>; 155 }; 156 }; 157 }; 158 i2c1 { 159 i2c1_default_mux: i2c1_mux { 160 i2c1_default_mux { 161 function = "i2c1"; 162 groups = "i2c1_a_1"; 163 }; 164 }; 165 i2c1_default_mode: i2c1_default { 166 i2c1_default_cfg { 167 pins = "GPIO53_L4", "GPIO54_L3"; 168 ste,input = <0>; 169 }; 170 }; 171 }; 172 }; 173 174 src: src@101e0000 { 175 compatible = "stericsson,nomadik-src"; 176 reg = <0x101e0000 0x1000>; 177 178 /* 179 * MXTAL "Main Chrystal" is a chrystal oscillator @19.2 MHz 180 * that is parent of TIMCLK, PLL1 and PLL2 181 */ 182 mxtal: mxtal@19.2M { 183 #clock-cells = <0>; 184 compatible = "fixed-clock"; 185 clock-frequency = <19200000>; 186 }; 187 188 /* 189 * The 2.4 MHz TIMCLK reference clock is active at 190 * boot time, this is actually the MXTALCLK @19.2 MHz 191 * divided by 8. This clock is used by the timers and 192 * watchdog. See page 105 ff. 193 */ 194 timclk: timclk@2.4M { 195 #clock-cells = <0>; 196 compatible = "fixed-factor-clock"; 197 clock-div = <8>; 198 clock-mult = <1>; 199 clocks = <&mxtal>; 200 }; 201 202 /* PLL1 is locked to MXTALI and variable from 20.4 to 334 MHz */ 203 pll1: pll1@0 { 204 #clock-cells = <0>; 205 compatible = "st,nomadik-pll-clock"; 206 pll-id = <1>; 207 clocks = <&mxtal>; 208 }; 209 210 /* HCLK divides the PLL1 with 1,2,3 or 4 */ 211 hclk: hclk@0 { 212 #clock-cells = <0>; 213 compatible = "st,nomadik-hclk-clock"; 214 clocks = <&pll1>; 215 }; 216 /* The PCLK domain uses HCLK right off */ 217 pclk: pclk@0 { 218 #clock-cells = <0>; 219 compatible = "fixed-factor-clock"; 220 clock-div = <1>; 221 clock-mult = <1>; 222 clocks = <&hclk>; 223 }; 224 225 /* PLL2 is usually 864 MHz and divided into a few fixed rates */ 226 pll2: pll2@0 { 227 #clock-cells = <0>; 228 compatible = "st,nomadik-pll-clock"; 229 pll-id = <2>; 230 clocks = <&mxtal>; 231 }; 232 clk216: clk216@216M { 233 #clock-cells = <0>; 234 compatible = "fixed-factor-clock"; 235 clock-div = <4>; 236 clock-mult = <1>; 237 clocks = <&pll2>; 238 }; 239 clk108: clk108@108M { 240 #clock-cells = <0>; 241 compatible = "fixed-factor-clock"; 242 clock-div = <2>; 243 clock-mult = <1>; 244 clocks = <&clk216>; 245 }; 246 clk72: clk72@72M { 247 #clock-cells = <0>; 248 compatible = "fixed-factor-clock"; 249 /* The data sheet does not say how this is derived */ 250 clock-div = <12>; 251 clock-mult = <1>; 252 clocks = <&pll2>; 253 }; 254 clk48: clk48@48M { 255 #clock-cells = <0>; 256 compatible = "fixed-factor-clock"; 257 /* The data sheet does not say how this is derived */ 258 clock-div = <18>; 259 clock-mult = <1>; 260 clocks = <&pll2>; 261 }; 262 clk27: clk27@27M { 263 #clock-cells = <0>; 264 compatible = "fixed-factor-clock"; 265 clock-div = <4>; 266 clock-mult = <1>; 267 clocks = <&clk108>; 268 }; 269 270 /* This apparently exists as well */ 271 ulpiclk: ulpiclk@60M { 272 #clock-cells = <0>; 273 compatible = "fixed-clock"; 274 clock-frequency = <60000000>; 275 }; 276 277 /* 278 * IP AMBA bus clocks, driving the bus side of the 279 * peripheral clocking, clock gates. 280 */ 281 282 hclkdma0: hclkdma0@48M { 283 #clock-cells = <0>; 284 compatible = "st,nomadik-src-clock"; 285 clock-id = <0>; 286 clocks = <&hclk>; 287 }; 288 hclksmc: hclksmc@48M { 289 #clock-cells = <0>; 290 compatible = "st,nomadik-src-clock"; 291 clock-id = <1>; 292 clocks = <&hclk>; 293 }; 294 hclksdram: hclksdram@48M { 295 #clock-cells = <0>; 296 compatible = "st,nomadik-src-clock"; 297 clock-id = <2>; 298 clocks = <&hclk>; 299 }; 300 hclkdma1: hclkdma1@48M { 301 #clock-cells = <0>; 302 compatible = "st,nomadik-src-clock"; 303 clock-id = <3>; 304 clocks = <&hclk>; 305 }; 306 hclkclcd: hclkclcd@48M { 307 #clock-cells = <0>; 308 compatible = "st,nomadik-src-clock"; 309 clock-id = <4>; 310 clocks = <&hclk>; 311 }; 312 pclkirda: pclkirda@48M { 313 #clock-cells = <0>; 314 compatible = "st,nomadik-src-clock"; 315 clock-id = <5>; 316 clocks = <&pclk>; 317 }; 318 pclkssp: pclkssp@48M { 319 #clock-cells = <0>; 320 compatible = "st,nomadik-src-clock"; 321 clock-id = <6>; 322 clocks = <&pclk>; 323 }; 324 pclkuart0: pclkuart0@48M { 325 #clock-cells = <0>; 326 compatible = "st,nomadik-src-clock"; 327 clock-id = <7>; 328 clocks = <&pclk>; 329 }; 330 pclksdi: pclksdi@48M { 331 #clock-cells = <0>; 332 compatible = "st,nomadik-src-clock"; 333 clock-id = <8>; 334 clocks = <&pclk>; 335 }; 336 pclki2c0: pclki2c0@48M { 337 #clock-cells = <0>; 338 compatible = "st,nomadik-src-clock"; 339 clock-id = <9>; 340 clocks = <&pclk>; 341 }; 342 pclki2c1: pclki2c1@48M { 343 #clock-cells = <0>; 344 compatible = "st,nomadik-src-clock"; 345 clock-id = <10>; 346 clocks = <&pclk>; 347 }; 348 pclkuart1: pclkuart1@48M { 349 #clock-cells = <0>; 350 compatible = "st,nomadik-src-clock"; 351 clock-id = <11>; 352 clocks = <&pclk>; 353 }; 354 pclkmsp0: pclkmsp0@48M { 355 #clock-cells = <0>; 356 compatible = "st,nomadik-src-clock"; 357 clock-id = <12>; 358 clocks = <&pclk>; 359 }; 360 hclkusb: hclkusb@48M { 361 #clock-cells = <0>; 362 compatible = "st,nomadik-src-clock"; 363 clock-id = <13>; 364 clocks = <&hclk>; 365 }; 366 hclkdif: hclkdif@48M { 367 #clock-cells = <0>; 368 compatible = "st,nomadik-src-clock"; 369 clock-id = <14>; 370 clocks = <&hclk>; 371 }; 372 hclksaa: hclksaa@48M { 373 #clock-cells = <0>; 374 compatible = "st,nomadik-src-clock"; 375 clock-id = <15>; 376 clocks = <&hclk>; 377 }; 378 hclksva: hclksva@48M { 379 #clock-cells = <0>; 380 compatible = "st,nomadik-src-clock"; 381 clock-id = <16>; 382 clocks = <&hclk>; 383 }; 384 pclkhsi: pclkhsi@48M { 385 #clock-cells = <0>; 386 compatible = "st,nomadik-src-clock"; 387 clock-id = <17>; 388 clocks = <&pclk>; 389 }; 390 pclkxti: pclkxti@48M { 391 #clock-cells = <0>; 392 compatible = "st,nomadik-src-clock"; 393 clock-id = <18>; 394 clocks = <&pclk>; 395 }; 396 pclkuart2: pclkuart2@48M { 397 #clock-cells = <0>; 398 compatible = "st,nomadik-src-clock"; 399 clock-id = <19>; 400 clocks = <&pclk>; 401 }; 402 pclkmsp1: pclkmsp1@48M { 403 #clock-cells = <0>; 404 compatible = "st,nomadik-src-clock"; 405 clock-id = <20>; 406 clocks = <&pclk>; 407 }; 408 pclkmsp2: pclkmsp2@48M { 409 #clock-cells = <0>; 410 compatible = "st,nomadik-src-clock"; 411 clock-id = <21>; 412 clocks = <&pclk>; 413 }; 414 pclkowm: pclkowm@48M { 415 #clock-cells = <0>; 416 compatible = "st,nomadik-src-clock"; 417 clock-id = <22>; 418 clocks = <&pclk>; 419 }; 420 hclkhpi: hclkhpi@48M { 421 #clock-cells = <0>; 422 compatible = "st,nomadik-src-clock"; 423 clock-id = <23>; 424 clocks = <&hclk>; 425 }; 426 pclkske: pclkske@48M { 427 #clock-cells = <0>; 428 compatible = "st,nomadik-src-clock"; 429 clock-id = <24>; 430 clocks = <&pclk>; 431 }; 432 pclkhsem: pclkhsem@48M { 433 #clock-cells = <0>; 434 compatible = "st,nomadik-src-clock"; 435 clock-id = <25>; 436 clocks = <&pclk>; 437 }; 438 hclk3d: hclk3d@48M { 439 #clock-cells = <0>; 440 compatible = "st,nomadik-src-clock"; 441 clock-id = <26>; 442 clocks = <&hclk>; 443 }; 444 hclkhash: hclkhash@48M { 445 #clock-cells = <0>; 446 compatible = "st,nomadik-src-clock"; 447 clock-id = <27>; 448 clocks = <&hclk>; 449 }; 450 hclkcryp: hclkcryp@48M { 451 #clock-cells = <0>; 452 compatible = "st,nomadik-src-clock"; 453 clock-id = <28>; 454 clocks = <&hclk>; 455 }; 456 pclkmshc: pclkmshc@48M { 457 #clock-cells = <0>; 458 compatible = "st,nomadik-src-clock"; 459 clock-id = <29>; 460 clocks = <&pclk>; 461 }; 462 hclkusbm: hclkusbm@48M { 463 #clock-cells = <0>; 464 compatible = "st,nomadik-src-clock"; 465 clock-id = <30>; 466 clocks = <&hclk>; 467 }; 468 hclkrng: hclkrng@48M { 469 #clock-cells = <0>; 470 compatible = "st,nomadik-src-clock"; 471 clock-id = <31>; 472 clocks = <&hclk>; 473 }; 474 475 /* IP kernel clocks */ 476 clcdclk: clcdclk@0 { 477 #clock-cells = <0>; 478 compatible = "st,nomadik-src-clock"; 479 clock-id = <36>; 480 clocks = <&clk72 &clk48>; 481 }; 482 irdaclk: irdaclk@48M { 483 #clock-cells = <0>; 484 compatible = "st,nomadik-src-clock"; 485 clock-id = <37>; 486 clocks = <&clk48>; 487 }; 488 sspiclk: sspiclk@48M { 489 #clock-cells = <0>; 490 compatible = "st,nomadik-src-clock"; 491 clock-id = <38>; 492 clocks = <&clk48>; 493 }; 494 uart0clk: uart0clk@48M { 495 #clock-cells = <0>; 496 compatible = "st,nomadik-src-clock"; 497 clock-id = <39>; 498 clocks = <&clk48>; 499 }; 500 sdiclk: sdiclk@48M { 501 /* Also called MCCLK in some documents */ 502 #clock-cells = <0>; 503 compatible = "st,nomadik-src-clock"; 504 clock-id = <40>; 505 clocks = <&clk48>; 506 }; 507 i2c0clk: i2c0clk@48M { 508 #clock-cells = <0>; 509 compatible = "st,nomadik-src-clock"; 510 clock-id = <41>; 511 clocks = <&clk48>; 512 }; 513 i2c1clk: i2c1clk@48M { 514 #clock-cells = <0>; 515 compatible = "st,nomadik-src-clock"; 516 clock-id = <42>; 517 clocks = <&clk48>; 518 }; 519 uart1clk: uart1clk@48M { 520 #clock-cells = <0>; 521 compatible = "st,nomadik-src-clock"; 522 clock-id = <43>; 523 clocks = <&clk48>; 524 }; 525 mspclk0: mspclk0@48M { 526 #clock-cells = <0>; 527 compatible = "st,nomadik-src-clock"; 528 clock-id = <44>; 529 clocks = <&clk48>; 530 }; 531 usbclk: usbclk@48M { 532 #clock-cells = <0>; 533 compatible = "st,nomadik-src-clock"; 534 clock-id = <45>; 535 clocks = <&clk48>; /* 48 MHz not ULPI */ 536 }; 537 difclk: difclk@72M { 538 #clock-cells = <0>; 539 compatible = "st,nomadik-src-clock"; 540 clock-id = <46>; 541 clocks = <&clk72>; 542 }; 543 ipi2cclk: ipi2cclk@48M { 544 #clock-cells = <0>; 545 compatible = "st,nomadik-src-clock"; 546 clock-id = <47>; 547 clocks = <&clk48>; /* Guess */ 548 }; 549 ipbmcclk: ipbmcclk@48M { 550 #clock-cells = <0>; 551 compatible = "st,nomadik-src-clock"; 552 clock-id = <48>; 553 clocks = <&clk48>; /* Guess */ 554 }; 555 hsiclkrx: hsiclkrx@216M { 556 #clock-cells = <0>; 557 compatible = "st,nomadik-src-clock"; 558 clock-id = <49>; 559 clocks = <&clk216>; 560 }; 561 hsiclktx: hsiclktx@108M { 562 #clock-cells = <0>; 563 compatible = "st,nomadik-src-clock"; 564 clock-id = <50>; 565 clocks = <&clk108>; 566 }; 567 uart2clk: uart2clk@48M { 568 #clock-cells = <0>; 569 compatible = "st,nomadik-src-clock"; 570 clock-id = <51>; 571 clocks = <&clk48>; 572 }; 573 mspclk1: mspclk1@48M { 574 #clock-cells = <0>; 575 compatible = "st,nomadik-src-clock"; 576 clock-id = <52>; 577 clocks = <&clk48>; 578 }; 579 mspclk2: mspclk2@48M { 580 #clock-cells = <0>; 581 compatible = "st,nomadik-src-clock"; 582 clock-id = <53>; 583 clocks = <&clk48>; 584 }; 585 owmclk: owmclk@48M { 586 #clock-cells = <0>; 587 compatible = "st,nomadik-src-clock"; 588 clock-id = <54>; 589 clocks = <&clk48>; /* Guess */ 590 }; 591 skeclk: skeclk@48M { 592 #clock-cells = <0>; 593 compatible = "st,nomadik-src-clock"; 594 clock-id = <56>; 595 clocks = <&clk48>; /* Guess */ 596 }; 597 x3dclk: x3dclk@48M { 598 #clock-cells = <0>; 599 compatible = "st,nomadik-src-clock"; 600 clock-id = <58>; 601 clocks = <&clk48>; /* Guess */ 602 }; 603 pclkmsp3: pclkmsp3@48M { 604 #clock-cells = <0>; 605 compatible = "st,nomadik-src-clock"; 606 clock-id = <59>; 607 clocks = <&pclk>; 608 }; 609 mspclk3: mspclk3@48M { 610 #clock-cells = <0>; 611 compatible = "st,nomadik-src-clock"; 612 clock-id = <60>; 613 clocks = <&clk48>; 614 }; 615 mshcclk: mshcclk@48M { 616 #clock-cells = <0>; 617 compatible = "st,nomadik-src-clock"; 618 clock-id = <61>; 619 clocks = <&clk48>; /* Guess */ 620 }; 621 usbmclk: usbmclk@48M { 622 #clock-cells = <0>; 623 compatible = "st,nomadik-src-clock"; 624 clock-id = <62>; 625 /* Stated as "48 MHz not ULPI clock" */ 626 clocks = <&clk48>; 627 }; 628 rngcclk: rngcclk@48M { 629 #clock-cells = <0>; 630 compatible = "st,nomadik-src-clock"; 631 clock-id = <63>; 632 clocks = <&clk48>; /* Guess */ 633 }; 634 }; 635 636 /* A NAND flash of 128 MiB */ 637 fsmc: flash@40000000 { 638 compatible = "stericsson,fsmc-nand"; 639 #address-cells = <1>; 640 #size-cells = <1>; 641 reg = <0x10100000 0x1000>, /* FSMC Register*/ 642 <0x40000000 0x2000>, /* NAND Base DATA */ 643 <0x41000000 0x2000>, /* NAND Base ADDR */ 644 <0x40800000 0x2000>; /* NAND Base CMD */ 645 reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd"; 646 clocks = <&hclksmc>; 647 status = "okay"; 648 timings = /bits/ 8 <0 0 0 0x10 0x0a 0>; 649 650 partition@0 { 651 label = "X-Loader(NAND)"; 652 reg = <0x0 0x40000>; 653 }; 654 partition@40000 { 655 label = "MemInit(NAND)"; 656 reg = <0x40000 0x40000>; 657 }; 658 partition@80000 { 659 label = "BootLoader(NAND)"; 660 reg = <0x80000 0x200000>; 661 }; 662 partition@280000 { 663 label = "Kernel zImage(NAND)"; 664 reg = <0x280000 0x300000>; 665 }; 666 partition@580000 { 667 label = "Root Filesystem(NAND)"; 668 reg = <0x580000 0x1600000>; 669 }; 670 partition@1b80000 { 671 label = "User Filesystem(NAND)"; 672 reg = <0x1b80000 0x6480000>; 673 }; 674 }; 675 676 /* I2C0 connected to the STw4811 power management chip */ 677 i2c0 { 678 compatible = "st,nomadik-i2c", "arm,primecell"; 679 reg = <0x101f8000 0x1000>; 680 interrupt-parent = <&vica>; 681 interrupts = <20>; 682 clock-frequency = <100000>; 683 #address-cells = <1>; 684 #size-cells = <0>; 685 clocks = <&i2c0clk>, <&pclki2c0>; 686 clock-names = "mclk", "apb_pclk"; 687 pinctrl-names = "default"; 688 pinctrl-0 = <&i2c0_default_mux>, <&i2c0_default_mode>; 689 690 stw4811@2d { 691 compatible = "st,stw4811"; 692 reg = <0x2d>; 693 vmmc_regulator: vmmc { 694 compatible = "st,stw481x-vmmc"; 695 regulator-name = "VMMC"; 696 regulator-min-microvolt = <1800000>; 697 regulator-max-microvolt = <3300000>; 698 }; 699 }; 700 }; 701 702 /* I2C1 connected to various sensors */ 703 i2c1 { 704 compatible = "st,nomadik-i2c", "arm,primecell"; 705 reg = <0x101f7000 0x1000>; 706 interrupt-parent = <&vica>; 707 interrupts = <21>; 708 clock-frequency = <100000>; 709 #address-cells = <1>; 710 #size-cells = <0>; 711 clocks = <&i2c1clk>, <&pclki2c1>; 712 clock-names = "mclk", "apb_pclk"; 713 pinctrl-names = "default"; 714 pinctrl-0 = <&i2c1_default_mux>, <&i2c1_default_mode>; 715 716 camera@2d { 717 compatible = "st,camera"; 718 reg = <0x10>; 719 }; 720 stw5095@1a { 721 compatible = "st,stw5095"; 722 reg = <0x1a>; 723 }; 724 lis3lv02dl@1d { 725 compatible = "st,lis3lv02dl"; 726 reg = <0x1d>; 727 }; 728 }; 729 730 amba { 731 compatible = "arm,amba-bus"; 732 #address-cells = <1>; 733 #size-cells = <1>; 734 ranges; 735 736 vica: intc@10140000 { 737 compatible = "arm,versatile-vic"; 738 interrupt-controller; 739 #interrupt-cells = <1>; 740 reg = <0x10140000 0x20>; 741 }; 742 743 vicb: intc@10140020 { 744 compatible = "arm,versatile-vic"; 745 interrupt-controller; 746 #interrupt-cells = <1>; 747 reg = <0x10140020 0x20>; 748 }; 749 750 uart0: uart@101fd000 { 751 compatible = "arm,pl011", "arm,primecell"; 752 reg = <0x101fd000 0x1000>; 753 interrupt-parent = <&vica>; 754 interrupts = <12>; 755 clocks = <&uart0clk>, <&pclkuart0>; 756 clock-names = "uartclk", "apb_pclk"; 757 pinctrl-names = "default"; 758 pinctrl-0 = <&uart0_default_mux>; 759 }; 760 761 uart1: uart@101fb000 { 762 compatible = "arm,pl011", "arm,primecell"; 763 reg = <0x101fb000 0x1000>; 764 interrupt-parent = <&vica>; 765 interrupts = <17>; 766 clocks = <&uart1clk>, <&pclkuart1>; 767 clock-names = "uartclk", "apb_pclk"; 768 pinctrl-names = "default"; 769 pinctrl-0 = <&uart1_default_mux>; 770 }; 771 772 uart2: uart@101f2000 { 773 compatible = "arm,pl011", "arm,primecell"; 774 reg = <0x101f2000 0x1000>; 775 interrupt-parent = <&vica>; 776 interrupts = <28>; 777 clocks = <&uart2clk>, <&pclkuart2>; 778 clock-names = "uartclk", "apb_pclk"; 779 status = "disabled"; 780 }; 781 782 rng: rng@101b0000 { 783 compatible = "arm,primecell"; 784 reg = <0x101b0000 0x1000>; 785 clocks = <&rngcclk>, <&hclkrng>; 786 clock-names = "rng", "apb_pclk"; 787 }; 788 789 rtc: rtc@101e8000 { 790 compatible = "arm,pl031", "arm,primecell"; 791 reg = <0x101e8000 0x1000>; 792 clocks = <&pclk>; 793 clock-names = "apb_pclk"; 794 interrupt-parent = <&vica>; 795 interrupts = <10>; 796 }; 797 798 mmcsd: sdi@101f6000 { 799 compatible = "arm,pl18x", "arm,primecell"; 800 reg = <0x101f6000 0x1000>; 801 clocks = <&sdiclk>, <&pclksdi>; 802 clock-names = "mclk", "apb_pclk"; 803 interrupt-parent = <&vica>; 804 interrupts = <22>; 805 max-frequency = <48000000>; 806 bus-width = <4>; 807 cap-mmc-highspeed; 808 cap-sd-highspeed; 809 pinctrl-names = "default"; 810 pinctrl-0 = <&mmcsd_default_mux>, <&mmcsd_default_mode>; 811 vmmc-supply = <&vmmc_regulator>; 812 }; 813 }; 814}; 815