ste-dbx5x0.dtsi revision 284090 
1/*
2 * Copyright 2012 Linaro Ltd
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include <dt-bindings/interrupt-controller/irq.h>
13#include <dt-bindings/mfd/dbx500-prcmu.h>
14#include <dt-bindings/arm/ux500_pm_domains.h>
15#include "skeleton.dtsi"
16
17/ {
18	soc {
19		#address-cells = <1>;
20		#size-cells = <1>;
21		compatible = "stericsson,db8500";
22		interrupt-parent = <&intc>;
23		ranges;
24
25		intc: interrupt-controller@a0411000 {
26			compatible = "arm,cortex-a9-gic";
27			#interrupt-cells = <3>;
28			#address-cells = <1>;
29			interrupt-controller;
30			reg = <0xa0411000 0x1000>,
31			      <0xa0410100 0x100>;
32		};
33
34		L2: l2-cache {
35			compatible = "arm,pl310-cache";
36			reg = <0xa0412000 0x1000>;
37			interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>;
38			cache-unified;
39			cache-level = <2>;
40		};
41
42		pmu {
43			compatible = "arm,cortex-a9-pmu";
44			interrupts = <0 7 IRQ_TYPE_LEVEL_HIGH>;
45		};
46
47		pm_domains: pm_domains0 {
48			compatible = "stericsson,ux500-pm-domains";
49			#power-domain-cells = <1>;
50		};
51
52		clocks {
53			compatible = "stericsson,u8500-clks";
54
55			prcmu_clk: prcmu-clock {
56				#clock-cells = <1>;
57			};
58
59			prcc_pclk: prcc-periph-clock {
60				#clock-cells = <2>;
61			};
62
63			prcc_kclk: prcc-kernel-clock {
64				#clock-cells = <2>;
65			};
66
67			rtc_clk: rtc32k-clock {
68				#clock-cells = <0>;
69			};
70
71			smp_twd_clk: smp-twd-clock {
72				#clock-cells = <0>;
73			};
74		};
75
76		mtu@a03c6000 {
77			/* Nomadik System Timer */
78			compatible = "st,nomadik-mtu";
79			reg = <0xa03c6000 0x1000>;
80			interrupts = <0 4 IRQ_TYPE_LEVEL_HIGH>;
81
82			clocks = <&prcmu_clk PRCMU_TIMCLK>, <&prcc_pclk 6 6>;
83			clock-names = "timclk", "apb_pclk";
84		};
85
86		timer@a0410600 {
87			compatible = "arm,cortex-a9-twd-timer";
88			reg = <0xa0410600 0x20>;
89			interrupts = <1 13 0x304>; /* IRQ level high per-CPU */
90
91			clocks = <&smp_twd_clk>;
92		};
93
94		rtc@80154000 {
95			compatible = "arm,rtc-pl031", "arm,primecell";
96			reg = <0x80154000 0x1000>;
97			interrupts = <0 18 IRQ_TYPE_LEVEL_HIGH>;
98
99			clocks = <&rtc_clk>;
100			clock-names = "apb_pclk";
101		};
102
103		gpio0: gpio@8012e000 {
104			compatible = "stericsson,db8500-gpio",
105				"st,nomadik-gpio";
106			reg =  <0x8012e000 0x80>;
107			interrupts = <0 119 IRQ_TYPE_LEVEL_HIGH>;
108			interrupt-controller;
109			#interrupt-cells = <2>;
110			st,supports-sleepmode;
111			gpio-controller;
112			#gpio-cells = <2>;
113			gpio-bank = <0>;
114
115			clocks = <&prcc_pclk 1 9>;
116		};
117
118		gpio1: gpio@8012e080 {
119			compatible = "stericsson,db8500-gpio",
120				"st,nomadik-gpio";
121			reg =  <0x8012e080 0x80>;
122			interrupts = <0 120 IRQ_TYPE_LEVEL_HIGH>;
123			interrupt-controller;
124			#interrupt-cells = <2>;
125			st,supports-sleepmode;
126			gpio-controller;
127			#gpio-cells = <2>;
128			gpio-bank = <1>;
129
130			clocks = <&prcc_pclk 1 9>;
131		};
132
133		gpio2: gpio@8000e000 {
134			compatible = "stericsson,db8500-gpio",
135				"st,nomadik-gpio";
136			reg =  <0x8000e000 0x80>;
137			interrupts = <0 121 IRQ_TYPE_LEVEL_HIGH>;
138			interrupt-controller;
139			#interrupt-cells = <2>;
140			st,supports-sleepmode;
141			gpio-controller;
142			#gpio-cells = <2>;
143			gpio-bank = <2>;
144
145			clocks = <&prcc_pclk 3 8>;
146		};
147
148		gpio3: gpio@8000e080 {
149			compatible = "stericsson,db8500-gpio",
150				"st,nomadik-gpio";
151			reg =  <0x8000e080 0x80>;
152			interrupts = <0 122 IRQ_TYPE_LEVEL_HIGH>;
153			interrupt-controller;
154			#interrupt-cells = <2>;
155			st,supports-sleepmode;
156			gpio-controller;
157			#gpio-cells = <2>;
158			gpio-bank = <3>;
159
160			clocks = <&prcc_pclk 3 8>;
161		};
162
163		gpio4: gpio@8000e100 {
164			compatible = "stericsson,db8500-gpio",
165				"st,nomadik-gpio";
166			reg =  <0x8000e100 0x80>;
167			interrupts = <0 123 IRQ_TYPE_LEVEL_HIGH>;
168			interrupt-controller;
169			#interrupt-cells = <2>;
170			st,supports-sleepmode;
171			gpio-controller;
172			#gpio-cells = <2>;
173			gpio-bank = <4>;
174
175			clocks = <&prcc_pclk 3 8>;
176		};
177
178		gpio5: gpio@8000e180 {
179			compatible = "stericsson,db8500-gpio",
180				"st,nomadik-gpio";
181			reg =  <0x8000e180 0x80>;
182			interrupts = <0 124 IRQ_TYPE_LEVEL_HIGH>;
183			interrupt-controller;
184			#interrupt-cells = <2>;
185			st,supports-sleepmode;
186			gpio-controller;
187			#gpio-cells = <2>;
188			gpio-bank = <5>;
189
190			clocks = <&prcc_pclk 3 8>;
191		};
192
193		gpio6: gpio@8011e000 {
194			compatible = "stericsson,db8500-gpio",
195				"st,nomadik-gpio";
196			reg =  <0x8011e000 0x80>;
197			interrupts = <0 125 IRQ_TYPE_LEVEL_HIGH>;
198			interrupt-controller;
199			#interrupt-cells = <2>;
200			st,supports-sleepmode;
201			gpio-controller;
202			#gpio-cells = <2>;
203			gpio-bank = <6>;
204
205			clocks = <&prcc_pclk 2 11>;
206		};
207
208		gpio7: gpio@8011e080 {
209			compatible = "stericsson,db8500-gpio",
210				"st,nomadik-gpio";
211			reg =  <0x8011e080 0x80>;
212			interrupts = <0 126 IRQ_TYPE_LEVEL_HIGH>;
213			interrupt-controller;
214			#interrupt-cells = <2>;
215			st,supports-sleepmode;
216			gpio-controller;
217			#gpio-cells = <2>;
218			gpio-bank = <7>;
219
220			clocks = <&prcc_pclk 2 11>;
221		};
222
223		gpio8: gpio@a03fe000 {
224			compatible = "stericsson,db8500-gpio",
225				"st,nomadik-gpio";
226			reg =  <0xa03fe000 0x80>;
227			interrupts = <0 127 IRQ_TYPE_LEVEL_HIGH>;
228			interrupt-controller;
229			#interrupt-cells = <2>;
230			st,supports-sleepmode;
231			gpio-controller;
232			#gpio-cells = <2>;
233			gpio-bank = <8>;
234
235			clocks = <&prcc_pclk 5 1>;
236		};
237
238		pinctrl {
239			compatible = "stericsson,db8500-pinctrl";
240			prcm = <&prcmu>;
241		};
242
243		usb_per5@a03e0000 {
244			compatible = "stericsson,db8500-musb";
245			reg = <0xa03e0000 0x10000>;
246			interrupts = <0 23 IRQ_TYPE_LEVEL_HIGH>;
247			interrupt-names = "mc";
248
249			dr_mode = "otg";
250
251			dmas = <&dma 38 0 0x2>, /* Logical - DevToMem */
252			       <&dma 38 0 0x0>, /* Logical - MemToDev */
253			       <&dma 37 0 0x2>, /* Logical - DevToMem */
254			       <&dma 37 0 0x0>, /* Logical - MemToDev */
255			       <&dma 36 0 0x2>, /* Logical - DevToMem */
256			       <&dma 36 0 0x0>, /* Logical - MemToDev */
257			       <&dma 19 0 0x2>, /* Logical - DevToMem */
258			       <&dma 19 0 0x0>, /* Logical - MemToDev */
259			       <&dma 18 0 0x2>, /* Logical - DevToMem */
260			       <&dma 18 0 0x0>, /* Logical - MemToDev */
261			       <&dma 17 0 0x2>, /* Logical - DevToMem */
262			       <&dma 17 0 0x0>, /* Logical - MemToDev */
263			       <&dma 16 0 0x2>, /* Logical - DevToMem */
264			       <&dma 16 0 0x0>, /* Logical - MemToDev */
265			       <&dma 39 0 0x2>, /* Logical - DevToMem */
266			       <&dma 39 0 0x0>; /* Logical - MemToDev */
267
268			dma-names = "iep_1_9",  "oep_1_9",
269				    "iep_2_10", "oep_2_10",
270				    "iep_3_11", "oep_3_11",
271				    "iep_4_12", "oep_4_12",
272				    "iep_5_13", "oep_5_13",
273				    "iep_6_14", "oep_6_14",
274				    "iep_7_15", "oep_7_15",
275				    "iep_8",    "oep_8";
276
277			clocks = <&prcc_pclk 5 0>;
278		};
279
280		dma: dma-controller@801C0000 {
281			compatible = "stericsson,db8500-dma40", "stericsson,dma40";
282			reg = <0x801C0000 0x1000 0x40010000 0x800>;
283			reg-names = "base", "lcpa";
284			interrupts = <0 25 IRQ_TYPE_LEVEL_HIGH>;
285
286			#dma-cells = <3>;
287			memcpy-channels = <56 57 58 59 60>;
288
289			clocks = <&prcmu_clk PRCMU_DMACLK>;
290		};
291
292		prcmu: prcmu@80157000 {
293			compatible = "stericsson,db8500-prcmu";
294			reg = <0x80157000 0x2000>, <0x801b0000 0x8000>, <0x801b8000 0x1000>;
295			reg-names = "prcmu", "prcmu-tcpm", "prcmu-tcdm";
296			interrupts = <0 47 IRQ_TYPE_LEVEL_HIGH>;
297			#address-cells = <1>;
298			#size-cells = <1>;
299			interrupt-controller;
300			#interrupt-cells = <2>;
301			ranges;
302
303			prcmu-timer-4@80157450 {
304				compatible = "stericsson,db8500-prcmu-timer-4";
305				reg = <0x80157450 0xC>;
306			};
307
308			cpufreq {
309				compatible = "stericsson,cpufreq-ux500";
310				clocks = <&prcmu_clk PRCMU_ARMSS>;
311				clock-names = "armss";
312				status = "disabled";
313			};
314
315			thermal@801573c0 {
316				compatible = "stericsson,db8500-thermal";
317				reg = <0x801573c0 0x40>;
318				interrupts = <21 IRQ_TYPE_LEVEL_HIGH>,
319					     <22 IRQ_TYPE_LEVEL_HIGH>;
320				interrupt-names = "IRQ_HOTMON_LOW", "IRQ_HOTMON_HIGH";
321				status = "disabled";
322			};
323
324			db8500-prcmu-regulators {
325				compatible = "stericsson,db8500-prcmu-regulator";
326
327				// DB8500_REGULATOR_VAPE
328				db8500_vape_reg: db8500_vape {
329					regulator-compatible = "db8500_vape";
330					regulator-always-on;
331				};
332
333				// DB8500_REGULATOR_VARM
334				db8500_varm_reg: db8500_varm {
335					regulator-compatible = "db8500_varm";
336				};
337
338				// DB8500_REGULATOR_VMODEM
339				db8500_vmodem_reg: db8500_vmodem {
340					regulator-compatible = "db8500_vmodem";
341				};
342
343				// DB8500_REGULATOR_VPLL
344				db8500_vpll_reg: db8500_vpll {
345					regulator-compatible = "db8500_vpll";
346				};
347
348				// DB8500_REGULATOR_VSMPS1
349				db8500_vsmps1_reg: db8500_vsmps1 {
350					regulator-compatible = "db8500_vsmps1";
351				};
352
353				// DB8500_REGULATOR_VSMPS2
354				db8500_vsmps2_reg: db8500_vsmps2 {
355					regulator-compatible = "db8500_vsmps2";
356				};
357
358				// DB8500_REGULATOR_VSMPS3
359				db8500_vsmps3_reg: db8500_vsmps3 {
360					regulator-compatible = "db8500_vsmps3";
361				};
362
363				// DB8500_REGULATOR_VRF1
364				db8500_vrf1_reg: db8500_vrf1 {
365					regulator-compatible = "db8500_vrf1";
366				};
367
368				// DB8500_REGULATOR_SWITCH_SVAMMDSP
369				db8500_sva_mmdsp_reg: db8500_sva_mmdsp {
370					regulator-compatible = "db8500_sva_mmdsp";
371				};
372
373				// DB8500_REGULATOR_SWITCH_SVAMMDSPRET
374				db8500_sva_mmdsp_ret_reg: db8500_sva_mmdsp_ret {
375					regulator-compatible = "db8500_sva_mmdsp_ret";
376				};
377
378				// DB8500_REGULATOR_SWITCH_SVAPIPE
379				db8500_sva_pipe_reg: db8500_sva_pipe {
380					regulator-compatible = "db8500_sva_pipe";
381				};
382
383				// DB8500_REGULATOR_SWITCH_SIAMMDSP
384				db8500_sia_mmdsp_reg: db8500_sia_mmdsp {
385					regulator-compatible = "db8500_sia_mmdsp";
386				};
387
388				// DB8500_REGULATOR_SWITCH_SIAMMDSPRET
389				db8500_sia_mmdsp_ret_reg: db8500_sia_mmdsp_ret {
390				};
391
392				// DB8500_REGULATOR_SWITCH_SIAPIPE
393				db8500_sia_pipe_reg: db8500_sia_pipe {
394					regulator-compatible = "db8500_sia_pipe";
395				};
396
397				// DB8500_REGULATOR_SWITCH_SGA
398				db8500_sga_reg: db8500_sga {
399					regulator-compatible = "db8500_sga";
400					vin-supply = <&db8500_vape_reg>;
401				};
402
403				// DB8500_REGULATOR_SWITCH_B2R2_MCDE
404				db8500_b2r2_mcde_reg: db8500_b2r2_mcde {
405					regulator-compatible = "db8500_b2r2_mcde";
406					vin-supply = <&db8500_vape_reg>;
407				};
408
409				// DB8500_REGULATOR_SWITCH_ESRAM12
410				db8500_esram12_reg: db8500_esram12 {
411					regulator-compatible = "db8500_esram12";
412				};
413
414				// DB8500_REGULATOR_SWITCH_ESRAM12RET
415				db8500_esram12_ret_reg: db8500_esram12_ret {
416					regulator-compatible = "db8500_esram12_ret";
417				};
418
419				// DB8500_REGULATOR_SWITCH_ESRAM34
420				db8500_esram34_reg: db8500_esram34 {
421					regulator-compatible = "db8500_esram34";
422				};
423
424				// DB8500_REGULATOR_SWITCH_ESRAM34RET
425				db8500_esram34_ret_reg: db8500_esram34_ret {
426					regulator-compatible = "db8500_esram34_ret";
427				};
428			};
429
430			ab8500 {
431				compatible = "stericsson,ab8500";
432				interrupt-parent = <&intc>;
433				interrupts = <0 40 IRQ_TYPE_LEVEL_HIGH>;
434				interrupt-controller;
435				#interrupt-cells = <2>;
436
437				ab8500_gpio: ab8500-gpio {
438					gpio-controller;
439					#gpio-cells = <2>;
440				};
441
442				ab8500-rtc {
443					compatible = "stericsson,ab8500-rtc";
444					interrupts = <17 IRQ_TYPE_LEVEL_HIGH
445						      18 IRQ_TYPE_LEVEL_HIGH>;
446					interrupt-names = "60S", "ALARM";
447				};
448
449				ab8500-gpadc {
450					compatible = "stericsson,ab8500-gpadc";
451					interrupts = <32 IRQ_TYPE_LEVEL_HIGH
452						      39 IRQ_TYPE_LEVEL_HIGH>;
453					interrupt-names = "HW_CONV_END", "SW_CONV_END";
454					vddadc-supply = <&ab8500_ldo_tvout_reg>;
455				};
456
457				ab8500_battery: ab8500_battery {
458					stericsson,battery-type = "LIPO";
459					thermistor-on-batctrl;
460				};
461
462				ab8500_fg {
463					compatible = "stericsson,ab8500-fg";
464					battery	   = <&ab8500_battery>;
465				};
466
467				ab8500_btemp {
468					compatible = "stericsson,ab8500-btemp";
469					battery	   = <&ab8500_battery>;
470				};
471
472				ab8500_charger {
473					compatible	= "stericsson,ab8500-charger";
474					battery		= <&ab8500_battery>;
475					vddadc-supply	= <&ab8500_ldo_tvout_reg>;
476				};
477
478				ab8500_chargalg {
479					compatible	= "stericsson,ab8500-chargalg";
480					battery		= <&ab8500_battery>;
481				};
482
483				ab8500_usb {
484					compatible = "stericsson,ab8500-usb";
485					interrupts = < 90 IRQ_TYPE_LEVEL_HIGH
486						       96 IRQ_TYPE_LEVEL_HIGH
487						       14 IRQ_TYPE_LEVEL_HIGH
488						       15 IRQ_TYPE_LEVEL_HIGH
489						       79 IRQ_TYPE_LEVEL_HIGH
490						       74 IRQ_TYPE_LEVEL_HIGH
491						       75 IRQ_TYPE_LEVEL_HIGH>;
492					interrupt-names = "ID_WAKEUP_R",
493							  "ID_WAKEUP_F",
494							  "VBUS_DET_F",
495							  "VBUS_DET_R",
496							  "USB_LINK_STATUS",
497							  "USB_ADP_PROBE_PLUG",
498							  "USB_ADP_PROBE_UNPLUG";
499					vddulpivio18-supply = <&ab8500_ldo_intcore_reg>;
500					v-ape-supply = <&db8500_vape_reg>;
501					musb_1v8-supply = <&db8500_vsmps2_reg>;
502				};
503
504				ab8500-ponkey {
505					compatible = "stericsson,ab8500-poweron-key";
506					interrupts = <6 IRQ_TYPE_LEVEL_HIGH
507						      7 IRQ_TYPE_LEVEL_HIGH>;
508					interrupt-names = "ONKEY_DBF", "ONKEY_DBR";
509				};
510
511				ab8500-sysctrl {
512					compatible = "stericsson,ab8500-sysctrl";
513				};
514
515				ab8500-pwm {
516					compatible = "stericsson,ab8500-pwm";
517				};
518
519				ab8500-debugfs {
520					compatible = "stericsson,ab8500-debug";
521				};
522
523				codec: ab8500-codec {
524					compatible = "stericsson,ab8500-codec";
525
526					V-AUD-supply = <&ab8500_ldo_audio_reg>;
527					V-AMIC1-supply = <&ab8500_ldo_anamic1_reg>;
528					V-AMIC2-supply = <&ab8500_ldo_anamic2_reg>;
529					V-DMIC-supply = <&ab8500_ldo_dmic_reg>;
530
531					stericsson,earpeice-cmv = <950>; /* Units in mV. */
532				};
533
534				ext_regulators: ab8500-ext-regulators {
535					compatible = "stericsson,ab8500-ext-regulator";
536
537					ab8500_ext1_reg: ab8500_ext1 {
538						regulator-compatible = "ab8500_ext1";
539						regulator-min-microvolt = <1800000>;
540						regulator-max-microvolt = <1800000>;
541						regulator-boot-on;
542						regulator-always-on;
543					};
544
545					ab8500_ext2_reg: ab8500_ext2 {
546						regulator-compatible = "ab8500_ext2";
547						regulator-min-microvolt = <1360000>;
548						regulator-max-microvolt = <1360000>;
549						regulator-boot-on;
550						regulator-always-on;
551					};
552
553					ab8500_ext3_reg: ab8500_ext3 {
554						regulator-compatible = "ab8500_ext3";
555						regulator-min-microvolt = <3400000>;
556						regulator-max-microvolt = <3400000>;
557						regulator-boot-on;
558					};
559				};
560
561				ab8500-regulators {
562					compatible = "stericsson,ab8500-regulator";
563					vin-supply = <&ab8500_ext3_reg>;
564
565					// supplies to the display/camera
566					ab8500_ldo_aux1_reg: ab8500_ldo_aux1 {
567						regulator-compatible = "ab8500_ldo_aux1";
568						regulator-min-microvolt = <2500000>;
569						regulator-max-microvolt = <2900000>;
570						regulator-boot-on;
571						/* BUG: If turned off MMC will be affected. */
572						regulator-always-on;
573					};
574
575					// supplies to the on-board eMMC
576					ab8500_ldo_aux2_reg: ab8500_ldo_aux2 {
577						regulator-compatible = "ab8500_ldo_aux2";
578						regulator-min-microvolt = <1100000>;
579						regulator-max-microvolt = <3300000>;
580					};
581
582					// supply for VAUX3; SDcard slots
583					ab8500_ldo_aux3_reg: ab8500_ldo_aux3 {
584						regulator-compatible = "ab8500_ldo_aux3";
585						regulator-min-microvolt = <1100000>;
586						regulator-max-microvolt = <3300000>;
587					};
588
589					// supply for v-intcore12; VINTCORE12 LDO
590					ab8500_ldo_intcore_reg: ab8500_ldo_intcore {
591						regulator-compatible = "ab8500_ldo_intcore";
592					};
593
594					// supply for tvout; gpadc; TVOUT LDO
595					ab8500_ldo_tvout_reg: ab8500_ldo_tvout {
596						regulator-compatible = "ab8500_ldo_tvout";
597					};
598
599					// supply for ab8500-usb; USB LDO
600					ab8500_ldo_usb_reg: ab8500_ldo_usb {
601						regulator-compatible = "ab8500_ldo_usb";
602					};
603
604					// supply for ab8500-vaudio; VAUDIO LDO
605					ab8500_ldo_audio_reg: ab8500_ldo_audio {
606						regulator-compatible = "ab8500_ldo_audio";
607					};
608
609					// supply for v-anamic1 VAMIC1 LDO
610					ab8500_ldo_anamic1_reg: ab8500_ldo_anamic1 {
611						regulator-compatible = "ab8500_ldo_anamic1";
612					};
613
614					// supply for v-amic2; VAMIC2 LDO; reuse constants for AMIC1
615					ab8500_ldo_anamic2_reg: ab8500_ldo_anamic2 {
616						regulator-compatible = "ab8500_ldo_anamic2";
617					};
618
619					// supply for v-dmic; VDMIC LDO
620					ab8500_ldo_dmic_reg: ab8500_ldo_dmic {
621						regulator-compatible = "ab8500_ldo_dmic";
622					};
623
624					// supply for U8500 CSI/DSI; VANA LDO
625					ab8500_ldo_ana_reg: ab8500_ldo_ana {
626						regulator-compatible = "ab8500_ldo_ana";
627					};
628				};
629			};
630		};
631
632		i2c@80004000 {
633			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
634			reg = <0x80004000 0x1000>;
635			interrupts = <0 21 IRQ_TYPE_LEVEL_HIGH>;
636
637			#address-cells = <1>;
638			#size-cells = <0>;
639			v-i2c-supply = <&db8500_vape_reg>;
640
641			clock-frequency = <400000>;
642			clocks = <&prcc_kclk 3 3>, <&prcc_pclk 3 3>;
643			clock-names = "i2cclk", "apb_pclk";
644			power-domains = <&pm_domains DOMAIN_VAPE>;
645		};
646
647		i2c@80122000 {
648			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
649			reg = <0x80122000 0x1000>;
650			interrupts = <0 22 IRQ_TYPE_LEVEL_HIGH>;
651
652			#address-cells = <1>;
653			#size-cells = <0>;
654			v-i2c-supply = <&db8500_vape_reg>;
655
656			clock-frequency = <400000>;
657
658			clocks = <&prcc_kclk 1 2>, <&prcc_pclk 1 2>;
659			clock-names = "i2cclk", "apb_pclk";
660			power-domains = <&pm_domains DOMAIN_VAPE>;
661		};
662
663		i2c@80128000 {
664			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
665			reg = <0x80128000 0x1000>;
666			interrupts = <0 55 IRQ_TYPE_LEVEL_HIGH>;
667
668			#address-cells = <1>;
669			#size-cells = <0>;
670			v-i2c-supply = <&db8500_vape_reg>;
671
672			clock-frequency = <400000>;
673
674			clocks = <&prcc_kclk 1 6>, <&prcc_pclk 1 6>;
675			clock-names = "i2cclk", "apb_pclk";
676			power-domains = <&pm_domains DOMAIN_VAPE>;
677		};
678
679		i2c@80110000 {
680			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
681			reg = <0x80110000 0x1000>;
682			interrupts = <0 12 IRQ_TYPE_LEVEL_HIGH>;
683
684			#address-cells = <1>;
685			#size-cells = <0>;
686			v-i2c-supply = <&db8500_vape_reg>;
687
688			clock-frequency = <400000>;
689
690			clocks = <&prcc_kclk 2 0>, <&prcc_pclk 2 0>;
691			clock-names = "i2cclk", "apb_pclk";
692			power-domains = <&pm_domains DOMAIN_VAPE>;
693		};
694
695		i2c@8012a000 {
696			compatible = "stericsson,db8500-i2c", "st,nomadik-i2c", "arm,primecell";
697			reg = <0x8012a000 0x1000>;
698			interrupts = <0 51 IRQ_TYPE_LEVEL_HIGH>;
699
700			#address-cells = <1>;
701			#size-cells = <0>;
702			v-i2c-supply = <&db8500_vape_reg>;
703
704			clock-frequency = <400000>;
705
706			clocks = <&prcc_kclk 1 9>, <&prcc_pclk 1 10>;
707			clock-names = "i2cclk", "apb_pclk";
708			power-domains = <&pm_domains DOMAIN_VAPE>;
709		};
710
711		ssp@80002000 {
712			compatible = "arm,pl022", "arm,primecell";
713			reg = <0x80002000 0x1000>;
714			interrupts = <0 14 IRQ_TYPE_LEVEL_HIGH>;
715			#address-cells = <1>;
716			#size-cells = <0>;
717			clocks = <&prcc_kclk 3 1>, <&prcc_pclk 3 1>;
718			clock-names = "SSPCLK", "apb_pclk";
719			dmas = <&dma 8 0 0x2>, /* Logical - DevToMem */
720			       <&dma 8 0 0x0>; /* Logical - MemToDev */
721			dma-names = "rx", "tx";
722			power-domains = <&pm_domains DOMAIN_VAPE>;
723		};
724
725		ssp@80003000 {
726			compatible = "arm,pl022", "arm,primecell";
727			reg = <0x80003000 0x1000>;
728			interrupts = <0 52 IRQ_TYPE_LEVEL_HIGH>;
729			#address-cells = <1>;
730			#size-cells = <0>;
731			clocks = <&prcc_kclk 3 2>, <&prcc_pclk 3 2>;
732			clock-names = "SSPCLK", "apb_pclk";
733			dmas = <&dma 9 0 0x2>, /* Logical - DevToMem */
734			       <&dma 9 0 0x0>; /* Logical - MemToDev */
735			dma-names = "rx", "tx";
736			power-domains = <&pm_domains DOMAIN_VAPE>;
737		};
738
739		spi@8011a000 {
740			compatible = "arm,pl022", "arm,primecell";
741			reg = <0x8011a000 0x1000>;
742			interrupts = <0 8 IRQ_TYPE_LEVEL_HIGH>;
743			#address-cells = <1>;
744			#size-cells = <0>;
745			/* Same clock wired to kernel and pclk */
746			clocks = <&prcc_pclk 2 8>, <&prcc_pclk 2 8>;
747			clock-names = "SSPCLK", "apb_pclk";
748			dmas = <&dma 0 0 0x2>, /* Logical - DevToMem */
749			       <&dma 0 0 0x0>; /* Logical - MemToDev */
750			dma-names = "rx", "tx";
751			power-domains = <&pm_domains DOMAIN_VAPE>;
752		};
753
754		spi@80112000 {
755			compatible = "arm,pl022", "arm,primecell";
756			reg = <0x80112000 0x1000>;
757			interrupts = <0 96 IRQ_TYPE_LEVEL_HIGH>;
758			#address-cells = <1>;
759			#size-cells = <0>;
760			/* Same clock wired to kernel and pclk */
761			clocks = <&prcc_pclk 2 2>, <&prcc_pclk 2 2>;
762			clock-names = "SSPCLK", "apb_pclk";
763			dmas = <&dma 35 0 0x2>, /* Logical - DevToMem */
764			       <&dma 35 0 0x0>; /* Logical - MemToDev */
765			dma-names = "rx", "tx";
766			power-domains = <&pm_domains DOMAIN_VAPE>;
767		};
768
769		spi@80111000 {
770			compatible = "arm,pl022", "arm,primecell";
771			reg = <0x80111000 0x1000>;
772			interrupts = <0 6 IRQ_TYPE_LEVEL_HIGH>;
773			#address-cells = <1>;
774			#size-cells = <0>;
775			/* Same clock wired to kernel and pclk */
776			clocks = <&prcc_pclk 2 1>, <&prcc_pclk 2 1>;
777			clock-names = "SSPCLK", "apb_pclk";
778			dmas = <&dma 33 0 0x2>, /* Logical - DevToMem */
779			       <&dma 33 0 0x0>; /* Logical - MemToDev */
780			dma-names = "rx", "tx";
781			power-domains = <&pm_domains DOMAIN_VAPE>;
782		};
783
784		spi@80129000 {
785			compatible = "arm,pl022", "arm,primecell";
786			reg = <0x80129000 0x1000>;
787			interrupts = <0 49 IRQ_TYPE_LEVEL_HIGH>;
788			#address-cells = <1>;
789			#size-cells = <0>;
790			/* Same clock wired to kernel and pclk */
791			clocks = <&prcc_pclk 1 7>, <&prcc_pclk 1 7>;
792			clock-names = "SSPCLK", "apb_pclk";
793			dmas = <&dma 40 0 0x2>, /* Logical - DevToMem */
794			       <&dma 40 0 0x0>; /* Logical - MemToDev */
795			dma-names = "rx", "tx";
796			power-domains = <&pm_domains DOMAIN_VAPE>;
797		};
798
799		uart@80120000 {
800			compatible = "arm,pl011", "arm,primecell";
801			reg = <0x80120000 0x1000>;
802			interrupts = <0 11 IRQ_TYPE_LEVEL_HIGH>;
803
804			dmas = <&dma 13 0 0x2>, /* Logical - DevToMem */
805			       <&dma 13 0 0x0>; /* Logical - MemToDev */
806			dma-names = "rx", "tx";
807
808			clocks = <&prcc_kclk 1 0>, <&prcc_pclk 1 0>;
809			clock-names = "uart", "apb_pclk";
810
811			status = "disabled";
812		};
813
814		uart@80121000 {
815			compatible = "arm,pl011", "arm,primecell";
816			reg = <0x80121000 0x1000>;
817			interrupts = <0 19 IRQ_TYPE_LEVEL_HIGH>;
818
819			dmas = <&dma 12 0 0x2>, /* Logical - DevToMem */
820			       <&dma 12 0 0x0>; /* Logical - MemToDev */
821			dma-names = "rx", "tx";
822
823			clocks = <&prcc_kclk 1 1>, <&prcc_pclk 1 1>;
824			clock-names = "uart", "apb_pclk";
825
826			status = "disabled";
827		};
828
829		uart@80007000 {
830			compatible = "arm,pl011", "arm,primecell";
831			reg = <0x80007000 0x1000>;
832			interrupts = <0 26 IRQ_TYPE_LEVEL_HIGH>;
833
834			dmas = <&dma 11 0 0x2>, /* Logical - DevToMem */
835			       <&dma 11 0 0x0>; /* Logical - MemToDev */
836			dma-names = "rx", "tx";
837
838			clocks = <&prcc_kclk 3 6>, <&prcc_pclk 3 6>;
839			clock-names = "uart", "apb_pclk";
840
841			status = "disabled";
842		};
843
844		sdi0_per1@80126000 {
845			compatible = "arm,pl18x", "arm,primecell";
846			reg = <0x80126000 0x1000>;
847			interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
848
849			dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */
850			       <&dma 29 0 0x0>; /* Logical - MemToDev */
851			dma-names = "rx", "tx";
852
853			clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>;
854			clock-names = "sdi", "apb_pclk";
855			power-domains = <&pm_domains DOMAIN_VAPE>;
856
857			status = "disabled";
858		};
859
860		sdi1_per2@80118000 {
861			compatible = "arm,pl18x", "arm,primecell";
862			reg = <0x80118000 0x1000>;
863			interrupts = <0 50 IRQ_TYPE_LEVEL_HIGH>;
864
865			dmas = <&dma 32 0 0x2>, /* Logical - DevToMem */
866			       <&dma 32 0 0x0>; /* Logical - MemToDev */
867			dma-names = "rx", "tx";
868
869			clocks = <&prcc_kclk 2 4>, <&prcc_pclk 2 6>;
870			clock-names = "sdi", "apb_pclk";
871			power-domains = <&pm_domains DOMAIN_VAPE>;
872
873			status = "disabled";
874		};
875
876		sdi2_per3@80005000 {
877			compatible = "arm,pl18x", "arm,primecell";
878			reg = <0x80005000 0x1000>;
879			interrupts = <0 41 IRQ_TYPE_LEVEL_HIGH>;
880
881			dmas = <&dma 28 0 0x2>, /* Logical - DevToMem */
882			       <&dma 28 0 0x0>; /* Logical - MemToDev */
883			dma-names = "rx", "tx";
884
885			clocks = <&prcc_kclk 3 4>, <&prcc_pclk 3 4>;
886			clock-names = "sdi", "apb_pclk";
887			power-domains = <&pm_domains DOMAIN_VAPE>;
888
889			status = "disabled";
890		};
891
892		sdi3_per2@80119000 {
893			compatible = "arm,pl18x", "arm,primecell";
894			reg = <0x80119000 0x1000>;
895			interrupts = <0 59 IRQ_TYPE_LEVEL_HIGH>;
896
897			dmas = <&dma 41 0 0x2>, /* Logical - DevToMem */
898			       <&dma 41 0 0x0>; /* Logical - MemToDev */
899			dma-names = "rx", "tx";
900
901			clocks = <&prcc_kclk 2 5>, <&prcc_pclk 2 7>;
902			clock-names = "sdi", "apb_pclk";
903			power-domains = <&pm_domains DOMAIN_VAPE>;
904
905			status = "disabled";
906		};
907
908		sdi4_per2@80114000 {
909			compatible = "arm,pl18x", "arm,primecell";
910			reg = <0x80114000 0x1000>;
911			interrupts = <0 99 IRQ_TYPE_LEVEL_HIGH>;
912
913			dmas = <&dma 42 0 0x2>, /* Logical - DevToMem */
914			       <&dma 42 0 0x0>; /* Logical - MemToDev */
915			dma-names = "rx", "tx";
916
917			clocks = <&prcc_kclk 2 2>, <&prcc_pclk 2 4>;
918			clock-names = "sdi", "apb_pclk";
919			power-domains = <&pm_domains DOMAIN_VAPE>;
920
921			status = "disabled";
922		};
923
924		sdi5_per3@80008000 {
925			compatible = "arm,pl18x", "arm,primecell";
926			reg = <0x80008000 0x1000>;
927			interrupts = <0 100 IRQ_TYPE_LEVEL_HIGH>;
928
929			dmas = <&dma 43 0 0x2>, /* Logical - DevToMem */
930			       <&dma 43 0 0x0>; /* Logical - MemToDev */
931			dma-names = "rx", "tx";
932
933			clocks = <&prcc_kclk 3 7>, <&prcc_pclk 3 7>;
934			clock-names = "sdi", "apb_pclk";
935			power-domains = <&pm_domains DOMAIN_VAPE>;
936
937			status = "disabled";
938		};
939
940		msp0: msp@80123000 {
941			compatible = "stericsson,ux500-msp-i2s";
942			reg = <0x80123000 0x1000>;
943			interrupts = <0 31 IRQ_TYPE_LEVEL_HIGH>;
944			v-ape-supply = <&db8500_vape_reg>;
945
946			dmas = <&dma 31 0 0x12>, /* Logical - DevToMem - HighPrio */
947			       <&dma 31 0 0x10>; /* Logical - MemToDev - HighPrio */
948			dma-names = "rx", "tx";
949
950			clocks = <&prcc_kclk 1 3>, <&prcc_pclk 1 3>;
951			clock-names = "msp", "apb_pclk";
952
953			status = "disabled";
954		};
955
956		msp1: msp@80124000 {
957			compatible = "stericsson,ux500-msp-i2s";
958			reg = <0x80124000 0x1000>;
959			interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
960			v-ape-supply = <&db8500_vape_reg>;
961
962			/* This DMA channel only exist on DB8500 v1 */
963			dmas = <&dma 30 0 0x10>; /* Logical - MemToDev - HighPrio */
964			dma-names = "tx";
965
966			clocks = <&prcc_kclk 1 4>, <&prcc_pclk 1 4>;
967			clock-names = "msp", "apb_pclk";
968
969			status = "disabled";
970		};
971
972		// HDMI sound
973		msp2: msp@80117000 {
974			compatible = "stericsson,ux500-msp-i2s";
975			reg = <0x80117000 0x1000>;
976			interrupts = <0 98 IRQ_TYPE_LEVEL_HIGH>;
977			v-ape-supply = <&db8500_vape_reg>;
978
979			dmas = <&dma 14 0 0x12>, /* Logical  - DevToMem - HighPrio */
980			       <&dma 14 1 0x19>; /* Physical Chan 1 - MemToDev
981                                                    HighPrio - Fixed */
982			dma-names = "rx", "tx";
983
984			clocks = <&prcc_kclk 2 3>, <&prcc_pclk 2 5>;
985			clock-names = "msp", "apb_pclk";
986
987			status = "disabled";
988		};
989
990		msp3: msp@80125000 {
991			compatible = "stericsson,ux500-msp-i2s";
992			reg = <0x80125000 0x1000>;
993			interrupts = <0 62 IRQ_TYPE_LEVEL_HIGH>;
994			v-ape-supply = <&db8500_vape_reg>;
995
996			/* This DMA channel only exist on DB8500 v2 */
997			dmas = <&dma 30 0 0x12>; /* Logical - DevToMem - HighPrio */
998			dma-names = "rx";
999
1000			clocks = <&prcc_kclk 1 10>, <&prcc_pclk 1 11>;
1001			clock-names = "msp", "apb_pclk";
1002
1003			status = "disabled";
1004		};
1005
1006		external-bus@50000000 {
1007			compatible = "simple-bus";
1008			reg = <0x50000000 0x4000000>;
1009			#address-cells = <1>;
1010			#size-cells = <1>;
1011			ranges = <0 0x50000000 0x4000000>;
1012			status = "disabled";
1013		};
1014
1015		cpufreq-cooling {
1016			compatible = "stericsson,db8500-cpufreq-cooling";
1017			status = "disabled";
1018		};
1019
1020		vmmci: regulator-gpio {
1021			compatible = "regulator-gpio";
1022
1023			regulator-min-microvolt = <1800000>;
1024			regulator-max-microvolt = <2900000>;
1025			regulator-name = "mmci-reg";
1026			regulator-type = "voltage";
1027
1028			startup-delay-us = <100>;
1029			enable-active-high;
1030
1031			states = <1800000 0x1
1032				  2900000 0x0>;
1033
1034			status = "disabled";
1035		};
1036
1037		mcde@a0350000 {
1038			compatible = "stericsson,mcde";
1039			reg = <0xa0350000 0x1000>, /* MCDE */
1040			      <0xa0351000 0x1000>, /* DSI link 1 */
1041			      <0xa0352000 0x1000>, /* DSI link 2 */
1042			      <0xa0353000 0x1000>; /* DSI link 3 */
1043			interrupts = <0 48 IRQ_TYPE_LEVEL_HIGH>;
1044			clocks = <&prcmu_clk PRCMU_MCDECLK>, /* Main MCDE clock */
1045				 <&prcmu_clk PRCMU_LCDCLK>, /* LCD clock */
1046				 <&prcmu_clk PRCMU_PLLDSI>, /* HDMI clock */
1047				 <&prcmu_clk PRCMU_DSI0CLK>, /* DSI 0 */
1048				 <&prcmu_clk PRCMU_DSI1CLK>, /* DSI 1 */
1049				 <&prcmu_clk PRCMU_DSI0ESCCLK>, /* TVout clock 0 */
1050				 <&prcmu_clk PRCMU_DSI1ESCCLK>, /* TVout clock 1 */
1051				 <&prcmu_clk PRCMU_DSI2ESCCLK>; /* TVout clock 2 */
1052		};
1053
1054		cryp@a03cb000 {
1055			compatible = "stericsson,ux500-cryp";
1056			reg = <0xa03cb000 0x1000>;
1057			interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
1058
1059			v-ape-supply = <&db8500_vape_reg>;
1060			clocks = <&prcc_pclk 6 1>;
1061		};
1062
1063		hash@a03c2000 {
1064			compatible = "stericsson,ux500-hash";
1065			reg = <0xa03c2000 0x1000>;
1066
1067			v-ape-supply = <&db8500_vape_reg>;
1068			clocks = <&prcc_pclk 6 2>;
1069		};
1070	};
1071};
1072