spear310.dtsi revision 284090 
1/*
2 * DTS file for SPEAr310 SoC
3 *
4 * Copyright 2012 Viresh Kumar <viresh.linux@gmail.com>
5 *
6 * The code contained herein is licensed under the GNU General Public
7 * License. You may obtain a copy of the GNU General Public License
8 * Version 2 or later at the following locations:
9 *
10 * http://www.opensource.org/licenses/gpl-license.html
11 * http://www.gnu.org/copyleft/gpl.html
12 */
13
14/include/ "spear3xx.dtsi"
15
16/ {
17	ahb {
18		#address-cells = <1>;
19		#size-cells = <1>;
20		compatible = "simple-bus";
21		ranges = <0x40000000 0x40000000 0x10000000
22			  0xb0000000 0xb0000000 0x10000000
23			  0xd0000000 0xd0000000 0x30000000>;
24
25		pinmux: pinmux@b4000000 {
26			compatible = "st,spear310-pinmux";
27			reg = <0xb4000000 0x1000>;
28			#gpio-range-cells = <3>;
29		};
30
31		fsmc: flash@44000000 {
32			compatible = "st,spear600-fsmc-nand";
33			#address-cells = <1>;
34			#size-cells = <1>;
35			reg = <0x44000000 0x1000	/* FSMC Register */
36			       0x40000000 0x0010	/* NAND Base DATA */
37			       0x40020000 0x0010	/* NAND Base ADDR */
38			       0x40010000 0x0010>;	/* NAND Base CMD */
39			reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
40			status = "disabled";
41		};
42
43		shirq: interrupt-controller@0xb4000000 {
44			compatible = "st,spear310-shirq";
45			reg = <0xb4000000 0x1000>;
46			interrupts = <28 29 30 1>;
47			#interrupt-cells = <1>;
48			interrupt-controller;
49		};
50
51		apb {
52			#address-cells = <1>;
53			#size-cells = <1>;
54			compatible = "simple-bus";
55			ranges = <0xb0000000 0xb0000000 0x10000000
56				  0xd0000000 0xd0000000 0x30000000>;
57
58			serial@b2000000 {
59				compatible = "arm,pl011", "arm,primecell";
60				reg = <0xb2000000 0x1000>;
61				interrupts = <8>;
62				interrupt-parent = <&shirq>;
63				status = "disabled";
64			};
65
66			serial@b2080000 {
67				compatible = "arm,pl011", "arm,primecell";
68				reg = <0xb2080000 0x1000>;
69				interrupts = <9>;
70				interrupt-parent = <&shirq>;
71				status = "disabled";
72			};
73
74			serial@b2100000 {
75				compatible = "arm,pl011", "arm,primecell";
76				reg = <0xb2100000 0x1000>;
77				interrupts = <10>;
78				interrupt-parent = <&shirq>;
79				status = "disabled";
80			};
81
82			serial@b2180000 {
83				compatible = "arm,pl011", "arm,primecell";
84				reg = <0xb2180000 0x1000>;
85				interrupts = <11>;
86				interrupt-parent = <&shirq>;
87				status = "disabled";
88			};
89
90			serial@b2200000 {
91				compatible = "arm,pl011", "arm,primecell";
92				reg = <0xb2200000 0x1000>;
93				interrupts = <12>;
94				interrupt-parent = <&shirq>;
95				status = "disabled";
96			};
97
98			gpiopinctrl: gpio@b4000000 {
99				compatible = "st,spear-plgpio";
100				reg = <0xb4000000 0x1000>;
101				#interrupt-cells = <1>;
102				interrupt-controller;
103				gpio-controller;
104				#gpio-cells = <2>;
105				gpio-ranges = <&pinmux 0 0 102>;
106				status = "disabled";
107
108				st-plgpio,ngpio = <102>;
109				st-plgpio,enb-reg = <0x10>;
110				st-plgpio,wdata-reg = <0x20>;
111				st-plgpio,dir-reg = <0x30>;
112				st-plgpio,ie-reg = <0x50>;
113				st-plgpio,rdata-reg = <0x40>;
114				st-plgpio,mis-reg = <0x60>;
115			};
116		};
117	};
118};
119