omap4.dtsi revision 284090
1131476Spjd/* 2142727Spjd * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ 3131476Spjd * 4131476Spjd * This program is free software; you can redistribute it and/or modify 5131476Spjd * it under the terms of the GNU General Public License version 2 as 6131476Spjd * published by the Free Software Foundation. 7131476Spjd */ 8131476Spjd 9131476Spjd#include <dt-bindings/gpio/gpio.h> 10131476Spjd#include <dt-bindings/interrupt-controller/arm-gic.h> 11131476Spjd#include <dt-bindings/pinctrl/omap.h> 12131476Spjd 13155175Spjd#include "skeleton.dtsi" 14131476Spjd 15131476Spjd/ { 16131476Spjd compatible = "ti,omap4430", "ti,omap4"; 17131476Spjd interrupt-parent = <&gic>; 18131476Spjd 19131476Spjd aliases { 20131476Spjd i2c0 = &i2c1; 21131476Spjd i2c1 = &i2c2; 22131476Spjd i2c2 = &i2c3; 23131476Spjd i2c3 = &i2c4; 24131476Spjd serial0 = &uart1; 25131476Spjd serial1 = &uart2; 26131476Spjd serial2 = &uart3; 27131476Spjd serial3 = &uart4; 28131476Spjd }; 29131476Spjd 30131476Spjd cpus { 31131476Spjd #address-cells = <1>; 32131476Spjd #size-cells = <0>; 33131476Spjd 34131476Spjd cpu@0 { 35131476Spjd compatible = "arm,cortex-a9"; 36131476Spjd device_type = "cpu"; 37131476Spjd next-level-cache = <&L2>; 38131476Spjd reg = <0x0>; 39131476Spjd 40131476Spjd clocks = <&dpll_mpu_ck>; 41131476Spjd clock-names = "cpu"; 42131476Spjd 43179550Smarcel clock-latency = <300000>; /* From omap-cpufreq driver */ 44176852Sdelphij }; 45176852Sdelphij cpu@1 { 46176852Sdelphij compatible = "arm,cortex-a9"; 47176852Sdelphij device_type = "cpu"; 48131476Spjd next-level-cache = <&L2>; 49176852Sdelphij reg = <0x1>; 50176852Sdelphij }; 51131476Spjd }; 52131476Spjd 53132344Spjd gic: interrupt-controller@48241000 { 54132344Spjd compatible = "arm,cortex-a9-gic"; 55131476Spjd interrupt-controller; 56131476Spjd #interrupt-cells = <3>; 57176852Sdelphij reg = <0x48241000 0x1000>, 58212554Spjd <0x48240100 0x0100>; 59143586Spjd }; 60143586Spjd 61143586Spjd L2: l2-cache-controller@48242000 { 62212554Spjd compatible = "arm,pl310-cache"; 63143586Spjd reg = <0x48242000 0x1000>; 64131476Spjd cache-unified; 65131476Spjd cache-level = <2>; 66162868Spjd }; 67131476Spjd 68143586Spjd local-timer@48240600 { 69212554Spjd compatible = "arm,cortex-a9-twd-timer"; 70131476Spjd clocks = <&mpu_periphclk>; 71212554Spjd reg = <0x48240600 0x20>; 72143586Spjd interrupts = <GIC_PPI 13 (GIC_CPU_MASK_RAW(3) | IRQ_TYPE_LEVEL_HIGH)>; 73143586Spjd }; 74143586Spjd 75212554Spjd /* 76143586Spjd * The soc node represents the soc top level view. It is used for IPs 77131649Spjd * that are not memory mapped in the MPU view or for the MPU itself. 78131649Spjd */ 79162868Spjd soc { 80131649Spjd compatible = "ti,omap-infra"; 81143586Spjd mpu { 82212554Spjd compatible = "ti,omap4-mpu"; 83131649Spjd ti,hwmods = "mpu"; 84131476Spjd sram = <&ocmcram>; 85131476Spjd }; 86131476Spjd 87131476Spjd dsp { 88131476Spjd compatible = "ti,omap3-c64"; 89131476Spjd ti,hwmods = "dsp"; 90131476Spjd }; 91131476Spjd 92131476Spjd iva { 93131476Spjd compatible = "ti,ivahd"; 94131476Spjd ti,hwmods = "iva"; 95131476Spjd }; 96131476Spjd }; 97153190Spjd 98131476Spjd /* 99131476Spjd * XXX: Use a flat representation of the OMAP4 interconnect. 100131476Spjd * The real OMAP interconnect network is quite complex. 101131476Spjd * Since it will not bring real advantage to represent that in DT for 102131476Spjd * the moment, just use a fake OCP bus entry to represent the whole bus 103131476Spjd * hierarchy. 104131476Spjd */ 105131476Spjd ocp { 106132344Spjd compatible = "ti,omap4-l3-noc", "simple-bus"; 107132344Spjd #address-cells = <1>; 108131476Spjd #size-cells = <1>; 109131476Spjd ranges; 110131476Spjd ti,hwmods = "l3_main_1", "l3_main_2", "l3_main_3"; 111131476Spjd reg = <0x44000000 0x1000>, 112131476Spjd <0x44800000 0x2000>, 113131476Spjd <0x45000000 0x1000>; 114131476Spjd interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>, 115131476Spjd <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 116131476Spjd 117131476Spjd cm1: cm1@4a004000 { 118153190Spjd compatible = "ti,omap4-cm1"; 119131476Spjd reg = <0x4a004000 0x2000>; 120330737Sasomers 121153190Spjd cm1_clocks: clocks { 122153190Spjd #address-cells = <1>; 123131476Spjd #size-cells = <0>; 124131476Spjd }; 125131476Spjd 126131476Spjd cm1_clockdomains: clockdomains { 127131476Spjd }; 128131476Spjd }; 129131476Spjd 130153190Spjd prm: prm@4a306000 { 131131476Spjd compatible = "ti,omap4-prm"; 132131476Spjd reg = <0x4a306000 0x3000>; 133131476Spjd interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 134131476Spjd 135131476Spjd prm_clocks: clocks { 136131476Spjd #address-cells = <1>; 137131476Spjd #size-cells = <0>; 138131476Spjd }; 139131476Spjd 140153190Spjd prm_clockdomains: clockdomains { 141330737Sasomers }; 142131476Spjd }; 143142727Spjd 144142727Spjd cm2: cm2@4a008000 { 145142727Spjd compatible = "ti,omap4-cm2"; 146142727Spjd reg = <0x4a008000 0x3000>; 147142727Spjd 148142727Spjd cm2_clocks: clocks { 149131476Spjd #address-cells = <1>; 150131476Spjd #size-cells = <0>; 151131476Spjd }; 152131476Spjd 153131476Spjd cm2_clockdomains: clockdomains { 154131476Spjd }; 155131476Spjd }; 156131476Spjd 157131476Spjd scrm: scrm@4a30a000 { 158131476Spjd compatible = "ti,omap4-scrm"; 159131476Spjd reg = <0x4a30a000 0x2000>; 160131476Spjd 161131476Spjd scrm_clocks: clocks { 162131476Spjd #address-cells = <1>; 163131476Spjd #size-cells = <0>; 164131476Spjd }; 165131476Spjd 166131476Spjd scrm_clockdomains: clockdomains { 167131476Spjd }; 168153190Spjd }; 169131476Spjd 170153190Spjd counter32k: counter@4a304000 { 171153190Spjd compatible = "ti,omap-counter32k"; 172131476Spjd reg = <0x4a304000 0x20>; 173131476Spjd ti,hwmods = "counter_32k"; 174131476Spjd }; 175131476Spjd 176153190Spjd omap4_pmx_core: pinmux@4a100040 { 177153190Spjd compatible = "ti,omap4-padconf", "pinctrl-single"; 178131476Spjd reg = <0x4a100040 0x0196>; 179131476Spjd #address-cells = <1>; 180131476Spjd #size-cells = <0>; 181131476Spjd #interrupt-cells = <1>; 182131476Spjd interrupt-controller; 183131476Spjd pinctrl-single,register-width = <16>; 184131476Spjd pinctrl-single,function-mask = <0x7fff>; 185131476Spjd }; 186155175Spjd omap4_pmx_wkup: pinmux@4a31e040 { 187131476Spjd compatible = "ti,omap4-padconf", "pinctrl-single"; 188131476Spjd reg = <0x4a31e040 0x0038>; 189132344Spjd #address-cells = <1>; 190155175Spjd #size-cells = <0>; 191132344Spjd #interrupt-cells = <1>; 192132344Spjd interrupt-controller; 193132344Spjd pinctrl-single,register-width = <16>; 194155175Spjd pinctrl-single,function-mask = <0x7fff>; 195132344Spjd }; 196132344Spjd 197132344Spjd omap4_padconf_global: tisyscon@4a1005a0 { 198132344Spjd compatible = "syscon"; 199132344Spjd reg = <0x4a1005a0 0x170>; 200132344Spjd }; 201132344Spjd 202132344Spjd pbias_regulator: pbias_regulator { 203132344Spjd compatible = "ti,pbias-omap"; 204153190Spjd reg = <0x60 0x4>; 205132344Spjd syscon = <&omap4_padconf_global>; 206153190Spjd pbias_mmc_reg: pbias_mmc_omap4 { 207153190Spjd regulator-name = "pbias_mmc_omap4"; 208132344Spjd regulator-min-microvolt = <1800000>; 209132344Spjd regulator-max-microvolt = <3000000>; 210132344Spjd }; 211132344Spjd }; 212153190Spjd 213153190Spjd ocmcram: ocmcram@40304000 { 214132344Spjd compatible = "mmio-sram"; 215132344Spjd reg = <0x40304000 0xa000>; /* 40k */ 216132344Spjd }; 217132344Spjd 218132344Spjd sdma: dma-controller@4a056000 { 219132344Spjd compatible = "ti,omap4430-sdma"; 220132344Spjd reg = <0x4a056000 0x1000>; 221132344Spjd interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>, 222132344Spjd <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, 223132344Spjd <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, 224132344Spjd <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>; 225132344Spjd #dma-cells = <1>; 226132344Spjd #dma-channels = <32>; 227132344Spjd #dma-requests = <127>; 228 }; 229 230 gpio1: gpio@4a310000 { 231 compatible = "ti,omap4-gpio"; 232 reg = <0x4a310000 0x200>; 233 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>; 234 ti,hwmods = "gpio1"; 235 ti,gpio-always-on; 236 gpio-controller; 237 #gpio-cells = <2>; 238 interrupt-controller; 239 #interrupt-cells = <2>; 240 }; 241 242 gpio2: gpio@48055000 { 243 compatible = "ti,omap4-gpio"; 244 reg = <0x48055000 0x200>; 245 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>; 246 ti,hwmods = "gpio2"; 247 gpio-controller; 248 #gpio-cells = <2>; 249 interrupt-controller; 250 #interrupt-cells = <2>; 251 }; 252 253 gpio3: gpio@48057000 { 254 compatible = "ti,omap4-gpio"; 255 reg = <0x48057000 0x200>; 256 interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>; 257 ti,hwmods = "gpio3"; 258 gpio-controller; 259 #gpio-cells = <2>; 260 interrupt-controller; 261 #interrupt-cells = <2>; 262 }; 263 264 gpio4: gpio@48059000 { 265 compatible = "ti,omap4-gpio"; 266 reg = <0x48059000 0x200>; 267 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; 268 ti,hwmods = "gpio4"; 269 gpio-controller; 270 #gpio-cells = <2>; 271 interrupt-controller; 272 #interrupt-cells = <2>; 273 }; 274 275 gpio5: gpio@4805b000 { 276 compatible = "ti,omap4-gpio"; 277 reg = <0x4805b000 0x200>; 278 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>; 279 ti,hwmods = "gpio5"; 280 gpio-controller; 281 #gpio-cells = <2>; 282 interrupt-controller; 283 #interrupt-cells = <2>; 284 }; 285 286 gpio6: gpio@4805d000 { 287 compatible = "ti,omap4-gpio"; 288 reg = <0x4805d000 0x200>; 289 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 290 ti,hwmods = "gpio6"; 291 gpio-controller; 292 #gpio-cells = <2>; 293 interrupt-controller; 294 #interrupt-cells = <2>; 295 }; 296 297 gpmc: gpmc@50000000 { 298 compatible = "ti,omap4430-gpmc"; 299 reg = <0x50000000 0x1000>; 300 #address-cells = <2>; 301 #size-cells = <1>; 302 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 303 gpmc,num-cs = <8>; 304 gpmc,num-waitpins = <4>; 305 ti,hwmods = "gpmc"; 306 ti,no-idle-on-init; 307 clocks = <&l3_div_ck>; 308 clock-names = "fck"; 309 }; 310 311 uart1: serial@4806a000 { 312 compatible = "ti,omap4-uart"; 313 reg = <0x4806a000 0x100>; 314 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 315 ti,hwmods = "uart1"; 316 clock-frequency = <48000000>; 317 }; 318 319 uart2: serial@4806c000 { 320 compatible = "ti,omap4-uart"; 321 reg = <0x4806c000 0x100>; 322 interrupts-extended = <&gic GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 323 ti,hwmods = "uart2"; 324 clock-frequency = <48000000>; 325 }; 326 327 uart3: serial@48020000 { 328 compatible = "ti,omap4-uart"; 329 reg = <0x48020000 0x100>; 330 interrupts-extended = <&gic GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 331 ti,hwmods = "uart3"; 332 clock-frequency = <48000000>; 333 }; 334 335 uart4: serial@4806e000 { 336 compatible = "ti,omap4-uart"; 337 reg = <0x4806e000 0x100>; 338 interrupts-extended = <&gic GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>; 339 ti,hwmods = "uart4"; 340 clock-frequency = <48000000>; 341 }; 342 343 hwspinlock: spinlock@4a0f6000 { 344 compatible = "ti,omap4-hwspinlock"; 345 reg = <0x4a0f6000 0x1000>; 346 ti,hwmods = "spinlock"; 347 #hwlock-cells = <1>; 348 }; 349 350 i2c1: i2c@48070000 { 351 compatible = "ti,omap4-i2c"; 352 reg = <0x48070000 0x100>; 353 interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 354 #address-cells = <1>; 355 #size-cells = <0>; 356 ti,hwmods = "i2c1"; 357 }; 358 359 i2c2: i2c@48072000 { 360 compatible = "ti,omap4-i2c"; 361 reg = <0x48072000 0x100>; 362 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 363 #address-cells = <1>; 364 #size-cells = <0>; 365 ti,hwmods = "i2c2"; 366 }; 367 368 i2c3: i2c@48060000 { 369 compatible = "ti,omap4-i2c"; 370 reg = <0x48060000 0x100>; 371 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 372 #address-cells = <1>; 373 #size-cells = <0>; 374 ti,hwmods = "i2c3"; 375 }; 376 377 i2c4: i2c@48350000 { 378 compatible = "ti,omap4-i2c"; 379 reg = <0x48350000 0x100>; 380 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 381 #address-cells = <1>; 382 #size-cells = <0>; 383 ti,hwmods = "i2c4"; 384 }; 385 386 mcspi1: spi@48098000 { 387 compatible = "ti,omap4-mcspi"; 388 reg = <0x48098000 0x200>; 389 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 390 #address-cells = <1>; 391 #size-cells = <0>; 392 ti,hwmods = "mcspi1"; 393 ti,spi-num-cs = <4>; 394 dmas = <&sdma 35>, 395 <&sdma 36>, 396 <&sdma 37>, 397 <&sdma 38>, 398 <&sdma 39>, 399 <&sdma 40>, 400 <&sdma 41>, 401 <&sdma 42>; 402 dma-names = "tx0", "rx0", "tx1", "rx1", 403 "tx2", "rx2", "tx3", "rx3"; 404 }; 405 406 mcspi2: spi@4809a000 { 407 compatible = "ti,omap4-mcspi"; 408 reg = <0x4809a000 0x200>; 409 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 410 #address-cells = <1>; 411 #size-cells = <0>; 412 ti,hwmods = "mcspi2"; 413 ti,spi-num-cs = <2>; 414 dmas = <&sdma 43>, 415 <&sdma 44>, 416 <&sdma 45>, 417 <&sdma 46>; 418 dma-names = "tx0", "rx0", "tx1", "rx1"; 419 }; 420 421 mcspi3: spi@480b8000 { 422 compatible = "ti,omap4-mcspi"; 423 reg = <0x480b8000 0x200>; 424 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 425 #address-cells = <1>; 426 #size-cells = <0>; 427 ti,hwmods = "mcspi3"; 428 ti,spi-num-cs = <2>; 429 dmas = <&sdma 15>, <&sdma 16>; 430 dma-names = "tx0", "rx0"; 431 }; 432 433 mcspi4: spi@480ba000 { 434 compatible = "ti,omap4-mcspi"; 435 reg = <0x480ba000 0x200>; 436 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>; 437 #address-cells = <1>; 438 #size-cells = <0>; 439 ti,hwmods = "mcspi4"; 440 ti,spi-num-cs = <1>; 441 dmas = <&sdma 70>, <&sdma 71>; 442 dma-names = "tx0", "rx0"; 443 }; 444 445 mmc1: mmc@4809c000 { 446 compatible = "ti,omap4-hsmmc"; 447 reg = <0x4809c000 0x400>; 448 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 449 ti,hwmods = "mmc1"; 450 ti,dual-volt; 451 ti,needs-special-reset; 452 dmas = <&sdma 61>, <&sdma 62>; 453 dma-names = "tx", "rx"; 454 pbias-supply = <&pbias_mmc_reg>; 455 }; 456 457 mmc2: mmc@480b4000 { 458 compatible = "ti,omap4-hsmmc"; 459 reg = <0x480b4000 0x400>; 460 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 461 ti,hwmods = "mmc2"; 462 ti,needs-special-reset; 463 dmas = <&sdma 47>, <&sdma 48>; 464 dma-names = "tx", "rx"; 465 }; 466 467 mmc3: mmc@480ad000 { 468 compatible = "ti,omap4-hsmmc"; 469 reg = <0x480ad000 0x400>; 470 interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; 471 ti,hwmods = "mmc3"; 472 ti,needs-special-reset; 473 dmas = <&sdma 77>, <&sdma 78>; 474 dma-names = "tx", "rx"; 475 }; 476 477 mmc4: mmc@480d1000 { 478 compatible = "ti,omap4-hsmmc"; 479 reg = <0x480d1000 0x400>; 480 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; 481 ti,hwmods = "mmc4"; 482 ti,needs-special-reset; 483 dmas = <&sdma 57>, <&sdma 58>; 484 dma-names = "tx", "rx"; 485 }; 486 487 mmc5: mmc@480d5000 { 488 compatible = "ti,omap4-hsmmc"; 489 reg = <0x480d5000 0x400>; 490 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 491 ti,hwmods = "mmc5"; 492 ti,needs-special-reset; 493 dmas = <&sdma 59>, <&sdma 60>; 494 dma-names = "tx", "rx"; 495 }; 496 497 mmu_dsp: mmu@4a066000 { 498 compatible = "ti,omap4-iommu"; 499 reg = <0x4a066000 0x100>; 500 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 501 ti,hwmods = "mmu_dsp"; 502 }; 503 504 mmu_ipu: mmu@55082000 { 505 compatible = "ti,omap4-iommu"; 506 reg = <0x55082000 0x100>; 507 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>; 508 ti,hwmods = "mmu_ipu"; 509 ti,iommu-bus-err-back; 510 }; 511 512 wdt2: wdt@4a314000 { 513 compatible = "ti,omap4-wdt", "ti,omap3-wdt"; 514 reg = <0x4a314000 0x80>; 515 interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; 516 ti,hwmods = "wd_timer2"; 517 }; 518 519 mcpdm: mcpdm@40132000 { 520 compatible = "ti,omap4-mcpdm"; 521 reg = <0x40132000 0x7f>, /* MPU private access */ 522 <0x49032000 0x7f>; /* L3 Interconnect */ 523 reg-names = "mpu", "dma"; 524 interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; 525 ti,hwmods = "mcpdm"; 526 dmas = <&sdma 65>, 527 <&sdma 66>; 528 dma-names = "up_link", "dn_link"; 529 status = "disabled"; 530 }; 531 532 dmic: dmic@4012e000 { 533 compatible = "ti,omap4-dmic"; 534 reg = <0x4012e000 0x7f>, /* MPU private access */ 535 <0x4902e000 0x7f>; /* L3 Interconnect */ 536 reg-names = "mpu", "dma"; 537 interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; 538 ti,hwmods = "dmic"; 539 dmas = <&sdma 67>; 540 dma-names = "up_link"; 541 status = "disabled"; 542 }; 543 544 mcbsp1: mcbsp@40122000 { 545 compatible = "ti,omap4-mcbsp"; 546 reg = <0x40122000 0xff>, /* MPU private access */ 547 <0x49022000 0xff>; /* L3 Interconnect */ 548 reg-names = "mpu", "dma"; 549 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 550 interrupt-names = "common"; 551 ti,buffer-size = <128>; 552 ti,hwmods = "mcbsp1"; 553 dmas = <&sdma 33>, 554 <&sdma 34>; 555 dma-names = "tx", "rx"; 556 status = "disabled"; 557 }; 558 559 mcbsp2: mcbsp@40124000 { 560 compatible = "ti,omap4-mcbsp"; 561 reg = <0x40124000 0xff>, /* MPU private access */ 562 <0x49024000 0xff>; /* L3 Interconnect */ 563 reg-names = "mpu", "dma"; 564 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 565 interrupt-names = "common"; 566 ti,buffer-size = <128>; 567 ti,hwmods = "mcbsp2"; 568 dmas = <&sdma 17>, 569 <&sdma 18>; 570 dma-names = "tx", "rx"; 571 status = "disabled"; 572 }; 573 574 mcbsp3: mcbsp@40126000 { 575 compatible = "ti,omap4-mcbsp"; 576 reg = <0x40126000 0xff>, /* MPU private access */ 577 <0x49026000 0xff>; /* L3 Interconnect */ 578 reg-names = "mpu", "dma"; 579 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 580 interrupt-names = "common"; 581 ti,buffer-size = <128>; 582 ti,hwmods = "mcbsp3"; 583 dmas = <&sdma 19>, 584 <&sdma 20>; 585 dma-names = "tx", "rx"; 586 status = "disabled"; 587 }; 588 589 mcbsp4: mcbsp@48096000 { 590 compatible = "ti,omap4-mcbsp"; 591 reg = <0x48096000 0xff>; /* L4 Interconnect */ 592 reg-names = "mpu"; 593 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 594 interrupt-names = "common"; 595 ti,buffer-size = <128>; 596 ti,hwmods = "mcbsp4"; 597 dmas = <&sdma 31>, 598 <&sdma 32>; 599 dma-names = "tx", "rx"; 600 status = "disabled"; 601 }; 602 603 keypad: keypad@4a31c000 { 604 compatible = "ti,omap4-keypad"; 605 reg = <0x4a31c000 0x80>; 606 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; 607 reg-names = "mpu"; 608 ti,hwmods = "kbd"; 609 }; 610 611 dmm@4e000000 { 612 compatible = "ti,omap4-dmm"; 613 reg = <0x4e000000 0x800>; 614 interrupts = <0 113 0x4>; 615 ti,hwmods = "dmm"; 616 }; 617 618 emif1: emif@4c000000 { 619 compatible = "ti,emif-4d"; 620 reg = <0x4c000000 0x100>; 621 interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; 622 ti,hwmods = "emif1"; 623 ti,no-idle-on-init; 624 phy-type = <1>; 625 hw-caps-read-idle-ctrl; 626 hw-caps-ll-interface; 627 hw-caps-temp-alert; 628 }; 629 630 emif2: emif@4d000000 { 631 compatible = "ti,emif-4d"; 632 reg = <0x4d000000 0x100>; 633 interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; 634 ti,hwmods = "emif2"; 635 ti,no-idle-on-init; 636 phy-type = <1>; 637 hw-caps-read-idle-ctrl; 638 hw-caps-ll-interface; 639 hw-caps-temp-alert; 640 }; 641 642 ocp2scp@4a0ad000 { 643 compatible = "ti,omap-ocp2scp"; 644 reg = <0x4a0ad000 0x1f>; 645 #address-cells = <1>; 646 #size-cells = <1>; 647 ranges; 648 ti,hwmods = "ocp2scp_usb_phy"; 649 usb2_phy: usb2phy@4a0ad080 { 650 compatible = "ti,omap-usb2"; 651 reg = <0x4a0ad080 0x58>; 652 ctrl-module = <&omap_control_usb2phy>; 653 clocks = <&usb_phy_cm_clk32k>; 654 clock-names = "wkupclk"; 655 #phy-cells = <0>; 656 }; 657 }; 658 659 mailbox: mailbox@4a0f4000 { 660 compatible = "ti,omap4-mailbox"; 661 reg = <0x4a0f4000 0x200>; 662 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 663 ti,hwmods = "mailbox"; 664 #mbox-cells = <1>; 665 ti,mbox-num-users = <3>; 666 ti,mbox-num-fifos = <8>; 667 mbox_ipu: mbox_ipu { 668 ti,mbox-tx = <0 0 0>; 669 ti,mbox-rx = <1 0 0>; 670 }; 671 mbox_dsp: mbox_dsp { 672 ti,mbox-tx = <3 0 0>; 673 ti,mbox-rx = <2 0 0>; 674 }; 675 }; 676 677 timer1: timer@4a318000 { 678 compatible = "ti,omap3430-timer"; 679 reg = <0x4a318000 0x80>; 680 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; 681 ti,hwmods = "timer1"; 682 ti,timer-alwon; 683 }; 684 685 timer2: timer@48032000 { 686 compatible = "ti,omap3430-timer"; 687 reg = <0x48032000 0x80>; 688 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 689 ti,hwmods = "timer2"; 690 }; 691 692 timer3: timer@48034000 { 693 compatible = "ti,omap4430-timer"; 694 reg = <0x48034000 0x80>; 695 interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; 696 ti,hwmods = "timer3"; 697 }; 698 699 timer4: timer@48036000 { 700 compatible = "ti,omap4430-timer"; 701 reg = <0x48036000 0x80>; 702 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 703 ti,hwmods = "timer4"; 704 }; 705 706 timer5: timer@40138000 { 707 compatible = "ti,omap4430-timer"; 708 reg = <0x40138000 0x80>, 709 <0x49038000 0x80>; 710 interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; 711 ti,hwmods = "timer5"; 712 ti,timer-dsp; 713 }; 714 715 timer6: timer@4013a000 { 716 compatible = "ti,omap4430-timer"; 717 reg = <0x4013a000 0x80>, 718 <0x4903a000 0x80>; 719 interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; 720 ti,hwmods = "timer6"; 721 ti,timer-dsp; 722 }; 723 724 timer7: timer@4013c000 { 725 compatible = "ti,omap4430-timer"; 726 reg = <0x4013c000 0x80>, 727 <0x4903c000 0x80>; 728 interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>; 729 ti,hwmods = "timer7"; 730 ti,timer-dsp; 731 }; 732 733 timer8: timer@4013e000 { 734 compatible = "ti,omap4430-timer"; 735 reg = <0x4013e000 0x80>, 736 <0x4903e000 0x80>; 737 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; 738 ti,hwmods = "timer8"; 739 ti,timer-pwm; 740 ti,timer-dsp; 741 }; 742 743 timer9: timer@4803e000 { 744 compatible = "ti,omap4430-timer"; 745 reg = <0x4803e000 0x80>; 746 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; 747 ti,hwmods = "timer9"; 748 ti,timer-pwm; 749 }; 750 751 timer10: timer@48086000 { 752 compatible = "ti,omap3430-timer"; 753 reg = <0x48086000 0x80>; 754 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>; 755 ti,hwmods = "timer10"; 756 ti,timer-pwm; 757 }; 758 759 timer11: timer@48088000 { 760 compatible = "ti,omap4430-timer"; 761 reg = <0x48088000 0x80>; 762 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; 763 ti,hwmods = "timer11"; 764 ti,timer-pwm; 765 }; 766 767 usbhstll: usbhstll@4a062000 { 768 compatible = "ti,usbhs-tll"; 769 reg = <0x4a062000 0x1000>; 770 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; 771 ti,hwmods = "usb_tll_hs"; 772 }; 773 774 usbhshost: usbhshost@4a064000 { 775 compatible = "ti,usbhs-host"; 776 reg = <0x4a064000 0x800>; 777 ti,hwmods = "usb_host_hs"; 778 #address-cells = <1>; 779 #size-cells = <1>; 780 ranges; 781 clocks = <&init_60m_fclk>, 782 <&xclk60mhsp1_ck>, 783 <&xclk60mhsp2_ck>; 784 clock-names = "refclk_60m_int", 785 "refclk_60m_ext_p1", 786 "refclk_60m_ext_p2"; 787 788 usbhsohci: ohci@4a064800 { 789 compatible = "ti,ohci-omap3"; 790 reg = <0x4a064800 0x400>; 791 interrupt-parent = <&gic>; 792 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 793 }; 794 795 usbhsehci: ehci@4a064c00 { 796 compatible = "ti,ehci-omap"; 797 reg = <0x4a064c00 0x400>; 798 interrupt-parent = <&gic>; 799 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 800 }; 801 }; 802 803 omap_control_usb2phy: control-phy@4a002300 { 804 compatible = "ti,control-phy-usb2"; 805 reg = <0x4a002300 0x4>; 806 reg-names = "power"; 807 }; 808 809 omap_control_usbotg: control-phy@4a00233c { 810 compatible = "ti,control-phy-otghs"; 811 reg = <0x4a00233c 0x4>; 812 reg-names = "otghs_control"; 813 }; 814 815 usb_otg_hs: usb_otg_hs@4a0ab000 { 816 compatible = "ti,omap4-musb"; 817 reg = <0x4a0ab000 0x7ff>; 818 interrupts = <GIC_SPI 92 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>; 819 interrupt-names = "mc", "dma"; 820 ti,hwmods = "usb_otg_hs"; 821 usb-phy = <&usb2_phy>; 822 phys = <&usb2_phy>; 823 phy-names = "usb2-phy"; 824 multipoint = <1>; 825 num-eps = <16>; 826 ram-bits = <12>; 827 ctrl-module = <&omap_control_usbotg>; 828 }; 829 830 aes: aes@4b501000 { 831 compatible = "ti,omap4-aes"; 832 ti,hwmods = "aes"; 833 reg = <0x4b501000 0xa0>; 834 interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 835 dmas = <&sdma 111>, <&sdma 110>; 836 dma-names = "tx", "rx"; 837 }; 838 839 des: des@480a5000 { 840 compatible = "ti,omap4-des"; 841 ti,hwmods = "des"; 842 reg = <0x480a5000 0xa0>; 843 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 844 dmas = <&sdma 117>, <&sdma 116>; 845 dma-names = "tx", "rx"; 846 }; 847 848 abb_mpu: regulator-abb-mpu { 849 compatible = "ti,abb-v2"; 850 regulator-name = "abb_mpu"; 851 #address-cells = <0>; 852 #size-cells = <0>; 853 ti,tranxdone-status-mask = <0x80>; 854 clocks = <&sys_clkin_ck>; 855 ti,settling-time = <50>; 856 ti,clock-cycles = <16>; 857 858 status = "disabled"; 859 }; 860 861 abb_iva: regulator-abb-iva { 862 compatible = "ti,abb-v2"; 863 regulator-name = "abb_iva"; 864 #address-cells = <0>; 865 #size-cells = <0>; 866 ti,tranxdone-status-mask = <0x80000000>; 867 clocks = <&sys_clkin_ck>; 868 ti,settling-time = <50>; 869 ti,clock-cycles = <16>; 870 871 status = "disabled"; 872 }; 873 874 dss: dss@58000000 { 875 compatible = "ti,omap4-dss"; 876 reg = <0x58000000 0x80>; 877 status = "disabled"; 878 ti,hwmods = "dss_core"; 879 clocks = <&dss_dss_clk>; 880 clock-names = "fck"; 881 #address-cells = <1>; 882 #size-cells = <1>; 883 ranges; 884 885 dispc@58001000 { 886 compatible = "ti,omap4-dispc"; 887 reg = <0x58001000 0x1000>; 888 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 889 ti,hwmods = "dss_dispc"; 890 clocks = <&dss_dss_clk>; 891 clock-names = "fck"; 892 }; 893 894 rfbi: encoder@58002000 { 895 compatible = "ti,omap4-rfbi"; 896 reg = <0x58002000 0x1000>; 897 status = "disabled"; 898 ti,hwmods = "dss_rfbi"; 899 clocks = <&dss_dss_clk>, <&l3_div_ck>; 900 clock-names = "fck", "ick"; 901 }; 902 903 venc: encoder@58003000 { 904 compatible = "ti,omap4-venc"; 905 reg = <0x58003000 0x1000>; 906 status = "disabled"; 907 ti,hwmods = "dss_venc"; 908 clocks = <&dss_tv_clk>; 909 clock-names = "fck"; 910 }; 911 912 dsi1: encoder@58004000 { 913 compatible = "ti,omap4-dsi"; 914 reg = <0x58004000 0x200>, 915 <0x58004200 0x40>, 916 <0x58004300 0x20>; 917 reg-names = "proto", "phy", "pll"; 918 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>; 919 status = "disabled"; 920 ti,hwmods = "dss_dsi1"; 921 clocks = <&dss_dss_clk>, <&dss_sys_clk>; 922 clock-names = "fck", "sys_clk"; 923 }; 924 925 dsi2: encoder@58005000 { 926 compatible = "ti,omap4-dsi"; 927 reg = <0x58005000 0x200>, 928 <0x58005200 0x40>, 929 <0x58005300 0x20>; 930 reg-names = "proto", "phy", "pll"; 931 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; 932 status = "disabled"; 933 ti,hwmods = "dss_dsi2"; 934 clocks = <&dss_dss_clk>, <&dss_sys_clk>; 935 clock-names = "fck", "sys_clk"; 936 }; 937 938 hdmi: encoder@58006000 { 939 compatible = "ti,omap4-hdmi"; 940 reg = <0x58006000 0x200>, 941 <0x58006200 0x100>, 942 <0x58006300 0x100>, 943 <0x58006400 0x1000>; 944 reg-names = "wp", "pll", "phy", "core"; 945 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; 946 status = "disabled"; 947 ti,hwmods = "dss_hdmi"; 948 clocks = <&dss_48mhz_clk>, <&dss_sys_clk>; 949 clock-names = "fck", "sys_clk"; 950 dmas = <&sdma 76>; 951 dma-names = "audio_tx"; 952 }; 953 }; 954 }; 955}; 956 957/include/ "omap44xx-clocks.dtsi" 958