omap24xx-clocks.dtsi revision 284090 
1/*
2 * Device Tree Source for OMAP24xx clock data
3 *
4 * Copyright (C) 2014 Texas Instruments, Inc.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10&scrm_clocks {
11	mcbsp1_mux_fck: mcbsp1_mux_fck {
12		#clock-cells = <0>;
13		compatible = "ti,composite-mux-clock";
14		clocks = <&func_96m_ck>, <&mcbsp_clks>;
15		ti,bit-shift = <2>;
16		reg = <0x0274>;
17	};
18
19	mcbsp1_fck: mcbsp1_fck {
20		#clock-cells = <0>;
21		compatible = "ti,composite-clock";
22		clocks = <&mcbsp1_gate_fck>, <&mcbsp1_mux_fck>;
23	};
24
25	mcbsp2_mux_fck: mcbsp2_mux_fck {
26		#clock-cells = <0>;
27		compatible = "ti,composite-mux-clock";
28		clocks = <&func_96m_ck>, <&mcbsp_clks>;
29		ti,bit-shift = <6>;
30		reg = <0x0274>;
31	};
32
33	mcbsp2_fck: mcbsp2_fck {
34		#clock-cells = <0>;
35		compatible = "ti,composite-clock";
36		clocks = <&mcbsp2_gate_fck>, <&mcbsp2_mux_fck>;
37	};
38};
39
40&prcm_clocks {
41	func_32k_ck: func_32k_ck {
42		#clock-cells = <0>;
43		compatible = "fixed-clock";
44		clock-frequency = <32768>;
45	};
46
47	secure_32k_ck: secure_32k_ck {
48		#clock-cells = <0>;
49		compatible = "fixed-clock";
50		clock-frequency = <32768>;
51	};
52
53	virt_12m_ck: virt_12m_ck {
54		#clock-cells = <0>;
55		compatible = "fixed-clock";
56		clock-frequency = <12000000>;
57	};
58
59	virt_13m_ck: virt_13m_ck {
60		#clock-cells = <0>;
61		compatible = "fixed-clock";
62		clock-frequency = <13000000>;
63	};
64
65	virt_19200000_ck: virt_19200000_ck {
66		#clock-cells = <0>;
67		compatible = "fixed-clock";
68		clock-frequency = <19200000>;
69	};
70
71	virt_26m_ck: virt_26m_ck {
72		#clock-cells = <0>;
73		compatible = "fixed-clock";
74		clock-frequency = <26000000>;
75	};
76
77	aplls_clkin_ck: aplls_clkin_ck {
78		#clock-cells = <0>;
79		compatible = "ti,mux-clock";
80		clocks = <&virt_19200000_ck>, <&virt_26m_ck>, <&virt_13m_ck>, <&virt_12m_ck>;
81		ti,bit-shift = <23>;
82		reg = <0x0540>;
83	};
84
85	aplls_clkin_x2_ck: aplls_clkin_x2_ck {
86		#clock-cells = <0>;
87		compatible = "fixed-factor-clock";
88		clocks = <&aplls_clkin_ck>;
89		clock-mult = <2>;
90		clock-div = <1>;
91	};
92
93	osc_ck: osc_ck {
94		#clock-cells = <0>;
95		compatible = "ti,mux-clock";
96		clocks = <&aplls_clkin_ck>, <&aplls_clkin_x2_ck>;
97		ti,bit-shift = <6>;
98		reg = <0x0060>;
99		ti,index-starts-at-one;
100	};
101
102	sys_ck: sys_ck {
103		#clock-cells = <0>;
104		compatible = "ti,divider-clock";
105		clocks = <&osc_ck>;
106		ti,bit-shift = <6>;
107		ti,max-div = <3>;
108		reg = <0x0060>;
109		ti,index-starts-at-one;
110	};
111
112	alt_ck: alt_ck {
113		#clock-cells = <0>;
114		compatible = "fixed-clock";
115		clock-frequency = <54000000>;
116	};
117
118	mcbsp_clks: mcbsp_clks {
119		#clock-cells = <0>;
120		compatible = "fixed-clock";
121		clock-frequency = <0x0>;
122	};
123
124	dpll_ck: dpll_ck {
125		#clock-cells = <0>;
126		compatible = "ti,omap2-dpll-core-clock";
127		clocks = <&sys_ck>, <&sys_ck>;
128		reg = <0x0500>, <0x0540>;
129	};
130
131	apll96_ck: apll96_ck {
132		#clock-cells = <0>;
133		compatible = "ti,omap2-apll-clock";
134		clocks = <&sys_ck>;
135		ti,bit-shift = <2>;
136		ti,idlest-shift = <8>;
137		ti,clock-frequency = <96000000>;
138		reg = <0x0500>, <0x0530>, <0x0520>;
139	};
140
141	apll54_ck: apll54_ck {
142		#clock-cells = <0>;
143		compatible = "ti,omap2-apll-clock";
144		clocks = <&sys_ck>;
145		ti,bit-shift = <6>;
146		ti,idlest-shift = <9>;
147		ti,clock-frequency = <54000000>;
148		reg = <0x0500>, <0x0530>, <0x0520>;
149	};
150
151	func_54m_ck: func_54m_ck {
152		#clock-cells = <0>;
153		compatible = "ti,mux-clock";
154		clocks = <&apll54_ck>, <&alt_ck>;
155		ti,bit-shift = <5>;
156		reg = <0x0540>;
157	};
158
159	core_ck: core_ck {
160		#clock-cells = <0>;
161		compatible = "fixed-factor-clock";
162		clocks = <&dpll_ck>;
163		clock-mult = <1>;
164		clock-div = <1>;
165	};
166
167	func_96m_ck: func_96m_ck {
168		#clock-cells = <0>;
169	};
170
171	apll96_d2_ck: apll96_d2_ck {
172		#clock-cells = <0>;
173		compatible = "fixed-factor-clock";
174		clocks = <&apll96_ck>;
175		clock-mult = <1>;
176		clock-div = <2>;
177	};
178
179	func_48m_ck: func_48m_ck {
180		#clock-cells = <0>;
181		compatible = "ti,mux-clock";
182		clocks = <&apll96_d2_ck>, <&alt_ck>;
183		ti,bit-shift = <3>;
184		reg = <0x0540>;
185	};
186
187	func_12m_ck: func_12m_ck {
188		#clock-cells = <0>;
189		compatible = "fixed-factor-clock";
190		clocks = <&func_48m_ck>;
191		clock-mult = <1>;
192		clock-div = <4>;
193	};
194
195	sys_clkout_src_gate: sys_clkout_src_gate {
196		#clock-cells = <0>;
197		compatible = "ti,composite-no-wait-gate-clock";
198		clocks = <&core_ck>;
199		ti,bit-shift = <7>;
200		reg = <0x0070>;
201	};
202
203	sys_clkout_src_mux: sys_clkout_src_mux {
204		#clock-cells = <0>;
205		compatible = "ti,composite-mux-clock";
206		clocks = <&core_ck>, <&sys_ck>, <&func_96m_ck>, <&func_54m_ck>;
207		reg = <0x0070>;
208	};
209
210	sys_clkout_src: sys_clkout_src {
211		#clock-cells = <0>;
212		compatible = "ti,composite-clock";
213		clocks = <&sys_clkout_src_gate>, <&sys_clkout_src_mux>;
214	};
215
216	sys_clkout: sys_clkout {
217		#clock-cells = <0>;
218		compatible = "ti,divider-clock";
219		clocks = <&sys_clkout_src>;
220		ti,bit-shift = <3>;
221		ti,max-div = <64>;
222		reg = <0x0070>;
223		ti,index-power-of-two;
224	};
225
226	emul_ck: emul_ck {
227		#clock-cells = <0>;
228		compatible = "ti,gate-clock";
229		clocks = <&func_54m_ck>;
230		ti,bit-shift = <0>;
231		reg = <0x0078>;
232	};
233
234	mpu_ck: mpu_ck {
235		#clock-cells = <0>;
236		compatible = "ti,divider-clock";
237		clocks = <&core_ck>;
238		ti,max-div = <31>;
239		reg = <0x0140>;
240		ti,index-starts-at-one;
241	};
242
243	dsp_gate_fck: dsp_gate_fck {
244		#clock-cells = <0>;
245		compatible = "ti,composite-gate-clock";
246		clocks = <&core_ck>;
247		ti,bit-shift = <0>;
248		reg = <0x0800>;
249	};
250
251	dsp_div_fck: dsp_div_fck {
252		#clock-cells = <0>;
253		compatible = "ti,composite-divider-clock";
254		clocks = <&core_ck>;
255		reg = <0x0840>;
256	};
257
258	dsp_fck: dsp_fck {
259		#clock-cells = <0>;
260		compatible = "ti,composite-clock";
261		clocks = <&dsp_gate_fck>, <&dsp_div_fck>;
262	};
263
264	core_l3_ck: core_l3_ck {
265		#clock-cells = <0>;
266		compatible = "ti,divider-clock";
267		clocks = <&core_ck>;
268		ti,max-div = <31>;
269		reg = <0x0240>;
270		ti,index-starts-at-one;
271	};
272
273	gfx_3d_gate_fck: gfx_3d_gate_fck {
274		#clock-cells = <0>;
275		compatible = "ti,composite-gate-clock";
276		clocks = <&core_l3_ck>;
277		ti,bit-shift = <2>;
278		reg = <0x0300>;
279	};
280
281	gfx_3d_div_fck: gfx_3d_div_fck {
282		#clock-cells = <0>;
283		compatible = "ti,composite-divider-clock";
284		clocks = <&core_l3_ck>;
285		ti,max-div = <4>;
286		reg = <0x0340>;
287		ti,index-starts-at-one;
288	};
289
290	gfx_3d_fck: gfx_3d_fck {
291		#clock-cells = <0>;
292		compatible = "ti,composite-clock";
293		clocks = <&gfx_3d_gate_fck>, <&gfx_3d_div_fck>;
294	};
295
296	gfx_2d_gate_fck: gfx_2d_gate_fck {
297		#clock-cells = <0>;
298		compatible = "ti,composite-gate-clock";
299		clocks = <&core_l3_ck>;
300		ti,bit-shift = <1>;
301		reg = <0x0300>;
302	};
303
304	gfx_2d_div_fck: gfx_2d_div_fck {
305		#clock-cells = <0>;
306		compatible = "ti,composite-divider-clock";
307		clocks = <&core_l3_ck>;
308		ti,max-div = <4>;
309		reg = <0x0340>;
310		ti,index-starts-at-one;
311	};
312
313	gfx_2d_fck: gfx_2d_fck {
314		#clock-cells = <0>;
315		compatible = "ti,composite-clock";
316		clocks = <&gfx_2d_gate_fck>, <&gfx_2d_div_fck>;
317	};
318
319	gfx_ick: gfx_ick {
320		#clock-cells = <0>;
321		compatible = "ti,wait-gate-clock";
322		clocks = <&core_l3_ck>;
323		ti,bit-shift = <0>;
324		reg = <0x0310>;
325	};
326
327	l4_ck: l4_ck {
328		#clock-cells = <0>;
329		compatible = "ti,divider-clock";
330		clocks = <&core_l3_ck>;
331		ti,bit-shift = <5>;
332		ti,max-div = <3>;
333		reg = <0x0240>;
334		ti,index-starts-at-one;
335	};
336
337	dss_ick: dss_ick {
338		#clock-cells = <0>;
339		compatible = "ti,omap3-no-wait-interface-clock";
340		clocks = <&l4_ck>;
341		ti,bit-shift = <0>;
342		reg = <0x0210>;
343	};
344
345	dss1_gate_fck: dss1_gate_fck {
346		#clock-cells = <0>;
347		compatible = "ti,composite-no-wait-gate-clock";
348		clocks = <&core_ck>;
349		ti,bit-shift = <0>;
350		reg = <0x0200>;
351	};
352
353	core_d2_ck: core_d2_ck {
354		#clock-cells = <0>;
355		compatible = "fixed-factor-clock";
356		clocks = <&core_ck>;
357		clock-mult = <1>;
358		clock-div = <2>;
359	};
360
361	core_d3_ck: core_d3_ck {
362		#clock-cells = <0>;
363		compatible = "fixed-factor-clock";
364		clocks = <&core_ck>;
365		clock-mult = <1>;
366		clock-div = <3>;
367	};
368
369	core_d4_ck: core_d4_ck {
370		#clock-cells = <0>;
371		compatible = "fixed-factor-clock";
372		clocks = <&core_ck>;
373		clock-mult = <1>;
374		clock-div = <4>;
375	};
376
377	core_d5_ck: core_d5_ck {
378		#clock-cells = <0>;
379		compatible = "fixed-factor-clock";
380		clocks = <&core_ck>;
381		clock-mult = <1>;
382		clock-div = <5>;
383	};
384
385	core_d6_ck: core_d6_ck {
386		#clock-cells = <0>;
387		compatible = "fixed-factor-clock";
388		clocks = <&core_ck>;
389		clock-mult = <1>;
390		clock-div = <6>;
391	};
392
393	dummy_ck: dummy_ck {
394		#clock-cells = <0>;
395		compatible = "fixed-clock";
396		clock-frequency = <0>;
397	};
398
399	core_d8_ck: core_d8_ck {
400		#clock-cells = <0>;
401		compatible = "fixed-factor-clock";
402		clocks = <&core_ck>;
403		clock-mult = <1>;
404		clock-div = <8>;
405	};
406
407	core_d9_ck: core_d9_ck {
408		#clock-cells = <0>;
409		compatible = "fixed-factor-clock";
410		clocks = <&core_ck>;
411		clock-mult = <1>;
412		clock-div = <9>;
413	};
414
415	core_d12_ck: core_d12_ck {
416		#clock-cells = <0>;
417		compatible = "fixed-factor-clock";
418		clocks = <&core_ck>;
419		clock-mult = <1>;
420		clock-div = <12>;
421	};
422
423	core_d16_ck: core_d16_ck {
424		#clock-cells = <0>;
425		compatible = "fixed-factor-clock";
426		clocks = <&core_ck>;
427		clock-mult = <1>;
428		clock-div = <16>;
429	};
430
431	dss1_mux_fck: dss1_mux_fck {
432		#clock-cells = <0>;
433		compatible = "ti,composite-mux-clock";
434		clocks = <&sys_ck>, <&core_ck>, <&core_d2_ck>, <&core_d3_ck>, <&core_d4_ck>, <&core_d5_ck>, <&core_d6_ck>, <&core_d8_ck>, <&core_d9_ck>, <&core_d12_ck>, <&core_d16_ck>;
435		ti,bit-shift = <8>;
436		reg = <0x0240>;
437	};
438
439	dss1_fck: dss1_fck {
440		#clock-cells = <0>;
441		compatible = "ti,composite-clock";
442		clocks = <&dss1_gate_fck>, <&dss1_mux_fck>;
443	};
444
445	dss2_gate_fck: dss2_gate_fck {
446		#clock-cells = <0>;
447		compatible = "ti,composite-no-wait-gate-clock";
448		clocks = <&func_48m_ck>;
449		ti,bit-shift = <1>;
450		reg = <0x0200>;
451	};
452
453	dss2_mux_fck: dss2_mux_fck {
454		#clock-cells = <0>;
455		compatible = "ti,composite-mux-clock";
456		clocks = <&sys_ck>, <&func_48m_ck>;
457		ti,bit-shift = <13>;
458		reg = <0x0240>;
459	};
460
461	dss2_fck: dss2_fck {
462		#clock-cells = <0>;
463		compatible = "ti,composite-clock";
464		clocks = <&dss2_gate_fck>, <&dss2_mux_fck>;
465	};
466
467	dss_54m_fck: dss_54m_fck {
468		#clock-cells = <0>;
469		compatible = "ti,wait-gate-clock";
470		clocks = <&func_54m_ck>;
471		ti,bit-shift = <2>;
472		reg = <0x0200>;
473	};
474
475	ssi_ssr_sst_gate_fck: ssi_ssr_sst_gate_fck {
476		#clock-cells = <0>;
477		compatible = "ti,composite-gate-clock";
478		clocks = <&core_ck>;
479		ti,bit-shift = <1>;
480		reg = <0x0204>;
481	};
482
483	ssi_ssr_sst_div_fck: ssi_ssr_sst_div_fck {
484		#clock-cells = <0>;
485		compatible = "ti,composite-divider-clock";
486		clocks = <&core_ck>;
487		ti,bit-shift = <20>;
488		reg = <0x0240>;
489	};
490
491	ssi_ssr_sst_fck: ssi_ssr_sst_fck {
492		#clock-cells = <0>;
493		compatible = "ti,composite-clock";
494		clocks = <&ssi_ssr_sst_gate_fck>, <&ssi_ssr_sst_div_fck>;
495	};
496
497	usb_l4_gate_ick: usb_l4_gate_ick {
498		#clock-cells = <0>;
499		compatible = "ti,composite-interface-clock";
500		clocks = <&core_l3_ck>;
501		ti,bit-shift = <0>;
502		reg = <0x0214>;
503	};
504
505	usb_l4_div_ick: usb_l4_div_ick {
506		#clock-cells = <0>;
507		compatible = "ti,composite-divider-clock";
508		clocks = <&core_l3_ck>;
509		ti,bit-shift = <25>;
510		reg = <0x0240>;
511		ti,dividers = <0>, <1>, <2>, <0>, <4>;
512	};
513
514	usb_l4_ick: usb_l4_ick {
515		#clock-cells = <0>;
516		compatible = "ti,composite-clock";
517		clocks = <&usb_l4_gate_ick>, <&usb_l4_div_ick>;
518	};
519
520	ssi_l4_ick: ssi_l4_ick {
521		#clock-cells = <0>;
522		compatible = "ti,omap3-interface-clock";
523		clocks = <&l4_ck>;
524		ti,bit-shift = <1>;
525		reg = <0x0214>;
526	};
527
528	gpt1_ick: gpt1_ick {
529		#clock-cells = <0>;
530		compatible = "ti,omap3-interface-clock";
531		clocks = <&sys_ck>;
532		ti,bit-shift = <0>;
533		reg = <0x0410>;
534	};
535
536	gpt1_gate_fck: gpt1_gate_fck {
537		#clock-cells = <0>;
538		compatible = "ti,composite-gate-clock";
539		clocks = <&func_32k_ck>;
540		ti,bit-shift = <0>;
541		reg = <0x0400>;
542	};
543
544	gpt1_mux_fck: gpt1_mux_fck {
545		#clock-cells = <0>;
546		compatible = "ti,composite-mux-clock";
547		clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
548		reg = <0x0440>;
549	};
550
551	gpt1_fck: gpt1_fck {
552		#clock-cells = <0>;
553		compatible = "ti,composite-clock";
554		clocks = <&gpt1_gate_fck>, <&gpt1_mux_fck>;
555	};
556
557	gpt2_ick: gpt2_ick {
558		#clock-cells = <0>;
559		compatible = "ti,omap3-interface-clock";
560		clocks = <&l4_ck>;
561		ti,bit-shift = <4>;
562		reg = <0x0210>;
563	};
564
565	gpt2_gate_fck: gpt2_gate_fck {
566		#clock-cells = <0>;
567		compatible = "ti,composite-gate-clock";
568		clocks = <&func_32k_ck>;
569		ti,bit-shift = <4>;
570		reg = <0x0200>;
571	};
572
573	gpt2_mux_fck: gpt2_mux_fck {
574		#clock-cells = <0>;
575		compatible = "ti,composite-mux-clock";
576		clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
577		ti,bit-shift = <2>;
578		reg = <0x0244>;
579	};
580
581	gpt2_fck: gpt2_fck {
582		#clock-cells = <0>;
583		compatible = "ti,composite-clock";
584		clocks = <&gpt2_gate_fck>, <&gpt2_mux_fck>;
585	};
586
587	gpt3_ick: gpt3_ick {
588		#clock-cells = <0>;
589		compatible = "ti,omap3-interface-clock";
590		clocks = <&l4_ck>;
591		ti,bit-shift = <5>;
592		reg = <0x0210>;
593	};
594
595	gpt3_gate_fck: gpt3_gate_fck {
596		#clock-cells = <0>;
597		compatible = "ti,composite-gate-clock";
598		clocks = <&func_32k_ck>;
599		ti,bit-shift = <5>;
600		reg = <0x0200>;
601	};
602
603	gpt3_mux_fck: gpt3_mux_fck {
604		#clock-cells = <0>;
605		compatible = "ti,composite-mux-clock";
606		clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
607		ti,bit-shift = <4>;
608		reg = <0x0244>;
609	};
610
611	gpt3_fck: gpt3_fck {
612		#clock-cells = <0>;
613		compatible = "ti,composite-clock";
614		clocks = <&gpt3_gate_fck>, <&gpt3_mux_fck>;
615	};
616
617	gpt4_ick: gpt4_ick {
618		#clock-cells = <0>;
619		compatible = "ti,omap3-interface-clock";
620		clocks = <&l4_ck>;
621		ti,bit-shift = <6>;
622		reg = <0x0210>;
623	};
624
625	gpt4_gate_fck: gpt4_gate_fck {
626		#clock-cells = <0>;
627		compatible = "ti,composite-gate-clock";
628		clocks = <&func_32k_ck>;
629		ti,bit-shift = <6>;
630		reg = <0x0200>;
631	};
632
633	gpt4_mux_fck: gpt4_mux_fck {
634		#clock-cells = <0>;
635		compatible = "ti,composite-mux-clock";
636		clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
637		ti,bit-shift = <6>;
638		reg = <0x0244>;
639	};
640
641	gpt4_fck: gpt4_fck {
642		#clock-cells = <0>;
643		compatible = "ti,composite-clock";
644		clocks = <&gpt4_gate_fck>, <&gpt4_mux_fck>;
645	};
646
647	gpt5_ick: gpt5_ick {
648		#clock-cells = <0>;
649		compatible = "ti,omap3-interface-clock";
650		clocks = <&l4_ck>;
651		ti,bit-shift = <7>;
652		reg = <0x0210>;
653	};
654
655	gpt5_gate_fck: gpt5_gate_fck {
656		#clock-cells = <0>;
657		compatible = "ti,composite-gate-clock";
658		clocks = <&func_32k_ck>;
659		ti,bit-shift = <7>;
660		reg = <0x0200>;
661	};
662
663	gpt5_mux_fck: gpt5_mux_fck {
664		#clock-cells = <0>;
665		compatible = "ti,composite-mux-clock";
666		clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
667		ti,bit-shift = <8>;
668		reg = <0x0244>;
669	};
670
671	gpt5_fck: gpt5_fck {
672		#clock-cells = <0>;
673		compatible = "ti,composite-clock";
674		clocks = <&gpt5_gate_fck>, <&gpt5_mux_fck>;
675	};
676
677	gpt6_ick: gpt6_ick {
678		#clock-cells = <0>;
679		compatible = "ti,omap3-interface-clock";
680		clocks = <&l4_ck>;
681		ti,bit-shift = <8>;
682		reg = <0x0210>;
683	};
684
685	gpt6_gate_fck: gpt6_gate_fck {
686		#clock-cells = <0>;
687		compatible = "ti,composite-gate-clock";
688		clocks = <&func_32k_ck>;
689		ti,bit-shift = <8>;
690		reg = <0x0200>;
691	};
692
693	gpt6_mux_fck: gpt6_mux_fck {
694		#clock-cells = <0>;
695		compatible = "ti,composite-mux-clock";
696		clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
697		ti,bit-shift = <10>;
698		reg = <0x0244>;
699	};
700
701	gpt6_fck: gpt6_fck {
702		#clock-cells = <0>;
703		compatible = "ti,composite-clock";
704		clocks = <&gpt6_gate_fck>, <&gpt6_mux_fck>;
705	};
706
707	gpt7_ick: gpt7_ick {
708		#clock-cells = <0>;
709		compatible = "ti,omap3-interface-clock";
710		clocks = <&l4_ck>;
711		ti,bit-shift = <9>;
712		reg = <0x0210>;
713	};
714
715	gpt7_gate_fck: gpt7_gate_fck {
716		#clock-cells = <0>;
717		compatible = "ti,composite-gate-clock";
718		clocks = <&func_32k_ck>;
719		ti,bit-shift = <9>;
720		reg = <0x0200>;
721	};
722
723	gpt7_mux_fck: gpt7_mux_fck {
724		#clock-cells = <0>;
725		compatible = "ti,composite-mux-clock";
726		clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
727		ti,bit-shift = <12>;
728		reg = <0x0244>;
729	};
730
731	gpt7_fck: gpt7_fck {
732		#clock-cells = <0>;
733		compatible = "ti,composite-clock";
734		clocks = <&gpt7_gate_fck>, <&gpt7_mux_fck>;
735	};
736
737	gpt8_ick: gpt8_ick {
738		#clock-cells = <0>;
739		compatible = "ti,omap3-interface-clock";
740		clocks = <&l4_ck>;
741		ti,bit-shift = <10>;
742		reg = <0x0210>;
743	};
744
745	gpt8_gate_fck: gpt8_gate_fck {
746		#clock-cells = <0>;
747		compatible = "ti,composite-gate-clock";
748		clocks = <&func_32k_ck>;
749		ti,bit-shift = <10>;
750		reg = <0x0200>;
751	};
752
753	gpt8_mux_fck: gpt8_mux_fck {
754		#clock-cells = <0>;
755		compatible = "ti,composite-mux-clock";
756		clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
757		ti,bit-shift = <14>;
758		reg = <0x0244>;
759	};
760
761	gpt8_fck: gpt8_fck {
762		#clock-cells = <0>;
763		compatible = "ti,composite-clock";
764		clocks = <&gpt8_gate_fck>, <&gpt8_mux_fck>;
765	};
766
767	gpt9_ick: gpt9_ick {
768		#clock-cells = <0>;
769		compatible = "ti,omap3-interface-clock";
770		clocks = <&l4_ck>;
771		ti,bit-shift = <11>;
772		reg = <0x0210>;
773	};
774
775	gpt9_gate_fck: gpt9_gate_fck {
776		#clock-cells = <0>;
777		compatible = "ti,composite-gate-clock";
778		clocks = <&func_32k_ck>;
779		ti,bit-shift = <11>;
780		reg = <0x0200>;
781	};
782
783	gpt9_mux_fck: gpt9_mux_fck {
784		#clock-cells = <0>;
785		compatible = "ti,composite-mux-clock";
786		clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
787		ti,bit-shift = <16>;
788		reg = <0x0244>;
789	};
790
791	gpt9_fck: gpt9_fck {
792		#clock-cells = <0>;
793		compatible = "ti,composite-clock";
794		clocks = <&gpt9_gate_fck>, <&gpt9_mux_fck>;
795	};
796
797	gpt10_ick: gpt10_ick {
798		#clock-cells = <0>;
799		compatible = "ti,omap3-interface-clock";
800		clocks = <&l4_ck>;
801		ti,bit-shift = <12>;
802		reg = <0x0210>;
803	};
804
805	gpt10_gate_fck: gpt10_gate_fck {
806		#clock-cells = <0>;
807		compatible = "ti,composite-gate-clock";
808		clocks = <&func_32k_ck>;
809		ti,bit-shift = <12>;
810		reg = <0x0200>;
811	};
812
813	gpt10_mux_fck: gpt10_mux_fck {
814		#clock-cells = <0>;
815		compatible = "ti,composite-mux-clock";
816		clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
817		ti,bit-shift = <18>;
818		reg = <0x0244>;
819	};
820
821	gpt10_fck: gpt10_fck {
822		#clock-cells = <0>;
823		compatible = "ti,composite-clock";
824		clocks = <&gpt10_gate_fck>, <&gpt10_mux_fck>;
825	};
826
827	gpt11_ick: gpt11_ick {
828		#clock-cells = <0>;
829		compatible = "ti,omap3-interface-clock";
830		clocks = <&l4_ck>;
831		ti,bit-shift = <13>;
832		reg = <0x0210>;
833	};
834
835	gpt11_gate_fck: gpt11_gate_fck {
836		#clock-cells = <0>;
837		compatible = "ti,composite-gate-clock";
838		clocks = <&func_32k_ck>;
839		ti,bit-shift = <13>;
840		reg = <0x0200>;
841	};
842
843	gpt11_mux_fck: gpt11_mux_fck {
844		#clock-cells = <0>;
845		compatible = "ti,composite-mux-clock";
846		clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
847		ti,bit-shift = <20>;
848		reg = <0x0244>;
849	};
850
851	gpt11_fck: gpt11_fck {
852		#clock-cells = <0>;
853		compatible = "ti,composite-clock";
854		clocks = <&gpt11_gate_fck>, <&gpt11_mux_fck>;
855	};
856
857	gpt12_ick: gpt12_ick {
858		#clock-cells = <0>;
859		compatible = "ti,omap3-interface-clock";
860		clocks = <&l4_ck>;
861		ti,bit-shift = <14>;
862		reg = <0x0210>;
863	};
864
865	gpt12_gate_fck: gpt12_gate_fck {
866		#clock-cells = <0>;
867		compatible = "ti,composite-gate-clock";
868		clocks = <&func_32k_ck>;
869		ti,bit-shift = <14>;
870		reg = <0x0200>;
871	};
872
873	gpt12_mux_fck: gpt12_mux_fck {
874		#clock-cells = <0>;
875		compatible = "ti,composite-mux-clock";
876		clocks = <&func_32k_ck>, <&sys_ck>, <&alt_ck>;
877		ti,bit-shift = <22>;
878		reg = <0x0244>;
879	};
880
881	gpt12_fck: gpt12_fck {
882		#clock-cells = <0>;
883		compatible = "ti,composite-clock";
884		clocks = <&gpt12_gate_fck>, <&gpt12_mux_fck>;
885	};
886
887	mcbsp1_ick: mcbsp1_ick {
888		#clock-cells = <0>;
889		compatible = "ti,omap3-interface-clock";
890		clocks = <&l4_ck>;
891		ti,bit-shift = <15>;
892		reg = <0x0210>;
893	};
894
895	mcbsp1_gate_fck: mcbsp1_gate_fck {
896		#clock-cells = <0>;
897		compatible = "ti,composite-gate-clock";
898		clocks = <&mcbsp_clks>;
899		ti,bit-shift = <15>;
900		reg = <0x0200>;
901	};
902
903	mcbsp2_ick: mcbsp2_ick {
904		#clock-cells = <0>;
905		compatible = "ti,omap3-interface-clock";
906		clocks = <&l4_ck>;
907		ti,bit-shift = <16>;
908		reg = <0x0210>;
909	};
910
911	mcbsp2_gate_fck: mcbsp2_gate_fck {
912		#clock-cells = <0>;
913		compatible = "ti,composite-gate-clock";
914		clocks = <&mcbsp_clks>;
915		ti,bit-shift = <16>;
916		reg = <0x0200>;
917	};
918
919	mcspi1_ick: mcspi1_ick {
920		#clock-cells = <0>;
921		compatible = "ti,omap3-interface-clock";
922		clocks = <&l4_ck>;
923		ti,bit-shift = <17>;
924		reg = <0x0210>;
925	};
926
927	mcspi1_fck: mcspi1_fck {
928		#clock-cells = <0>;
929		compatible = "ti,wait-gate-clock";
930		clocks = <&func_48m_ck>;
931		ti,bit-shift = <17>;
932		reg = <0x0200>;
933	};
934
935	mcspi2_ick: mcspi2_ick {
936		#clock-cells = <0>;
937		compatible = "ti,omap3-interface-clock";
938		clocks = <&l4_ck>;
939		ti,bit-shift = <18>;
940		reg = <0x0210>;
941	};
942
943	mcspi2_fck: mcspi2_fck {
944		#clock-cells = <0>;
945		compatible = "ti,wait-gate-clock";
946		clocks = <&func_48m_ck>;
947		ti,bit-shift = <18>;
948		reg = <0x0200>;
949	};
950
951	uart1_ick: uart1_ick {
952		#clock-cells = <0>;
953		compatible = "ti,omap3-interface-clock";
954		clocks = <&l4_ck>;
955		ti,bit-shift = <21>;
956		reg = <0x0210>;
957	};
958
959	uart1_fck: uart1_fck {
960		#clock-cells = <0>;
961		compatible = "ti,wait-gate-clock";
962		clocks = <&func_48m_ck>;
963		ti,bit-shift = <21>;
964		reg = <0x0200>;
965	};
966
967	uart2_ick: uart2_ick {
968		#clock-cells = <0>;
969		compatible = "ti,omap3-interface-clock";
970		clocks = <&l4_ck>;
971		ti,bit-shift = <22>;
972		reg = <0x0210>;
973	};
974
975	uart2_fck: uart2_fck {
976		#clock-cells = <0>;
977		compatible = "ti,wait-gate-clock";
978		clocks = <&func_48m_ck>;
979		ti,bit-shift = <22>;
980		reg = <0x0200>;
981	};
982
983	uart3_ick: uart3_ick {
984		#clock-cells = <0>;
985		compatible = "ti,omap3-interface-clock";
986		clocks = <&l4_ck>;
987		ti,bit-shift = <2>;
988		reg = <0x0214>;
989	};
990
991	uart3_fck: uart3_fck {
992		#clock-cells = <0>;
993		compatible = "ti,wait-gate-clock";
994		clocks = <&func_48m_ck>;
995		ti,bit-shift = <2>;
996		reg = <0x0204>;
997	};
998
999	gpios_ick: gpios_ick {
1000		#clock-cells = <0>;
1001		compatible = "ti,omap3-interface-clock";
1002		clocks = <&sys_ck>;
1003		ti,bit-shift = <2>;
1004		reg = <0x0410>;
1005	};
1006
1007	gpios_fck: gpios_fck {
1008		#clock-cells = <0>;
1009		compatible = "ti,wait-gate-clock";
1010		clocks = <&func_32k_ck>;
1011		ti,bit-shift = <2>;
1012		reg = <0x0400>;
1013	};
1014
1015	mpu_wdt_ick: mpu_wdt_ick {
1016		#clock-cells = <0>;
1017		compatible = "ti,omap3-interface-clock";
1018		clocks = <&sys_ck>;
1019		ti,bit-shift = <3>;
1020		reg = <0x0410>;
1021	};
1022
1023	mpu_wdt_fck: mpu_wdt_fck {
1024		#clock-cells = <0>;
1025		compatible = "ti,wait-gate-clock";
1026		clocks = <&func_32k_ck>;
1027		ti,bit-shift = <3>;
1028		reg = <0x0400>;
1029	};
1030
1031	sync_32k_ick: sync_32k_ick {
1032		#clock-cells = <0>;
1033		compatible = "ti,omap3-interface-clock";
1034		clocks = <&sys_ck>;
1035		ti,bit-shift = <1>;
1036		reg = <0x0410>;
1037	};
1038
1039	wdt1_ick: wdt1_ick {
1040		#clock-cells = <0>;
1041		compatible = "ti,omap3-interface-clock";
1042		clocks = <&sys_ck>;
1043		ti,bit-shift = <4>;
1044		reg = <0x0410>;
1045	};
1046
1047	omapctrl_ick: omapctrl_ick {
1048		#clock-cells = <0>;
1049		compatible = "ti,omap3-interface-clock";
1050		clocks = <&sys_ck>;
1051		ti,bit-shift = <5>;
1052		reg = <0x0410>;
1053	};
1054
1055	cam_fck: cam_fck {
1056		#clock-cells = <0>;
1057		compatible = "ti,gate-clock";
1058		clocks = <&func_96m_ck>;
1059		ti,bit-shift = <31>;
1060		reg = <0x0200>;
1061	};
1062
1063	cam_ick: cam_ick {
1064		#clock-cells = <0>;
1065		compatible = "ti,omap3-no-wait-interface-clock";
1066		clocks = <&l4_ck>;
1067		ti,bit-shift = <31>;
1068		reg = <0x0210>;
1069	};
1070
1071	mailboxes_ick: mailboxes_ick {
1072		#clock-cells = <0>;
1073		compatible = "ti,omap3-interface-clock";
1074		clocks = <&l4_ck>;
1075		ti,bit-shift = <30>;
1076		reg = <0x0210>;
1077	};
1078
1079	wdt4_ick: wdt4_ick {
1080		#clock-cells = <0>;
1081		compatible = "ti,omap3-interface-clock";
1082		clocks = <&l4_ck>;
1083		ti,bit-shift = <29>;
1084		reg = <0x0210>;
1085	};
1086
1087	wdt4_fck: wdt4_fck {
1088		#clock-cells = <0>;
1089		compatible = "ti,wait-gate-clock";
1090		clocks = <&func_32k_ck>;
1091		ti,bit-shift = <29>;
1092		reg = <0x0200>;
1093	};
1094
1095	mspro_ick: mspro_ick {
1096		#clock-cells = <0>;
1097		compatible = "ti,omap3-interface-clock";
1098		clocks = <&l4_ck>;
1099		ti,bit-shift = <27>;
1100		reg = <0x0210>;
1101	};
1102
1103	mspro_fck: mspro_fck {
1104		#clock-cells = <0>;
1105		compatible = "ti,wait-gate-clock";
1106		clocks = <&func_96m_ck>;
1107		ti,bit-shift = <27>;
1108		reg = <0x0200>;
1109	};
1110
1111	fac_ick: fac_ick {
1112		#clock-cells = <0>;
1113		compatible = "ti,omap3-interface-clock";
1114		clocks = <&l4_ck>;
1115		ti,bit-shift = <25>;
1116		reg = <0x0210>;
1117	};
1118
1119	fac_fck: fac_fck {
1120		#clock-cells = <0>;
1121		compatible = "ti,wait-gate-clock";
1122		clocks = <&func_12m_ck>;
1123		ti,bit-shift = <25>;
1124		reg = <0x0200>;
1125	};
1126
1127	hdq_ick: hdq_ick {
1128		#clock-cells = <0>;
1129		compatible = "ti,omap3-interface-clock";
1130		clocks = <&l4_ck>;
1131		ti,bit-shift = <23>;
1132		reg = <0x0210>;
1133	};
1134
1135	hdq_fck: hdq_fck {
1136		#clock-cells = <0>;
1137		compatible = "ti,wait-gate-clock";
1138		clocks = <&func_12m_ck>;
1139		ti,bit-shift = <23>;
1140		reg = <0x0200>;
1141	};
1142
1143	i2c1_ick: i2c1_ick {
1144		#clock-cells = <0>;
1145		compatible = "ti,omap3-interface-clock";
1146		clocks = <&l4_ck>;
1147		ti,bit-shift = <19>;
1148		reg = <0x0210>;
1149	};
1150
1151	i2c2_ick: i2c2_ick {
1152		#clock-cells = <0>;
1153		compatible = "ti,omap3-interface-clock";
1154		clocks = <&l4_ck>;
1155		ti,bit-shift = <20>;
1156		reg = <0x0210>;
1157	};
1158
1159	gpmc_fck: gpmc_fck {
1160		#clock-cells = <0>;
1161		compatible = "ti,fixed-factor-clock";
1162		clocks = <&core_l3_ck>;
1163		ti,clock-div = <1>;
1164		ti,autoidle-shift = <1>;
1165		reg = <0x0238>;
1166		ti,clock-mult = <1>;
1167	};
1168
1169	sdma_fck: sdma_fck {
1170		#clock-cells = <0>;
1171		compatible = "fixed-factor-clock";
1172		clocks = <&core_l3_ck>;
1173		clock-mult = <1>;
1174		clock-div = <1>;
1175	};
1176
1177	sdma_ick: sdma_ick {
1178		#clock-cells = <0>;
1179		compatible = "ti,fixed-factor-clock";
1180		clocks = <&core_l3_ck>;
1181		ti,clock-div = <1>;
1182		ti,autoidle-shift = <0>;
1183		reg = <0x0238>;
1184		ti,clock-mult = <1>;
1185	};
1186
1187	sdrc_ick: sdrc_ick {
1188		#clock-cells = <0>;
1189		compatible = "ti,fixed-factor-clock";
1190		clocks = <&core_l3_ck>;
1191		ti,clock-div = <1>;
1192		ti,autoidle-shift = <2>;
1193		reg = <0x0238>;
1194		ti,clock-mult = <1>;
1195	};
1196
1197	des_ick: des_ick {
1198		#clock-cells = <0>;
1199		compatible = "ti,omap3-interface-clock";
1200		clocks = <&l4_ck>;
1201		ti,bit-shift = <0>;
1202		reg = <0x021c>;
1203	};
1204
1205	sha_ick: sha_ick {
1206		#clock-cells = <0>;
1207		compatible = "ti,omap3-interface-clock";
1208		clocks = <&l4_ck>;
1209		ti,bit-shift = <1>;
1210		reg = <0x021c>;
1211	};
1212
1213	rng_ick: rng_ick {
1214		#clock-cells = <0>;
1215		compatible = "ti,omap3-interface-clock";
1216		clocks = <&l4_ck>;
1217		ti,bit-shift = <2>;
1218		reg = <0x021c>;
1219	};
1220
1221	aes_ick: aes_ick {
1222		#clock-cells = <0>;
1223		compatible = "ti,omap3-interface-clock";
1224		clocks = <&l4_ck>;
1225		ti,bit-shift = <3>;
1226		reg = <0x021c>;
1227	};
1228
1229	pka_ick: pka_ick {
1230		#clock-cells = <0>;
1231		compatible = "ti,omap3-interface-clock";
1232		clocks = <&l4_ck>;
1233		ti,bit-shift = <4>;
1234		reg = <0x021c>;
1235	};
1236
1237	usb_fck: usb_fck {
1238		#clock-cells = <0>;
1239		compatible = "ti,wait-gate-clock";
1240		clocks = <&func_48m_ck>;
1241		ti,bit-shift = <0>;
1242		reg = <0x0204>;
1243	};
1244};
1245