imx6q-dmo-edmqmx6.dts revision 284090 
1/*
2 * Copyright 2013 Data Modul AG
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12/dts-v1/;
13
14#include <dt-bindings/gpio/gpio.h>
15#include "imx6q.dtsi"
16
17/ {
18	model = "Data Modul eDM-QMX6 Board";
19	compatible = "dmo,imx6q-edmqmx6", "fsl,imx6q";
20
21	chosen {
22		stdout-path = &uart2;
23	};
24
25	aliases {
26		gpio7 = &stmpe_gpio1;
27		gpio8 = &stmpe_gpio2;
28		stmpe-i2c0 = &stmpe1;
29		stmpe-i2c1 = &stmpe2;
30	};
31
32	memory {
33		reg = <0x10000000 0x80000000>;
34	};
35
36	regulators {
37		compatible = "simple-bus";
38		#address-cells = <1>;
39		#size-cells = <0>;
40
41		reg_3p3v: regulator@0 {
42			compatible = "regulator-fixed";
43			reg = <0>;
44			regulator-name = "3P3V";
45			regulator-min-microvolt = <3300000>;
46			regulator-max-microvolt = <3300000>;
47			regulator-always-on;
48		};
49
50		reg_usb_otg_switch: regulator@1 {
51			compatible = "regulator-fixed";
52			reg = <1>;
53			regulator-name = "usb_otg_switch";
54			regulator-min-microvolt = <5000000>;
55			regulator-max-microvolt = <5000000>;
56			gpio = <&gpio7 12 0>;
57			regulator-boot-on;
58			regulator-always-on;
59		};
60
61		reg_usb_host1: regulator@2 {
62			compatible = "regulator-fixed";
63			reg = <2>;
64			regulator-name = "usb_host1_en";
65			regulator-min-microvolt = <3300000>;
66			regulator-max-microvolt = <3300000>;
67			gpio = <&gpio3 31 0>;
68			enable-active-high;
69		};
70	};
71
72	gpio-leds {
73		compatible = "gpio-leds";
74
75		led-blue {
76			label = "blue";
77			gpios = <&stmpe_gpio1 8 GPIO_ACTIVE_HIGH>;
78			linux,default-trigger = "heartbeat";
79		};
80
81		led-green {
82			label = "green";
83			gpios = <&stmpe_gpio1 9 GPIO_ACTIVE_HIGH>;
84		};
85
86		led-pink {
87			label = "pink";
88			gpios = <&stmpe_gpio1 10 GPIO_ACTIVE_HIGH>;
89		};
90
91		led-red {
92			label = "red";
93			gpios = <&stmpe_gpio1 11 GPIO_ACTIVE_HIGH>;
94		};
95	};
96};
97
98&can1 {
99	pinctrl-names = "default";
100	pinctrl-0 = <&pinctrl_can1>;
101	status = "okay";
102};
103
104&ecspi5 {
105	pinctrl-names = "default";
106	pinctrl-0 = <&pinctrl_ecspi5>;
107	fsl,spi-num-chipselects = <1>;
108	cs-gpios = <&gpio1 12 0>;
109	status = "okay";
110
111	flash: m25p80@0 {
112		compatible = "m25p80";
113		spi-max-frequency = <40000000>;
114		reg = <0>;
115	};
116};
117
118&fec {
119	pinctrl-names = "default";
120	pinctrl-0 = <&pinctrl_enet>;
121	phy-mode = "rgmii";
122	phy-reset-gpios = <&gpio1 25 0>;
123	phy-supply = <&vgen2_1v2_eth>;
124	status = "okay";
125};
126
127&i2c1 {
128	clock-frequency = <100000>;
129	pinctrl-names = "default";
130	pinctrl-0 = <&pinctrl_i2c1>;
131	status = "okay";
132};
133
134&i2c2 {
135	clock-frequency = <100000>;
136	pinctrl-names = "default";
137	pinctrl-0 = <&pinctrl_i2c2
138		     &pinctrl_stmpe1
139		     &pinctrl_stmpe2
140		     &pinctrl_pfuze>;
141	status = "okay";
142
143	pmic: pfuze100@08 {
144		compatible = "fsl,pfuze100";
145		reg = <0x08>;
146		interrupt-parent = <&gpio3>;
147		interrupts = <20 8>;
148
149		regulators {
150			sw1a_reg: sw1ab {
151				regulator-min-microvolt = <300000>;
152				regulator-max-microvolt = <1875000>;
153				regulator-boot-on;
154				regulator-always-on;
155			};
156
157			sw1c_reg: sw1c {
158				regulator-min-microvolt = <300000>;
159				regulator-max-microvolt = <1875000>;
160				regulator-boot-on;
161				regulator-always-on;
162			};
163
164			sw2_reg: sw2 {
165				regulator-min-microvolt = <800000>;
166				regulator-max-microvolt = <3300000>;
167				regulator-boot-on;
168				regulator-always-on;
169			};
170
171			sw3a_reg: sw3a {
172				regulator-min-microvolt = <400000>;
173				regulator-max-microvolt = <1975000>;
174				regulator-boot-on;
175				regulator-always-on;
176			};
177
178			sw3b_reg: sw3b {
179				regulator-min-microvolt = <400000>;
180				regulator-max-microvolt = <1975000>;
181				regulator-boot-on;
182				regulator-always-on;
183			};
184
185			sw4_reg: sw4 {
186				regulator-min-microvolt = <400000>;
187				regulator-max-microvolt = <1975000>;
188				regulator-always-on;
189			};
190
191			swbst_reg: swbst {
192				regulator-min-microvolt = <5000000>;
193				regulator-max-microvolt = <5150000>;
194				regulator-always-on;
195			};
196
197			snvs_reg: vsnvs {
198				regulator-min-microvolt = <1000000>;
199				regulator-max-microvolt = <3000000>;
200				regulator-boot-on;
201				regulator-always-on;
202			};
203
204			vref_reg: vrefddr {
205				regulator-boot-on;
206				regulator-always-on;
207			};
208
209			vgen1_reg: vgen1 {
210				regulator-min-microvolt = <800000>;
211				regulator-max-microvolt = <1550000>;
212			};
213
214			vgen2_1v2_eth: vgen2 {
215				regulator-min-microvolt = <800000>;
216				regulator-max-microvolt = <1550000>;
217			};
218
219			vdd_high_in: vgen3 {
220				regulator-min-microvolt = <1800000>;
221				regulator-max-microvolt = <3300000>;
222				regulator-boot-on;
223				regulator-always-on;
224			};
225
226			vgen4_reg: vgen4 {
227				regulator-min-microvolt = <1800000>;
228				regulator-max-microvolt = <3300000>;
229				regulator-always-on;
230			};
231
232			vgen5_reg: vgen5 {
233				regulator-min-microvolt = <1800000>;
234				regulator-max-microvolt = <3300000>;
235				regulator-always-on;
236			};
237
238			vgen6_reg: vgen6 {
239				regulator-min-microvolt = <1800000>;
240				regulator-max-microvolt = <3300000>;
241				regulator-always-on;
242			};
243		};
244	};
245
246	stmpe1: stmpe1601@40 {
247		compatible = "st,stmpe1601";
248		reg = <0x40>;
249		interrupts = <30 0>;
250		interrupt-parent = <&gpio3>;
251		vcc-supply = <&sw2_reg>;
252		vio-supply = <&sw2_reg>;
253
254		stmpe_gpio1: stmpe_gpio {
255			#gpio-cells = <2>;
256			compatible = "st,stmpe-gpio";
257		};
258	};
259
260	stmpe2: stmpe1601@44 {
261		compatible = "st,stmpe1601";
262		reg = <0x44>;
263		interrupts = <2 0>;
264		interrupt-parent = <&gpio5>;
265		vcc-supply = <&sw2_reg>;
266		vio-supply = <&sw2_reg>;
267
268		stmpe_gpio2: stmpe_gpio {
269			#gpio-cells = <2>;
270			compatible = "st,stmpe-gpio";
271		};
272	};
273
274	temp1: ad7414@4c {
275		compatible = "ad,ad7414";
276		reg = <0x4c>;
277	};
278
279	temp2: ad7414@4d {
280		compatible = "ad,ad7414";
281		reg = <0x4d>;
282	};
283
284	rtc: m41t62@68 {
285		compatible = "stm,m41t62";
286		reg = <0x68>;
287	};
288};
289
290&i2c3 {
291	clock-frequency = <100000>;
292	pinctrl-names = "default";
293	pinctrl-0 = <&pinctrl_i2c3>;
294	status = "okay";
295};
296
297&iomuxc {
298	pinctrl-names = "default";
299	pinctrl-0 = <&pinctrl_hog>;
300
301	imx6q-dmo-edmqmx6 {
302		pinctrl_hog: hoggrp {
303			fsl,pins = <
304				MX6QDL_PAD_EIM_A16__GPIO2_IO22 0x80000000
305				MX6QDL_PAD_EIM_A17__GPIO2_IO21 0x80000000
306			>;
307		};
308
309		pinctrl_can1: can1grp {
310			fsl,pins = <
311				MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX	0x1b0b0
312				MX6QDL_PAD_GPIO_7__FLEXCAN1_TX		0x1b0b0
313			>;
314		};
315
316		pinctrl_ecspi5: ecspi5rp-1 {
317			fsl,pins = <
318				MX6QDL_PAD_SD1_DAT0__ECSPI5_MISO	0x80000000
319				MX6QDL_PAD_SD1_CMD__ECSPI5_MOSI		0x80000000
320				MX6QDL_PAD_SD1_CLK__ECSPI5_SCLK		0x80000000
321				MX6QDL_PAD_SD2_DAT3__GPIO1_IO12		0x80000000
322			>;
323		};
324
325		pinctrl_enet: enetgrp {
326			fsl,pins = <
327				MX6QDL_PAD_RGMII_RXC__RGMII_RXC		0x1b0b0
328				MX6QDL_PAD_RGMII_RD0__RGMII_RD0		0x1b0b0
329				MX6QDL_PAD_RGMII_RD1__RGMII_RD1		0x1b0b0
330				MX6QDL_PAD_RGMII_RD2__RGMII_RD2		0x1b0b0
331				MX6QDL_PAD_RGMII_RD3__RGMII_RD3		0x1b0b0
332				MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL	0x1b0b0
333				MX6QDL_PAD_RGMII_TXC__RGMII_TXC		0x1b0b0
334				MX6QDL_PAD_RGMII_TD0__RGMII_TD0		0x1b0b0
335				MX6QDL_PAD_RGMII_TD1__RGMII_TD1		0x1b0b0
336				MX6QDL_PAD_RGMII_TD2__RGMII_TD2		0x1b0b0
337				MX6QDL_PAD_RGMII_TD3__RGMII_TD3		0x1b0b0
338				MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL	0x1b0b0
339				MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK	0x1b0b0
340				MX6QDL_PAD_ENET_MDIO__ENET_MDIO		0x1b0b0
341				MX6QDL_PAD_ENET_MDC__ENET_MDC		0x1b0b0
342				MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25	0x1b0b0
343				MX6QDL_PAD_GPIO_16__ENET_REF_CLK	0x4001b0a8
344			>;
345		};
346
347		pinctrl_i2c1: i2c1grp {
348			fsl,pins = <
349				MX6QDL_PAD_EIM_D21__I2C1_SCL		0x4001b8b1
350				MX6QDL_PAD_EIM_D28__I2C1_SDA		0x4001b8b1
351			>;
352		};
353
354		pinctrl_i2c2: i2c2grp {
355			fsl,pins = <
356				MX6QDL_PAD_EIM_EB2__I2C2_SCL		0x4001b8b1
357				MX6QDL_PAD_KEY_ROW3__I2C2_SDA		0x4001b8b1
358			>;
359		};
360
361		pinctrl_i2c3: i2c3grp {
362			fsl,pins = <
363				MX6QDL_PAD_EIM_D17__I2C3_SCL		0x4001b8b1
364				MX6QDL_PAD_GPIO_6__I2C3_SDA		0x4001b8b1
365			>;
366		};
367
368		pinctrl_pcie: pciegrp {
369			fsl,pins = <
370				MX6QDL_PAD_KEY_COL1__GPIO4_IO08		0x100b1
371			>;
372		};
373
374		pinctrl_pfuze: pfuze100grp1 {
375			fsl,pins = <
376				MX6QDL_PAD_EIM_D20__GPIO3_IO20		0x80000000
377			>;
378		};
379
380		pinctrl_stmpe1: stmpe1grp {
381			fsl,pins = <MX6QDL_PAD_EIM_D30__GPIO3_IO30 0x80000000>;
382		};
383
384		pinctrl_stmpe2: stmpe2grp {
385			fsl,pins = <MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x80000000>;
386		};
387
388		pinctrl_uart1: uart1grp {
389			fsl,pins = <
390				MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA	0x1b0b1
391				MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA	0x1b0b1
392			>;
393		};
394
395		pinctrl_uart2: uart2grp {
396			fsl,pins = <
397				MX6QDL_PAD_EIM_D26__UART2_TX_DATA	0x1b0b1
398				MX6QDL_PAD_EIM_D27__UART2_RX_DATA	0x1b0b1
399			>;
400		};
401
402		pinctrl_usbotg: usbotggrp {
403			fsl,pins = <
404				MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID	0x17059
405			>;
406		};
407
408		pinctrl_usdhc3: usdhc3grp {
409			fsl,pins = <
410				MX6QDL_PAD_SD3_CMD__SD3_CMD		0x17059
411				MX6QDL_PAD_SD3_CLK__SD3_CLK		0x10059
412				MX6QDL_PAD_SD3_DAT0__SD3_DATA0		0x17059
413				MX6QDL_PAD_SD3_DAT1__SD3_DATA1		0x17059
414				MX6QDL_PAD_SD3_DAT2__SD3_DATA2		0x17059
415				MX6QDL_PAD_SD3_DAT3__SD3_DATA3		0x17059
416			>;
417		};
418
419		pinctrl_usdhc4: usdhc4grp {
420			fsl,pins = <
421				MX6QDL_PAD_SD4_CMD__SD4_CMD		0x17059
422				MX6QDL_PAD_SD4_CLK__SD4_CLK		0x10059
423				MX6QDL_PAD_SD4_DAT0__SD4_DATA0		0x17059
424				MX6QDL_PAD_SD4_DAT1__SD4_DATA1		0x17059
425				MX6QDL_PAD_SD4_DAT2__SD4_DATA2		0x17059
426				MX6QDL_PAD_SD4_DAT3__SD4_DATA3		0x17059
427				MX6QDL_PAD_SD4_DAT4__SD4_DATA4		0x17059
428				MX6QDL_PAD_SD4_DAT5__SD4_DATA5		0x17059
429				MX6QDL_PAD_SD4_DAT6__SD4_DATA6		0x17059
430				MX6QDL_PAD_SD4_DAT7__SD4_DATA7		0x17059
431			>;
432		};
433	};
434};
435
436&pcie {
437	pinctrl-names = "default";
438	pinctrl-0 = <&pinctrl_pcie>;
439	reset-gpio = <&gpio4 8 0>;
440	status = "okay";
441};
442
443&sata {
444	status = "okay";
445};
446
447&uart1 {
448	pinctrl-names = "default";
449	pinctrl-0 = <&pinctrl_uart1>;
450	status = "okay";
451};
452
453&uart2 {
454	pinctrl-names = "default";
455	pinctrl-0 = <&pinctrl_uart2>;
456	status = "okay";
457};
458
459&usbh1 {
460	vbus-supply = <&reg_usb_host1>;
461	disable-over-current;
462	dr_mode = "host";
463	status = "okay";
464};
465
466&usbotg {
467	pinctrl-names = "default";
468	pinctrl-0 = <&pinctrl_usbotg>;
469	disable-over-current;
470	status = "okay";
471};
472
473&usdhc3 {
474	pinctrl-names = "default";
475	pinctrl-0 = <&pinctrl_usdhc3>;
476	vmmc-supply = <&reg_3p3v>;
477	status = "okay";
478};
479
480&usdhc4 {
481	pinctrl-names = "default";
482	pinctrl-0 = <&pinctrl_usdhc4>;
483	vmmc-supply = <&reg_3p3v>;
484	non-removable;
485	bus-width = <8>;
486	status = "okay";
487};
488