imx1.dtsi revision 284090 
1/*
2 * Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru>
3 *
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
7 *
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
10 */
11
12#include "skeleton.dtsi"
13#include "imx1-pinfunc.h"
14
15#include <dt-bindings/clock/imx1-clock.h>
16#include <dt-bindings/gpio/gpio.h>
17#include <dt-bindings/interrupt-controller/irq.h>
18
19/ {
20	aliases {
21		gpio0 = &gpio1;
22		gpio1 = &gpio2;
23		gpio2 = &gpio3;
24		gpio3 = &gpio4;
25		i2c0 = &i2c;
26		serial0 = &uart1;
27		serial1 = &uart2;
28		serial2 = &uart3;
29		spi0 = &cspi1;
30		spi1 = &cspi2;
31	};
32
33	aitc: aitc-interrupt-controller@00223000 {
34		compatible = "fsl,imx1-aitc", "fsl,avic";
35		interrupt-controller;
36		#interrupt-cells = <1>;
37		reg = <0x00223000 0x1000>;
38	};
39
40	cpus {
41		#size-cells = <0>;
42		#address-cells = <1>;
43
44		cpu: cpu@0 {
45			device_type = "cpu";
46			compatible = "arm,arm920t";
47			operating-points = <200000 1900000>;
48			clock-latency = <62500>;
49			clocks = <&clks IMX1_CLK_MCU>;
50			voltage-tolerance = <5>;
51		};
52	};
53
54	soc {
55		#address-cells = <1>;
56		#size-cells = <1>;
57		compatible = "simple-bus";
58		interrupt-parent = <&aitc>;
59		ranges;
60
61		aipi@00200000 {
62			compatible = "fsl,aipi-bus", "simple-bus";
63			#address-cells = <1>;
64			#size-cells = <1>;
65			reg = <0x00200000 0x10000>;
66			ranges;
67
68			gpt1: timer@00202000 {
69				compatible = "fsl,imx1-gpt";
70				reg = <0x00202000 0x1000>;
71				interrupts = <59>;
72				clocks = <&clks IMX1_CLK_HCLK>,
73					 <&clks IMX1_CLK_PER1>;
74				clock-names = "ipg", "per";
75			};
76
77			gpt2: timer@00203000 {
78				compatible = "fsl,imx1-gpt";
79				reg = <0x00203000 0x1000>;
80				interrupts = <58>;
81				clocks = <&clks IMX1_CLK_HCLK>,
82					 <&clks IMX1_CLK_PER1>;
83				clock-names = "ipg", "per";
84			};
85
86			fb: fb@00205000 {
87				compatible = "fsl,imx1-fb";
88				reg = <0x00205000 0x1000>;
89				interrupts = <14>;
90				clocks = <&clks IMX1_CLK_DUMMY>,
91					 <&clks IMX1_CLK_DUMMY>,
92					 <&clks IMX1_CLK_PER2>;
93				clock-names = "ipg", "ahb", "per";
94				status = "disabled";
95			};
96
97			uart1: serial@00206000 {
98				compatible = "fsl,imx1-uart";
99				reg = <0x00206000 0x1000>;
100				interrupts = <30 29 26>;
101				clocks = <&clks IMX1_CLK_HCLK>,
102					 <&clks IMX1_CLK_PER1>;
103				clock-names = "ipg", "per";
104				status = "disabled";
105			};
106
107			uart2: serial@00207000 {
108				compatible = "fsl,imx1-uart";
109				reg = <0x00207000 0x1000>;
110				interrupts = <24 23 20>;
111				clocks = <&clks IMX1_CLK_HCLK>,
112					 <&clks IMX1_CLK_PER1>;
113				clock-names = "ipg", "per";
114				status = "disabled";
115			};
116
117			pwm: pwm@00208000 {
118				#pwm-cells = <2>;
119				compatible = "fsl,imx1-pwm";
120				reg = <0x00208000 0x1000>;
121				interrupts = <34>;
122				clocks = <&clks IMX1_CLK_DUMMY>,
123					 <&clks IMX1_CLK_PER1>;
124				clock-names = "ipg", "per";
125			};
126
127			dma: dma@00209000 {
128				compatible = "fsl,imx1-dma";
129				reg = <0x00209000 0x1000>;
130				interrupts = <61 60>;
131				clocks = <&clks IMX1_CLK_HCLK>,
132					 <&clks IMX1_CLK_DMA_GATE>;
133				clock-names = "ipg", "ahb";
134				#dma-cells = <1>;
135			};
136
137			uart3: serial@0020a000 {
138				compatible = "fsl,imx1-uart";
139				reg = <0x0020a000 0x1000>;
140				interrupts = <54 4 1>;
141				clocks = <&clks IMX1_CLK_UART3_GATE>,
142					 <&clks IMX1_CLK_PER1>;
143				clock-names = "ipg", "per";
144				status = "disabled";
145			};
146		};
147
148		aipi@00210000 {
149			compatible = "fsl,aipi-bus", "simple-bus";
150			#address-cells = <1>;
151			#size-cells = <1>;
152			reg = <0x00210000 0x10000>;
153			ranges;
154
155			cspi1: cspi@00213000 {
156				#address-cells = <1>;
157				#size-cells = <0>;
158				compatible = "fsl,imx1-cspi";
159				reg = <0x00213000 0x1000>;
160				interrupts = <41>;
161				clocks = <&clks IMX1_CLK_DUMMY>,
162					 <&clks IMX1_CLK_PER1>;
163				clock-names = "ipg", "per";
164				status = "disabled";
165			};
166
167			i2c: i2c@00217000 {
168				#address-cells = <1>;
169				#size-cells = <0>;
170				compatible = "fsl,imx1-i2c";
171				reg = <0x00217000 0x1000>;
172				interrupts = <39>;
173				clocks = <&clks IMX1_CLK_HCLK>;
174				status = "disabled";
175			};
176
177			cspi2: cspi@00219000 {
178				#address-cells = <1>;
179				#size-cells = <0>;
180				compatible = "fsl,imx1-cspi";
181				reg = <0x00219000 0x1000>;
182				interrupts = <40>;
183				clocks = <&clks IMX1_CLK_DUMMY>,
184					 <&clks IMX1_CLK_PER1>;
185				clock-names = "ipg", "per";
186				status = "disabled";
187			};
188
189			clks: ccm@0021b000 {
190				compatible = "fsl,imx1-ccm";
191				reg = <0x0021b000 0x1000>;
192				#clock-cells = <1>;
193			};
194
195			iomuxc: iomuxc@0021c000 {
196				compatible = "fsl,imx1-iomuxc";
197				reg = <0x0021c000 0x1000>;
198				#address-cells = <1>;
199				#size-cells = <1>;
200				ranges;
201
202				gpio1: gpio@0021c000 {
203					compatible = "fsl,imx1-gpio";
204					reg = <0x0021c000 0x100>;
205					interrupts = <11>;
206					gpio-controller;
207					#gpio-cells = <2>;
208					interrupt-controller;
209					#interrupt-cells = <2>;
210				};
211
212				gpio2: gpio@0021c100 {
213					compatible = "fsl,imx1-gpio";
214					reg = <0x0021c100 0x100>;
215					interrupts = <12>;
216					gpio-controller;
217					#gpio-cells = <2>;
218					interrupt-controller;
219					#interrupt-cells = <2>;
220				};
221
222				gpio3: gpio@0021c200 {
223					compatible = "fsl,imx1-gpio";
224					reg = <0x0021c200 0x100>;
225					interrupts = <13>;
226					gpio-controller;
227					#gpio-cells = <2>;
228					interrupt-controller;
229					#interrupt-cells = <2>;
230				};
231
232				gpio4: gpio@0021c300 {
233					compatible = "fsl,imx1-gpio";
234					reg = <0x0021c300 0x100>;
235					interrupts = <62>;
236					gpio-controller;
237					#gpio-cells = <2>;
238					interrupt-controller;
239					#interrupt-cells = <2>;
240				};
241			};
242		};
243
244		weim: weim@00220000 {
245			#address-cells = <2>;
246			#size-cells = <1>;
247			compatible = "fsl,imx1-weim";
248			reg = <0x00220000 0x1000>;
249			clocks = <&clks IMX1_CLK_DUMMY>;
250			ranges = <
251				0 0 0x10000000 0x02000000
252				1 0 0x12000000 0x01000000
253				2 0 0x13000000 0x01000000
254				3 0 0x14000000 0x01000000
255				4 0 0x15000000 0x01000000
256				5 0 0x16000000 0x01000000
257			>;
258			status = "disabled";
259		};
260
261		esram: esram@00300000 {
262			compatible = "mmio-sram";
263			reg = <0x00300000 0x20000>;
264		};
265	};
266};
267