highbank.dts revision 284090 
11556Srgrimes/*
21556Srgrimes * Copyright 2011-2012 Calxeda, Inc.
31556Srgrimes *
41556Srgrimes * This program is free software; you can redistribute it and/or modify it
51556Srgrimes * under the terms and conditions of the GNU General Public License,
61556Srgrimes * version 2, as published by the Free Software Foundation.
71556Srgrimes *
81556Srgrimes * This program is distributed in the hope it will be useful, but WITHOUT
91556Srgrimes * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
101556Srgrimes * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
111556Srgrimes * more details.
121556Srgrimes *
131556Srgrimes * You should have received a copy of the GNU General Public License along with
141556Srgrimes * this program.  If not, see <http://www.gnu.org/licenses/>.
151556Srgrimes */
161556Srgrimes
171556Srgrimes/dts-v1/;
181556Srgrimes
191556Srgrimes/* First 4KB has pen for secondary cores. */
201556Srgrimes/memreserve/ 0x00000000 0x0001000;
211556Srgrimes
221556Srgrimes/ {
231556Srgrimes	model = "Calxeda Highbank";
241556Srgrimes	compatible = "calxeda,highbank";
251556Srgrimes	#address-cells = <1>;
261556Srgrimes	#size-cells = <1>;
271556Srgrimes	clock-ranges;
281556Srgrimes
291556Srgrimes	cpus {
301556Srgrimes		#address-cells = <1>;
311556Srgrimes		#size-cells = <0>;
3217987Speter
3350471Speter		cpu@900 {
341556Srgrimes			compatible = "arm,cortex-a9";
351556Srgrimes			device_type = "cpu";
361556Srgrimes			reg = <0x900>;
371556Srgrimes			next-level-cache = <&L2>;
381556Srgrimes			clocks = <&a9pll>;
391556Srgrimes			clock-names = "cpu";
401556Srgrimes			operating-points = <
411556Srgrimes				/* kHz    ignored */
421556Srgrimes				 1300000  1000000
431556Srgrimes				 1200000  1000000
441556Srgrimes				 1100000  1000000
451556Srgrimes				  800000  1000000
461556Srgrimes				  400000  1000000
471556Srgrimes				  200000  1000000
481556Srgrimes			>;
491556Srgrimes			clock-latency = <100000>;
501556Srgrimes		};
511556Srgrimes
521556Srgrimes		cpu@901 {
531556Srgrimes			compatible = "arm,cortex-a9";
54214512Sjilles			device_type = "cpu";
55214512Sjilles			reg = <0x901>;
561556Srgrimes			next-level-cache = <&L2>;
571556Srgrimes			clocks = <&a9pll>;
581556Srgrimes			clock-names = "cpu";
5990111Simp		};
6090111Simp
61200956Sjilles		cpu@902 {
62			compatible = "arm,cortex-a9";
63			device_type = "cpu";
64			reg = <0x902>;
65			next-level-cache = <&L2>;
66			clocks = <&a9pll>;
67			clock-names = "cpu";
68		};
69
70		cpu@903 {
71			compatible = "arm,cortex-a9";
72			device_type = "cpu";
73			reg = <0x903>;
74			next-level-cache = <&L2>;
75			clocks = <&a9pll>;
76			clock-names = "cpu";
77		};
78	};
79
80	memory {
81		name = "memory";
82		device_type = "memory";
83		reg = <0x00000000 0xff900000>;
84	};
85
86	soc {
87		ranges = <0x00000000 0x00000000 0xffffffff>;
88
89		memory-controller@fff00000 {
90			compatible = "calxeda,hb-ddr-ctrl";
91			reg = <0xfff00000 0x1000>;
92			interrupts = <0 91 4>;
93		};
94
95		timer@fff10600 {
96			compatible = "arm,cortex-a9-twd-timer";
97			reg = <0xfff10600 0x20>;
98			interrupts = <1 13 0xf01>;
99			clocks = <&a9periphclk>;
100		};
101
102		watchdog@fff10620 {
103			compatible = "arm,cortex-a9-twd-wdt";
104			reg = <0xfff10620 0x20>;
105			interrupts = <1 14 0xf01>;
106			clocks = <&a9periphclk>;
107		};
108
109		intc: interrupt-controller@fff11000 {
110			compatible = "arm,cortex-a9-gic";
111			#interrupt-cells = <3>;
112			#size-cells = <0>;
113			#address-cells = <1>;
114			interrupt-controller;
115			reg = <0xfff11000 0x1000>,
116			      <0xfff10100 0x100>;
117		};
118
119		L2: l2-cache {
120			compatible = "arm,pl310-cache";
121			reg = <0xfff12000 0x1000>;
122			interrupts = <0 70 4>;
123			cache-unified;
124			cache-level = <2>;
125		};
126
127		pmu {
128			compatible = "arm,cortex-a9-pmu";
129			interrupts = <0 76 4  0 75 4  0 74 4  0 73 4>;
130		};
131
132
133		sregs@fff3c200 {
134			compatible = "calxeda,hb-sregs-l2-ecc";
135			reg = <0xfff3c200 0x100>;
136			interrupts = <0 71 4  0 72 4>;
137		};
138
139	};
140};
141
142/include/ "ecx-common.dtsi"
143