bcm-cygnus.dtsi revision 284090
1128612Sphk/* 2128612Sphk * BSD LICENSE 3128612Sphk * 4139103Sru * Copyright(c) 2014 Broadcom Corporation. All rights reserved. 5128612Sphk * 6128612Sphk * Redistribution and use in source and binary forms, with or without 7128612Sphk * modification, are permitted provided that the following conditions 8 * are met: 9 * 10 * * Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * * Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in 14 * the documentation and/or other materials provided with the 15 * distribution. 16 * * Neither the name of Broadcom Corporation nor the names of its 17 * contributors may be used to endorse or promote products derived 18 * from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 21 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 22 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 23 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 24 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 25 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 26 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 30 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <dt-bindings/interrupt-controller/arm-gic.h> 34#include <dt-bindings/interrupt-controller/irq.h> 35 36#include "skeleton.dtsi" 37 38/ { 39 compatible = "brcm,cygnus"; 40 model = "Broadcom Cygnus SoC"; 41 interrupt-parent = <&gic>; 42 43 cpus { 44 #address-cells = <1>; 45 #size-cells = <0>; 46 47 cpu@0 { 48 device_type = "cpu"; 49 compatible = "arm,cortex-a9"; 50 next-level-cache = <&L2>; 51 reg = <0x0>; 52 }; 53 }; 54 55 /include/ "bcm-cygnus-clock.dtsi" 56 57 amba { 58 #address-cells = <1>; 59 #size-cells = <1>; 60 compatible = "arm,amba-bus", "simple-bus"; 61 interrupt-parent = <&gic>; 62 ranges; 63 64 wdt@18009000 { 65 compatible = "arm,sp805" , "arm,primecell"; 66 reg = <0x18009000 0x1000>; 67 interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>; 68 clocks = <&axi81_clk>; 69 clock-names = "apb_pclk"; 70 }; 71 }; 72 73 i2c0: i2c@18008000 { 74 compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c"; 75 reg = <0x18008000 0x100>; 76 #address-cells = <1>; 77 #size-cells = <0>; 78 interrupts = <GIC_SPI 85 IRQ_TYPE_NONE>; 79 clock-frequency = <100000>; 80 status = "disabled"; 81 }; 82 83 i2c1: i2c@1800b000 { 84 compatible = "brcm,cygnus-iproc-i2c", "brcm,iproc-i2c"; 85 reg = <0x1800b000 0x100>; 86 #address-cells = <1>; 87 #size-cells = <0>; 88 interrupts = <GIC_SPI 86 IRQ_TYPE_NONE>; 89 clock-frequency = <100000>; 90 status = "disabled"; 91 }; 92 93 uart0: serial@18020000 { 94 compatible = "snps,dw-apb-uart"; 95 reg = <0x18020000 0x100>; 96 reg-shift = <2>; 97 reg-io-width = <4>; 98 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; 99 clocks = <&axi81_clk>; 100 clock-frequency = <100000000>; 101 status = "disabled"; 102 }; 103 104 uart1: serial@18021000 { 105 compatible = "snps,dw-apb-uart"; 106 reg = <0x18021000 0x100>; 107 reg-shift = <2>; 108 reg-io-width = <4>; 109 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; 110 clocks = <&axi81_clk>; 111 clock-frequency = <100000000>; 112 status = "disabled"; 113 }; 114 115 uart2: serial@18022000 { 116 compatible = "snps,dw-apb-uart"; 117 reg = <0x18020000 0x100>; 118 reg-shift = <2>; 119 reg-io-width = <4>; 120 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; 121 clocks = <&axi81_clk>; 122 clock-frequency = <100000000>; 123 status = "disabled"; 124 }; 125 126 uart3: serial@18023000 { 127 compatible = "snps,dw-apb-uart"; 128 reg = <0x18023000 0x100>; 129 reg-shift = <2>; 130 reg-io-width = <4>; 131 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>; 132 clocks = <&axi81_clk>; 133 clock-frequency = <100000000>; 134 status = "disabled"; 135 }; 136 137 gic: interrupt-controller@19021000 { 138 compatible = "arm,cortex-a9-gic"; 139 #interrupt-cells = <3>; 140 #address-cells = <0>; 141 interrupt-controller; 142 reg = <0x19021000 0x1000>, 143 <0x19020100 0x100>; 144 }; 145 146 L2: l2-cache { 147 compatible = "arm,pl310-cache"; 148 reg = <0x19022000 0x1000>; 149 cache-unified; 150 cache-level = <2>; 151 }; 152 153 timer@19020200 { 154 compatible = "arm,cortex-a9-global-timer"; 155 reg = <0x19020200 0x100>; 156 interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>; 157 clocks = <&periph_clk>; 158 }; 159 160}; 161