armada-xp-db.dts revision 284090
1/* 2 * Device Tree file for Marvell Armada XP evaluation board 3 * (DB-78460-BP) 4 * 5 * Copyright (C) 2012-2014 Marvell 6 * 7 * Lior Amsalem <alior@marvell.com> 8 * Gregory CLEMENT <gregory.clement@free-electrons.com> 9 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com> 10 * 11 * This file is dual-licensed: you can use it either under the terms 12 * of the GPL or the X11 license, at your option. Note that this dual 13 * licensing only applies to this file, and not this project as a 14 * whole. 15 * 16 * a) This file is free software; you can redistribute it and/or 17 * modify it under the terms of the GNU General Public License as 18 * published by the Free Software Foundation; either version 2 of the 19 * License, or (at your option) any later version. 20 * 21 * This file is distributed in the hope that it will be useful 22 * but WITHOUT ANY WARRANTY; without even the implied warranty of 23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 24 * GNU General Public License for more details. 25 * 26 * Or, alternatively 27 * 28 * b) Permission is hereby granted, free of charge, to any person 29 * obtaining a copy of this software and associated documentation 30 * files (the "Software"), to deal in the Software without 31 * restriction, including without limitation the rights to use 32 * copy, modify, merge, publish, distribute, sublicense, and/or 33 * sell copies of the Software, and to permit persons to whom the 34 * Software is furnished to do so, subject to the following 35 * conditions: 36 * 37 * The above copyright notice and this permission notice shall be 38 * included in all copies or substantial portions of the Software. 39 * 40 * THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND 41 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES 42 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 43 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT 44 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY 45 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 46 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 47 * OTHER DEALINGS IN THE SOFTWARE. 48 * 49 * Note: this Device Tree assumes that the bootloader has remapped the 50 * internal registers to 0xf1000000 (instead of the default 51 * 0xd0000000). The 0xf1000000 is the default used by the recent, 52 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier 53 * boards were delivered with an older version of the bootloader that 54 * left internal registers mapped at 0xd0000000. If you are in this 55 * situation, you should either update your bootloader (preferred 56 * solution) or the below Device Tree should be adjusted. 57 */ 58 59/dts-v1/; 60#include "armada-xp-mv78460.dtsi" 61 62/ { 63 model = "Marvell Armada XP Evaluation Board"; 64 compatible = "marvell,axp-db", "marvell,armadaxp-mv78460", "marvell,armadaxp", "marvell,armada-370-xp"; 65 66 chosen { 67 bootargs = "console=ttyS0,115200 earlyprintk"; 68 }; 69 70 memory { 71 device_type = "memory"; 72 reg = <0 0x00000000 0 0x80000000>; /* 2 GB */ 73 }; 74 75 soc { 76 ranges = <MBUS_ID(0xf0, 0x01) 0 0 0xf1000000 0x100000 77 MBUS_ID(0x01, 0x1d) 0 0 0xfff00000 0x100000 78 MBUS_ID(0x01, 0x2f) 0 0 0xf0000000 0x1000000>; 79 80 devbus-bootcs { 81 status = "okay"; 82 83 /* Device Bus parameters are required */ 84 85 /* Read parameters */ 86 devbus,bus-width = <16>; 87 devbus,turn-off-ps = <60000>; 88 devbus,badr-skew-ps = <0>; 89 devbus,acc-first-ps = <124000>; 90 devbus,acc-next-ps = <248000>; 91 devbus,rd-setup-ps = <0>; 92 devbus,rd-hold-ps = <0>; 93 94 /* Write parameters */ 95 devbus,sync-enable = <0>; 96 devbus,wr-high-ps = <60000>; 97 devbus,wr-low-ps = <60000>; 98 devbus,ale-wr-ps = <60000>; 99 100 /* NOR 16 MiB */ 101 nor@0 { 102 compatible = "cfi-flash"; 103 reg = <0 0x1000000>; 104 bank-width = <2>; 105 }; 106 }; 107 108 pcie-controller { 109 status = "okay"; 110 111 /* 112 * All 6 slots are physically present as 113 * standard PCIe slots on the board. 114 */ 115 pcie@1,0 { 116 /* Port 0, Lane 0 */ 117 status = "okay"; 118 }; 119 pcie@2,0 { 120 /* Port 0, Lane 1 */ 121 status = "okay"; 122 }; 123 pcie@3,0 { 124 /* Port 0, Lane 2 */ 125 status = "okay"; 126 }; 127 pcie@4,0 { 128 /* Port 0, Lane 3 */ 129 status = "okay"; 130 }; 131 pcie@9,0 { 132 /* Port 2, Lane 0 */ 133 status = "okay"; 134 }; 135 pcie@10,0 { 136 /* Port 3, Lane 0 */ 137 status = "okay"; 138 }; 139 }; 140 141 internal-regs { 142 serial@12000 { 143 status = "okay"; 144 }; 145 serial@12100 { 146 status = "okay"; 147 }; 148 serial@12200 { 149 status = "okay"; 150 }; 151 serial@12300 { 152 status = "okay"; 153 }; 154 155 sata@a0000 { 156 nr-ports = <2>; 157 status = "okay"; 158 }; 159 160 mdio { 161 phy0: ethernet-phy@0 { 162 reg = <0>; 163 }; 164 165 phy1: ethernet-phy@1 { 166 reg = <1>; 167 }; 168 169 phy2: ethernet-phy@2 { 170 reg = <25>; 171 }; 172 173 phy3: ethernet-phy@3 { 174 reg = <27>; 175 }; 176 }; 177 178 ethernet@70000 { 179 status = "okay"; 180 phy = <&phy0>; 181 phy-mode = "rgmii-id"; 182 }; 183 ethernet@74000 { 184 status = "okay"; 185 phy = <&phy1>; 186 phy-mode = "rgmii-id"; 187 }; 188 ethernet@30000 { 189 status = "okay"; 190 phy = <&phy2>; 191 phy-mode = "sgmii"; 192 }; 193 ethernet@34000 { 194 status = "okay"; 195 phy = <&phy3>; 196 phy-mode = "sgmii"; 197 }; 198 199 mvsdio@d4000 { 200 pinctrl-0 = <&sdio_pins>; 201 pinctrl-names = "default"; 202 status = "okay"; 203 /* No CD or WP GPIOs */ 204 broken-cd; 205 }; 206 207 usb@50000 { 208 status = "okay"; 209 }; 210 211 usb@51000 { 212 status = "okay"; 213 }; 214 215 usb@52000 { 216 status = "okay"; 217 }; 218 219 spi0: spi@10600 { 220 status = "okay"; 221 222 spi-flash@0 { 223 #address-cells = <1>; 224 #size-cells = <1>; 225 compatible = "m25p64"; 226 reg = <0>; /* Chip select 0 */ 227 spi-max-frequency = <20000000>; 228 }; 229 }; 230 }; 231 }; 232}; 233