armada-375.dtsi revision 284090 
1/*
2 * Device Tree Include file for Marvell Armada 375 family SoC
3 *
4 * Copyright (C) 2014 Marvell
5 *
6 * Gregory CLEMENT <gregory.clement@free-electrons.com>
7 * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
8 *
9 * This file is dual-licensed: you can use it either under the terms
10 * of the GPL or the X11 license, at your option. Note that this dual
11 * licensing only applies to this file, and not this project as a
12 * whole.
13 *
14 *  a) This file is free software; you can redistribute it and/or
15 *     modify it under the terms of the GNU General Public License as
16 *     published by the Free Software Foundation; either version 2 of the
17 *     License, or (at your option) any later version.
18 *
19 *     This file is distributed in the hope that it will be useful
20 *     but WITHOUT ANY WARRANTY; without even the implied warranty of
21 *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
22 *     GNU General Public License for more details.
23 *
24 * Or, alternatively
25 *
26 *  b) Permission is hereby granted, free of charge, to any person
27 *     obtaining a copy of this software and associated documentation
28 *     files (the "Software"), to deal in the Software without
29 *     restriction, including without limitation the rights to use
30 *     copy, modify, merge, publish, distribute, sublicense, and/or
31 *     sell copies of the Software, and to permit persons to whom the
32 *     Software is furnished to do so, subject to the following
33 *     conditions:
34 *
35 *     The above copyright notice and this permission notice shall be
36 *     included in all copies or substantial portions of the Software.
37 *
38 *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
39 *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40 *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41 *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42 *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
43 *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44 *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45 *     OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48#include "skeleton.dtsi"
49#include <dt-bindings/interrupt-controller/arm-gic.h>
50#include <dt-bindings/interrupt-controller/irq.h>
51#include <dt-bindings/phy/phy.h>
52
53#define MBUS_ID(target,attributes) (((target) << 24) | ((attributes) << 16))
54
55/ {
56	model = "Marvell Armada 375 family SoC";
57	compatible = "marvell,armada375";
58
59	aliases {
60		gpio0 = &gpio0;
61		gpio1 = &gpio1;
62		gpio2 = &gpio2;
63		ethernet0 = &eth0;
64		ethernet1 = &eth1;
65	};
66
67	clocks {
68		/* 2 GHz fixed main PLL */
69		mainpll: mainpll {
70			compatible = "fixed-clock";
71			#clock-cells = <0>;
72			clock-frequency = <2000000000>;
73		};
74		/* 25 MHz reference crystal */
75		refclk: oscillator {
76			compatible = "fixed-clock";
77			#clock-cells = <0>;
78			clock-frequency = <25000000>;
79		};
80	};
81
82	cpus {
83		#address-cells = <1>;
84		#size-cells = <0>;
85		enable-method = "marvell,armada-375-smp";
86
87		cpu@0 {
88			device_type = "cpu";
89			compatible = "arm,cortex-a9";
90			reg = <0>;
91		};
92		cpu@1 {
93			device_type = "cpu";
94			compatible = "arm,cortex-a9";
95			reg = <1>;
96		};
97	};
98
99	soc {
100		compatible = "marvell,armada375-mbus", "simple-bus";
101		#address-cells = <2>;
102		#size-cells = <1>;
103		controller = <&mbusc>;
104		interrupt-parent = <&gic>;
105		pcie-mem-aperture = <0xe0000000 0x8000000>;
106		pcie-io-aperture  = <0xe8000000 0x100000>;
107
108		bootrom {
109			compatible = "marvell,bootrom";
110			reg = <MBUS_ID(0x01, 0x1d) 0 0x100000>;
111		};
112
113		devbus-bootcs {
114			compatible = "marvell,mvebu-devbus";
115			reg = <MBUS_ID(0xf0, 0x01) 0x10400 0x8>;
116			ranges = <0 MBUS_ID(0x01, 0x2f) 0 0xffffffff>;
117			#address-cells = <1>;
118			#size-cells = <1>;
119			clocks = <&coreclk 0>;
120			status = "disabled";
121		};
122
123		devbus-cs0 {
124			compatible = "marvell,mvebu-devbus";
125			reg = <MBUS_ID(0xf0, 0x01) 0x10408 0x8>;
126			ranges = <0 MBUS_ID(0x01, 0x3e) 0 0xffffffff>;
127			#address-cells = <1>;
128			#size-cells = <1>;
129			clocks = <&coreclk 0>;
130			status = "disabled";
131		};
132
133		devbus-cs1 {
134			compatible = "marvell,mvebu-devbus";
135			reg = <MBUS_ID(0xf0, 0x01) 0x10410 0x8>;
136			ranges = <0 MBUS_ID(0x01, 0x3d) 0 0xffffffff>;
137			#address-cells = <1>;
138			#size-cells = <1>;
139			clocks = <&coreclk 0>;
140			status = "disabled";
141		};
142
143		devbus-cs2 {
144			compatible = "marvell,mvebu-devbus";
145			reg = <MBUS_ID(0xf0, 0x01) 0x10418 0x8>;
146			ranges = <0 MBUS_ID(0x01, 0x3b) 0 0xffffffff>;
147			#address-cells = <1>;
148			#size-cells = <1>;
149			clocks = <&coreclk 0>;
150			status = "disabled";
151		};
152
153		devbus-cs3 {
154			compatible = "marvell,mvebu-devbus";
155			reg = <MBUS_ID(0xf0, 0x01) 0x10420 0x8>;
156			ranges = <0 MBUS_ID(0x01, 0x37) 0 0xffffffff>;
157			#address-cells = <1>;
158			#size-cells = <1>;
159			clocks = <&coreclk 0>;
160			status = "disabled";
161		};
162
163		internal-regs {
164			compatible = "simple-bus";
165			#address-cells = <1>;
166			#size-cells = <1>;
167			ranges = <0 MBUS_ID(0xf0, 0x01) 0 0x100000>;
168
169			L2: cache-controller@8000 {
170				compatible = "arm,pl310-cache";
171				reg = <0x8000 0x1000>;
172				cache-unified;
173				cache-level = <2>;
174			};
175
176			scu@c000 {
177				compatible = "arm,cortex-a9-scu";
178				reg = <0xc000 0x58>;
179			};
180
181			timer@c600 {
182				compatible = "arm,cortex-a9-twd-timer";
183				reg = <0xc600 0x20>;
184				interrupts = <GIC_PPI 13 (IRQ_TYPE_EDGE_RISING | GIC_CPU_MASK_SIMPLE(2))>;
185				clocks = <&coreclk 2>;
186			};
187
188			gic: interrupt-controller@d000 {
189				compatible = "arm,cortex-a9-gic";
190				#interrupt-cells = <3>;
191				#size-cells = <0>;
192				interrupt-controller;
193				reg = <0xd000 0x1000>,
194				      <0xc100 0x100>;
195			};
196
197			mdio {
198				#address-cells = <1>;
199				#size-cells = <0>;
200				compatible = "marvell,orion-mdio";
201				reg = <0xc0054 0x4>;
202				clocks = <&gateclk 19>;
203			};
204
205			/* Network controller */
206			ethernet@f0000 {
207				compatible = "marvell,armada-375-pp2";
208				reg = <0xf0000 0xa000>, /* Packet Processor regs */
209				      <0xc0000 0x3060>, /* LMS regs */
210				      <0xc4000 0x100>,  /* eth0 regs */
211				      <0xc5000 0x100>;  /* eth1 regs */
212				clocks = <&gateclk 3>, <&gateclk 19>;
213				clock-names = "pp_clk", "gop_clk";
214				status = "disabled";
215
216				eth0: eth0@c4000 {
217					interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
218					port-id = <0>;
219					status = "disabled";
220				};
221
222				eth1: eth1@c5000 {
223					interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
224					port-id = <1>;
225					status = "disabled";
226				};
227			};
228
229			rtc@10300 {
230				compatible = "marvell,orion-rtc";
231				reg = <0x10300 0x20>;
232				interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>;
233			};
234
235			spi0: spi@10600 {
236				compatible = "marvell,orion-spi";
237				reg = <0x10600 0x50>;
238				#address-cells = <1>;
239				#size-cells = <0>;
240				cell-index = <0>;
241				interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
242				clocks = <&coreclk 0>;
243				status = "disabled";
244			};
245
246			spi1: spi@10680 {
247				compatible = "marvell,orion-spi";
248				reg = <0x10680 0x50>;
249				#address-cells = <1>;
250				#size-cells = <0>;
251				cell-index = <1>;
252				interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
253				clocks = <&coreclk 0>;
254				status = "disabled";
255			};
256
257			i2c0: i2c@11000 {
258				compatible = "marvell,mv64xxx-i2c";
259				reg = <0x11000 0x20>;
260				#address-cells = <1>;
261				#size-cells = <0>;
262				interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
263				timeout-ms = <1000>;
264				clocks = <&coreclk 0>;
265				status = "disabled";
266			};
267
268			i2c1: i2c@11100 {
269				compatible = "marvell,mv64xxx-i2c";
270				reg = <0x11100 0x20>;
271				#address-cells = <1>;
272				#size-cells = <0>;
273				interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
274				timeout-ms = <1000>;
275				clocks = <&coreclk 0>;
276				status = "disabled";
277			};
278
279			serial@12000 {
280				compatible = "snps,dw-apb-uart";
281				reg = <0x12000 0x100>;
282				reg-shift = <2>;
283				interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
284				reg-io-width = <1>;
285				clocks = <&coreclk 0>;
286				status = "disabled";
287			};
288
289			serial@12100 {
290				compatible = "snps,dw-apb-uart";
291				reg = <0x12100 0x100>;
292				reg-shift = <2>;
293				interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
294				reg-io-width = <1>;
295				clocks = <&coreclk 0>;
296				status = "disabled";
297			};
298
299			pinctrl {
300				compatible = "marvell,mv88f6720-pinctrl";
301				reg = <0x18000 0x24>;
302
303				i2c0_pins: i2c0-pins {
304					marvell,pins = "mpp14",  "mpp15";
305					marvell,function = "i2c0";
306				};
307
308				i2c1_pins: i2c1-pins {
309					marvell,pins = "mpp61",  "mpp62";
310					marvell,function = "i2c1";
311				};
312
313				nand_pins: nand-pins {
314					marvell,pins = "mpp0", "mpp1", "mpp2",
315						"mpp3", "mpp4", "mpp5",
316						"mpp6", "mpp7", "mpp8",
317						"mpp9", "mpp10", "mpp11",
318						"mpp12", "mpp13";
319					marvell,function = "nand";
320				};
321
322				sdio_pins: sdio-pins {
323					marvell,pins = "mpp24",  "mpp25", "mpp26",
324						     "mpp27", "mpp28", "mpp29";
325					marvell,function = "sd";
326				};
327
328				spi0_pins: spi0-pins {
329					marvell,pins = "mpp0",  "mpp1", "mpp4",
330						     "mpp5", "mpp8", "mpp9";
331					marvell,function = "spi0";
332				};
333			};
334
335			gpio0: gpio@18100 {
336				compatible = "marvell,orion-gpio";
337				reg = <0x18100 0x40>;
338				ngpios = <32>;
339				gpio-controller;
340				#gpio-cells = <2>;
341				interrupt-controller;
342				#interrupt-cells = <2>;
343				interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
344					     <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
345					     <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>,
346					     <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
347			};
348
349			gpio1: gpio@18140 {
350				compatible = "marvell,orion-gpio";
351				reg = <0x18140 0x40>;
352				ngpios = <32>;
353				gpio-controller;
354				#gpio-cells = <2>;
355				interrupt-controller;
356				#interrupt-cells = <2>;
357				interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>,
358					     <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>,
359					     <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>,
360					     <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
361			};
362
363			gpio2: gpio@18180 {
364				compatible = "marvell,orion-gpio";
365				reg = <0x18180 0x40>;
366				ngpios = <3>;
367				gpio-controller;
368				#gpio-cells = <2>;
369				interrupt-controller;
370				#interrupt-cells = <2>;
371				interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
372			};
373
374			system-controller@18200 {
375				compatible = "marvell,armada-375-system-controller";
376				reg = <0x18200 0x100>;
377			};
378
379			gateclk: clock-gating-control@18220 {
380				compatible = "marvell,armada-375-gating-clock";
381				reg = <0x18220 0x4>;
382				clocks = <&coreclk 0>;
383				#clock-cells = <1>;
384			};
385
386			usbcluster: usb-cluster@18400 {
387				compatible = "marvell,armada-375-usb-cluster";
388				reg = <0x18400 0x4>;
389				#phy-cells = <1>;
390			};
391
392			mbusc: mbus-controller@20000 {
393				compatible = "marvell,mbus-controller";
394				reg = <0x20000 0x100>, <0x20180 0x20>;
395			};
396
397			mpic: interrupt-controller@20000 {
398				compatible = "marvell,mpic";
399				reg = <0x20a00 0x2d0>, <0x21070 0x58>;
400				#interrupt-cells = <1>;
401				#size-cells = <1>;
402				interrupt-controller;
403				msi-controller;
404				interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;
405			};
406
407			timer@20300 {
408				compatible = "marvell,armada-375-timer", "marvell,armada-370-timer";
409				reg = <0x20300 0x30>, <0x21040 0x30>;
410				interrupts-extended = <&gic  GIC_SPI  8 IRQ_TYPE_LEVEL_HIGH>,
411						      <&gic  GIC_SPI  9 IRQ_TYPE_LEVEL_HIGH>,
412						      <&gic  GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>,
413						      <&gic  GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
414						      <&mpic 5>,
415						      <&mpic 6>;
416				clocks = <&coreclk 0>, <&refclk>;
417				clock-names = "nbclk", "fixed";
418			};
419
420			watchdog@20300 {
421				compatible = "marvell,armada-375-wdt";
422				reg = <0x20300 0x34>, <0x20704 0x4>, <0x18254 0x4>;
423				clocks = <&coreclk 0>, <&refclk>;
424				clock-names = "nbclk", "fixed";
425			};
426
427			cpurst@20800 {
428				compatible = "marvell,armada-370-cpu-reset";
429				reg = <0x20800 0x10>;
430			};
431
432			coherency-fabric@21010 {
433				compatible = "marvell,armada-375-coherency-fabric";
434				reg = <0x21010 0x1c>;
435			};
436
437			usb@50000 {
438				compatible = "marvell,orion-ehci";
439				reg = <0x50000 0x500>;
440				interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
441				clocks = <&gateclk 18>;
442				phys = <&usbcluster PHY_TYPE_USB2>;
443				phy-names = "usb";
444				status = "disabled";
445			};
446
447			usb@54000 {
448				compatible = "marvell,orion-ehci";
449				reg = <0x54000 0x500>;
450				interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>;
451				clocks = <&gateclk 26>;
452				status = "disabled";
453			};
454
455			usb3@58000 {
456				compatible = "marvell,armada-375-xhci";
457				reg = <0x58000 0x20000>,<0x5b880 0x80>;
458				interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
459				clocks = <&gateclk 16>;
460				phys = <&usbcluster PHY_TYPE_USB3>;
461				phy-names = "usb";
462				status = "disabled";
463			};
464
465			xor@60800 {
466				compatible = "marvell,orion-xor";
467				reg = <0x60800 0x100
468				       0x60A00 0x100>;
469				clocks = <&gateclk 22>;
470				status = "okay";
471
472				xor00 {
473					interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
474					dmacap,memcpy;
475					dmacap,xor;
476				};
477				xor01 {
478					interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
479					dmacap,memcpy;
480					dmacap,xor;
481					dmacap,memset;
482				};
483			};
484
485			xor@60900 {
486				compatible = "marvell,orion-xor";
487				reg = <0x60900 0x100
488				       0x60b00 0x100>;
489				clocks = <&gateclk 23>;
490				status = "okay";
491
492				xor10 {
493					interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
494					dmacap,memcpy;
495					dmacap,xor;
496				};
497				xor11 {
498					interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
499					dmacap,memcpy;
500					dmacap,xor;
501					dmacap,memset;
502				};
503			};
504
505			sata@a0000 {
506				compatible = "marvell,orion-sata";
507				reg = <0xa0000 0x5000>;
508				interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
509				clocks = <&gateclk 14>, <&gateclk 20>;
510				clock-names = "0", "1";
511				status = "disabled";
512			};
513
514			nand@d0000 {
515				compatible = "marvell,armada370-nand";
516				reg = <0xd0000 0x54>;
517				#address-cells = <1>;
518				#size-cells = <1>;
519				interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
520				clocks = <&gateclk 11>;
521				status = "disabled";
522			};
523
524			mvsdio@d4000 {
525				compatible = "marvell,orion-sdio";
526				reg = <0xd4000 0x200>;
527				interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
528				clocks = <&gateclk 17>;
529				bus-width = <4>;
530				cap-sdio-irq;
531				cap-sd-highspeed;
532				cap-mmc-highspeed;
533				status = "disabled";
534			};
535
536			thermal@e8078 {
537				compatible = "marvell,armada375-thermal";
538				reg = <0xe8078 0x4>, <0xe807c 0x8>;
539				status = "okay";
540			};
541
542			coreclk: mvebu-sar@e8204 {
543				compatible = "marvell,armada-375-core-clock";
544				reg = <0xe8204 0x04>;
545				#clock-cells = <1>;
546			};
547
548			coredivclk: corediv-clock@e8250 {
549				compatible = "marvell,armada-375-corediv-clock";
550				reg = <0xe8250 0xc>;
551				#clock-cells = <1>;
552				clocks = <&mainpll>;
553				clock-output-names = "nand";
554			};
555		};
556
557		pcie-controller {
558			compatible = "marvell,armada-370-pcie";
559			status = "disabled";
560			device_type = "pci";
561
562			#address-cells = <3>;
563			#size-cells = <2>;
564
565			msi-parent = <&mpic>;
566			bus-range = <0x00 0xff>;
567
568			ranges =
569			       <0x82000000 0 0x40000 MBUS_ID(0xf0, 0x01) 0x40000 0 0x00002000
570				0x82000000 0 0x44000 MBUS_ID(0xf0, 0x01) 0x44000 0 0x00002000
571				0x82000000 0x1 0       MBUS_ID(0x04, 0xe8) 0 1 0 /* Port 0 MEM */
572				0x81000000 0x1 0       MBUS_ID(0x04, 0xe0) 0 1 0 /* Port 0 IO  */
573				0x82000000 0x2 0       MBUS_ID(0x04, 0xd8) 0 1 0 /* Port 1 MEM */
574				0x81000000 0x2 0       MBUS_ID(0x04, 0xd0) 0 1 0 /* Port 1 IO  */>;
575
576			pcie@1,0 {
577				device_type = "pci";
578				assigned-addresses = <0x82000800 0 0x40000 0 0x2000>;
579				reg = <0x0800 0 0 0 0>;
580				#address-cells = <3>;
581				#size-cells = <2>;
582				#interrupt-cells = <1>;
583				ranges = <0x82000000 0 0 0x82000000 0x1 0 1 0
584					  0x81000000 0 0 0x81000000 0x1 0 1 0>;
585				interrupt-map-mask = <0 0 0 0>;
586				interrupt-map = <0 0 0 0 &gic GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
587				marvell,pcie-port = <0>;
588				marvell,pcie-lane = <0>;
589				clocks = <&gateclk 5>;
590				status = "disabled";
591			};
592
593			pcie@2,0 {
594				device_type = "pci";
595				assigned-addresses = <0x82000800 0 0x44000 0 0x2000>;
596				reg = <0x1000 0 0 0 0>;
597				#address-cells = <3>;
598				#size-cells = <2>;
599				#interrupt-cells = <1>;
600				ranges = <0x82000000 0 0 0x82000000 0x2 0 1 0
601					  0x81000000 0 0 0x81000000 0x2 0 1 0>;
602				interrupt-map-mask = <0 0 0 0>;
603				interrupt-map = <0 0 0 0 &gic GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
604				marvell,pcie-port = <0>;
605				marvell,pcie-lane = <1>;
606				clocks = <&gateclk 6>;
607				status = "disabled";
608			};
609
610		};
611	};
612};
613