armada-370-rd.dts revision 284090
1129202Scognet/*
2129202Scognet * Device Tree file for Marvell Armada 370 Reference Design board
3129202Scognet * (RD-88F6710-A1)
4129202Scognet *
5129202Scognet *  Copied from arch/arm/boot/dts/armada-370-db.dts
6129202Scognet *
7129202Scognet *  Copyright (C) 2013 Florian Fainelli <florian@openwrt.org>
8129202Scognet *
9129202Scognet * This file is dual-licensed: you can use it either under the terms
10129202Scognet * of the GPL or the X11 license, at your option. Note that this dual
11129202Scognet * licensing only applies to this file, and not this project as a
12129202Scognet * whole.
13129202Scognet *
14129202Scognet *  a) This file is free software; you can redistribute it and/or
15129202Scognet *     modify it under the terms of the GNU General Public License as
16129202Scognet *     published by the Free Software Foundation; either version 2 of the
17129202Scognet *     License, or (at your option) any later version.
18129202Scognet *
19129202Scognet *     This file is distributed in the hope that it will be useful
20129202Scognet *     but WITHOUT ANY WARRANTY; without even the implied warranty of
21129202Scognet *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
22129202Scognet *     GNU General Public License for more details.
23129202Scognet *
24129202Scognet * Or, alternatively
25129202Scognet *
26129202Scognet *  b) Permission is hereby granted, free of charge, to any person
27129202Scognet *     obtaining a copy of this software and associated documentation
28129202Scognet *     files (the "Software"), to deal in the Software without
29129202Scognet *     restriction, including without limitation the rights to use
30129202Scognet *     copy, modify, merge, publish, distribute, sublicense, and/or
31129202Scognet *     sell copies of the Software, and to permit persons to whom the
32129202Scognet *     Software is furnished to do so, subject to the following
33129202Scognet *     conditions:
34129202Scognet *
35129202Scognet *     The above copyright notice and this permission notice shall be
36129202Scognet *     included in all copies or substantial portions of the Software.
37129202Scognet *
38129202Scognet *     THE SOFTWARE IS PROVIDED , WITHOUT WARRANTY OF ANY KIND
39129202Scognet *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
40129202Scognet *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
41164109Scognet *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
42129202Scognet *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY
43129202Scognet *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
44129202Scognet *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
45129202Scognet *     OTHER DEALINGS IN THE SOFTWARE.
46129202Scognet *
47129202Scognet * Note: this Device Tree assumes that the bootloader has remapped the
48137464Scognet * internal registers to 0xf1000000 (instead of the default
49271337Sian * 0xd0000000). The 0xf1000000 is the default used by the recent,
50 * DT-capable, U-Boot bootloaders provided by Marvell. Some earlier
51 * boards were delivered with an older version of the bootloader that
52 * left internal registers mapped at 0xd0000000. If you are in this
53 * situation, you should either update your bootloader (preferred
54 * solution) or the below Device Tree should be adjusted.
55 */
56
57/dts-v1/;
58#include <dt-bindings/input/input.h>
59#include <dt-bindings/gpio/gpio.h>
60#include "armada-370.dtsi"
61
62/ {
63	model = "Marvell Armada 370 Reference Design";
64	compatible = "marvell,a370-rd", "marvell,armada370", "marvell,armada-370-xp";
65
66	chosen {
67		bootargs = "console=ttyS0,115200 earlyprintk";
68	};
69
70	memory {
71		device_type = "memory";
72		reg = <0x00000000 0x20000000>; /* 512 MB */
73	};
74
75	soc {
76		ranges = <MBUS_ID(0xf0, 0x01) 0 0xf1000000 0x100000
77			  MBUS_ID(0x01, 0xe0) 0 0xfff00000 0x100000>;
78
79		pcie-controller {
80			status = "okay";
81
82			/* Internal mini-PCIe connector */
83			pcie@1,0 {
84				/* Port 0, Lane 0 */
85				status = "okay";
86			};
87
88			/* Internal mini-PCIe connector */
89			pcie@2,0 {
90				/* Port 1, Lane 0 */
91				status = "okay";
92			};
93		};
94
95		internal-regs {
96			serial@12000 {
97				status = "okay";
98			};
99			sata@a0000 {
100				nr-ports = <2>;
101				status = "okay";
102			};
103
104			mdio {
105				pinctrl-0 = <&mdio_pins>;
106				pinctrl-names = "default";
107				phy0: ethernet-phy@0 {
108					reg = <0>;
109				};
110			};
111
112			ethernet@70000 {
113				status = "okay";
114				phy = <&phy0>;
115				phy-mode = "sgmii";
116			};
117			ethernet@74000 {
118				pinctrl-0 = <&ge1_rgmii_pins>;
119				pinctrl-names = "default";
120				status = "okay";
121				phy-mode = "rgmii-id";
122				fixed-link {
123					   speed = <1000>;
124					   full-duplex;
125				};
126			};
127
128			mvsdio@d4000 {
129				pinctrl-0 = <&sdio_pins1>;
130				pinctrl-names = "default";
131				status = "okay";
132				/* No CD or WP GPIOs */
133				broken-cd;
134			};
135
136			usb@50000 {
137				status = "okay";
138			};
139
140			usb@51000 {
141				status = "okay";
142			};
143
144			gpio-keys {
145				compatible = "gpio-keys";
146				#address-cells = <1>;
147				#size-cells = <0>;
148				button@1 {
149					label = "Software Button";
150					linux,code = <KEY_POWER>;
151					gpios = <&gpio0 6 GPIO_ACTIVE_LOW>;
152				};
153			};
154
155			gpio-fan {
156				compatible = "gpio-fan";
157				gpios = <&gpio0 8 GPIO_ACTIVE_HIGH>;
158				gpio-fan,speed-map = <0 0 3000 1>;
159				pinctrl-0 = <&fan_pins>;
160				pinctrl-names = "default";
161			};
162
163			gpio_leds {
164				compatible = "gpio-leds";
165				pinctrl-names = "default";
166				pinctrl-0 = <&led_pins>;
167
168				sw_led {
169					label = "370rd:green:sw";
170					gpios = <&gpio1 0 GPIO_ACTIVE_LOW>;
171					default-state = "keep";
172				};
173			};
174
175			nand@d0000 {
176				status = "okay";
177				num-cs = <1>;
178				marvell,nand-keep-config;
179				marvell,nand-enable-arbiter;
180				nand-on-flash-bbt;
181
182				partition@0 {
183					label = "U-Boot";
184					reg = <0 0x800000>;
185				};
186				partition@800000 {
187					label = "Linux";
188					reg = <0x800000 0x800000>;
189				};
190				partition@1000000 {
191					label = "Filesystem";
192					reg = <0x1000000 0x3f000000>;
193				};
194			};
195		};
196	};
197
198	dsa@0 {
199		compatible = "marvell,dsa";
200		#address-cells = <2>;
201		#size-cells = <0>;
202
203		dsa,ethernet = <&eth1>;
204		dsa,mii-bus = <&mdio>;
205
206		switch@0 {
207			#address-cells = <1>;
208			#size-cells = <0>;
209			reg = <0x10 0>;	/* MDIO address 16, switch 0 in tree */
210
211			port@0 {
212				reg = <0>;
213				label = "lan0";
214			};
215
216			port@1 {
217			       reg = <1>;
218			       label = "lan1";
219			};
220
221			port@2 {
222			       reg = <2>;
223			       label = "lan2";
224			};
225
226			port@3 {
227			       reg = <3>;
228			       label = "lan3";
229			};
230
231			port@5 {
232			      reg = <5>;
233			      label = "cpu";
234			};
235		};
236	 };
237 };
238
239&pinctrl {
240	fan_pins: fan-pins {
241		marvell,pins = "mpp8";
242		marvell,function = "gpio";
243	};
244
245	led_pins: led-pins {
246		marvell,pins = "mpp32";
247		marvell,function = "gpio";
248	};
249};
250