am43x-epos-evm.dts revision 284090
1/* 2 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8 9/* AM43x EPOS EVM */ 10 11/dts-v1/; 12 13#include "am4372.dtsi" 14#include <dt-bindings/pinctrl/am43xx.h> 15#include <dt-bindings/gpio/gpio.h> 16#include <dt-bindings/pwm/pwm.h> 17 18/ { 19 model = "TI AM43x EPOS EVM"; 20 compatible = "ti,am43x-epos-evm","ti,am4372","ti,am43"; 21 22 aliases { 23 display0 = &lcd0; 24 }; 25 26 vmmcsd_fixed: fixedregulator-sd { 27 compatible = "regulator-fixed"; 28 regulator-name = "vmmcsd_fixed"; 29 regulator-min-microvolt = <3300000>; 30 regulator-max-microvolt = <3300000>; 31 enable-active-high; 32 }; 33 34 lcd0: display { 35 compatible = "osddisplays,osd057T0559-34ts", "panel-dpi"; 36 label = "lcd"; 37 38 pinctrl-names = "default"; 39 pinctrl-0 = <&lcd_pins>; 40 41 /* 42 * SelLCDorHDMI, LOW to select HDMI. This is not really the 43 * panel's enable GPIO, but we don't have HDMI driver support nor 44 * support to switch between two displays, so using this gpio as 45 * panel's enable should be safe. 46 */ 47 enable-gpios = <&gpio2 1 GPIO_ACTIVE_HIGH>; 48 49 panel-timing { 50 clock-frequency = <33000000>; 51 hactive = <800>; 52 vactive = <480>; 53 hfront-porch = <210>; 54 hback-porch = <16>; 55 hsync-len = <30>; 56 vback-porch = <10>; 57 vfront-porch = <22>; 58 vsync-len = <13>; 59 hsync-active = <0>; 60 vsync-active = <0>; 61 de-active = <1>; 62 pixelclk-active = <1>; 63 }; 64 65 port { 66 lcd_in: endpoint { 67 remote-endpoint = <&dpi_out>; 68 }; 69 }; 70 }; 71 72 am43xx_pinmux: pinmux@44e10800 { 73 cpsw_default: cpsw_default { 74 pinctrl-single,pins = < 75 /* Slave 1 */ 76 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_crs.rmii1_crs */ 77 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxerr.rmii1_rxerr */ 78 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txen.rmii1_txen */ 79 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxdv.rmii1_rxdv */ 80 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd1.rmii1_txd1 */ 81 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE1) /* mii1_txd0.rmii1_txd0 */ 82 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd1.rmii1_rxd1 */ 83 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE1) /* mii1_rxd0.rmii1_rxd0 */ 84 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* rmii1_refclk.rmii1_refclk */ 85 >; 86 }; 87 88 cpsw_sleep: cpsw_sleep { 89 pinctrl-single,pins = < 90 /* Slave 1 reset value */ 91 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE7) 92 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE7) 93 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) 94 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) 95 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) 96 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) 97 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) 98 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) 99 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE7) 100 >; 101 }; 102 103 davinci_mdio_default: davinci_mdio_default { 104 pinctrl-single,pins = < 105 /* MDIO */ 106 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ 107 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ 108 >; 109 }; 110 111 davinci_mdio_sleep: davinci_mdio_sleep { 112 pinctrl-single,pins = < 113 /* MDIO reset value */ 114 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) 115 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) 116 >; 117 }; 118 119 i2c0_pins: pinmux_i2c0_pins { 120 pinctrl-single,pins = < 121 0x188 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_sda.i2c0_sda */ 122 0x18c (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* i2c0_scl.i2c0_scl */ 123 >; 124 }; 125 126 nand_flash_x8: nand_flash_x8 { 127 pinctrl-single,pins = < 128 0x40 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a0.SELQSPIorNAND/GPIO */ 129 0x0 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ 130 0x4 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ 131 0x8 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ 132 0xc (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ 133 0x10 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ 134 0x14 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ 135 0x18 (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ 136 0x1c (PIN_INPUT_PULLDOWN | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ 137 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ 138 0x74 (PIN_OUTPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpmc_wpn */ 139 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ 140 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ 141 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ 142 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ 143 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ 144 >; 145 }; 146 147 ecap0_pins: backlight_pins { 148 pinctrl-single,pins = < 149 0x164 MUX_MODE0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ 150 >; 151 }; 152 153 i2c2_pins: pinmux_i2c2_pins { 154 pinctrl-single,pins = < 155 0x1c0 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_sda.i2c2_sda */ 156 0x1c4 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE8) /* i2c2_scl.i2c2_scl */ 157 >; 158 }; 159 160 spi0_pins: pinmux_spi0_pins { 161 pinctrl-single,pins = < 162 0x150 (PIN_INPUT | MUX_MODE0) /* spi0_clk.spi0_clk */ 163 0x154 (PIN_OUTPUT | MUX_MODE0) /* spi0_d0.spi0_d0 */ 164 0x158 (PIN_INPUT | MUX_MODE0) /* spi0_d1.spi0_d1 */ 165 0x15c (PIN_OUTPUT | MUX_MODE0) /* spi0_cs0.spi0_cs0 */ 166 >; 167 }; 168 169 spi1_pins: pinmux_spi1_pins { 170 pinctrl-single,pins = < 171 0x190 (PIN_INPUT | MUX_MODE3) /* mcasp0_aclkx.spi1_clk */ 172 0x194 (PIN_OUTPUT | MUX_MODE3) /* mcasp0_fsx.spi1_d0 */ 173 0x198 (PIN_INPUT | MUX_MODE3) /* mcasp0_axr0.spi1_d1 */ 174 0x19c (PIN_OUTPUT | MUX_MODE3) /* mcasp0_ahclkr.spi1_cs0 */ 175 >; 176 }; 177 178 mmc1_pins: pinmux_mmc1_pins { 179 pinctrl-single,pins = < 180 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ 181 >; 182 }; 183 184 qspi1_default: qspi1_default { 185 pinctrl-single,pins = < 186 0x7c (PIN_INPUT_PULLUP | MUX_MODE3) 187 0x88 (PIN_INPUT_PULLUP | MUX_MODE2) 188 0x90 (PIN_INPUT_PULLUP | MUX_MODE3) 189 0x94 (PIN_INPUT_PULLUP | MUX_MODE3) 190 0x98 (PIN_INPUT_PULLUP | MUX_MODE3) 191 0x9c (PIN_INPUT_PULLUP | MUX_MODE3) 192 >; 193 }; 194 195 pixcir_ts_pins: pixcir_ts_pins { 196 pinctrl-single,pins = < 197 0x44 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_a1.gpio1_17 */ 198 >; 199 }; 200 201 hdq_pins: pinmux_hdq_pins { 202 pinctrl-single,pins = < 203 0x234 (PIN_INPUT_PULLUP | MUX_MODE1) /* cam1_wen.hdq_gpio */ 204 >; 205 }; 206 207 dss_pins: dss_pins { 208 pinctrl-single,pins = < 209 0x020 (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 8 -> DSS DATA 23 */ 210 0x024 (PIN_OUTPUT_PULLUP | MUX_MODE1) 211 0x028 (PIN_OUTPUT_PULLUP | MUX_MODE1) 212 0x02C (PIN_OUTPUT_PULLUP | MUX_MODE1) 213 0x030 (PIN_OUTPUT_PULLUP | MUX_MODE1) 214 0x034 (PIN_OUTPUT_PULLUP | MUX_MODE1) 215 0x038 (PIN_OUTPUT_PULLUP | MUX_MODE1) 216 0x03C (PIN_OUTPUT_PULLUP | MUX_MODE1) /*gpmc ad 15 -> DSS DATA 16 */ 217 0x0A0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 0 */ 218 0x0A4 (PIN_OUTPUT_PULLUP | MUX_MODE0) 219 0x0A8 (PIN_OUTPUT_PULLUP | MUX_MODE0) 220 0x0AC (PIN_OUTPUT_PULLUP | MUX_MODE0) 221 0x0B0 (PIN_OUTPUT_PULLUP | MUX_MODE0) 222 0x0B4 (PIN_OUTPUT_PULLUP | MUX_MODE0) 223 0x0B8 (PIN_OUTPUT_PULLUP | MUX_MODE0) 224 0x0BC (PIN_OUTPUT_PULLUP | MUX_MODE0) 225 0x0C0 (PIN_OUTPUT_PULLUP | MUX_MODE0) 226 0x0C4 (PIN_OUTPUT_PULLUP | MUX_MODE0) 227 0x0C8 (PIN_OUTPUT_PULLUP | MUX_MODE0) 228 0x0CC (PIN_OUTPUT_PULLUP | MUX_MODE0) 229 0x0D0 (PIN_OUTPUT_PULLUP | MUX_MODE0) 230 0x0D4 (PIN_OUTPUT_PULLUP | MUX_MODE0) 231 0x0D8 (PIN_OUTPUT_PULLUP | MUX_MODE0) 232 0x0DC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS DATA 15 */ 233 0x0E0 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS VSYNC */ 234 0x0E4 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS HSYNC */ 235 0x0E8 (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS PCLK */ 236 0x0EC (PIN_OUTPUT_PULLUP | MUX_MODE0) /* DSS AC BIAS EN */ 237 >; 238 }; 239 240 lcd_pins: lcd_pins { 241 pinctrl-single,pins = < 242 /* GPMC CLK -> GPIO 2_1 to select LCD / HDMI */ 243 0x08C (PIN_OUTPUT_PULLUP | MUX_MODE7) 244 >; 245 }; 246 247 vpfe1_pins_default: vpfe1_pins_default { 248 pinctrl-single,pins = < 249 0x1cc (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data9 mode 0 */ 250 0x1d0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data8 mode 0 */ 251 0x1d4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_hd mode 0 */ 252 0x1d8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_vd mode 0 */ 253 0x1dc (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_pclk mode 0 */ 254 0x1e8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data0 mode 0 */ 255 0x1ec (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data1 mode 0 */ 256 0x1f0 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data2 mode 0 */ 257 0x1f4 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data3 mode 0 */ 258 0x1f8 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data4 mode 0 */ 259 0x1fc (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data5 mode 0 */ 260 0x200 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data6 mode 0 */ 261 0x204 (PIN_INPUT_PULLUP | MUX_MODE0) /* cam1_data7 mode 0 */ 262 >; 263 }; 264 265 vpfe1_pins_sleep: vpfe1_pins_sleep { 266 pinctrl-single,pins = < 267 0x1cc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 268 0x1d0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 269 0x1d4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 270 0x1d8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 271 0x1dc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 272 0x1e8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 273 0x1ec (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 274 0x1f0 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 275 0x1f4 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 276 0x1f8 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 277 0x1fc (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 278 0x200 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 279 0x204 (DS0_PULL_UP_DOWN_EN | INPUT_EN | MUX_MODE7) 280 >; 281 }; 282 }; 283 284 matrix_keypad: matrix_keypad@0 { 285 compatible = "gpio-matrix-keypad"; 286 debounce-delay-ms = <5>; 287 col-scan-delay-us = <2>; 288 289 row-gpios = <&gpio0 12 GPIO_ACTIVE_HIGH /* Bank0, pin12 */ 290 &gpio0 13 GPIO_ACTIVE_HIGH /* Bank0, pin13 */ 291 &gpio0 14 GPIO_ACTIVE_HIGH /* Bank0, pin14 */ 292 &gpio0 15 GPIO_ACTIVE_HIGH>; /* Bank0, pin15 */ 293 294 col-gpios = <&gpio3 9 GPIO_ACTIVE_HIGH /* Bank3, pin9 */ 295 &gpio3 10 GPIO_ACTIVE_HIGH /* Bank3, pin10 */ 296 &gpio2 18 GPIO_ACTIVE_HIGH /* Bank2, pin18 */ 297 &gpio2 19 GPIO_ACTIVE_HIGH>; /* Bank2, pin19 */ 298 299 linux,keymap = <0x00000201 /* P1 */ 300 0x01000204 /* P4 */ 301 0x02000207 /* P7 */ 302 0x0300020a /* NUMERIC_STAR */ 303 0x00010202 /* P2 */ 304 0x01010205 /* P5 */ 305 0x02010208 /* P8 */ 306 0x03010200 /* P0 */ 307 0x00020203 /* P3 */ 308 0x01020206 /* P6 */ 309 0x02020209 /* P9 */ 310 0x0302020b /* NUMERIC_POUND */ 311 0x00030067 /* UP */ 312 0x0103006a /* RIGHT */ 313 0x0203006c /* DOWN */ 314 0x03030069>; /* LEFT */ 315 }; 316 317 backlight { 318 compatible = "pwm-backlight"; 319 pwms = <&ecap0 0 50000 PWM_POLARITY_INVERTED>; 320 brightness-levels = <0 51 53 56 62 75 101 152 255>; 321 default-brightness-level = <8>; 322 }; 323}; 324 325&mmc1 { 326 status = "okay"; 327 vmmc-supply = <&vmmcsd_fixed>; 328 bus-width = <4>; 329 pinctrl-names = "default"; 330 pinctrl-0 = <&mmc1_pins>; 331 cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; 332}; 333 334&mac { 335 pinctrl-names = "default", "sleep"; 336 pinctrl-0 = <&cpsw_default>; 337 pinctrl-1 = <&cpsw_sleep>; 338 status = "okay"; 339}; 340 341&davinci_mdio { 342 pinctrl-names = "default", "sleep"; 343 pinctrl-0 = <&davinci_mdio_default>; 344 pinctrl-1 = <&davinci_mdio_sleep>; 345 status = "okay"; 346}; 347 348&cpsw_emac0 { 349 phy_id = <&davinci_mdio>, <16>; 350 phy-mode = "rmii"; 351}; 352 353&cpsw_emac1 { 354 phy_id = <&davinci_mdio>, <1>; 355 phy-mode = "rmii"; 356}; 357 358&phy_sel { 359 rmii-clock-ext; 360}; 361 362&i2c0 { 363 status = "okay"; 364 pinctrl-names = "default"; 365 pinctrl-0 = <&i2c0_pins>; 366 clock-frequency = <400000>; 367 368 tps65218: tps65218@24 { 369 reg = <0x24>; 370 compatible = "ti,tps65218"; 371 interrupts = <GIC_SPI 7 IRQ_TYPE_NONE>; /* NMIn */ 372 interrupt-parent = <&gic>; 373 interrupt-controller; 374 #interrupt-cells = <2>; 375 376 dcdc1: regulator-dcdc1 { 377 compatible = "ti,tps65218-dcdc1"; 378 regulator-name = "vdd_core"; 379 regulator-min-microvolt = <912000>; 380 regulator-max-microvolt = <1144000>; 381 regulator-boot-on; 382 regulator-always-on; 383 }; 384 385 dcdc2: regulator-dcdc2 { 386 compatible = "ti,tps65218-dcdc2"; 387 regulator-name = "vdd_mpu"; 388 regulator-min-microvolt = <912000>; 389 regulator-max-microvolt = <1378000>; 390 regulator-boot-on; 391 regulator-always-on; 392 }; 393 394 dcdc3: regulator-dcdc3 { 395 compatible = "ti,tps65218-dcdc3"; 396 regulator-name = "vdcdc3"; 397 regulator-min-microvolt = <1500000>; 398 regulator-max-microvolt = <1500000>; 399 regulator-boot-on; 400 regulator-always-on; 401 }; 402 403 dcdc5: regulator-dcdc5 { 404 compatible = "ti,tps65218-dcdc5"; 405 regulator-name = "v1_0bat"; 406 regulator-min-microvolt = <1000000>; 407 regulator-max-microvolt = <1000000>; 408 }; 409 410 dcdc6: regulator-dcdc6 { 411 compatible = "ti,tps65218-dcdc6"; 412 regulator-name = "v1_8bat"; 413 regulator-min-microvolt = <1800000>; 414 regulator-max-microvolt = <1800000>; 415 }; 416 417 ldo1: regulator-ldo1 { 418 compatible = "ti,tps65218-ldo1"; 419 regulator-min-microvolt = <1800000>; 420 regulator-max-microvolt = <1800000>; 421 regulator-boot-on; 422 regulator-always-on; 423 }; 424 }; 425 426 at24@50 { 427 compatible = "at24,24c256"; 428 pagesize = <64>; 429 reg = <0x50>; 430 }; 431 432 pixcir_ts@5c { 433 compatible = "pixcir,pixcir_tangoc"; 434 pinctrl-names = "default"; 435 pinctrl-0 = <&pixcir_ts_pins>; 436 reg = <0x5c>; 437 interrupt-parent = <&gpio1>; 438 interrupts = <17 0>; 439 440 attb-gpio = <&gpio1 17 GPIO_ACTIVE_HIGH>; 441 442 touchscreen-size-x = <1024>; 443 touchscreen-size-y = <600>; 444 }; 445}; 446 447&i2c2 { 448 pinctrl-names = "default"; 449 pinctrl-0 = <&i2c2_pins>; 450 status = "okay"; 451}; 452 453&gpio0 { 454 status = "okay"; 455}; 456 457&gpio1 { 458 status = "okay"; 459}; 460 461&gpio2 { 462 status = "okay"; 463}; 464 465&gpio3 { 466 status = "okay"; 467}; 468 469&elm { 470 status = "okay"; 471}; 472 473&gpmc { 474 status = "okay"; /* Disable QSPI when enabling GPMC (NAND) */ 475 pinctrl-names = "default"; 476 pinctrl-0 = <&nand_flash_x8>; 477 ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ 478 nand@0,0 { 479 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 480 ti,nand-ecc-opt = "bch16"; 481 ti,elm-id = <&elm>; 482 nand-bus-width = <8>; 483 gpmc,device-width = <1>; 484 gpmc,sync-clk-ps = <0>; 485 gpmc,cs-on-ns = <0>; 486 gpmc,cs-rd-off-ns = <40>; /* tCEA + tCHZ + 1 */ 487 gpmc,cs-wr-off-ns = <40>; 488 gpmc,adv-on-ns = <0>; /* cs-on-ns */ 489 gpmc,adv-rd-off-ns = <25>; /* min( tALH + tALS + 1) */ 490 gpmc,adv-wr-off-ns = <25>; /* min( tALH + tALS + 1) */ 491 gpmc,we-on-ns = <0>; /* cs-on-ns */ 492 gpmc,we-off-ns = <20>; /* we-on-time + tWP + 2 */ 493 gpmc,oe-on-ns = <3>; /* cs-on-ns + tRR + 2 */ 494 gpmc,oe-off-ns = <30>; /* oe-on-ns + tRP + 2 */ 495 gpmc,access-ns = <30>; /* tCEA + 4*/ 496 gpmc,rd-cycle-ns = <40>; 497 gpmc,wr-cycle-ns = <40>; 498 gpmc,wait-pin = <0>; 499 gpmc,bus-turnaround-ns = <0>; 500 gpmc,cycle2cycle-delay-ns = <0>; 501 gpmc,clk-activation-ns = <0>; 502 gpmc,wait-monitoring-ns = <0>; 503 gpmc,wr-access-ns = <40>; 504 gpmc,wr-data-mux-bus-ns = <0>; 505 /* MTD partition table */ 506 /* All SPL-* partitions are sized to minimal length 507 * which can be independently programmable. For 508 * NAND flash this is equal to size of erase-block */ 509 #address-cells = <1>; 510 #size-cells = <1>; 511 partition@0 { 512 label = "NAND.SPL"; 513 reg = <0x00000000 0x00040000>; 514 }; 515 partition@1 { 516 label = "NAND.SPL.backup1"; 517 reg = <0x00040000 0x00040000>; 518 }; 519 partition@2 { 520 label = "NAND.SPL.backup2"; 521 reg = <0x00080000 0x00040000>; 522 }; 523 partition@3 { 524 label = "NAND.SPL.backup3"; 525 reg = <0x000C0000 0x00040000>; 526 }; 527 partition@4 { 528 label = "NAND.u-boot-spl-os"; 529 reg = <0x00100000 0x00080000>; 530 }; 531 partition@5 { 532 label = "NAND.u-boot"; 533 reg = <0x00180000 0x00100000>; 534 }; 535 partition@6 { 536 label = "NAND.u-boot-env"; 537 reg = <0x00280000 0x00040000>; 538 }; 539 partition@7 { 540 label = "NAND.u-boot-env.backup1"; 541 reg = <0x002C0000 0x00040000>; 542 }; 543 partition@8 { 544 label = "NAND.kernel"; 545 reg = <0x00300000 0x00700000>; 546 }; 547 partition@9 { 548 label = "NAND.file-system"; 549 reg = <0x00a00000 0x1f600000>; 550 }; 551 }; 552}; 553 554&epwmss0 { 555 status = "okay"; 556}; 557 558&tscadc { 559 status = "okay"; 560 561 adc { 562 ti,adc-channels = <0 1 2 3 4 5 6 7>; 563 }; 564}; 565 566&ecap0 { 567 status = "okay"; 568 pinctrl-names = "default"; 569 pinctrl-0 = <&ecap0_pins>; 570}; 571 572&spi0 { 573 pinctrl-names = "default"; 574 pinctrl-0 = <&spi0_pins>; 575 status = "okay"; 576}; 577 578&spi1 { 579 pinctrl-names = "default"; 580 pinctrl-0 = <&spi1_pins>; 581 status = "okay"; 582}; 583 584&usb2_phy1 { 585 status = "okay"; 586}; 587 588&usb1 { 589 dr_mode = "peripheral"; 590 status = "okay"; 591}; 592 593&usb2_phy2 { 594 status = "okay"; 595}; 596 597&usb2 { 598 dr_mode = "host"; 599 status = "okay"; 600}; 601 602&qspi { 603 status = "disabled"; /* Disable GPMC (NAND) when enabling QSPI */ 604 pinctrl-names = "default"; 605 pinctrl-0 = <&qspi1_default>; 606 607 spi-max-frequency = <48000000>; 608 m25p80@0 { 609 compatible = "mx66l51235l"; 610 spi-max-frequency = <48000000>; 611 reg = <0>; 612 spi-cpol; 613 spi-cpha; 614 spi-tx-bus-width = <1>; 615 spi-rx-bus-width = <4>; 616 #address-cells = <1>; 617 #size-cells = <1>; 618 619 /* MTD partition table. 620 * The ROM checks the first 512KiB 621 * for a valid file to boot(XIP). 622 */ 623 partition@0 { 624 label = "QSPI.U_BOOT"; 625 reg = <0x00000000 0x000080000>; 626 }; 627 partition@1 { 628 label = "QSPI.U_BOOT.backup"; 629 reg = <0x00080000 0x00080000>; 630 }; 631 partition@2 { 632 label = "QSPI.U-BOOT-SPL_OS"; 633 reg = <0x00100000 0x00010000>; 634 }; 635 partition@3 { 636 label = "QSPI.U_BOOT_ENV"; 637 reg = <0x00110000 0x00010000>; 638 }; 639 partition@4 { 640 label = "QSPI.U-BOOT-ENV.backup"; 641 reg = <0x00120000 0x00010000>; 642 }; 643 partition@5 { 644 label = "QSPI.KERNEL"; 645 reg = <0x00130000 0x0800000>; 646 }; 647 partition@6 { 648 label = "QSPI.FILESYSTEM"; 649 reg = <0x00930000 0x36D0000>; 650 }; 651 }; 652}; 653 654&hdq { 655 status = "okay"; 656 pinctrl-names = "default"; 657 pinctrl-0 = <&hdq_pins>; 658}; 659 660&dss { 661 status = "ok"; 662 663 pinctrl-names = "default"; 664 pinctrl-0 = <&dss_pins>; 665 666 port { 667 dpi_out: endpoint@0 { 668 remote-endpoint = <&lcd_in>; 669 data-lines = <24>; 670 }; 671 }; 672}; 673 674&vpfe1 { 675 status = "okay"; 676 pinctrl-names = "default", "sleep"; 677 pinctrl-0 = <&vpfe1_pins_default>; 678 pinctrl-1 = <&vpfe1_pins_sleep>; 679 680 port { 681 vpfe1_ep: endpoint { 682 /* remote-endpoint = <&sensor>; add once we have it */ 683 ti,am437x-vpfe-interface = <0>; 684 bus-width = <8>; 685 hsync-active = <0>; 686 vsync-active = <0>; 687 }; 688 }; 689}; 690