am33xx-clocks.dtsi revision 284090
1/* 2 * Device Tree Source for AM33xx clock data 3 * 4 * Copyright (C) 2013 Texas Instruments, Inc. 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 */ 10&scrm_clocks { 11 sys_clkin_ck: sys_clkin_ck { 12 #clock-cells = <0>; 13 compatible = "ti,mux-clock"; 14 clocks = <&virt_19200000_ck>, <&virt_24000000_ck>, <&virt_25000000_ck>, <&virt_26000000_ck>; 15 ti,bit-shift = <22>; 16 reg = <0x0040>; 17 }; 18 19 adc_tsc_fck: adc_tsc_fck { 20 #clock-cells = <0>; 21 compatible = "fixed-factor-clock"; 22 clocks = <&sys_clkin_ck>; 23 clock-mult = <1>; 24 clock-div = <1>; 25 }; 26 27 dcan0_fck: dcan0_fck { 28 #clock-cells = <0>; 29 compatible = "fixed-factor-clock"; 30 clocks = <&sys_clkin_ck>; 31 clock-mult = <1>; 32 clock-div = <1>; 33 }; 34 35 dcan1_fck: dcan1_fck { 36 #clock-cells = <0>; 37 compatible = "fixed-factor-clock"; 38 clocks = <&sys_clkin_ck>; 39 clock-mult = <1>; 40 clock-div = <1>; 41 }; 42 43 mcasp0_fck: mcasp0_fck { 44 #clock-cells = <0>; 45 compatible = "fixed-factor-clock"; 46 clocks = <&sys_clkin_ck>; 47 clock-mult = <1>; 48 clock-div = <1>; 49 }; 50 51 mcasp1_fck: mcasp1_fck { 52 #clock-cells = <0>; 53 compatible = "fixed-factor-clock"; 54 clocks = <&sys_clkin_ck>; 55 clock-mult = <1>; 56 clock-div = <1>; 57 }; 58 59 smartreflex0_fck: smartreflex0_fck { 60 #clock-cells = <0>; 61 compatible = "fixed-factor-clock"; 62 clocks = <&sys_clkin_ck>; 63 clock-mult = <1>; 64 clock-div = <1>; 65 }; 66 67 smartreflex1_fck: smartreflex1_fck { 68 #clock-cells = <0>; 69 compatible = "fixed-factor-clock"; 70 clocks = <&sys_clkin_ck>; 71 clock-mult = <1>; 72 clock-div = <1>; 73 }; 74 75 sha0_fck: sha0_fck { 76 #clock-cells = <0>; 77 compatible = "fixed-factor-clock"; 78 clocks = <&sys_clkin_ck>; 79 clock-mult = <1>; 80 clock-div = <1>; 81 }; 82 83 aes0_fck: aes0_fck { 84 #clock-cells = <0>; 85 compatible = "fixed-factor-clock"; 86 clocks = <&sys_clkin_ck>; 87 clock-mult = <1>; 88 clock-div = <1>; 89 }; 90 91 rng_fck: rng_fck { 92 #clock-cells = <0>; 93 compatible = "fixed-factor-clock"; 94 clocks = <&sys_clkin_ck>; 95 clock-mult = <1>; 96 clock-div = <1>; 97 }; 98 99 ehrpwm0_tbclk: ehrpwm0_tbclk@44e10664 { 100 #clock-cells = <0>; 101 compatible = "ti,gate-clock"; 102 clocks = <&dpll_per_m2_ck>; 103 ti,bit-shift = <0>; 104 reg = <0x0664>; 105 }; 106 107 ehrpwm1_tbclk: ehrpwm1_tbclk@44e10664 { 108 #clock-cells = <0>; 109 compatible = "ti,gate-clock"; 110 clocks = <&dpll_per_m2_ck>; 111 ti,bit-shift = <1>; 112 reg = <0x0664>; 113 }; 114 115 ehrpwm2_tbclk: ehrpwm2_tbclk@44e10664 { 116 #clock-cells = <0>; 117 compatible = "ti,gate-clock"; 118 clocks = <&dpll_per_m2_ck>; 119 ti,bit-shift = <2>; 120 reg = <0x0664>; 121 }; 122}; 123&prcm_clocks { 124 clk_32768_ck: clk_32768_ck { 125 #clock-cells = <0>; 126 compatible = "fixed-clock"; 127 clock-frequency = <32768>; 128 }; 129 130 clk_rc32k_ck: clk_rc32k_ck { 131 #clock-cells = <0>; 132 compatible = "fixed-clock"; 133 clock-frequency = <32000>; 134 }; 135 136 virt_19200000_ck: virt_19200000_ck { 137 #clock-cells = <0>; 138 compatible = "fixed-clock"; 139 clock-frequency = <19200000>; 140 }; 141 142 virt_24000000_ck: virt_24000000_ck { 143 #clock-cells = <0>; 144 compatible = "fixed-clock"; 145 clock-frequency = <24000000>; 146 }; 147 148 virt_25000000_ck: virt_25000000_ck { 149 #clock-cells = <0>; 150 compatible = "fixed-clock"; 151 clock-frequency = <25000000>; 152 }; 153 154 virt_26000000_ck: virt_26000000_ck { 155 #clock-cells = <0>; 156 compatible = "fixed-clock"; 157 clock-frequency = <26000000>; 158 }; 159 160 tclkin_ck: tclkin_ck { 161 #clock-cells = <0>; 162 compatible = "fixed-clock"; 163 clock-frequency = <12000000>; 164 }; 165 166 dpll_core_ck: dpll_core_ck { 167 #clock-cells = <0>; 168 compatible = "ti,am3-dpll-core-clock"; 169 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 170 reg = <0x0490>, <0x045c>, <0x0468>; 171 }; 172 173 dpll_core_x2_ck: dpll_core_x2_ck { 174 #clock-cells = <0>; 175 compatible = "ti,am3-dpll-x2-clock"; 176 clocks = <&dpll_core_ck>; 177 }; 178 179 dpll_core_m4_ck: dpll_core_m4_ck { 180 #clock-cells = <0>; 181 compatible = "ti,divider-clock"; 182 clocks = <&dpll_core_x2_ck>; 183 ti,max-div = <31>; 184 reg = <0x0480>; 185 ti,index-starts-at-one; 186 }; 187 188 dpll_core_m5_ck: dpll_core_m5_ck { 189 #clock-cells = <0>; 190 compatible = "ti,divider-clock"; 191 clocks = <&dpll_core_x2_ck>; 192 ti,max-div = <31>; 193 reg = <0x0484>; 194 ti,index-starts-at-one; 195 }; 196 197 dpll_core_m6_ck: dpll_core_m6_ck { 198 #clock-cells = <0>; 199 compatible = "ti,divider-clock"; 200 clocks = <&dpll_core_x2_ck>; 201 ti,max-div = <31>; 202 reg = <0x04d8>; 203 ti,index-starts-at-one; 204 }; 205 206 dpll_mpu_ck: dpll_mpu_ck { 207 #clock-cells = <0>; 208 compatible = "ti,am3-dpll-clock"; 209 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 210 reg = <0x0488>, <0x0420>, <0x042c>; 211 }; 212 213 dpll_mpu_m2_ck: dpll_mpu_m2_ck { 214 #clock-cells = <0>; 215 compatible = "ti,divider-clock"; 216 clocks = <&dpll_mpu_ck>; 217 ti,max-div = <31>; 218 reg = <0x04a8>; 219 ti,index-starts-at-one; 220 }; 221 222 dpll_ddr_ck: dpll_ddr_ck { 223 #clock-cells = <0>; 224 compatible = "ti,am3-dpll-no-gate-clock"; 225 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 226 reg = <0x0494>, <0x0434>, <0x0440>; 227 }; 228 229 dpll_ddr_m2_ck: dpll_ddr_m2_ck { 230 #clock-cells = <0>; 231 compatible = "ti,divider-clock"; 232 clocks = <&dpll_ddr_ck>; 233 ti,max-div = <31>; 234 reg = <0x04a0>; 235 ti,index-starts-at-one; 236 }; 237 238 dpll_ddr_m2_div2_ck: dpll_ddr_m2_div2_ck { 239 #clock-cells = <0>; 240 compatible = "fixed-factor-clock"; 241 clocks = <&dpll_ddr_m2_ck>; 242 clock-mult = <1>; 243 clock-div = <2>; 244 }; 245 246 dpll_disp_ck: dpll_disp_ck { 247 #clock-cells = <0>; 248 compatible = "ti,am3-dpll-no-gate-clock"; 249 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 250 reg = <0x0498>, <0x0448>, <0x0454>; 251 }; 252 253 dpll_disp_m2_ck: dpll_disp_m2_ck { 254 #clock-cells = <0>; 255 compatible = "ti,divider-clock"; 256 clocks = <&dpll_disp_ck>; 257 ti,max-div = <31>; 258 reg = <0x04a4>; 259 ti,index-starts-at-one; 260 ti,set-rate-parent; 261 }; 262 263 dpll_per_ck: dpll_per_ck { 264 #clock-cells = <0>; 265 compatible = "ti,am3-dpll-no-gate-j-type-clock"; 266 clocks = <&sys_clkin_ck>, <&sys_clkin_ck>; 267 reg = <0x048c>, <0x0470>, <0x049c>; 268 }; 269 270 dpll_per_m2_ck: dpll_per_m2_ck { 271 #clock-cells = <0>; 272 compatible = "ti,divider-clock"; 273 clocks = <&dpll_per_ck>; 274 ti,max-div = <31>; 275 reg = <0x04ac>; 276 ti,index-starts-at-one; 277 }; 278 279 dpll_per_m2_div4_wkupdm_ck: dpll_per_m2_div4_wkupdm_ck { 280 #clock-cells = <0>; 281 compatible = "fixed-factor-clock"; 282 clocks = <&dpll_per_m2_ck>; 283 clock-mult = <1>; 284 clock-div = <4>; 285 }; 286 287 dpll_per_m2_div4_ck: dpll_per_m2_div4_ck { 288 #clock-cells = <0>; 289 compatible = "fixed-factor-clock"; 290 clocks = <&dpll_per_m2_ck>; 291 clock-mult = <1>; 292 clock-div = <4>; 293 }; 294 295 cefuse_fck: cefuse_fck { 296 #clock-cells = <0>; 297 compatible = "ti,gate-clock"; 298 clocks = <&sys_clkin_ck>; 299 ti,bit-shift = <1>; 300 reg = <0x0a20>; 301 }; 302 303 clk_24mhz: clk_24mhz { 304 #clock-cells = <0>; 305 compatible = "fixed-factor-clock"; 306 clocks = <&dpll_per_m2_ck>; 307 clock-mult = <1>; 308 clock-div = <8>; 309 }; 310 311 clkdiv32k_ck: clkdiv32k_ck { 312 #clock-cells = <0>; 313 compatible = "fixed-factor-clock"; 314 clocks = <&clk_24mhz>; 315 clock-mult = <1>; 316 clock-div = <732>; 317 }; 318 319 clkdiv32k_ick: clkdiv32k_ick { 320 #clock-cells = <0>; 321 compatible = "ti,gate-clock"; 322 clocks = <&clkdiv32k_ck>; 323 ti,bit-shift = <1>; 324 reg = <0x014c>; 325 }; 326 327 l3_gclk: l3_gclk { 328 #clock-cells = <0>; 329 compatible = "fixed-factor-clock"; 330 clocks = <&dpll_core_m4_ck>; 331 clock-mult = <1>; 332 clock-div = <1>; 333 }; 334 335 pruss_ocp_gclk: pruss_ocp_gclk { 336 #clock-cells = <0>; 337 compatible = "ti,mux-clock"; 338 clocks = <&l3_gclk>, <&dpll_disp_m2_ck>; 339 reg = <0x0530>; 340 }; 341 342 mmu_fck: mmu_fck { 343 #clock-cells = <0>; 344 compatible = "ti,gate-clock"; 345 clocks = <&dpll_core_m4_ck>; 346 ti,bit-shift = <1>; 347 reg = <0x0914>; 348 }; 349 350 timer1_fck: timer1_fck { 351 #clock-cells = <0>; 352 compatible = "ti,mux-clock"; 353 clocks = <&sys_clkin_ck>, <&clkdiv32k_ick>, <&tclkin_ck>, <&clk_rc32k_ck>, <&clk_32768_ck>; 354 reg = <0x0528>; 355 }; 356 357 timer2_fck: timer2_fck { 358 #clock-cells = <0>; 359 compatible = "ti,mux-clock"; 360 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 361 reg = <0x0508>; 362 }; 363 364 timer3_fck: timer3_fck { 365 #clock-cells = <0>; 366 compatible = "ti,mux-clock"; 367 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 368 reg = <0x050c>; 369 }; 370 371 timer4_fck: timer4_fck { 372 #clock-cells = <0>; 373 compatible = "ti,mux-clock"; 374 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 375 reg = <0x0510>; 376 }; 377 378 timer5_fck: timer5_fck { 379 #clock-cells = <0>; 380 compatible = "ti,mux-clock"; 381 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 382 reg = <0x0518>; 383 }; 384 385 timer6_fck: timer6_fck { 386 #clock-cells = <0>; 387 compatible = "ti,mux-clock"; 388 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 389 reg = <0x051c>; 390 }; 391 392 timer7_fck: timer7_fck { 393 #clock-cells = <0>; 394 compatible = "ti,mux-clock"; 395 clocks = <&tclkin_ck>, <&sys_clkin_ck>, <&clkdiv32k_ick>; 396 reg = <0x0504>; 397 }; 398 399 usbotg_fck: usbotg_fck { 400 #clock-cells = <0>; 401 compatible = "ti,gate-clock"; 402 clocks = <&dpll_per_ck>; 403 ti,bit-shift = <8>; 404 reg = <0x047c>; 405 }; 406 407 dpll_core_m4_div2_ck: dpll_core_m4_div2_ck { 408 #clock-cells = <0>; 409 compatible = "fixed-factor-clock"; 410 clocks = <&dpll_core_m4_ck>; 411 clock-mult = <1>; 412 clock-div = <2>; 413 }; 414 415 ieee5000_fck: ieee5000_fck { 416 #clock-cells = <0>; 417 compatible = "ti,gate-clock"; 418 clocks = <&dpll_core_m4_div2_ck>; 419 ti,bit-shift = <1>; 420 reg = <0x00e4>; 421 }; 422 423 wdt1_fck: wdt1_fck { 424 #clock-cells = <0>; 425 compatible = "ti,mux-clock"; 426 clocks = <&clk_rc32k_ck>, <&clkdiv32k_ick>; 427 reg = <0x0538>; 428 }; 429 430 l4_rtc_gclk: l4_rtc_gclk { 431 #clock-cells = <0>; 432 compatible = "fixed-factor-clock"; 433 clocks = <&dpll_core_m4_ck>; 434 clock-mult = <1>; 435 clock-div = <2>; 436 }; 437 438 l4hs_gclk: l4hs_gclk { 439 #clock-cells = <0>; 440 compatible = "fixed-factor-clock"; 441 clocks = <&dpll_core_m4_ck>; 442 clock-mult = <1>; 443 clock-div = <1>; 444 }; 445 446 l3s_gclk: l3s_gclk { 447 #clock-cells = <0>; 448 compatible = "fixed-factor-clock"; 449 clocks = <&dpll_core_m4_div2_ck>; 450 clock-mult = <1>; 451 clock-div = <1>; 452 }; 453 454 l4fw_gclk: l4fw_gclk { 455 #clock-cells = <0>; 456 compatible = "fixed-factor-clock"; 457 clocks = <&dpll_core_m4_div2_ck>; 458 clock-mult = <1>; 459 clock-div = <1>; 460 }; 461 462 l4ls_gclk: l4ls_gclk { 463 #clock-cells = <0>; 464 compatible = "fixed-factor-clock"; 465 clocks = <&dpll_core_m4_div2_ck>; 466 clock-mult = <1>; 467 clock-div = <1>; 468 }; 469 470 sysclk_div_ck: sysclk_div_ck { 471 #clock-cells = <0>; 472 compatible = "fixed-factor-clock"; 473 clocks = <&dpll_core_m4_ck>; 474 clock-mult = <1>; 475 clock-div = <1>; 476 }; 477 478 cpsw_125mhz_gclk: cpsw_125mhz_gclk { 479 #clock-cells = <0>; 480 compatible = "fixed-factor-clock"; 481 clocks = <&dpll_core_m5_ck>; 482 clock-mult = <1>; 483 clock-div = <2>; 484 }; 485 486 cpsw_cpts_rft_clk: cpsw_cpts_rft_clk { 487 #clock-cells = <0>; 488 compatible = "ti,mux-clock"; 489 clocks = <&dpll_core_m5_ck>, <&dpll_core_m4_ck>; 490 reg = <0x0520>; 491 }; 492 493 gpio0_dbclk_mux_ck: gpio0_dbclk_mux_ck { 494 #clock-cells = <0>; 495 compatible = "ti,mux-clock"; 496 clocks = <&clk_rc32k_ck>, <&clk_32768_ck>, <&clkdiv32k_ick>; 497 reg = <0x053c>; 498 }; 499 500 gpio0_dbclk: gpio0_dbclk { 501 #clock-cells = <0>; 502 compatible = "ti,gate-clock"; 503 clocks = <&gpio0_dbclk_mux_ck>; 504 ti,bit-shift = <18>; 505 reg = <0x0408>; 506 }; 507 508 gpio1_dbclk: gpio1_dbclk { 509 #clock-cells = <0>; 510 compatible = "ti,gate-clock"; 511 clocks = <&clkdiv32k_ick>; 512 ti,bit-shift = <18>; 513 reg = <0x00ac>; 514 }; 515 516 gpio2_dbclk: gpio2_dbclk { 517 #clock-cells = <0>; 518 compatible = "ti,gate-clock"; 519 clocks = <&clkdiv32k_ick>; 520 ti,bit-shift = <18>; 521 reg = <0x00b0>; 522 }; 523 524 gpio3_dbclk: gpio3_dbclk { 525 #clock-cells = <0>; 526 compatible = "ti,gate-clock"; 527 clocks = <&clkdiv32k_ick>; 528 ti,bit-shift = <18>; 529 reg = <0x00b4>; 530 }; 531 532 lcd_gclk: lcd_gclk { 533 #clock-cells = <0>; 534 compatible = "ti,mux-clock"; 535 clocks = <&dpll_disp_m2_ck>, <&dpll_core_m5_ck>, <&dpll_per_m2_ck>; 536 reg = <0x0534>; 537 ti,set-rate-parent; 538 }; 539 540 mmc_clk: mmc_clk { 541 #clock-cells = <0>; 542 compatible = "fixed-factor-clock"; 543 clocks = <&dpll_per_m2_ck>; 544 clock-mult = <1>; 545 clock-div = <2>; 546 }; 547 548 gfx_fclk_clksel_ck: gfx_fclk_clksel_ck { 549 #clock-cells = <0>; 550 compatible = "ti,mux-clock"; 551 clocks = <&dpll_core_m4_ck>, <&dpll_per_m2_ck>; 552 ti,bit-shift = <1>; 553 reg = <0x052c>; 554 }; 555 556 gfx_fck_div_ck: gfx_fck_div_ck { 557 #clock-cells = <0>; 558 compatible = "ti,divider-clock"; 559 clocks = <&gfx_fclk_clksel_ck>; 560 reg = <0x052c>; 561 ti,max-div = <2>; 562 }; 563 564 sysclkout_pre_ck: sysclkout_pre_ck { 565 #clock-cells = <0>; 566 compatible = "ti,mux-clock"; 567 clocks = <&clk_32768_ck>, <&l3_gclk>, <&dpll_ddr_m2_ck>, <&dpll_per_m2_ck>, <&lcd_gclk>; 568 reg = <0x0700>; 569 }; 570 571 clkout2_div_ck: clkout2_div_ck { 572 #clock-cells = <0>; 573 compatible = "ti,divider-clock"; 574 clocks = <&sysclkout_pre_ck>; 575 ti,bit-shift = <3>; 576 ti,max-div = <8>; 577 reg = <0x0700>; 578 }; 579 580 dbg_sysclk_ck: dbg_sysclk_ck { 581 #clock-cells = <0>; 582 compatible = "ti,gate-clock"; 583 clocks = <&sys_clkin_ck>; 584 ti,bit-shift = <19>; 585 reg = <0x0414>; 586 }; 587 588 dbg_clka_ck: dbg_clka_ck { 589 #clock-cells = <0>; 590 compatible = "ti,gate-clock"; 591 clocks = <&dpll_core_m4_ck>; 592 ti,bit-shift = <30>; 593 reg = <0x0414>; 594 }; 595 596 stm_pmd_clock_mux_ck: stm_pmd_clock_mux_ck { 597 #clock-cells = <0>; 598 compatible = "ti,mux-clock"; 599 clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>; 600 ti,bit-shift = <22>; 601 reg = <0x0414>; 602 }; 603 604 trace_pmd_clk_mux_ck: trace_pmd_clk_mux_ck { 605 #clock-cells = <0>; 606 compatible = "ti,mux-clock"; 607 clocks = <&dbg_sysclk_ck>, <&dbg_clka_ck>; 608 ti,bit-shift = <20>; 609 reg = <0x0414>; 610 }; 611 612 stm_clk_div_ck: stm_clk_div_ck { 613 #clock-cells = <0>; 614 compatible = "ti,divider-clock"; 615 clocks = <&stm_pmd_clock_mux_ck>; 616 ti,bit-shift = <27>; 617 ti,max-div = <64>; 618 reg = <0x0414>; 619 ti,index-power-of-two; 620 }; 621 622 trace_clk_div_ck: trace_clk_div_ck { 623 #clock-cells = <0>; 624 compatible = "ti,divider-clock"; 625 clocks = <&trace_pmd_clk_mux_ck>; 626 ti,bit-shift = <24>; 627 ti,max-div = <64>; 628 reg = <0x0414>; 629 ti,index-power-of-two; 630 }; 631 632 clkout2_ck: clkout2_ck { 633 #clock-cells = <0>; 634 compatible = "ti,gate-clock"; 635 clocks = <&clkout2_div_ck>; 636 ti,bit-shift = <7>; 637 reg = <0x0700>; 638 }; 639}; 640 641&prcm_clockdomains { 642 clk_24mhz_clkdm: clk_24mhz_clkdm { 643 compatible = "ti,clockdomain"; 644 clocks = <&clkdiv32k_ick>; 645 }; 646}; 647