am335x-evm.dts revision 284090
1/* 2 * Copyright (C) 2012 Texas Instruments Incorporated - http://www.ti.com/ 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 */ 8/dts-v1/; 9 10#include "am33xx.dtsi" 11 12/ { 13 model = "TI AM335x EVM"; 14 compatible = "ti,am335x-evm", "ti,am33xx"; 15 16 cpus { 17 cpu@0 { 18 cpu0-supply = <&vdd1_reg>; 19 }; 20 }; 21 22 memory { 23 device_type = "memory"; 24 reg = <0x80000000 0x10000000>; /* 256 MB */ 25 }; 26 27 vbat: fixedregulator@0 { 28 compatible = "regulator-fixed"; 29 regulator-name = "vbat"; 30 regulator-min-microvolt = <5000000>; 31 regulator-max-microvolt = <5000000>; 32 regulator-boot-on; 33 }; 34 35 lis3_reg: fixedregulator@1 { 36 compatible = "regulator-fixed"; 37 regulator-name = "lis3_reg"; 38 regulator-boot-on; 39 }; 40 41 matrix_keypad: matrix_keypad@0 { 42 compatible = "gpio-matrix-keypad"; 43 debounce-delay-ms = <5>; 44 col-scan-delay-us = <2>; 45 46 row-gpios = <&gpio1 25 GPIO_ACTIVE_HIGH /* Bank1, pin25 */ 47 &gpio1 26 GPIO_ACTIVE_HIGH /* Bank1, pin26 */ 48 &gpio1 27 GPIO_ACTIVE_HIGH>; /* Bank1, pin27 */ 49 50 col-gpios = <&gpio1 21 GPIO_ACTIVE_HIGH /* Bank1, pin21 */ 51 &gpio1 22 GPIO_ACTIVE_HIGH>; /* Bank1, pin22 */ 52 53 linux,keymap = <0x0000008b /* MENU */ 54 0x0100009e /* BACK */ 55 0x02000069 /* LEFT */ 56 0x0001006a /* RIGHT */ 57 0x0101001c /* ENTER */ 58 0x0201006c>; /* DOWN */ 59 }; 60 61 gpio_keys: volume_keys@0 { 62 compatible = "gpio-keys"; 63 #address-cells = <1>; 64 #size-cells = <0>; 65 autorepeat; 66 67 switch@9 { 68 label = "volume-up"; 69 linux,code = <115>; 70 gpios = <&gpio0 2 GPIO_ACTIVE_LOW>; 71 gpio-key,wakeup; 72 }; 73 74 switch@10 { 75 label = "volume-down"; 76 linux,code = <114>; 77 gpios = <&gpio0 3 GPIO_ACTIVE_LOW>; 78 gpio-key,wakeup; 79 }; 80 }; 81 82 backlight { 83 compatible = "pwm-backlight"; 84 pwms = <&ecap0 0 50000 0>; 85 brightness-levels = <0 51 53 56 62 75 101 152 255>; 86 default-brightness-level = <8>; 87 }; 88 89 panel { 90 compatible = "ti,tilcdc,panel"; 91 status = "okay"; 92 pinctrl-names = "default"; 93 pinctrl-0 = <&lcd_pins_s0>; 94 panel-info { 95 ac-bias = <255>; 96 ac-bias-intrpt = <0>; 97 dma-burst-sz = <16>; 98 bpp = <32>; 99 fdd = <0x80>; 100 sync-edge = <0>; 101 sync-ctrl = <1>; 102 raster-order = <0>; 103 fifo-th = <0>; 104 }; 105 106 display-timings { 107 800x480p62 { 108 clock-frequency = <30000000>; 109 hactive = <800>; 110 vactive = <480>; 111 hfront-porch = <39>; 112 hback-porch = <39>; 113 hsync-len = <47>; 114 vback-porch = <29>; 115 vfront-porch = <13>; 116 vsync-len = <2>; 117 hsync-active = <1>; 118 vsync-active = <1>; 119 }; 120 }; 121 }; 122 123 sound { 124 compatible = "ti,da830-evm-audio"; 125 ti,model = "AM335x-EVM"; 126 ti,audio-codec = <&tlv320aic3106>; 127 ti,mcasp-controller = <&mcasp1>; 128 ti,codec-clock-rate = <12000000>; 129 ti,audio-routing = 130 "Headphone Jack", "HPLOUT", 131 "Headphone Jack", "HPROUT", 132 "LINE1L", "Line In", 133 "LINE1R", "Line In"; 134 }; 135}; 136 137&am33xx_pinmux { 138 pinctrl-names = "default"; 139 pinctrl-0 = <&matrix_keypad_s0 &volume_keys_s0 &clkout2_pin>; 140 141 matrix_keypad_s0: matrix_keypad_s0 { 142 pinctrl-single,pins = < 143 0x54 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a5.gpio1_21 */ 144 0x58 (PIN_OUTPUT_PULLDOWN | MUX_MODE7) /* gpmc_a6.gpio1_22 */ 145 0x64 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a9.gpio1_25 */ 146 0x68 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a10.gpio1_26 */ 147 0x6c (PIN_INPUT_PULLDOWN | MUX_MODE7) /* gpmc_a11.gpio1_27 */ 148 >; 149 }; 150 151 volume_keys_s0: volume_keys_s0 { 152 pinctrl-single,pins = < 153 0x150 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_sclk.gpio0_2 */ 154 0x154 (PIN_INPUT_PULLDOWN | MUX_MODE7) /* spi0_d0.gpio0_3 */ 155 >; 156 }; 157 158 i2c0_pins: pinmux_i2c0_pins { 159 pinctrl-single,pins = < 160 0x188 (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_sda.i2c0_sda */ 161 0x18c (PIN_INPUT_PULLUP | MUX_MODE0) /* i2c0_scl.i2c0_scl */ 162 >; 163 }; 164 165 i2c1_pins: pinmux_i2c1_pins { 166 pinctrl-single,pins = < 167 0x158 (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_d1.i2c1_sda */ 168 0x15c (PIN_INPUT_PULLUP | MUX_MODE2) /* spi0_cs0.i2c1_scl */ 169 >; 170 }; 171 172 uart0_pins: pinmux_uart0_pins { 173 pinctrl-single,pins = < 174 0x170 (PIN_INPUT_PULLUP | MUX_MODE0) /* uart0_rxd.uart0_rxd */ 175 0x174 (PIN_OUTPUT_PULLDOWN | MUX_MODE0) /* uart0_txd.uart0_txd */ 176 >; 177 }; 178 179 clkout2_pin: pinmux_clkout2_pin { 180 pinctrl-single,pins = < 181 0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */ 182 >; 183 }; 184 185 nandflash_pins_s0: nandflash_pins_s0 { 186 pinctrl-single,pins = < 187 0x0 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad0.gpmc_ad0 */ 188 0x4 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad1.gpmc_ad1 */ 189 0x8 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad2.gpmc_ad2 */ 190 0xc (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad3.gpmc_ad3 */ 191 0x10 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad4.gpmc_ad4 */ 192 0x14 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad5.gpmc_ad5 */ 193 0x18 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad6.gpmc_ad6 */ 194 0x1c (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_ad7.gpmc_ad7 */ 195 0x70 (PIN_INPUT_PULLUP | MUX_MODE0) /* gpmc_wait0.gpmc_wait0 */ 196 0x74 (PIN_INPUT_PULLUP | MUX_MODE7) /* gpmc_wpn.gpio0_30 */ 197 0x7c (PIN_OUTPUT | MUX_MODE0) /* gpmc_csn0.gpmc_csn0 */ 198 0x90 (PIN_OUTPUT | MUX_MODE0) /* gpmc_advn_ale.gpmc_advn_ale */ 199 0x94 (PIN_OUTPUT | MUX_MODE0) /* gpmc_oen_ren.gpmc_oen_ren */ 200 0x98 (PIN_OUTPUT | MUX_MODE0) /* gpmc_wen.gpmc_wen */ 201 0x9c (PIN_OUTPUT | MUX_MODE0) /* gpmc_be0n_cle.gpmc_be0n_cle */ 202 >; 203 }; 204 205 ecap0_pins: backlight_pins { 206 pinctrl-single,pins = < 207 0x164 0x0 /* eCAP0_in_PWM0_out.eCAP0_in_PWM0_out MODE0 */ 208 >; 209 }; 210 211 cpsw_default: cpsw_default { 212 pinctrl-single,pins = < 213 /* Slave 1 */ 214 0x114 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txen.rgmii1_tctl */ 215 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxdv.rgmii1_rctl */ 216 0x11c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd3.rgmii1_td3 */ 217 0x120 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd2.rgmii1_td2 */ 218 0x124 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd1.rgmii1_td1 */ 219 0x128 (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txd0.rgmii1_td0 */ 220 0x12c (PIN_OUTPUT_PULLDOWN | MUX_MODE2) /* mii1_txclk.rgmii1_tclk */ 221 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxclk.rgmii1_rclk */ 222 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd3.rgmii1_rd3 */ 223 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd2.rgmii1_rd2 */ 224 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd1.rgmii1_rd1 */ 225 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE2) /* mii1_rxd0.rgmii1_rd0 */ 226 >; 227 }; 228 229 cpsw_sleep: cpsw_sleep { 230 pinctrl-single,pins = < 231 /* Slave 1 reset value */ 232 0x114 (PIN_INPUT_PULLDOWN | MUX_MODE7) 233 0x118 (PIN_INPUT_PULLDOWN | MUX_MODE7) 234 0x11c (PIN_INPUT_PULLDOWN | MUX_MODE7) 235 0x120 (PIN_INPUT_PULLDOWN | MUX_MODE7) 236 0x124 (PIN_INPUT_PULLDOWN | MUX_MODE7) 237 0x128 (PIN_INPUT_PULLDOWN | MUX_MODE7) 238 0x12c (PIN_INPUT_PULLDOWN | MUX_MODE7) 239 0x130 (PIN_INPUT_PULLDOWN | MUX_MODE7) 240 0x134 (PIN_INPUT_PULLDOWN | MUX_MODE7) 241 0x138 (PIN_INPUT_PULLDOWN | MUX_MODE7) 242 0x13c (PIN_INPUT_PULLDOWN | MUX_MODE7) 243 0x140 (PIN_INPUT_PULLDOWN | MUX_MODE7) 244 >; 245 }; 246 247 davinci_mdio_default: davinci_mdio_default { 248 pinctrl-single,pins = < 249 /* MDIO */ 250 0x148 (PIN_INPUT_PULLUP | SLEWCTRL_FAST | MUX_MODE0) /* mdio_data.mdio_data */ 251 0x14c (PIN_OUTPUT_PULLUP | MUX_MODE0) /* mdio_clk.mdio_clk */ 252 >; 253 }; 254 255 davinci_mdio_sleep: davinci_mdio_sleep { 256 pinctrl-single,pins = < 257 /* MDIO reset value */ 258 0x148 (PIN_INPUT_PULLDOWN | MUX_MODE7) 259 0x14c (PIN_INPUT_PULLDOWN | MUX_MODE7) 260 >; 261 }; 262 263 mmc1_pins: pinmux_mmc1_pins { 264 pinctrl-single,pins = < 265 0x160 (PIN_INPUT | MUX_MODE7) /* spi0_cs1.gpio0_6 */ 266 >; 267 }; 268 269 lcd_pins_s0: lcd_pins_s0 { 270 pinctrl-single,pins = < 271 0x20 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad8.lcd_data23 */ 272 0x24 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad9.lcd_data22 */ 273 0x28 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad10.lcd_data21 */ 274 0x2c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad11.lcd_data20 */ 275 0x30 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad12.lcd_data19 */ 276 0x34 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad13.lcd_data18 */ 277 0x38 (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad14.lcd_data17 */ 278 0x3c (PIN_OUTPUT | MUX_MODE1) /* gpmc_ad15.lcd_data16 */ 279 0xa0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data0.lcd_data0 */ 280 0xa4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data1.lcd_data1 */ 281 0xa8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data2.lcd_data2 */ 282 0xac (PIN_OUTPUT | MUX_MODE0) /* lcd_data3.lcd_data3 */ 283 0xb0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data4.lcd_data4 */ 284 0xb4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data5.lcd_data5 */ 285 0xb8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data6.lcd_data6 */ 286 0xbc (PIN_OUTPUT | MUX_MODE0) /* lcd_data7.lcd_data7 */ 287 0xc0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data8.lcd_data8 */ 288 0xc4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data9.lcd_data9 */ 289 0xc8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data10.lcd_data10 */ 290 0xcc (PIN_OUTPUT | MUX_MODE0) /* lcd_data11.lcd_data11 */ 291 0xd0 (PIN_OUTPUT | MUX_MODE0) /* lcd_data12.lcd_data12 */ 292 0xd4 (PIN_OUTPUT | MUX_MODE0) /* lcd_data13.lcd_data13 */ 293 0xd8 (PIN_OUTPUT | MUX_MODE0) /* lcd_data14.lcd_data14 */ 294 0xdc (PIN_OUTPUT | MUX_MODE0) /* lcd_data15.lcd_data15 */ 295 0xe0 (PIN_OUTPUT | MUX_MODE0) /* lcd_vsync.lcd_vsync */ 296 0xe4 (PIN_OUTPUT | MUX_MODE0) /* lcd_hsync.lcd_hsync */ 297 0xe8 (PIN_OUTPUT | MUX_MODE0) /* lcd_pclk.lcd_pclk */ 298 0xec (PIN_OUTPUT | MUX_MODE0) /* lcd_ac_bias_en.lcd_ac_bias_en */ 299 >; 300 }; 301 302 am335x_evm_audio_pins: am335x_evm_audio_pins { 303 pinctrl-single,pins = < 304 0x10c (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_crs.mcasp1_aclkx */ 305 0x110 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* mii1_rxerr.mcasp1_fsx */ 306 0x108 (PIN_OUTPUT_PULLDOWN | MUX_MODE4) /* mii1_col.mcasp1_axr2 */ 307 0x144 (PIN_INPUT_PULLDOWN | MUX_MODE4) /* rmii1_ref_clk.mcasp1_axr3 */ 308 >; 309 }; 310 311 dcan1_pins_default: dcan1_pins_default { 312 pinctrl-single,pins = < 313 0x168 (PIN_OUTPUT | MUX_MODE2) /* uart0_ctsn.d_can1_tx */ 314 0x16c (PIN_INPUT_PULLDOWN | MUX_MODE2) /* uart0_rtsn.d_can1_rx */ 315 >; 316 }; 317}; 318 319&uart0 { 320 pinctrl-names = "default"; 321 pinctrl-0 = <&uart0_pins>; 322 323 status = "okay"; 324}; 325 326&i2c0 { 327 pinctrl-names = "default"; 328 pinctrl-0 = <&i2c0_pins>; 329 330 status = "okay"; 331 clock-frequency = <400000>; 332 333 tps: tps@2d { 334 reg = <0x2d>; 335 }; 336}; 337 338&usb { 339 status = "okay"; 340}; 341 342&usb_ctrl_mod { 343 status = "okay"; 344}; 345 346&usb0_phy { 347 status = "okay"; 348}; 349 350&usb1_phy { 351 status = "okay"; 352}; 353 354&usb0 { 355 status = "okay"; 356}; 357 358&usb1 { 359 status = "okay"; 360 dr_mode = "host"; 361}; 362 363&cppi41dma { 364 status = "okay"; 365}; 366 367&i2c1 { 368 pinctrl-names = "default"; 369 pinctrl-0 = <&i2c1_pins>; 370 371 status = "okay"; 372 clock-frequency = <100000>; 373 374 lis331dlh: lis331dlh@18 { 375 compatible = "st,lis331dlh", "st,lis3lv02d"; 376 reg = <0x18>; 377 Vdd-supply = <&lis3_reg>; 378 Vdd_IO-supply = <&lis3_reg>; 379 380 st,click-single-x; 381 st,click-single-y; 382 st,click-single-z; 383 st,click-thresh-x = <10>; 384 st,click-thresh-y = <10>; 385 st,click-thresh-z = <10>; 386 st,irq1-click; 387 st,irq2-click; 388 st,wakeup-x-lo; 389 st,wakeup-x-hi; 390 st,wakeup-y-lo; 391 st,wakeup-y-hi; 392 st,wakeup-z-lo; 393 st,wakeup-z-hi; 394 st,min-limit-x = <120>; 395 st,min-limit-y = <120>; 396 st,min-limit-z = <140>; 397 st,max-limit-x = <550>; 398 st,max-limit-y = <550>; 399 st,max-limit-z = <750>; 400 }; 401 402 tsl2550: tsl2550@39 { 403 compatible = "taos,tsl2550"; 404 reg = <0x39>; 405 }; 406 407 tmp275: tmp275@48 { 408 compatible = "ti,tmp275"; 409 reg = <0x48>; 410 }; 411 412 tlv320aic3106: tlv320aic3106@1b { 413 compatible = "ti,tlv320aic3106"; 414 reg = <0x1b>; 415 status = "okay"; 416 417 /* Regulators */ 418 AVDD-supply = <&vaux2_reg>; 419 IOVDD-supply = <&vaux2_reg>; 420 DRVDD-supply = <&vaux2_reg>; 421 DVDD-supply = <&vbat>; 422 }; 423}; 424 425&lcdc { 426 status = "okay"; 427}; 428 429&elm { 430 status = "okay"; 431}; 432 433&epwmss0 { 434 status = "okay"; 435 436 ecap0: ecap@48300100 { 437 status = "okay"; 438 pinctrl-names = "default"; 439 pinctrl-0 = <&ecap0_pins>; 440 }; 441}; 442 443&gpmc { 444 status = "okay"; 445 pinctrl-names = "default"; 446 pinctrl-0 = <&nandflash_pins_s0>; 447 ranges = <0 0 0x08000000 0x1000000>; /* CS0: 16MB for NAND */ 448 nand@0,0 { 449 reg = <0 0 4>; /* CS0, offset 0, IO size 4 */ 450 ti,nand-ecc-opt = "bch8"; 451 ti,elm-id = <&elm>; 452 nand-bus-width = <8>; 453 gpmc,device-width = <1>; 454 gpmc,sync-clk-ps = <0>; 455 gpmc,cs-on-ns = <0>; 456 gpmc,cs-rd-off-ns = <44>; 457 gpmc,cs-wr-off-ns = <44>; 458 gpmc,adv-on-ns = <6>; 459 gpmc,adv-rd-off-ns = <34>; 460 gpmc,adv-wr-off-ns = <44>; 461 gpmc,we-on-ns = <0>; 462 gpmc,we-off-ns = <40>; 463 gpmc,oe-on-ns = <0>; 464 gpmc,oe-off-ns = <54>; 465 gpmc,access-ns = <64>; 466 gpmc,rd-cycle-ns = <82>; 467 gpmc,wr-cycle-ns = <82>; 468 gpmc,wait-on-read = "true"; 469 gpmc,wait-on-write = "true"; 470 gpmc,bus-turnaround-ns = <0>; 471 gpmc,cycle2cycle-delay-ns = <0>; 472 gpmc,clk-activation-ns = <0>; 473 gpmc,wait-monitoring-ns = <0>; 474 gpmc,wr-access-ns = <40>; 475 gpmc,wr-data-mux-bus-ns = <0>; 476 /* MTD partition table */ 477 /* All SPL-* partitions are sized to minimal length 478 * which can be independently programmable. For 479 * NAND flash this is equal to size of erase-block */ 480 #address-cells = <1>; 481 #size-cells = <1>; 482 partition@0 { 483 label = "NAND.SPL"; 484 reg = <0x00000000 0x000020000>; 485 }; 486 partition@1 { 487 label = "NAND.SPL.backup1"; 488 reg = <0x00020000 0x00020000>; 489 }; 490 partition@2 { 491 label = "NAND.SPL.backup2"; 492 reg = <0x00040000 0x00020000>; 493 }; 494 partition@3 { 495 label = "NAND.SPL.backup3"; 496 reg = <0x00060000 0x00020000>; 497 }; 498 partition@4 { 499 label = "NAND.u-boot-spl-os"; 500 reg = <0x00080000 0x00040000>; 501 }; 502 partition@5 { 503 label = "NAND.u-boot"; 504 reg = <0x000C0000 0x00100000>; 505 }; 506 partition@6 { 507 label = "NAND.u-boot-env"; 508 reg = <0x001C0000 0x00020000>; 509 }; 510 partition@7 { 511 label = "NAND.u-boot-env.backup1"; 512 reg = <0x001E0000 0x00020000>; 513 }; 514 partition@8 { 515 label = "NAND.kernel"; 516 reg = <0x00200000 0x00800000>; 517 }; 518 partition@9 { 519 label = "NAND.file-system"; 520 reg = <0x00A00000 0x0F600000>; 521 }; 522 }; 523}; 524 525#include "tps65910.dtsi" 526 527&mcasp1 { 528 pinctrl-names = "default"; 529 pinctrl-0 = <&am335x_evm_audio_pins>; 530 531 status = "okay"; 532 533 op-mode = <0>; /* MCASP_IIS_MODE */ 534 tdm-slots = <2>; 535 /* 4 serializers */ 536 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 537 0 0 1 2 538 >; 539 tx-num-evt = <32>; 540 rx-num-evt = <32>; 541}; 542 543&tps { 544 vcc1-supply = <&vbat>; 545 vcc2-supply = <&vbat>; 546 vcc3-supply = <&vbat>; 547 vcc4-supply = <&vbat>; 548 vcc5-supply = <&vbat>; 549 vcc6-supply = <&vbat>; 550 vcc7-supply = <&vbat>; 551 vccio-supply = <&vbat>; 552 553 regulators { 554 vrtc_reg: regulator@0 { 555 regulator-always-on; 556 }; 557 558 vio_reg: regulator@1 { 559 regulator-always-on; 560 }; 561 562 vdd1_reg: regulator@2 { 563 /* VDD_MPU voltage limits 0.95V - 1.26V with +/-4% tolerance */ 564 regulator-name = "vdd_mpu"; 565 regulator-min-microvolt = <912500>; 566 regulator-max-microvolt = <1312500>; 567 regulator-boot-on; 568 regulator-always-on; 569 }; 570 571 vdd2_reg: regulator@3 { 572 /* VDD_CORE voltage limits 0.95V - 1.1V with +/-4% tolerance */ 573 regulator-name = "vdd_core"; 574 regulator-min-microvolt = <912500>; 575 regulator-max-microvolt = <1150000>; 576 regulator-boot-on; 577 regulator-always-on; 578 }; 579 580 vdd3_reg: regulator@4 { 581 regulator-always-on; 582 }; 583 584 vdig1_reg: regulator@5 { 585 regulator-always-on; 586 }; 587 588 vdig2_reg: regulator@6 { 589 regulator-always-on; 590 }; 591 592 vpll_reg: regulator@7 { 593 regulator-always-on; 594 }; 595 596 vdac_reg: regulator@8 { 597 regulator-always-on; 598 }; 599 600 vaux1_reg: regulator@9 { 601 regulator-always-on; 602 }; 603 604 vaux2_reg: regulator@10 { 605 regulator-always-on; 606 }; 607 608 vaux33_reg: regulator@11 { 609 regulator-always-on; 610 }; 611 612 vmmc_reg: regulator@12 { 613 regulator-min-microvolt = <1800000>; 614 regulator-max-microvolt = <3300000>; 615 regulator-always-on; 616 }; 617 }; 618}; 619 620&mac { 621 pinctrl-names = "default", "sleep"; 622 pinctrl-0 = <&cpsw_default>; 623 pinctrl-1 = <&cpsw_sleep>; 624 status = "okay"; 625}; 626 627&davinci_mdio { 628 pinctrl-names = "default", "sleep"; 629 pinctrl-0 = <&davinci_mdio_default>; 630 pinctrl-1 = <&davinci_mdio_sleep>; 631 status = "okay"; 632}; 633 634&cpsw_emac0 { 635 phy_id = <&davinci_mdio>, <0>; 636 phy-mode = "rgmii-txid"; 637}; 638 639&cpsw_emac1 { 640 phy_id = <&davinci_mdio>, <1>; 641 phy-mode = "rgmii-txid"; 642}; 643 644&tscadc { 645 status = "okay"; 646 tsc { 647 ti,wires = <4>; 648 ti,x-plate-resistance = <200>; 649 ti,coordinate-readouts = <5>; 650 ti,wire-config = <0x00 0x11 0x22 0x33>; 651 ti,charge-delay = <0x400>; 652 }; 653 654 adc { 655 ti,adc-channels = <4 5 6 7>; 656 }; 657}; 658 659&mmc1 { 660 status = "okay"; 661 vmmc-supply = <&vmmc_reg>; 662 bus-width = <4>; 663 pinctrl-names = "default"; 664 pinctrl-0 = <&mmc1_pins>; 665 cd-gpios = <&gpio0 6 GPIO_ACTIVE_HIGH>; 666}; 667 668&sham { 669 status = "okay"; 670}; 671 672&aes { 673 status = "okay"; 674}; 675 676&dcan1 { 677 status = "disabled"; /* Enable only if Profile 1 is selected */ 678 pinctrl-names = "default"; 679 pinctrl-0 = <&dcan1_pins_default>; 680}; 681