1184610Salfred/*- 2184610Salfred * Copyright (c) 1997, 1998, 1999 3184610Salfred * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 4184610Salfred * 5184610Salfred * Redistribution and use in source and binary forms, with or without 6184610Salfred * modification, are permitted provided that the following conditions 7184610Salfred * are met: 8184610Salfred * 1. Redistributions of source code must retain the above copyright 9184610Salfred * notice, this list of conditions and the following disclaimer. 10184610Salfred * 2. Redistributions in binary form must reproduce the above copyright 11184610Salfred * notice, this list of conditions and the following disclaimer in the 12184610Salfred * documentation and/or other materials provided with the distribution. 13184610Salfred * 3. All advertising materials mentioning features or use of this software 14184610Salfred * must display the following acknowledgement: 15184610Salfred * This product includes software developed by Bill Paul. 16184610Salfred * 4. Neither the name of the author nor the names of any co-contributors 17184610Salfred * may be used to endorse or promote products derived from this software 18184610Salfred * without specific prior written permission. 19184610Salfred * 20184610Salfred * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21184610Salfred * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22184610Salfred * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23184610Salfred * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24184610Salfred * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25184610Salfred * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26184610Salfred * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27184610Salfred * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28184610Salfred * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29184610Salfred * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30184610Salfred * THE POSSIBILITY OF SUCH DAMAGE. 31184610Salfred * 32184610Salfred * $FreeBSD$ 33184610Salfred */ 34184610Salfred 35184610Salfred/* 36184610Salfred * Register definitions for ADMtek Pegasus AN986 USB to Ethernet 37184610Salfred * chip. The Pegasus uses a total of four USB endpoints: the control 38184610Salfred * endpoint (0), a bulk read endpoint for receiving packets (1), 39184610Salfred * a bulk write endpoint for sending packets (2) and an interrupt 40184610Salfred * endpoint for passing RX and TX status (3). Endpoint 0 is used 41184610Salfred * to read and write the ethernet module's registers. All registers 42184610Salfred * are 8 bits wide. 43184610Salfred * 44184610Salfred * Packet transfer is done in 64 byte chunks. The last chunk in a 45188412Sthompsa * transfer is denoted by having a length less that 64 bytes. For 46184610Salfred * the RX case, the data includes an optional RX status word. 47184610Salfred */ 48184610Salfred 49184610Salfred#define AUE_UR_READREG 0xF0 50184610Salfred#define AUE_UR_WRITEREG 0xF1 51184610Salfred 52184610Salfred#define AUE_CONFIG_INDEX 0 /* config number 1 */ 53184610Salfred#define AUE_IFACE_IDX 0 54184610Salfred 55184610Salfred/* 56184610Salfred * Note that while the ADMtek technically has four endpoints, the control 57184610Salfred * endpoint (endpoint 0) is regarded as special by the USB code and drivers 58194228Sthompsa * don't have direct access to it (we access it using usbd_do_request() 59184610Salfred * when reading/writing registers. Consequently, our endpoint indexes 60184610Salfred * don't match those in the ADMtek Pegasus manual: we consider the RX data 61184610Salfred * endpoint to be index 0 and work up from there. 62184610Salfred */ 63187259Sthompsaenum { 64187259Sthompsa AUE_BULK_DT_WR, 65187259Sthompsa AUE_BULK_DT_RD, 66187259Sthompsa AUE_INTR_DT_RD, 67188412Sthompsa AUE_N_TRANSFER, 68187259Sthompsa}; 69184610Salfred 70184610Salfred#define AUE_INTR_PKTLEN 0x8 71184610Salfred 72184610Salfred#define AUE_CTL0 0x00 73184610Salfred#define AUE_CTL1 0x01 74184610Salfred#define AUE_CTL2 0x02 75184610Salfred#define AUE_MAR0 0x08 76184610Salfred#define AUE_MAR1 0x09 77184610Salfred#define AUE_MAR2 0x0A 78184610Salfred#define AUE_MAR3 0x0B 79184610Salfred#define AUE_MAR4 0x0C 80184610Salfred#define AUE_MAR5 0x0D 81184610Salfred#define AUE_MAR6 0x0E 82184610Salfred#define AUE_MAR7 0x0F 83184610Salfred#define AUE_MAR AUE_MAR0 84184610Salfred#define AUE_PAR0 0x10 85184610Salfred#define AUE_PAR1 0x11 86184610Salfred#define AUE_PAR2 0x12 87184610Salfred#define AUE_PAR3 0x13 88184610Salfred#define AUE_PAR4 0x14 89184610Salfred#define AUE_PAR5 0x15 90184610Salfred#define AUE_PAR AUE_PAR0 91184610Salfred#define AUE_PAUSE0 0x18 92184610Salfred#define AUE_PAUSE1 0x19 93184610Salfred#define AUE_PAUSE AUE_PAUSE0 94184610Salfred#define AUE_RX_FLOWCTL_CNT 0x1A 95184610Salfred#define AUE_RX_FLOWCTL_FIFO 0x1B 96184610Salfred#define AUE_REG_1D 0x1D 97184610Salfred#define AUE_EE_REG 0x20 98184610Salfred#define AUE_EE_DATA0 0x21 99184610Salfred#define AUE_EE_DATA1 0x22 100184610Salfred#define AUE_EE_DATA AUE_EE_DATA0 101184610Salfred#define AUE_EE_CTL 0x23 102184610Salfred#define AUE_PHY_ADDR 0x25 103184610Salfred#define AUE_PHY_DATA0 0x26 104184610Salfred#define AUE_PHY_DATA1 0x27 105184610Salfred#define AUE_PHY_DATA AUE_PHY_DATA0 106184610Salfred#define AUE_PHY_CTL 0x28 107184610Salfred#define AUE_USB_STS 0x2A 108184610Salfred#define AUE_TXSTAT0 0x2B 109184610Salfred#define AUE_TXSTAT1 0x2C 110184610Salfred#define AUE_TXSTAT AUE_TXSTAT0 111184610Salfred#define AUE_RXSTAT 0x2D 112184610Salfred#define AUE_PKTLOST0 0x2E 113184610Salfred#define AUE_PKTLOST1 0x2F 114184610Salfred#define AUE_PKTLOST AUE_PKTLOST0 115184610Salfred 116184610Salfred#define AUE_REG_7B 0x7B 117184610Salfred#define AUE_GPIO0 0x7E 118184610Salfred#define AUE_GPIO1 0x7F 119184610Salfred#define AUE_REG_81 0x81 120184610Salfred 121184610Salfred#define AUE_CTL0_INCLUDE_RXCRC 0x01 122184610Salfred#define AUE_CTL0_ALLMULTI 0x02 123184610Salfred#define AUE_CTL0_STOP_BACKOFF 0x04 124184610Salfred#define AUE_CTL0_RXSTAT_APPEND 0x08 125184610Salfred#define AUE_CTL0_WAKEON_ENB 0x10 126184610Salfred#define AUE_CTL0_RXPAUSE_ENB 0x20 127184610Salfred#define AUE_CTL0_RX_ENB 0x40 128184610Salfred#define AUE_CTL0_TX_ENB 0x80 129184610Salfred 130184610Salfred#define AUE_CTL1_HOMELAN 0x04 131184610Salfred#define AUE_CTL1_RESETMAC 0x08 132184610Salfred#define AUE_CTL1_SPEEDSEL 0x10 /* 0 = 10mbps, 1 = 100mbps */ 133184610Salfred#define AUE_CTL1_DUPLEX 0x20 /* 0 = half, 1 = full */ 134184610Salfred#define AUE_CTL1_DELAYHOME 0x40 135184610Salfred 136184610Salfred#define AUE_CTL2_EP3_CLR 0x01 /* reading EP3 clrs status regs */ 137184610Salfred#define AUE_CTL2_RX_BADFRAMES 0x02 138184610Salfred#define AUE_CTL2_RX_PROMISC 0x04 139184610Salfred#define AUE_CTL2_LOOPBACK 0x08 140184610Salfred#define AUE_CTL2_EEPROMWR_ENB 0x10 141184610Salfred#define AUE_CTL2_EEPROM_LOAD 0x20 142184610Salfred 143184610Salfred#define AUE_EECTL_WRITE 0x01 144184610Salfred#define AUE_EECTL_READ 0x02 145184610Salfred#define AUE_EECTL_DONE 0x04 146184610Salfred 147184610Salfred#define AUE_PHYCTL_PHYREG 0x1F 148184610Salfred#define AUE_PHYCTL_WRITE 0x20 149184610Salfred#define AUE_PHYCTL_READ 0x40 150184610Salfred#define AUE_PHYCTL_DONE 0x80 151184610Salfred 152184610Salfred#define AUE_USBSTS_SUSPEND 0x01 153184610Salfred#define AUE_USBSTS_RESUME 0x02 154184610Salfred 155184610Salfred#define AUE_TXSTAT0_JABTIMO 0x04 156184610Salfred#define AUE_TXSTAT0_CARLOSS 0x08 157184610Salfred#define AUE_TXSTAT0_NOCARRIER 0x10 158184610Salfred#define AUE_TXSTAT0_LATECOLL 0x20 159184610Salfred#define AUE_TXSTAT0_EXCESSCOLL 0x40 160184610Salfred#define AUE_TXSTAT0_UNDERRUN 0x80 161184610Salfred 162184610Salfred#define AUE_TXSTAT1_PKTCNT 0x0F 163184610Salfred#define AUE_TXSTAT1_FIFO_EMPTY 0x40 164184610Salfred#define AUE_TXSTAT1_FIFO_FULL 0x80 165184610Salfred 166184610Salfred#define AUE_RXSTAT_OVERRUN 0x01 167184610Salfred#define AUE_RXSTAT_PAUSE 0x02 168184610Salfred 169184610Salfred#define AUE_GPIO_IN0 0x01 170184610Salfred#define AUE_GPIO_OUT0 0x02 171184610Salfred#define AUE_GPIO_SEL0 0x04 172184610Salfred#define AUE_GPIO_IN1 0x08 173184610Salfred#define AUE_GPIO_OUT1 0x10 174184610Salfred#define AUE_GPIO_SEL1 0x20 175184610Salfred 176184610Salfred#define AUE_TIMEOUT 100 /* 10*ms */ 177184610Salfred#define AUE_MIN_FRAMELEN 60 178184610Salfred 179184610Salfred#define AUE_RXSTAT_MCAST 0x01 180184610Salfred#define AUE_RXSTAT_GIANT 0x02 181184610Salfred#define AUE_RXSTAT_RUNT 0x04 182184610Salfred#define AUE_RXSTAT_CRCERR 0x08 183184610Salfred#define AUE_RXSTAT_DRIBBLE 0x10 184184610Salfred#define AUE_RXSTAT_MASK 0x1E 185184610Salfred 186194228Sthompsa#define GET_MII(sc) uether_getmii(&(sc)->sc_ue) 187184610Salfred 188184610Salfredstruct aue_intrpkt { 189184610Salfred uint8_t aue_txstat0; 190184610Salfred uint8_t aue_txstat1; 191184610Salfred uint8_t aue_rxstat; 192184610Salfred uint8_t aue_rxlostpkt0; 193184610Salfred uint8_t aue_rxlostpkt1; 194184610Salfred uint8_t aue_wakeupstat; 195184610Salfred uint8_t aue_rsvd; 196184610Salfred} __packed; 197184610Salfred 198184610Salfredstruct aue_rxpkt { 199184610Salfred uint16_t aue_pktlen; 200184610Salfred uint8_t aue_rxstat; 201188412Sthompsa uint8_t pad; 202184610Salfred} __packed; 203184610Salfred 204184610Salfredstruct aue_softc { 205192984Sthompsa struct usb_ether sc_ue; 206188412Sthompsa struct mtx sc_mtx; 207192984Sthompsa struct usb_xfer *sc_xfer[AUE_N_TRANSFER]; 208184610Salfred 209188412Sthompsa int sc_flags; 210184610Salfred#define AUE_FLAG_LSYS 0x0001 /* use Linksys reset */ 211184610Salfred#define AUE_FLAG_PNA 0x0002 /* has Home PNA */ 212184610Salfred#define AUE_FLAG_PII 0x0004 /* Pegasus II chip */ 213188412Sthompsa#define AUE_FLAG_LINK 0x0008 /* wait for link to come up */ 214184610Salfred#define AUE_FLAG_VER_2 0x0200 /* chip is version 2 */ 215184610Salfred#define AUE_FLAG_DUAL_PHY 0x0400 /* chip has two transcivers */ 216188412Sthompsa}; 217184610Salfred 218188412Sthompsa#define AUE_LOCK(_sc) mtx_lock(&(_sc)->sc_mtx) 219188412Sthompsa#define AUE_UNLOCK(_sc) mtx_unlock(&(_sc)->sc_mtx) 220188412Sthompsa#define AUE_LOCK_ASSERT(_sc, t) mtx_assert(&(_sc)->sc_mtx, t) 221