uart_dev_ns8250.c revision 266046
1/*- 2 * Copyright (c) 2003 Marcel Moolenaar 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27#include "opt_platform.h" 28 29#include <sys/cdefs.h> 30__FBSDID("$FreeBSD: stable/10/sys/dev/uart/uart_dev_ns8250.c 266046 2014-05-14 16:32:27Z ian $"); 31 32#include <sys/param.h> 33#include <sys/systm.h> 34#include <sys/bus.h> 35#include <sys/conf.h> 36#include <sys/kernel.h> 37#include <sys/sysctl.h> 38#include <machine/bus.h> 39 40#ifdef FDT 41#include <dev/fdt/fdt_common.h> 42#include <dev/ofw/ofw_bus.h> 43#include <dev/ofw/ofw_bus_subr.h> 44#endif 45 46#include <dev/uart/uart.h> 47#include <dev/uart/uart_cpu.h> 48#include <dev/uart/uart_bus.h> 49#include <dev/uart/uart_dev_ns8250.h> 50 51#include <dev/ic/ns16550.h> 52 53#include "uart_if.h" 54 55#define DEFAULT_RCLK 1843200 56 57static int broken_txfifo = 0; 58SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RW | CTLFLAG_TUN, 59 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug"); 60TUNABLE_INT("hw.broken_txfifo", &broken_txfifo); 61 62/* 63 * Clear pending interrupts. THRE is cleared by reading IIR. Data 64 * that may have been received gets lost here. 65 */ 66static void 67ns8250_clrint(struct uart_bas *bas) 68{ 69 uint8_t iir, lsr; 70 71 iir = uart_getreg(bas, REG_IIR); 72 while ((iir & IIR_NOPEND) == 0) { 73 iir &= IIR_IMASK; 74 if (iir == IIR_RLS) { 75 lsr = uart_getreg(bas, REG_LSR); 76 if (lsr & (LSR_BI|LSR_FE|LSR_PE)) 77 (void)uart_getreg(bas, REG_DATA); 78 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT) 79 (void)uart_getreg(bas, REG_DATA); 80 else if (iir == IIR_MLSC) 81 (void)uart_getreg(bas, REG_MSR); 82 uart_barrier(bas); 83 iir = uart_getreg(bas, REG_IIR); 84 } 85} 86 87static int 88ns8250_delay(struct uart_bas *bas) 89{ 90 int divisor; 91 u_char lcr; 92 93 lcr = uart_getreg(bas, REG_LCR); 94 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 95 uart_barrier(bas); 96 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8); 97 uart_barrier(bas); 98 uart_setreg(bas, REG_LCR, lcr); 99 uart_barrier(bas); 100 101 /* 1/10th the time to transmit 1 character (estimate). */ 102 if (divisor <= 134) 103 return (16000000 * divisor / bas->rclk); 104 return (16000 * divisor / (bas->rclk / 1000)); 105} 106 107static int 108ns8250_divisor(int rclk, int baudrate) 109{ 110 int actual_baud, divisor; 111 int error; 112 113 if (baudrate == 0) 114 return (0); 115 116 divisor = (rclk / (baudrate << 3) + 1) >> 1; 117 if (divisor == 0 || divisor >= 65536) 118 return (0); 119 actual_baud = rclk / (divisor << 4); 120 121 /* 10 times error in percent: */ 122 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1; 123 124 /* 3.0% maximum error tolerance: */ 125 if (error < -30 || error > 30) 126 return (0); 127 128 return (divisor); 129} 130 131static int 132ns8250_drain(struct uart_bas *bas, int what) 133{ 134 int delay, limit; 135 136 delay = ns8250_delay(bas); 137 138 if (what & UART_DRAIN_TRANSMITTER) { 139 /* 140 * Pick an arbitrary high limit to avoid getting stuck in 141 * an infinite loop when the hardware is broken. Make the 142 * limit high enough to handle large FIFOs. 143 */ 144 limit = 10*1024; 145 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 146 DELAY(delay); 147 if (limit == 0) { 148 /* printf("ns8250: transmitter appears stuck... "); */ 149 return (EIO); 150 } 151 } 152 153 if (what & UART_DRAIN_RECEIVER) { 154 /* 155 * Pick an arbitrary high limit to avoid getting stuck in 156 * an infinite loop when the hardware is broken. Make the 157 * limit high enough to handle large FIFOs and integrated 158 * UARTs. The HP rx2600 for example has 3 UARTs on the 159 * management board that tend to get a lot of data send 160 * to it when the UART is first activated. 161 */ 162 limit=10*4096; 163 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) { 164 (void)uart_getreg(bas, REG_DATA); 165 uart_barrier(bas); 166 DELAY(delay << 2); 167 } 168 if (limit == 0) { 169 /* printf("ns8250: receiver appears broken... "); */ 170 return (EIO); 171 } 172 } 173 174 return (0); 175} 176 177/* 178 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be 179 * drained. WARNING: this function clobbers the FIFO setting! 180 */ 181static void 182ns8250_flush(struct uart_bas *bas, int what) 183{ 184 uint8_t fcr; 185 186 fcr = FCR_ENABLE; 187 if (what & UART_FLUSH_TRANSMITTER) 188 fcr |= FCR_XMT_RST; 189 if (what & UART_FLUSH_RECEIVER) 190 fcr |= FCR_RCV_RST; 191 uart_setreg(bas, REG_FCR, fcr); 192 uart_barrier(bas); 193} 194 195static int 196ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits, 197 int parity) 198{ 199 int divisor; 200 uint8_t lcr; 201 202 lcr = 0; 203 if (databits >= 8) 204 lcr |= LCR_8BITS; 205 else if (databits == 7) 206 lcr |= LCR_7BITS; 207 else if (databits == 6) 208 lcr |= LCR_6BITS; 209 else 210 lcr |= LCR_5BITS; 211 if (stopbits > 1) 212 lcr |= LCR_STOPB; 213 lcr |= parity << 3; 214 215 /* Set baudrate. */ 216 if (baudrate > 0) { 217 divisor = ns8250_divisor(bas->rclk, baudrate); 218 if (divisor == 0) 219 return (EINVAL); 220 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 221 uart_barrier(bas); 222 uart_setreg(bas, REG_DLL, divisor & 0xff); 223 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff); 224 uart_barrier(bas); 225 } 226 227 /* Set LCR and clear DLAB. */ 228 uart_setreg(bas, REG_LCR, lcr); 229 uart_barrier(bas); 230 return (0); 231} 232 233/* 234 * Low-level UART interface. 235 */ 236static int ns8250_probe(struct uart_bas *bas); 237static void ns8250_init(struct uart_bas *bas, int, int, int, int); 238static void ns8250_term(struct uart_bas *bas); 239static void ns8250_putc(struct uart_bas *bas, int); 240static int ns8250_rxready(struct uart_bas *bas); 241static int ns8250_getc(struct uart_bas *bas, struct mtx *); 242 243struct uart_ops uart_ns8250_ops = { 244 .probe = ns8250_probe, 245 .init = ns8250_init, 246 .term = ns8250_term, 247 .putc = ns8250_putc, 248 .rxready = ns8250_rxready, 249 .getc = ns8250_getc, 250}; 251 252static int 253ns8250_probe(struct uart_bas *bas) 254{ 255 u_char val; 256 257 /* Check known 0 bits that don't depend on DLAB. */ 258 val = uart_getreg(bas, REG_IIR); 259 if (val & 0x30) 260 return (ENXIO); 261 /* 262 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699 263 * chip, but otherwise doesn't seem to have a function. In 264 * other words, uart(4) works regardless. Ignore that bit so 265 * the probe succeeds. 266 */ 267 val = uart_getreg(bas, REG_MCR); 268 if (val & 0xa0) 269 return (ENXIO); 270 271 return (0); 272} 273 274static void 275ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits, 276 int parity) 277{ 278 u_char ier; 279 280 if (bas->rclk == 0) 281 bas->rclk = DEFAULT_RCLK; 282 ns8250_param(bas, baudrate, databits, stopbits, parity); 283 284 /* Disable all interrupt sources. */ 285 /* 286 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA 287 * UARTs split the receive time-out interrupt bit out separately as 288 * 0x10. This gets handled by ier_mask and ier_rxbits below. 289 */ 290 ier = uart_getreg(bas, REG_IER) & 0xe0; 291 uart_setreg(bas, REG_IER, ier); 292 uart_barrier(bas); 293 294 /* Disable the FIFO (if present). */ 295 uart_setreg(bas, REG_FCR, 0); 296 uart_barrier(bas); 297 298 /* Set RTS & DTR. */ 299 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR); 300 uart_barrier(bas); 301 302 ns8250_clrint(bas); 303} 304 305static void 306ns8250_term(struct uart_bas *bas) 307{ 308 309 /* Clear RTS & DTR. */ 310 uart_setreg(bas, REG_MCR, MCR_IE); 311 uart_barrier(bas); 312} 313 314static void 315ns8250_putc(struct uart_bas *bas, int c) 316{ 317 int limit; 318 319 limit = 250000; 320 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit) 321 DELAY(4); 322 uart_setreg(bas, REG_DATA, c); 323 uart_barrier(bas); 324 limit = 250000; 325 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit) 326 DELAY(4); 327} 328 329static int 330ns8250_rxready(struct uart_bas *bas) 331{ 332 333 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0); 334} 335 336static int 337ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx) 338{ 339 int c; 340 341 uart_lock(hwmtx); 342 343 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) { 344 uart_unlock(hwmtx); 345 DELAY(4); 346 uart_lock(hwmtx); 347 } 348 349 c = uart_getreg(bas, REG_DATA); 350 351 uart_unlock(hwmtx); 352 353 return (c); 354} 355 356static kobj_method_t ns8250_methods[] = { 357 KOBJMETHOD(uart_attach, ns8250_bus_attach), 358 KOBJMETHOD(uart_detach, ns8250_bus_detach), 359 KOBJMETHOD(uart_flush, ns8250_bus_flush), 360 KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 361 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 362 KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 363 KOBJMETHOD(uart_param, ns8250_bus_param), 364 KOBJMETHOD(uart_probe, ns8250_bus_probe), 365 KOBJMETHOD(uart_receive, ns8250_bus_receive), 366 KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 367 KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 368 KOBJMETHOD(uart_grab, ns8250_bus_grab), 369 KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab), 370 { 0, 0 } 371}; 372 373struct uart_class uart_ns8250_class = { 374 "ns8250", 375 ns8250_methods, 376 sizeof(struct ns8250_softc), 377 .uc_ops = &uart_ns8250_ops, 378 .uc_range = 8, 379 .uc_rclk = DEFAULT_RCLK 380}; 381 382#define SIGCHG(c, i, s, d) \ 383 if (c) { \ 384 i |= (i & s) ? s : s | d; \ 385 } else { \ 386 i = (i & s) ? (i & ~s) | d : i; \ 387 } 388 389int 390ns8250_bus_attach(struct uart_softc *sc) 391{ 392 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 393 struct uart_bas *bas; 394 unsigned int ivar; 395#ifdef FDT 396 phandle_t node; 397 pcell_t cell; 398#endif 399 400 ns8250->busy_detect = 0; 401 402#ifdef FDT 403 /* 404 * Check whether uart requires to read USR reg when IIR_BUSY and 405 * has broken txfifo. 406 */ 407 node = ofw_bus_get_node(sc->sc_dev); 408 if ((OF_getprop(node, "busy-detect", &cell, sizeof(cell))) > 0) 409 ns8250->busy_detect = 1; 410 if ((OF_getprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0) 411 broken_txfifo = 1; 412#endif 413 414 bas = &sc->sc_bas; 415 416 ns8250->mcr = uart_getreg(bas, REG_MCR); 417 ns8250->fcr = FCR_ENABLE; 418 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags", 419 &ivar)) { 420 if (UART_FLAGS_FCR_RX_LOW(ivar)) 421 ns8250->fcr |= FCR_RX_LOW; 422 else if (UART_FLAGS_FCR_RX_MEDL(ivar)) 423 ns8250->fcr |= FCR_RX_MEDL; 424 else if (UART_FLAGS_FCR_RX_HIGH(ivar)) 425 ns8250->fcr |= FCR_RX_HIGH; 426 else 427 ns8250->fcr |= FCR_RX_MEDH; 428 } else 429 ns8250->fcr |= FCR_RX_MEDH; 430 431 /* Get IER mask */ 432 ivar = 0xf0; 433 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask", 434 &ivar); 435 ns8250->ier_mask = (uint8_t)(ivar & 0xff); 436 437 /* Get IER RX interrupt bits */ 438 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY; 439 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits", 440 &ivar); 441 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff); 442 443 uart_setreg(bas, REG_FCR, ns8250->fcr); 444 uart_barrier(bas); 445 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 446 447 if (ns8250->mcr & MCR_DTR) 448 sc->sc_hwsig |= SER_DTR; 449 if (ns8250->mcr & MCR_RTS) 450 sc->sc_hwsig |= SER_RTS; 451 ns8250_bus_getsig(sc); 452 453 ns8250_clrint(bas); 454 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 455 ns8250->ier |= ns8250->ier_rxbits; 456 uart_setreg(bas, REG_IER, ns8250->ier); 457 uart_barrier(bas); 458 459 /* 460 * Timing of the H/W access was changed with r253161 of uart_core.c 461 * It has been observed that an ITE IT8513E would signal a break 462 * condition with pretty much every character it received, unless 463 * it had enough time to settle between ns8250_bus_attach() and 464 * ns8250_bus_ipend() -- which it accidentally had before r253161. 465 * It's not understood why the UART chip behaves this way and it 466 * could very well be that the DELAY make the H/W work in the same 467 * accidental manner as before. More analysis is warranted, but 468 * at least now we fixed a known regression. 469 */ 470 DELAY(200); 471 return (0); 472} 473 474int 475ns8250_bus_detach(struct uart_softc *sc) 476{ 477 struct ns8250_softc *ns8250; 478 struct uart_bas *bas; 479 u_char ier; 480 481 ns8250 = (struct ns8250_softc *)sc; 482 bas = &sc->sc_bas; 483 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 484 uart_setreg(bas, REG_IER, ier); 485 uart_barrier(bas); 486 ns8250_clrint(bas); 487 return (0); 488} 489 490int 491ns8250_bus_flush(struct uart_softc *sc, int what) 492{ 493 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 494 struct uart_bas *bas; 495 int error; 496 497 bas = &sc->sc_bas; 498 uart_lock(sc->sc_hwmtx); 499 if (sc->sc_rxfifosz > 1) { 500 ns8250_flush(bas, what); 501 uart_setreg(bas, REG_FCR, ns8250->fcr); 502 uart_barrier(bas); 503 error = 0; 504 } else 505 error = ns8250_drain(bas, what); 506 uart_unlock(sc->sc_hwmtx); 507 return (error); 508} 509 510int 511ns8250_bus_getsig(struct uart_softc *sc) 512{ 513 uint32_t new, old, sig; 514 uint8_t msr; 515 516 do { 517 old = sc->sc_hwsig; 518 sig = old; 519 uart_lock(sc->sc_hwmtx); 520 msr = uart_getreg(&sc->sc_bas, REG_MSR); 521 uart_unlock(sc->sc_hwmtx); 522 SIGCHG(msr & MSR_DSR, sig, SER_DSR, SER_DDSR); 523 SIGCHG(msr & MSR_CTS, sig, SER_CTS, SER_DCTS); 524 SIGCHG(msr & MSR_DCD, sig, SER_DCD, SER_DDCD); 525 SIGCHG(msr & MSR_RI, sig, SER_RI, SER_DRI); 526 new = sig & ~SER_MASK_DELTA; 527 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 528 return (sig); 529} 530 531int 532ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data) 533{ 534 struct uart_bas *bas; 535 int baudrate, divisor, error; 536 uint8_t efr, lcr; 537 538 bas = &sc->sc_bas; 539 error = 0; 540 uart_lock(sc->sc_hwmtx); 541 switch (request) { 542 case UART_IOCTL_BREAK: 543 lcr = uart_getreg(bas, REG_LCR); 544 if (data) 545 lcr |= LCR_SBREAK; 546 else 547 lcr &= ~LCR_SBREAK; 548 uart_setreg(bas, REG_LCR, lcr); 549 uart_barrier(bas); 550 break; 551 case UART_IOCTL_IFLOW: 552 lcr = uart_getreg(bas, REG_LCR); 553 uart_barrier(bas); 554 uart_setreg(bas, REG_LCR, 0xbf); 555 uart_barrier(bas); 556 efr = uart_getreg(bas, REG_EFR); 557 if (data) 558 efr |= EFR_RTS; 559 else 560 efr &= ~EFR_RTS; 561 uart_setreg(bas, REG_EFR, efr); 562 uart_barrier(bas); 563 uart_setreg(bas, REG_LCR, lcr); 564 uart_barrier(bas); 565 break; 566 case UART_IOCTL_OFLOW: 567 lcr = uart_getreg(bas, REG_LCR); 568 uart_barrier(bas); 569 uart_setreg(bas, REG_LCR, 0xbf); 570 uart_barrier(bas); 571 efr = uart_getreg(bas, REG_EFR); 572 if (data) 573 efr |= EFR_CTS; 574 else 575 efr &= ~EFR_CTS; 576 uart_setreg(bas, REG_EFR, efr); 577 uart_barrier(bas); 578 uart_setreg(bas, REG_LCR, lcr); 579 uart_barrier(bas); 580 break; 581 case UART_IOCTL_BAUD: 582 lcr = uart_getreg(bas, REG_LCR); 583 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB); 584 uart_barrier(bas); 585 divisor = uart_getreg(bas, REG_DLL) | 586 (uart_getreg(bas, REG_DLH) << 8); 587 uart_barrier(bas); 588 uart_setreg(bas, REG_LCR, lcr); 589 uart_barrier(bas); 590 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0; 591 if (baudrate > 0) 592 *(int*)data = baudrate; 593 else 594 error = ENXIO; 595 break; 596 default: 597 error = EINVAL; 598 break; 599 } 600 uart_unlock(sc->sc_hwmtx); 601 return (error); 602} 603 604int 605ns8250_bus_ipend(struct uart_softc *sc) 606{ 607 struct uart_bas *bas; 608 struct ns8250_softc *ns8250; 609 int ipend; 610 uint8_t iir, lsr; 611 612 ns8250 = (struct ns8250_softc *)sc; 613 bas = &sc->sc_bas; 614 uart_lock(sc->sc_hwmtx); 615 iir = uart_getreg(bas, REG_IIR); 616 617 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) { 618 (void)uart_getreg(bas, DW_REG_USR); 619 uart_unlock(sc->sc_hwmtx); 620 return (0); 621 } 622 if (iir & IIR_NOPEND) { 623 uart_unlock(sc->sc_hwmtx); 624 return (0); 625 } 626 ipend = 0; 627 if (iir & IIR_RXRDY) { 628 lsr = uart_getreg(bas, REG_LSR); 629 if (lsr & LSR_OE) 630 ipend |= SER_INT_OVERRUN; 631 if (lsr & LSR_BI) 632 ipend |= SER_INT_BREAK; 633 if (lsr & LSR_RXRDY) 634 ipend |= SER_INT_RXREADY; 635 } else { 636 if (iir & IIR_TXRDY) { 637 ipend |= SER_INT_TXIDLE; 638 uart_setreg(bas, REG_IER, ns8250->ier); 639 } else 640 ipend |= SER_INT_SIGCHG; 641 } 642 if (ipend == 0) 643 ns8250_clrint(bas); 644 uart_unlock(sc->sc_hwmtx); 645 return (ipend); 646} 647 648int 649ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits, 650 int stopbits, int parity) 651{ 652 struct ns8250_softc *ns8250; 653 struct uart_bas *bas; 654 int error, limit; 655 656 ns8250 = (struct ns8250_softc*)sc; 657 bas = &sc->sc_bas; 658 uart_lock(sc->sc_hwmtx); 659 /* 660 * When using DW UART with BUSY detection it is necessary to wait 661 * until all serial transfers are finished before manipulating the 662 * line control. LCR will not be affected when UART is busy. 663 */ 664 if (ns8250->busy_detect != 0) { 665 /* 666 * Pick an arbitrary high limit to avoid getting stuck in 667 * an infinite loop in case when the hardware is broken. 668 */ 669 limit = 10 * 1024; 670 while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) && 671 --limit) 672 DELAY(4); 673 674 if (limit <= 0) { 675 /* UART appears to be stuck */ 676 uart_unlock(sc->sc_hwmtx); 677 return (EIO); 678 } 679 } 680 681 error = ns8250_param(bas, baudrate, databits, stopbits, parity); 682 uart_unlock(sc->sc_hwmtx); 683 return (error); 684} 685 686int 687ns8250_bus_probe(struct uart_softc *sc) 688{ 689 struct ns8250_softc *ns8250; 690 struct uart_bas *bas; 691 int count, delay, error, limit; 692 uint8_t lsr, mcr, ier; 693 694 ns8250 = (struct ns8250_softc *)sc; 695 bas = &sc->sc_bas; 696 697 error = ns8250_probe(bas); 698 if (error) 699 return (error); 700 701 mcr = MCR_IE; 702 if (sc->sc_sysdev == NULL) { 703 /* By using ns8250_init() we also set DTR and RTS. */ 704 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE); 705 } else 706 mcr |= MCR_DTR | MCR_RTS; 707 708 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 709 if (error) 710 return (error); 711 712 /* 713 * Set loopback mode. This avoids having garbage on the wire and 714 * also allows us send and receive data. We set DTR and RTS to 715 * avoid the possibility that automatic flow-control prevents 716 * any data from being sent. 717 */ 718 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS); 719 uart_barrier(bas); 720 721 /* 722 * Enable FIFOs. And check that the UART has them. If not, we're 723 * done. Since this is the first time we enable the FIFOs, we reset 724 * them. 725 */ 726 uart_setreg(bas, REG_FCR, FCR_ENABLE); 727 uart_barrier(bas); 728 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) { 729 /* 730 * NS16450 or INS8250. We don't bother to differentiate 731 * between them. They're too old to be interesting. 732 */ 733 uart_setreg(bas, REG_MCR, mcr); 734 uart_barrier(bas); 735 sc->sc_rxfifosz = sc->sc_txfifosz = 1; 736 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible"); 737 return (0); 738 } 739 740 uart_setreg(bas, REG_FCR, FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST); 741 uart_barrier(bas); 742 743 count = 0; 744 delay = ns8250_delay(bas); 745 746 /* We have FIFOs. Drain the transmitter and receiver. */ 747 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER); 748 if (error) { 749 uart_setreg(bas, REG_MCR, mcr); 750 uart_setreg(bas, REG_FCR, 0); 751 uart_barrier(bas); 752 goto describe; 753 } 754 755 /* 756 * We should have a sufficiently clean "pipe" to determine the 757 * size of the FIFOs. We send as much characters as is reasonable 758 * and wait for the overflow bit in the LSR register to be 759 * asserted, counting the characters as we send them. Based on 760 * that count we know the FIFO size. 761 */ 762 do { 763 uart_setreg(bas, REG_DATA, 0); 764 uart_barrier(bas); 765 count++; 766 767 limit = 30; 768 lsr = 0; 769 /* 770 * LSR bits are cleared upon read, so we must accumulate 771 * them to be able to test LSR_OE below. 772 */ 773 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 && 774 --limit) 775 DELAY(delay); 776 if (limit == 0) { 777 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 778 uart_setreg(bas, REG_IER, ier); 779 uart_setreg(bas, REG_MCR, mcr); 780 uart_setreg(bas, REG_FCR, 0); 781 uart_barrier(bas); 782 count = 0; 783 goto describe; 784 } 785 } while ((lsr & LSR_OE) == 0 && count < 130); 786 count--; 787 788 uart_setreg(bas, REG_MCR, mcr); 789 790 /* Reset FIFOs. */ 791 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER); 792 793 describe: 794 if (count >= 14 && count <= 16) { 795 sc->sc_rxfifosz = 16; 796 device_set_desc(sc->sc_dev, "16550 or compatible"); 797 } else if (count >= 28 && count <= 32) { 798 sc->sc_rxfifosz = 32; 799 device_set_desc(sc->sc_dev, "16650 or compatible"); 800 } else if (count >= 56 && count <= 64) { 801 sc->sc_rxfifosz = 64; 802 device_set_desc(sc->sc_dev, "16750 or compatible"); 803 } else if (count >= 112 && count <= 128) { 804 sc->sc_rxfifosz = 128; 805 device_set_desc(sc->sc_dev, "16950 or compatible"); 806 } else { 807 sc->sc_rxfifosz = 16; 808 device_set_desc(sc->sc_dev, 809 "Non-standard ns8250 class UART with FIFOs"); 810 } 811 812 /* 813 * Force the Tx FIFO size to 16 bytes for now. We don't program the 814 * Tx trigger. Also, we assume that all data has been sent when the 815 * interrupt happens. 816 */ 817 sc->sc_txfifosz = 16; 818 819#if 0 820 /* 821 * XXX there are some issues related to hardware flow control and 822 * it's likely that uart(4) is the cause. This basicly needs more 823 * investigation, but we avoid using for hardware flow control 824 * until then. 825 */ 826 /* 16650s or higher have automatic flow control. */ 827 if (sc->sc_rxfifosz > 16) { 828 sc->sc_hwiflow = 1; 829 sc->sc_hwoflow = 1; 830 } 831#endif 832 833 return (0); 834} 835 836int 837ns8250_bus_receive(struct uart_softc *sc) 838{ 839 struct uart_bas *bas; 840 int xc; 841 uint8_t lsr; 842 843 bas = &sc->sc_bas; 844 uart_lock(sc->sc_hwmtx); 845 lsr = uart_getreg(bas, REG_LSR); 846 while (lsr & LSR_RXRDY) { 847 if (uart_rx_full(sc)) { 848 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN; 849 break; 850 } 851 xc = uart_getreg(bas, REG_DATA); 852 if (lsr & LSR_FE) 853 xc |= UART_STAT_FRAMERR; 854 if (lsr & LSR_PE) 855 xc |= UART_STAT_PARERR; 856 uart_rx_put(sc, xc); 857 lsr = uart_getreg(bas, REG_LSR); 858 } 859 /* Discard everything left in the Rx FIFO. */ 860 while (lsr & LSR_RXRDY) { 861 (void)uart_getreg(bas, REG_DATA); 862 uart_barrier(bas); 863 lsr = uart_getreg(bas, REG_LSR); 864 } 865 uart_unlock(sc->sc_hwmtx); 866 return (0); 867} 868 869int 870ns8250_bus_setsig(struct uart_softc *sc, int sig) 871{ 872 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 873 struct uart_bas *bas; 874 uint32_t new, old; 875 876 bas = &sc->sc_bas; 877 do { 878 old = sc->sc_hwsig; 879 new = old; 880 if (sig & SER_DDTR) { 881 SIGCHG(sig & SER_DTR, new, SER_DTR, 882 SER_DDTR); 883 } 884 if (sig & SER_DRTS) { 885 SIGCHG(sig & SER_RTS, new, SER_RTS, 886 SER_DRTS); 887 } 888 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new)); 889 uart_lock(sc->sc_hwmtx); 890 ns8250->mcr &= ~(MCR_DTR|MCR_RTS); 891 if (new & SER_DTR) 892 ns8250->mcr |= MCR_DTR; 893 if (new & SER_RTS) 894 ns8250->mcr |= MCR_RTS; 895 uart_setreg(bas, REG_MCR, ns8250->mcr); 896 uart_barrier(bas); 897 uart_unlock(sc->sc_hwmtx); 898 return (0); 899} 900 901int 902ns8250_bus_transmit(struct uart_softc *sc) 903{ 904 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 905 struct uart_bas *bas; 906 int i; 907 908 bas = &sc->sc_bas; 909 uart_lock(sc->sc_hwmtx); 910 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0) 911 ; 912 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY); 913 uart_barrier(bas); 914 for (i = 0; i < sc->sc_txdatasz; i++) { 915 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]); 916 uart_barrier(bas); 917 } 918 if (broken_txfifo) 919 ns8250_drain(bas, UART_DRAIN_TRANSMITTER); 920 else 921 sc->sc_txbusy = 1; 922 uart_unlock(sc->sc_hwmtx); 923 if (broken_txfifo) 924 uart_sched_softih(sc, SER_INT_TXIDLE); 925 return (0); 926} 927 928void 929ns8250_bus_grab(struct uart_softc *sc) 930{ 931 struct uart_bas *bas = &sc->sc_bas; 932 933 /* 934 * turn off all interrupts to enter polling mode. Leave the 935 * saved mask alone. We'll restore whatever it was in ungrab. 936 * All pending interupt signals are reset when IER is set to 0. 937 */ 938 uart_lock(sc->sc_hwmtx); 939 uart_setreg(bas, REG_IER, 0); 940 uart_barrier(bas); 941 uart_unlock(sc->sc_hwmtx); 942} 943 944void 945ns8250_bus_ungrab(struct uart_softc *sc) 946{ 947 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 948 struct uart_bas *bas = &sc->sc_bas; 949 950 /* 951 * Restore previous interrupt mask 952 */ 953 uart_lock(sc->sc_hwmtx); 954 uart_setreg(bas, REG_IER, ns8250->ier); 955 uart_barrier(bas); 956 uart_unlock(sc->sc_hwmtx); 957} 958