if_tsec.c revision 259235
1/*- 2 * Copyright (C) 2007-2008 Semihalf, Rafal Jaworowski 3 * Copyright (C) 2006-2007 Semihalf, Piotr Kruszynski 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN 18 * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 19 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED 20 * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR 21 * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF 22 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING 23 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 24 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27/* 28 * Freescale integrated Three-Speed Ethernet Controller (TSEC) driver. 29 */ 30#include <sys/cdefs.h> 31__FBSDID("$FreeBSD: stable/10/sys/dev/tsec/if_tsec.c 259235 2013-12-11 22:36:20Z andreast $"); 32 33#ifdef HAVE_KERNEL_OPTION_HEADERS 34#include "opt_device_polling.h" 35#endif 36 37#include <sys/param.h> 38#include <sys/systm.h> 39#include <sys/bus.h> 40#include <sys/endian.h> 41#include <sys/mbuf.h> 42#include <sys/kernel.h> 43#include <sys/module.h> 44#include <sys/socket.h> 45#include <sys/sockio.h> 46#include <sys/sysctl.h> 47 48#include <net/bpf.h> 49#include <net/ethernet.h> 50#include <net/if.h> 51#include <net/if_arp.h> 52#include <net/if_dl.h> 53#include <net/if_media.h> 54#include <net/if_types.h> 55#include <net/if_vlan_var.h> 56 57#include <netinet/in_systm.h> 58#include <netinet/in.h> 59#include <netinet/ip.h> 60 61#include <machine/bus.h> 62 63#include <dev/mii/mii.h> 64#include <dev/mii/miivar.h> 65 66#include <dev/tsec/if_tsec.h> 67#include <dev/tsec/if_tsecreg.h> 68 69static int tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag, 70 bus_dmamap_t *dmap, bus_size_t dsize, void **vaddr, void *raddr, 71 const char *dname); 72static void tsec_dma_ctl(struct tsec_softc *sc, int state); 73static int tsec_encap(struct tsec_softc *sc, struct mbuf *m_head, 74 int fcb_inserted); 75static void tsec_free_dma(struct tsec_softc *sc); 76static void tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr); 77static int tsec_ifmedia_upd(struct ifnet *ifp); 78static void tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr); 79static int tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map, 80 struct mbuf **mbufp, uint32_t *paddr); 81static void tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs, 82 int nseg, int error); 83static void tsec_intrs_ctl(struct tsec_softc *sc, int state); 84static void tsec_init(void *xsc); 85static void tsec_init_locked(struct tsec_softc *sc); 86static int tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data); 87static void tsec_reset_mac(struct tsec_softc *sc); 88static void tsec_setfilter(struct tsec_softc *sc); 89static void tsec_set_mac_address(struct tsec_softc *sc); 90static void tsec_start(struct ifnet *ifp); 91static void tsec_start_locked(struct ifnet *ifp); 92static void tsec_stop(struct tsec_softc *sc); 93static void tsec_tick(void *arg); 94static void tsec_watchdog(struct tsec_softc *sc); 95static void tsec_add_sysctls(struct tsec_softc *sc); 96static int tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS); 97static int tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS); 98static void tsec_set_rxic(struct tsec_softc *sc); 99static void tsec_set_txic(struct tsec_softc *sc); 100static int tsec_receive_intr_locked(struct tsec_softc *sc, int count); 101static void tsec_transmit_intr_locked(struct tsec_softc *sc); 102static void tsec_error_intr_locked(struct tsec_softc *sc, int count); 103static void tsec_offload_setup(struct tsec_softc *sc); 104static void tsec_offload_process_frame(struct tsec_softc *sc, 105 struct mbuf *m); 106static void tsec_setup_multicast(struct tsec_softc *sc); 107static int tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu); 108 109devclass_t tsec_devclass; 110DRIVER_MODULE(miibus, tsec, miibus_driver, miibus_devclass, 0, 0); 111MODULE_DEPEND(tsec, ether, 1, 1, 1); 112MODULE_DEPEND(tsec, miibus, 1, 1, 1); 113 114struct mtx tsec_phy_mtx; 115 116int 117tsec_attach(struct tsec_softc *sc) 118{ 119 uint8_t hwaddr[ETHER_ADDR_LEN]; 120 struct ifnet *ifp; 121 bus_dmamap_t *map_ptr; 122 bus_dmamap_t **map_pptr; 123 int error = 0; 124 int i; 125 126 /* Initialize global (because potentially shared) MII lock */ 127 if (!mtx_initialized(&tsec_phy_mtx)) 128 mtx_init(&tsec_phy_mtx, "tsec mii", NULL, MTX_DEF); 129 130 /* Reset all TSEC counters */ 131 TSEC_TX_RX_COUNTERS_INIT(sc); 132 133 /* Stop DMA engine if enabled by firmware */ 134 tsec_dma_ctl(sc, 0); 135 136 /* Reset MAC */ 137 tsec_reset_mac(sc); 138 139 /* Disable interrupts for now */ 140 tsec_intrs_ctl(sc, 0); 141 142 /* Configure defaults for interrupts coalescing */ 143 sc->rx_ic_time = 768; 144 sc->rx_ic_count = 16; 145 sc->tx_ic_time = 768; 146 sc->tx_ic_count = 16; 147 tsec_set_rxic(sc); 148 tsec_set_txic(sc); 149 tsec_add_sysctls(sc); 150 151 /* Allocate a busdma tag and DMA safe memory for TX descriptors. */ 152 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_tx_dtag, 153 &sc->tsec_tx_dmap, sizeof(*sc->tsec_tx_vaddr) * TSEC_TX_NUM_DESC, 154 (void **)&sc->tsec_tx_vaddr, &sc->tsec_tx_raddr, "TX"); 155 156 if (error) { 157 tsec_detach(sc); 158 return (ENXIO); 159 } 160 161 /* Allocate a busdma tag and DMA safe memory for RX descriptors. */ 162 error = tsec_alloc_dma_desc(sc->dev, &sc->tsec_rx_dtag, 163 &sc->tsec_rx_dmap, sizeof(*sc->tsec_rx_vaddr) * TSEC_RX_NUM_DESC, 164 (void **)&sc->tsec_rx_vaddr, &sc->tsec_rx_raddr, "RX"); 165 if (error) { 166 tsec_detach(sc); 167 return (ENXIO); 168 } 169 170 /* Allocate a busdma tag for TX mbufs. */ 171 error = bus_dma_tag_create(NULL, /* parent */ 172 TSEC_TXBUFFER_ALIGNMENT, 0, /* alignment, boundary */ 173 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 174 BUS_SPACE_MAXADDR, /* highaddr */ 175 NULL, NULL, /* filtfunc, filtfuncarg */ 176 MCLBYTES * (TSEC_TX_NUM_DESC - 1), /* maxsize */ 177 TSEC_TX_NUM_DESC - 1, /* nsegments */ 178 MCLBYTES, 0, /* maxsegsz, flags */ 179 NULL, NULL, /* lockfunc, lockfuncarg */ 180 &sc->tsec_tx_mtag); /* dmat */ 181 if (error) { 182 device_printf(sc->dev, "failed to allocate busdma tag " 183 "(tx mbufs)\n"); 184 tsec_detach(sc); 185 return (ENXIO); 186 } 187 188 /* Allocate a busdma tag for RX mbufs. */ 189 error = bus_dma_tag_create(NULL, /* parent */ 190 TSEC_RXBUFFER_ALIGNMENT, 0, /* alignment, boundary */ 191 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 192 BUS_SPACE_MAXADDR, /* highaddr */ 193 NULL, NULL, /* filtfunc, filtfuncarg */ 194 MCLBYTES, /* maxsize */ 195 1, /* nsegments */ 196 MCLBYTES, 0, /* maxsegsz, flags */ 197 NULL, NULL, /* lockfunc, lockfuncarg */ 198 &sc->tsec_rx_mtag); /* dmat */ 199 if (error) { 200 device_printf(sc->dev, "failed to allocate busdma tag " 201 "(rx mbufs)\n"); 202 tsec_detach(sc); 203 return (ENXIO); 204 } 205 206 /* Create TX busdma maps */ 207 map_ptr = sc->tx_map_data; 208 map_pptr = sc->tx_map_unused_data; 209 210 for (i = 0; i < TSEC_TX_NUM_DESC; i++) { 211 map_pptr[i] = &map_ptr[i]; 212 error = bus_dmamap_create(sc->tsec_tx_mtag, 0, map_pptr[i]); 213 if (error) { 214 device_printf(sc->dev, "failed to init TX ring\n"); 215 tsec_detach(sc); 216 return (ENXIO); 217 } 218 } 219 220 /* Create RX busdma maps and zero mbuf handlers */ 221 for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 222 error = bus_dmamap_create(sc->tsec_rx_mtag, 0, 223 &sc->rx_data[i].map); 224 if (error) { 225 device_printf(sc->dev, "failed to init RX ring\n"); 226 tsec_detach(sc); 227 return (ENXIO); 228 } 229 sc->rx_data[i].mbuf = NULL; 230 } 231 232 /* Create mbufs for RX buffers */ 233 for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 234 error = tsec_new_rxbuf(sc->tsec_rx_mtag, sc->rx_data[i].map, 235 &sc->rx_data[i].mbuf, &sc->rx_data[i].paddr); 236 if (error) { 237 device_printf(sc->dev, "can't load rx DMA map %d, " 238 "error = %d\n", i, error); 239 tsec_detach(sc); 240 return (error); 241 } 242 } 243 244 /* Create network interface for upper layers */ 245 ifp = sc->tsec_ifp = if_alloc(IFT_ETHER); 246 if (ifp == NULL) { 247 device_printf(sc->dev, "if_alloc() failed\n"); 248 tsec_detach(sc); 249 return (ENOMEM); 250 } 251 252 ifp->if_softc = sc; 253 if_initname(ifp, device_get_name(sc->dev), device_get_unit(sc->dev)); 254 ifp->if_flags = IFF_SIMPLEX | IFF_MULTICAST | IFF_BROADCAST; 255 ifp->if_init = tsec_init; 256 ifp->if_start = tsec_start; 257 ifp->if_ioctl = tsec_ioctl; 258 259 IFQ_SET_MAXLEN(&ifp->if_snd, TSEC_TX_NUM_DESC - 1); 260 ifp->if_snd.ifq_drv_maxlen = TSEC_TX_NUM_DESC - 1; 261 IFQ_SET_READY(&ifp->if_snd); 262 263 ifp->if_capabilities = IFCAP_VLAN_MTU; 264 if (sc->is_etsec) 265 ifp->if_capabilities |= IFCAP_HWCSUM; 266 267 ifp->if_capenable = ifp->if_capabilities; 268 269#ifdef DEVICE_POLLING 270 /* Advertise that polling is supported */ 271 ifp->if_capabilities |= IFCAP_POLLING; 272#endif 273 274 /* Attach PHY(s) */ 275 error = mii_attach(sc->dev, &sc->tsec_miibus, ifp, tsec_ifmedia_upd, 276 tsec_ifmedia_sts, BMSR_DEFCAPMASK, sc->phyaddr, MII_OFFSET_ANY, 277 0); 278 if (error) { 279 device_printf(sc->dev, "attaching PHYs failed\n"); 280 if_free(ifp); 281 sc->tsec_ifp = NULL; 282 tsec_detach(sc); 283 return (error); 284 } 285 sc->tsec_mii = device_get_softc(sc->tsec_miibus); 286 287 /* Set MAC address */ 288 tsec_get_hwaddr(sc, hwaddr); 289 ether_ifattach(ifp, hwaddr); 290 291 return (0); 292} 293 294int 295tsec_detach(struct tsec_softc *sc) 296{ 297 298 if (sc->tsec_ifp != NULL) { 299#ifdef DEVICE_POLLING 300 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) 301 ether_poll_deregister(sc->tsec_ifp); 302#endif 303 304 /* Stop TSEC controller and free TX queue */ 305 if (sc->sc_rres) 306 tsec_shutdown(sc->dev); 307 308 /* Detach network interface */ 309 ether_ifdetach(sc->tsec_ifp); 310 if_free(sc->tsec_ifp); 311 sc->tsec_ifp = NULL; 312 } 313 314 /* Free DMA resources */ 315 tsec_free_dma(sc); 316 317 return (0); 318} 319 320int 321tsec_shutdown(device_t dev) 322{ 323 struct tsec_softc *sc; 324 325 sc = device_get_softc(dev); 326 327 TSEC_GLOBAL_LOCK(sc); 328 tsec_stop(sc); 329 TSEC_GLOBAL_UNLOCK(sc); 330 return (0); 331} 332 333int 334tsec_suspend(device_t dev) 335{ 336 337 /* TODO not implemented! */ 338 return (0); 339} 340 341int 342tsec_resume(device_t dev) 343{ 344 345 /* TODO not implemented! */ 346 return (0); 347} 348 349static void 350tsec_init(void *xsc) 351{ 352 struct tsec_softc *sc = xsc; 353 354 TSEC_GLOBAL_LOCK(sc); 355 tsec_init_locked(sc); 356 TSEC_GLOBAL_UNLOCK(sc); 357} 358 359static void 360tsec_init_locked(struct tsec_softc *sc) 361{ 362 struct tsec_desc *tx_desc = sc->tsec_tx_vaddr; 363 struct tsec_desc *rx_desc = sc->tsec_rx_vaddr; 364 struct ifnet *ifp = sc->tsec_ifp; 365 uint32_t timeout, val, i; 366 367 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 368 return; 369 370 TSEC_GLOBAL_LOCK_ASSERT(sc); 371 tsec_stop(sc); 372 373 /* 374 * These steps are according to the MPC8555E PowerQUICCIII RM: 375 * 14.7 Initialization/Application Information 376 */ 377 378 /* Step 1: soft reset MAC */ 379 tsec_reset_mac(sc); 380 381 /* Step 2: Initialize MACCFG2 */ 382 TSEC_WRITE(sc, TSEC_REG_MACCFG2, 383 TSEC_MACCFG2_FULLDUPLEX | /* Full Duplex = 1 */ 384 TSEC_MACCFG2_PADCRC | /* PAD/CRC append */ 385 TSEC_MACCFG2_GMII | /* I/F Mode bit */ 386 TSEC_MACCFG2_PRECNT /* Preamble count = 7 */ 387 ); 388 389 /* Step 3: Initialize ECNTRL 390 * While the documentation states that R100M is ignored if RPM is 391 * not set, it does seem to be needed to get the orange boxes to 392 * work (which have a Marvell 88E1111 PHY). Go figure. 393 */ 394 395 /* 396 * XXX kludge - use circumstancial evidence to program ECNTRL 397 * correctly. Ideally we need some board information to guide 398 * us here. 399 */ 400 i = TSEC_READ(sc, TSEC_REG_ID2); 401 val = (i & 0xffff) 402 ? (TSEC_ECNTRL_TBIM | TSEC_ECNTRL_SGMIIM) /* Sumatra */ 403 : TSEC_ECNTRL_R100M; /* Orange + CDS */ 404 TSEC_WRITE(sc, TSEC_REG_ECNTRL, TSEC_ECNTRL_STEN | val); 405 406 /* Step 4: Initialize MAC station address */ 407 tsec_set_mac_address(sc); 408 409 /* 410 * Step 5: Assign a Physical address to the TBI so as to not conflict 411 * with the external PHY physical address 412 */ 413 TSEC_WRITE(sc, TSEC_REG_TBIPA, 5); 414 415 TSEC_PHY_LOCK(sc); 416 417 /* Step 6: Reset the management interface */ 418 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_RESETMGMT); 419 420 /* Step 7: Setup the MII Mgmt clock speed */ 421 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCFG, TSEC_MIIMCFG_CLKDIV28); 422 423 /* Step 8: Read MII Mgmt indicator register and check for Busy = 0 */ 424 timeout = TSEC_READ_RETRY; 425 while (--timeout && (TSEC_PHY_READ(sc, TSEC_REG_MIIMIND) & 426 TSEC_MIIMIND_BUSY)) 427 DELAY(TSEC_READ_DELAY); 428 if (timeout == 0) { 429 if_printf(ifp, "tsec_init_locked(): Mgmt busy timeout\n"); 430 return; 431 } 432 TSEC_PHY_UNLOCK(sc); 433 434 /* Step 9: Setup the MII Mgmt */ 435 mii_mediachg(sc->tsec_mii); 436 437 /* Step 10: Clear IEVENT register */ 438 TSEC_WRITE(sc, TSEC_REG_IEVENT, 0xffffffff); 439 440 /* Step 11: Enable interrupts */ 441#ifdef DEVICE_POLLING 442 /* 443 * ...only if polling is not turned on. Disable interrupts explicitly 444 * if polling is enabled. 445 */ 446 if (ifp->if_capenable & IFCAP_POLLING ) 447 tsec_intrs_ctl(sc, 0); 448 else 449#endif /* DEVICE_POLLING */ 450 tsec_intrs_ctl(sc, 1); 451 452 /* Step 12: Initialize IADDRn */ 453 TSEC_WRITE(sc, TSEC_REG_IADDR0, 0); 454 TSEC_WRITE(sc, TSEC_REG_IADDR1, 0); 455 TSEC_WRITE(sc, TSEC_REG_IADDR2, 0); 456 TSEC_WRITE(sc, TSEC_REG_IADDR3, 0); 457 TSEC_WRITE(sc, TSEC_REG_IADDR4, 0); 458 TSEC_WRITE(sc, TSEC_REG_IADDR5, 0); 459 TSEC_WRITE(sc, TSEC_REG_IADDR6, 0); 460 TSEC_WRITE(sc, TSEC_REG_IADDR7, 0); 461 462 /* Step 13: Initialize GADDRn */ 463 TSEC_WRITE(sc, TSEC_REG_GADDR0, 0); 464 TSEC_WRITE(sc, TSEC_REG_GADDR1, 0); 465 TSEC_WRITE(sc, TSEC_REG_GADDR2, 0); 466 TSEC_WRITE(sc, TSEC_REG_GADDR3, 0); 467 TSEC_WRITE(sc, TSEC_REG_GADDR4, 0); 468 TSEC_WRITE(sc, TSEC_REG_GADDR5, 0); 469 TSEC_WRITE(sc, TSEC_REG_GADDR6, 0); 470 TSEC_WRITE(sc, TSEC_REG_GADDR7, 0); 471 472 /* Step 14: Initialize RCTRL */ 473 TSEC_WRITE(sc, TSEC_REG_RCTRL, 0); 474 475 /* Step 15: Initialize DMACTRL */ 476 tsec_dma_ctl(sc, 1); 477 478 /* Step 16: Initialize FIFO_PAUSE_CTRL */ 479 TSEC_WRITE(sc, TSEC_REG_FIFO_PAUSE_CTRL, TSEC_FIFO_PAUSE_CTRL_EN); 480 481 /* 482 * Step 17: Initialize transmit/receive descriptor rings. 483 * Initialize TBASE and RBASE. 484 */ 485 TSEC_WRITE(sc, TSEC_REG_TBASE, sc->tsec_tx_raddr); 486 TSEC_WRITE(sc, TSEC_REG_RBASE, sc->tsec_rx_raddr); 487 488 for (i = 0; i < TSEC_TX_NUM_DESC; i++) { 489 tx_desc[i].bufptr = 0; 490 tx_desc[i].length = 0; 491 tx_desc[i].flags = ((i == TSEC_TX_NUM_DESC - 1) ? 492 TSEC_TXBD_W : 0); 493 } 494 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 495 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 496 497 for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 498 rx_desc[i].bufptr = sc->rx_data[i].paddr; 499 rx_desc[i].length = 0; 500 rx_desc[i].flags = TSEC_RXBD_E | TSEC_RXBD_I | 501 ((i == TSEC_RX_NUM_DESC - 1) ? TSEC_RXBD_W : 0); 502 } 503 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 504 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 505 506 /* Step 18: Initialize the maximum receive buffer length */ 507 TSEC_WRITE(sc, TSEC_REG_MRBLR, MCLBYTES); 508 509 /* Step 19: Configure ethernet frame sizes */ 510 TSEC_WRITE(sc, TSEC_REG_MINFLR, TSEC_MIN_FRAME_SIZE); 511 tsec_set_mtu(sc, ifp->if_mtu); 512 513 /* Step 20: Enable Rx and RxBD sdata snooping */ 514 TSEC_WRITE(sc, TSEC_REG_ATTR, TSEC_ATTR_RDSEN | TSEC_ATTR_RBDSEN); 515 TSEC_WRITE(sc, TSEC_REG_ATTRELI, 0); 516 517 /* Step 21: Reset collision counters in hardware */ 518 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0); 519 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0); 520 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0); 521 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0); 522 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0); 523 524 /* Step 22: Mask all CAM interrupts */ 525 TSEC_WRITE(sc, TSEC_REG_MON_CAM1, 0xffffffff); 526 TSEC_WRITE(sc, TSEC_REG_MON_CAM2, 0xffffffff); 527 528 /* Step 23: Enable Rx and Tx */ 529 val = TSEC_READ(sc, TSEC_REG_MACCFG1); 530 val |= (TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN); 531 TSEC_WRITE(sc, TSEC_REG_MACCFG1, val); 532 533 /* Step 24: Reset TSEC counters for Tx and Rx rings */ 534 TSEC_TX_RX_COUNTERS_INIT(sc); 535 536 /* Step 25: Setup TCP/IP Off-Load engine */ 537 if (sc->is_etsec) 538 tsec_offload_setup(sc); 539 540 /* Step 26: Setup multicast filters */ 541 tsec_setup_multicast(sc); 542 543 /* Step 27: Activate network interface */ 544 ifp->if_drv_flags |= IFF_DRV_RUNNING; 545 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 546 sc->tsec_if_flags = ifp->if_flags; 547 sc->tsec_watchdog = 0; 548 549 /* Schedule watchdog timeout */ 550 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc); 551} 552 553static void 554tsec_set_mac_address(struct tsec_softc *sc) 555{ 556 uint32_t macbuf[2] = { 0, 0 }; 557 char *macbufp, *curmac; 558 int i; 559 560 TSEC_GLOBAL_LOCK_ASSERT(sc); 561 562 KASSERT((ETHER_ADDR_LEN <= sizeof(macbuf)), 563 ("tsec_set_mac_address: (%d <= %d", ETHER_ADDR_LEN, 564 sizeof(macbuf))); 565 566 macbufp = (char *)macbuf; 567 curmac = (char *)IF_LLADDR(sc->tsec_ifp); 568 569 /* Correct order of MAC address bytes */ 570 for (i = 1; i <= ETHER_ADDR_LEN; i++) 571 macbufp[ETHER_ADDR_LEN-i] = curmac[i-1]; 572 573 /* Initialize MAC station address MACSTNADDR2 and MACSTNADDR1 */ 574 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR2, macbuf[1]); 575 TSEC_WRITE(sc, TSEC_REG_MACSTNADDR1, macbuf[0]); 576} 577 578/* 579 * DMA control function, if argument state is: 580 * 0 - DMA engine will be disabled 581 * 1 - DMA engine will be enabled 582 */ 583static void 584tsec_dma_ctl(struct tsec_softc *sc, int state) 585{ 586 device_t dev; 587 uint32_t dma_flags, timeout; 588 589 dev = sc->dev; 590 591 dma_flags = TSEC_READ(sc, TSEC_REG_DMACTRL); 592 593 switch (state) { 594 case 0: 595 /* Temporarily clear stop graceful stop bits. */ 596 tsec_dma_ctl(sc, 1000); 597 598 /* Set it again */ 599 dma_flags |= (TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS); 600 break; 601 case 1000: 602 case 1: 603 /* Set write with response (WWR), wait (WOP) and snoop bits */ 604 dma_flags |= (TSEC_DMACTRL_TDSEN | TSEC_DMACTRL_TBDSEN | 605 DMACTRL_WWR | DMACTRL_WOP); 606 607 /* Clear graceful stop bits */ 608 dma_flags &= ~(TSEC_DMACTRL_GRS | TSEC_DMACTRL_GTS); 609 break; 610 default: 611 device_printf(dev, "tsec_dma_ctl(): unknown state value: %d\n", 612 state); 613 } 614 615 TSEC_WRITE(sc, TSEC_REG_DMACTRL, dma_flags); 616 617 switch (state) { 618 case 0: 619 /* Wait for DMA stop */ 620 timeout = TSEC_READ_RETRY; 621 while (--timeout && (!(TSEC_READ(sc, TSEC_REG_IEVENT) & 622 (TSEC_IEVENT_GRSC | TSEC_IEVENT_GTSC)))) 623 DELAY(TSEC_READ_DELAY); 624 625 if (timeout == 0) 626 device_printf(dev, "tsec_dma_ctl(): timeout!\n"); 627 break; 628 case 1: 629 /* Restart transmission function */ 630 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT); 631 } 632} 633 634/* 635 * Interrupts control function, if argument state is: 636 * 0 - all TSEC interrupts will be masked 637 * 1 - all TSEC interrupts will be unmasked 638 */ 639static void 640tsec_intrs_ctl(struct tsec_softc *sc, int state) 641{ 642 device_t dev; 643 644 dev = sc->dev; 645 646 switch (state) { 647 case 0: 648 TSEC_WRITE(sc, TSEC_REG_IMASK, 0); 649 break; 650 case 1: 651 TSEC_WRITE(sc, TSEC_REG_IMASK, TSEC_IMASK_BREN | 652 TSEC_IMASK_RXCEN | TSEC_IMASK_BSYEN | TSEC_IMASK_EBERREN | 653 TSEC_IMASK_BTEN | TSEC_IMASK_TXEEN | TSEC_IMASK_TXBEN | 654 TSEC_IMASK_TXFEN | TSEC_IMASK_XFUNEN | TSEC_IMASK_RXFEN); 655 break; 656 default: 657 device_printf(dev, "tsec_intrs_ctl(): unknown state value: %d\n", 658 state); 659 } 660} 661 662static void 663tsec_reset_mac(struct tsec_softc *sc) 664{ 665 uint32_t maccfg1_flags; 666 667 /* Set soft reset bit */ 668 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1); 669 maccfg1_flags |= TSEC_MACCFG1_SOFT_RESET; 670 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags); 671 672 /* Clear soft reset bit */ 673 maccfg1_flags = TSEC_READ(sc, TSEC_REG_MACCFG1); 674 maccfg1_flags &= ~TSEC_MACCFG1_SOFT_RESET; 675 TSEC_WRITE(sc, TSEC_REG_MACCFG1, maccfg1_flags); 676} 677 678static void 679tsec_watchdog(struct tsec_softc *sc) 680{ 681 struct ifnet *ifp; 682 683 TSEC_GLOBAL_LOCK_ASSERT(sc); 684 685 if (sc->tsec_watchdog == 0 || --sc->tsec_watchdog > 0) 686 return; 687 688 ifp = sc->tsec_ifp; 689 ifp->if_oerrors++; 690 if_printf(ifp, "watchdog timeout\n"); 691 692 tsec_stop(sc); 693 tsec_init_locked(sc); 694} 695 696static void 697tsec_start(struct ifnet *ifp) 698{ 699 struct tsec_softc *sc = ifp->if_softc; 700 701 TSEC_TRANSMIT_LOCK(sc); 702 tsec_start_locked(ifp); 703 TSEC_TRANSMIT_UNLOCK(sc); 704} 705 706static void 707tsec_start_locked(struct ifnet *ifp) 708{ 709 struct tsec_softc *sc; 710 struct mbuf *m0, *mtmp; 711 struct tsec_tx_fcb *tx_fcb; 712 unsigned int queued = 0; 713 int csum_flags, fcb_inserted = 0; 714 715 sc = ifp->if_softc; 716 717 TSEC_TRANSMIT_LOCK_ASSERT(sc); 718 719 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 720 IFF_DRV_RUNNING) 721 return; 722 723 if (sc->tsec_link == 0) 724 return; 725 726 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 727 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 728 729 while (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 730 /* Get packet from the queue */ 731 IFQ_DRV_DEQUEUE(&ifp->if_snd, m0); 732 if (m0 == NULL) 733 break; 734 735 /* Insert TCP/IP Off-load frame control block */ 736 csum_flags = m0->m_pkthdr.csum_flags; 737 if (csum_flags) { 738 739 M_PREPEND(m0, sizeof(struct tsec_tx_fcb), M_NOWAIT); 740 if (m0 == NULL) 741 break; 742 743 tx_fcb = mtod(m0, struct tsec_tx_fcb *); 744 tx_fcb->flags = 0; 745 tx_fcb->l3_offset = ETHER_HDR_LEN; 746 tx_fcb->l4_offset = sizeof(struct ip); 747 748 if (csum_flags & CSUM_IP) 749 tx_fcb->flags |= TSEC_TX_FCB_IP4 | 750 TSEC_TX_FCB_CSUM_IP; 751 752 if (csum_flags & CSUM_TCP) 753 tx_fcb->flags |= TSEC_TX_FCB_TCP | 754 TSEC_TX_FCB_CSUM_TCP_UDP; 755 756 if (csum_flags & CSUM_UDP) 757 tx_fcb->flags |= TSEC_TX_FCB_UDP | 758 TSEC_TX_FCB_CSUM_TCP_UDP; 759 760 fcb_inserted = 1; 761 } 762 763 mtmp = m_defrag(m0, M_NOWAIT); 764 if (mtmp) 765 m0 = mtmp; 766 767 if (tsec_encap(sc, m0, fcb_inserted)) { 768 IFQ_DRV_PREPEND(&ifp->if_snd, m0); 769 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 770 break; 771 } 772 queued++; 773 BPF_MTAP(ifp, m0); 774 } 775 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 776 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 777 778 if (queued) { 779 /* Enable transmitter and watchdog timer */ 780 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT); 781 sc->tsec_watchdog = 5; 782 } 783} 784 785static int 786tsec_encap(struct tsec_softc *sc, struct mbuf *m0, int fcb_inserted) 787{ 788 struct tsec_desc *tx_desc = NULL; 789 struct ifnet *ifp; 790 bus_dma_segment_t segs[TSEC_TX_NUM_DESC]; 791 bus_dmamap_t *mapp; 792 int csum_flag = 0, error, seg, nsegs; 793 794 TSEC_TRANSMIT_LOCK_ASSERT(sc); 795 796 ifp = sc->tsec_ifp; 797 798 if (TSEC_FREE_TX_DESC(sc) == 0) { 799 /* No free descriptors */ 800 return (-1); 801 } 802 803 /* Fetch unused map */ 804 mapp = TSEC_ALLOC_TX_MAP(sc); 805 806 /* Create mapping in DMA memory */ 807 error = bus_dmamap_load_mbuf_sg(sc->tsec_tx_mtag, 808 *mapp, m0, segs, &nsegs, BUS_DMA_NOWAIT); 809 if (error != 0 || nsegs > TSEC_FREE_TX_DESC(sc) || nsegs <= 0) { 810 bus_dmamap_unload(sc->tsec_tx_mtag, *mapp); 811 TSEC_FREE_TX_MAP(sc, mapp); 812 return ((error != 0) ? error : -1); 813 } 814 bus_dmamap_sync(sc->tsec_tx_mtag, *mapp, BUS_DMASYNC_PREWRITE); 815 816 if ((ifp->if_flags & IFF_DEBUG) && (nsegs > 1)) 817 if_printf(ifp, "TX buffer has %d segments\n", nsegs); 818 819 if (fcb_inserted) 820 csum_flag = TSEC_TXBD_TOE; 821 822 /* Everything is ok, now we can send buffers */ 823 for (seg = 0; seg < nsegs; seg++) { 824 tx_desc = TSEC_GET_CUR_TX_DESC(sc); 825 826 tx_desc->length = segs[seg].ds_len; 827 tx_desc->bufptr = segs[seg].ds_addr; 828 829 /* 830 * Set flags: 831 * - wrap 832 * - checksum 833 * - ready to send 834 * - transmit the CRC sequence after the last data byte 835 * - interrupt after the last buffer 836 */ 837 tx_desc->flags = 838 (tx_desc->flags & TSEC_TXBD_W) | 839 ((seg == 0) ? csum_flag : 0) | TSEC_TXBD_R | TSEC_TXBD_TC | 840 ((seg == nsegs - 1) ? TSEC_TXBD_L | TSEC_TXBD_I : 0); 841 } 842 843 /* Save mbuf and DMA mapping for release at later stage */ 844 TSEC_PUT_TX_MBUF(sc, m0); 845 TSEC_PUT_TX_MAP(sc, mapp); 846 847 return (0); 848} 849 850static void 851tsec_setfilter(struct tsec_softc *sc) 852{ 853 struct ifnet *ifp; 854 uint32_t flags; 855 856 ifp = sc->tsec_ifp; 857 flags = TSEC_READ(sc, TSEC_REG_RCTRL); 858 859 /* Promiscuous mode */ 860 if (ifp->if_flags & IFF_PROMISC) 861 flags |= TSEC_RCTRL_PROM; 862 else 863 flags &= ~TSEC_RCTRL_PROM; 864 865 TSEC_WRITE(sc, TSEC_REG_RCTRL, flags); 866} 867 868#ifdef DEVICE_POLLING 869static poll_handler_t tsec_poll; 870 871static int 872tsec_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 873{ 874 uint32_t ie; 875 struct tsec_softc *sc = ifp->if_softc; 876 int rx_npkts; 877 878 rx_npkts = 0; 879 880 TSEC_GLOBAL_LOCK(sc); 881 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { 882 TSEC_GLOBAL_UNLOCK(sc); 883 return (rx_npkts); 884 } 885 886 if (cmd == POLL_AND_CHECK_STATUS) { 887 tsec_error_intr_locked(sc, count); 888 889 /* Clear all events reported */ 890 ie = TSEC_READ(sc, TSEC_REG_IEVENT); 891 TSEC_WRITE(sc, TSEC_REG_IEVENT, ie); 892 } 893 894 tsec_transmit_intr_locked(sc); 895 896 TSEC_GLOBAL_TO_RECEIVE_LOCK(sc); 897 898 rx_npkts = tsec_receive_intr_locked(sc, count); 899 900 TSEC_RECEIVE_UNLOCK(sc); 901 902 return (rx_npkts); 903} 904#endif /* DEVICE_POLLING */ 905 906static int 907tsec_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 908{ 909 struct tsec_softc *sc = ifp->if_softc; 910 struct ifreq *ifr = (struct ifreq *)data; 911 device_t dev; 912 int mask, error = 0; 913 914 dev = sc->dev; 915 916 switch (command) { 917 case SIOCSIFMTU: 918 TSEC_GLOBAL_LOCK(sc); 919 if (tsec_set_mtu(sc, ifr->ifr_mtu)) 920 ifp->if_mtu = ifr->ifr_mtu; 921 else 922 error = EINVAL; 923 TSEC_GLOBAL_UNLOCK(sc); 924 break; 925 case SIOCSIFFLAGS: 926 TSEC_GLOBAL_LOCK(sc); 927 if (ifp->if_flags & IFF_UP) { 928 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 929 if ((sc->tsec_if_flags ^ ifp->if_flags) & 930 IFF_PROMISC) 931 tsec_setfilter(sc); 932 933 if ((sc->tsec_if_flags ^ ifp->if_flags) & 934 IFF_ALLMULTI) 935 tsec_setup_multicast(sc); 936 } else 937 tsec_init_locked(sc); 938 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING) 939 tsec_stop(sc); 940 941 sc->tsec_if_flags = ifp->if_flags; 942 TSEC_GLOBAL_UNLOCK(sc); 943 break; 944 case SIOCADDMULTI: 945 case SIOCDELMULTI: 946 if (ifp->if_drv_flags & IFF_DRV_RUNNING) { 947 TSEC_GLOBAL_LOCK(sc); 948 tsec_setup_multicast(sc); 949 TSEC_GLOBAL_UNLOCK(sc); 950 } 951 case SIOCGIFMEDIA: 952 case SIOCSIFMEDIA: 953 error = ifmedia_ioctl(ifp, ifr, &sc->tsec_mii->mii_media, 954 command); 955 break; 956 case SIOCSIFCAP: 957 mask = ifp->if_capenable ^ ifr->ifr_reqcap; 958 if ((mask & IFCAP_HWCSUM) && sc->is_etsec) { 959 TSEC_GLOBAL_LOCK(sc); 960 ifp->if_capenable &= ~IFCAP_HWCSUM; 961 ifp->if_capenable |= IFCAP_HWCSUM & ifr->ifr_reqcap; 962 tsec_offload_setup(sc); 963 TSEC_GLOBAL_UNLOCK(sc); 964 } 965#ifdef DEVICE_POLLING 966 if (mask & IFCAP_POLLING) { 967 if (ifr->ifr_reqcap & IFCAP_POLLING) { 968 error = ether_poll_register(tsec_poll, ifp); 969 if (error) 970 return (error); 971 972 TSEC_GLOBAL_LOCK(sc); 973 /* Disable interrupts */ 974 tsec_intrs_ctl(sc, 0); 975 ifp->if_capenable |= IFCAP_POLLING; 976 TSEC_GLOBAL_UNLOCK(sc); 977 } else { 978 error = ether_poll_deregister(ifp); 979 TSEC_GLOBAL_LOCK(sc); 980 /* Enable interrupts */ 981 tsec_intrs_ctl(sc, 1); 982 ifp->if_capenable &= ~IFCAP_POLLING; 983 TSEC_GLOBAL_UNLOCK(sc); 984 } 985 } 986#endif 987 break; 988 989 default: 990 error = ether_ioctl(ifp, command, data); 991 } 992 993 /* Flush buffers if not empty */ 994 if (ifp->if_flags & IFF_UP) 995 tsec_start(ifp); 996 return (error); 997} 998 999static int 1000tsec_ifmedia_upd(struct ifnet *ifp) 1001{ 1002 struct tsec_softc *sc = ifp->if_softc; 1003 struct mii_data *mii; 1004 1005 TSEC_TRANSMIT_LOCK(sc); 1006 1007 mii = sc->tsec_mii; 1008 mii_mediachg(mii); 1009 1010 TSEC_TRANSMIT_UNLOCK(sc); 1011 return (0); 1012} 1013 1014static void 1015tsec_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1016{ 1017 struct tsec_softc *sc = ifp->if_softc; 1018 struct mii_data *mii; 1019 1020 TSEC_TRANSMIT_LOCK(sc); 1021 1022 mii = sc->tsec_mii; 1023 mii_pollstat(mii); 1024 1025 ifmr->ifm_active = mii->mii_media_active; 1026 ifmr->ifm_status = mii->mii_media_status; 1027 1028 TSEC_TRANSMIT_UNLOCK(sc); 1029} 1030 1031static int 1032tsec_new_rxbuf(bus_dma_tag_t tag, bus_dmamap_t map, struct mbuf **mbufp, 1033 uint32_t *paddr) 1034{ 1035 struct mbuf *new_mbuf; 1036 bus_dma_segment_t seg[1]; 1037 int error, nsegs; 1038 1039 KASSERT(mbufp != NULL, ("NULL mbuf pointer!")); 1040 1041 new_mbuf = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MCLBYTES); 1042 if (new_mbuf == NULL) 1043 return (ENOBUFS); 1044 new_mbuf->m_len = new_mbuf->m_pkthdr.len = new_mbuf->m_ext.ext_size; 1045 1046 if (*mbufp) { 1047 bus_dmamap_sync(tag, map, BUS_DMASYNC_POSTREAD); 1048 bus_dmamap_unload(tag, map); 1049 } 1050 1051 error = bus_dmamap_load_mbuf_sg(tag, map, new_mbuf, seg, &nsegs, 1052 BUS_DMA_NOWAIT); 1053 KASSERT(nsegs == 1, ("Too many segments returned!")); 1054 if (nsegs != 1 || error) 1055 panic("tsec_new_rxbuf(): nsegs(%d), error(%d)", nsegs, error); 1056 1057#if 0 1058 if (error) { 1059 printf("tsec: bus_dmamap_load_mbuf_sg() returned: %d!\n", 1060 error); 1061 m_freem(new_mbuf); 1062 return (ENOBUFS); 1063 } 1064#endif 1065 1066#if 0 1067 KASSERT(((seg->ds_addr) & (TSEC_RXBUFFER_ALIGNMENT-1)) == 0, 1068 ("Wrong alignment of RX buffer!")); 1069#endif 1070 bus_dmamap_sync(tag, map, BUS_DMASYNC_PREREAD); 1071 1072 (*mbufp) = new_mbuf; 1073 (*paddr) = seg->ds_addr; 1074 return (0); 1075} 1076 1077static void 1078tsec_map_dma_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 1079{ 1080 u_int32_t *paddr; 1081 1082 KASSERT(nseg == 1, ("wrong number of segments, should be 1")); 1083 paddr = arg; 1084 *paddr = segs->ds_addr; 1085} 1086 1087static int 1088tsec_alloc_dma_desc(device_t dev, bus_dma_tag_t *dtag, bus_dmamap_t *dmap, 1089 bus_size_t dsize, void **vaddr, void *raddr, const char *dname) 1090{ 1091 int error; 1092 1093 /* Allocate a busdma tag and DMA safe memory for TX/RX descriptors. */ 1094 error = bus_dma_tag_create(NULL, /* parent */ 1095 PAGE_SIZE, 0, /* alignment, boundary */ 1096 BUS_SPACE_MAXADDR_32BIT, /* lowaddr */ 1097 BUS_SPACE_MAXADDR, /* highaddr */ 1098 NULL, NULL, /* filtfunc, filtfuncarg */ 1099 dsize, 1, /* maxsize, nsegments */ 1100 dsize, 0, /* maxsegsz, flags */ 1101 NULL, NULL, /* lockfunc, lockfuncarg */ 1102 dtag); /* dmat */ 1103 1104 if (error) { 1105 device_printf(dev, "failed to allocate busdma %s tag\n", 1106 dname); 1107 (*vaddr) = NULL; 1108 return (ENXIO); 1109 } 1110 1111 error = bus_dmamem_alloc(*dtag, vaddr, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 1112 dmap); 1113 if (error) { 1114 device_printf(dev, "failed to allocate %s DMA safe memory\n", 1115 dname); 1116 bus_dma_tag_destroy(*dtag); 1117 (*vaddr) = NULL; 1118 return (ENXIO); 1119 } 1120 1121 error = bus_dmamap_load(*dtag, *dmap, *vaddr, dsize, 1122 tsec_map_dma_addr, raddr, BUS_DMA_NOWAIT); 1123 if (error) { 1124 device_printf(dev, "cannot get address of the %s " 1125 "descriptors\n", dname); 1126 bus_dmamem_free(*dtag, *vaddr, *dmap); 1127 bus_dma_tag_destroy(*dtag); 1128 (*vaddr) = NULL; 1129 return (ENXIO); 1130 } 1131 1132 return (0); 1133} 1134 1135static void 1136tsec_free_dma_desc(bus_dma_tag_t dtag, bus_dmamap_t dmap, void *vaddr) 1137{ 1138 1139 if (vaddr == NULL) 1140 return; 1141 1142 /* Unmap descriptors from DMA memory */ 1143 bus_dmamap_sync(dtag, dmap, BUS_DMASYNC_POSTREAD | 1144 BUS_DMASYNC_POSTWRITE); 1145 bus_dmamap_unload(dtag, dmap); 1146 1147 /* Free descriptors memory */ 1148 bus_dmamem_free(dtag, vaddr, dmap); 1149 1150 /* Destroy descriptors tag */ 1151 bus_dma_tag_destroy(dtag); 1152} 1153 1154static void 1155tsec_free_dma(struct tsec_softc *sc) 1156{ 1157 int i; 1158 1159 /* Free TX maps */ 1160 for (i = 0; i < TSEC_TX_NUM_DESC; i++) 1161 if (sc->tx_map_data[i] != NULL) 1162 bus_dmamap_destroy(sc->tsec_tx_mtag, 1163 sc->tx_map_data[i]); 1164 /* Destroy tag for TX mbufs */ 1165 bus_dma_tag_destroy(sc->tsec_tx_mtag); 1166 1167 /* Free RX mbufs and maps */ 1168 for (i = 0; i < TSEC_RX_NUM_DESC; i++) { 1169 if (sc->rx_data[i].mbuf) { 1170 /* Unload buffer from DMA */ 1171 bus_dmamap_sync(sc->tsec_rx_mtag, sc->rx_data[i].map, 1172 BUS_DMASYNC_POSTREAD); 1173 bus_dmamap_unload(sc->tsec_rx_mtag, 1174 sc->rx_data[i].map); 1175 1176 /* Free buffer */ 1177 m_freem(sc->rx_data[i].mbuf); 1178 } 1179 /* Destroy map for this buffer */ 1180 if (sc->rx_data[i].map != NULL) 1181 bus_dmamap_destroy(sc->tsec_rx_mtag, 1182 sc->rx_data[i].map); 1183 } 1184 /* Destroy tag for RX mbufs */ 1185 bus_dma_tag_destroy(sc->tsec_rx_mtag); 1186 1187 /* Unload TX/RX descriptors */ 1188 tsec_free_dma_desc(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 1189 sc->tsec_tx_vaddr); 1190 tsec_free_dma_desc(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 1191 sc->tsec_rx_vaddr); 1192} 1193 1194static void 1195tsec_stop(struct tsec_softc *sc) 1196{ 1197 struct ifnet *ifp; 1198 struct mbuf *m0; 1199 bus_dmamap_t *mapp; 1200 uint32_t tmpval; 1201 1202 TSEC_GLOBAL_LOCK_ASSERT(sc); 1203 1204 ifp = sc->tsec_ifp; 1205 1206 /* Disable interface and watchdog timer */ 1207 callout_stop(&sc->tsec_callout); 1208 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1209 sc->tsec_watchdog = 0; 1210 1211 /* Disable all interrupts and stop DMA */ 1212 tsec_intrs_ctl(sc, 0); 1213 tsec_dma_ctl(sc, 0); 1214 1215 /* Remove pending data from TX queue */ 1216 while (!TSEC_EMPTYQ_TX_MBUF(sc)) { 1217 m0 = TSEC_GET_TX_MBUF(sc); 1218 mapp = TSEC_GET_TX_MAP(sc); 1219 1220 bus_dmamap_sync(sc->tsec_tx_mtag, *mapp, 1221 BUS_DMASYNC_POSTWRITE); 1222 bus_dmamap_unload(sc->tsec_tx_mtag, *mapp); 1223 1224 TSEC_FREE_TX_MAP(sc, mapp); 1225 m_freem(m0); 1226 } 1227 1228 /* Disable RX and TX */ 1229 tmpval = TSEC_READ(sc, TSEC_REG_MACCFG1); 1230 tmpval &= ~(TSEC_MACCFG1_RX_EN | TSEC_MACCFG1_TX_EN); 1231 TSEC_WRITE(sc, TSEC_REG_MACCFG1, tmpval); 1232 DELAY(10); 1233} 1234 1235static void 1236tsec_tick(void *arg) 1237{ 1238 struct tsec_softc *sc = arg; 1239 struct ifnet *ifp; 1240 int link; 1241 1242 TSEC_GLOBAL_LOCK(sc); 1243 1244 tsec_watchdog(sc); 1245 1246 ifp = sc->tsec_ifp; 1247 link = sc->tsec_link; 1248 1249 mii_tick(sc->tsec_mii); 1250 1251 if (link == 0 && sc->tsec_link == 1 && 1252 (!IFQ_DRV_IS_EMPTY(&ifp->if_snd))) 1253 tsec_start_locked(ifp); 1254 1255 /* Schedule another timeout one second from now. */ 1256 callout_reset(&sc->tsec_callout, hz, tsec_tick, sc); 1257 1258 TSEC_GLOBAL_UNLOCK(sc); 1259} 1260 1261/* 1262 * This is the core RX routine. It replenishes mbufs in the descriptor and 1263 * sends data which have been dma'ed into host memory to upper layer. 1264 * 1265 * Loops at most count times if count is > 0, or until done if count < 0. 1266 */ 1267static int 1268tsec_receive_intr_locked(struct tsec_softc *sc, int count) 1269{ 1270 struct tsec_desc *rx_desc; 1271 struct ifnet *ifp; 1272 struct rx_data_type *rx_data; 1273 struct mbuf *m; 1274 device_t dev; 1275 uint32_t i; 1276 int c, rx_npkts; 1277 uint16_t flags; 1278 1279 TSEC_RECEIVE_LOCK_ASSERT(sc); 1280 1281 ifp = sc->tsec_ifp; 1282 rx_data = sc->rx_data; 1283 dev = sc->dev; 1284 rx_npkts = 0; 1285 1286 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 1287 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1288 1289 for (c = 0; ; c++) { 1290 if (count >= 0 && count-- == 0) 1291 break; 1292 1293 rx_desc = TSEC_GET_CUR_RX_DESC(sc); 1294 flags = rx_desc->flags; 1295 1296 /* Check if there is anything to receive */ 1297 if ((flags & TSEC_RXBD_E) || (c >= TSEC_RX_NUM_DESC)) { 1298 /* 1299 * Avoid generating another interrupt 1300 */ 1301 if (flags & TSEC_RXBD_E) 1302 TSEC_WRITE(sc, TSEC_REG_IEVENT, 1303 TSEC_IEVENT_RXB | TSEC_IEVENT_RXF); 1304 /* 1305 * We didn't consume current descriptor and have to 1306 * return it to the queue 1307 */ 1308 TSEC_BACK_CUR_RX_DESC(sc); 1309 break; 1310 } 1311 1312 if (flags & (TSEC_RXBD_LG | TSEC_RXBD_SH | TSEC_RXBD_NO | 1313 TSEC_RXBD_CR | TSEC_RXBD_OV | TSEC_RXBD_TR)) { 1314 1315 rx_desc->length = 0; 1316 rx_desc->flags = (rx_desc->flags & 1317 ~TSEC_RXBD_ZEROONINIT) | TSEC_RXBD_E | TSEC_RXBD_I; 1318 1319 if (sc->frame != NULL) { 1320 m_free(sc->frame); 1321 sc->frame = NULL; 1322 } 1323 1324 continue; 1325 } 1326 1327 /* Ok... process frame */ 1328 i = TSEC_GET_CUR_RX_DESC_CNT(sc); 1329 m = rx_data[i].mbuf; 1330 m->m_len = rx_desc->length; 1331 1332 if (sc->frame != NULL) { 1333 if ((flags & TSEC_RXBD_L) != 0) 1334 m->m_len -= m_length(sc->frame, NULL); 1335 1336 m->m_flags &= ~M_PKTHDR; 1337 m_cat(sc->frame, m); 1338 } else { 1339 sc->frame = m; 1340 } 1341 1342 m = NULL; 1343 1344 if ((flags & TSEC_RXBD_L) != 0) { 1345 m = sc->frame; 1346 sc->frame = NULL; 1347 } 1348 1349 if (tsec_new_rxbuf(sc->tsec_rx_mtag, rx_data[i].map, 1350 &rx_data[i].mbuf, &rx_data[i].paddr)) { 1351 ifp->if_ierrors++; 1352 /* 1353 * We ran out of mbufs; didn't consume current 1354 * descriptor and have to return it to the queue. 1355 */ 1356 TSEC_BACK_CUR_RX_DESC(sc); 1357 break; 1358 } 1359 1360 /* Attach new buffer to descriptor and clear flags */ 1361 rx_desc->bufptr = rx_data[i].paddr; 1362 rx_desc->length = 0; 1363 rx_desc->flags = (rx_desc->flags & ~TSEC_RXBD_ZEROONINIT) | 1364 TSEC_RXBD_E | TSEC_RXBD_I; 1365 1366 if (m != NULL) { 1367 m->m_pkthdr.rcvif = ifp; 1368 1369 m_fixhdr(m); 1370 m_adj(m, -ETHER_CRC_LEN); 1371 1372 if (sc->is_etsec) 1373 tsec_offload_process_frame(sc, m); 1374 1375 TSEC_RECEIVE_UNLOCK(sc); 1376 (*ifp->if_input)(ifp, m); 1377 TSEC_RECEIVE_LOCK(sc); 1378 rx_npkts++; 1379 } 1380 } 1381 1382 bus_dmamap_sync(sc->tsec_rx_dtag, sc->tsec_rx_dmap, 1383 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1384 1385 /* 1386 * Make sure TSEC receiver is not halted. 1387 * 1388 * Various conditions can stop the TSEC receiver, but not all are 1389 * signaled and handled by error interrupt, so make sure the receiver 1390 * is running. Writing to TSEC_REG_RSTAT restarts the receiver when 1391 * halted, and is harmless if already running. 1392 */ 1393 TSEC_WRITE(sc, TSEC_REG_RSTAT, TSEC_RSTAT_QHLT); 1394 return (rx_npkts); 1395} 1396 1397void 1398tsec_receive_intr(void *arg) 1399{ 1400 struct tsec_softc *sc = arg; 1401 1402 TSEC_RECEIVE_LOCK(sc); 1403 1404#ifdef DEVICE_POLLING 1405 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) { 1406 TSEC_RECEIVE_UNLOCK(sc); 1407 return; 1408 } 1409#endif 1410 1411 /* Confirm the interrupt was received by driver */ 1412 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXB | TSEC_IEVENT_RXF); 1413 tsec_receive_intr_locked(sc, -1); 1414 1415 TSEC_RECEIVE_UNLOCK(sc); 1416} 1417 1418static void 1419tsec_transmit_intr_locked(struct tsec_softc *sc) 1420{ 1421 struct tsec_desc *tx_desc; 1422 struct ifnet *ifp; 1423 struct mbuf *m0; 1424 bus_dmamap_t *mapp; 1425 int send = 0; 1426 1427 TSEC_TRANSMIT_LOCK_ASSERT(sc); 1428 1429 ifp = sc->tsec_ifp; 1430 1431 /* Update collision statistics */ 1432 ifp->if_collisions += TSEC_READ(sc, TSEC_REG_MON_TNCL); 1433 1434 /* Reset collision counters in hardware */ 1435 TSEC_WRITE(sc, TSEC_REG_MON_TSCL, 0); 1436 TSEC_WRITE(sc, TSEC_REG_MON_TMCL, 0); 1437 TSEC_WRITE(sc, TSEC_REG_MON_TLCL, 0); 1438 TSEC_WRITE(sc, TSEC_REG_MON_TXCL, 0); 1439 TSEC_WRITE(sc, TSEC_REG_MON_TNCL, 0); 1440 1441 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 1442 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1443 1444 while (TSEC_CUR_DIFF_DIRTY_TX_DESC(sc)) { 1445 tx_desc = TSEC_GET_DIRTY_TX_DESC(sc); 1446 if (tx_desc->flags & TSEC_TXBD_R) { 1447 TSEC_BACK_DIRTY_TX_DESC(sc); 1448 break; 1449 } 1450 1451 if ((tx_desc->flags & TSEC_TXBD_L) == 0) 1452 continue; 1453 1454 /* 1455 * This is the last buf in this packet, so unmap and free it. 1456 */ 1457 m0 = TSEC_GET_TX_MBUF(sc); 1458 mapp = TSEC_GET_TX_MAP(sc); 1459 1460 bus_dmamap_sync(sc->tsec_tx_mtag, *mapp, 1461 BUS_DMASYNC_POSTWRITE); 1462 bus_dmamap_unload(sc->tsec_tx_mtag, *mapp); 1463 1464 TSEC_FREE_TX_MAP(sc, mapp); 1465 m_freem(m0); 1466 1467 ifp->if_opackets++; 1468 send = 1; 1469 } 1470 bus_dmamap_sync(sc->tsec_tx_dtag, sc->tsec_tx_dmap, 1471 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1472 1473 if (send) { 1474 /* Now send anything that was pending */ 1475 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1476 tsec_start_locked(ifp); 1477 1478 /* Stop wathdog if all sent */ 1479 if (TSEC_EMPTYQ_TX_MBUF(sc)) 1480 sc->tsec_watchdog = 0; 1481 } 1482} 1483 1484void 1485tsec_transmit_intr(void *arg) 1486{ 1487 struct tsec_softc *sc = arg; 1488 1489 TSEC_TRANSMIT_LOCK(sc); 1490 1491#ifdef DEVICE_POLLING 1492 if (sc->tsec_ifp->if_capenable & IFCAP_POLLING) { 1493 TSEC_TRANSMIT_UNLOCK(sc); 1494 return; 1495 } 1496#endif 1497 /* Confirm the interrupt was received by driver */ 1498 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_TXB | TSEC_IEVENT_TXF); 1499 tsec_transmit_intr_locked(sc); 1500 1501 TSEC_TRANSMIT_UNLOCK(sc); 1502} 1503 1504static void 1505tsec_error_intr_locked(struct tsec_softc *sc, int count) 1506{ 1507 struct ifnet *ifp; 1508 uint32_t eflags; 1509 1510 TSEC_GLOBAL_LOCK_ASSERT(sc); 1511 1512 ifp = sc->tsec_ifp; 1513 1514 eflags = TSEC_READ(sc, TSEC_REG_IEVENT); 1515 1516 /* Clear events bits in hardware */ 1517 TSEC_WRITE(sc, TSEC_REG_IEVENT, TSEC_IEVENT_RXC | TSEC_IEVENT_BSY | 1518 TSEC_IEVENT_EBERR | TSEC_IEVENT_MSRO | TSEC_IEVENT_BABT | 1519 TSEC_IEVENT_TXC | TSEC_IEVENT_TXE | TSEC_IEVENT_LC | 1520 TSEC_IEVENT_CRL | TSEC_IEVENT_XFUN); 1521 1522 /* Check transmitter errors */ 1523 if (eflags & TSEC_IEVENT_TXE) { 1524 ifp->if_oerrors++; 1525 1526 if (eflags & TSEC_IEVENT_LC) 1527 ifp->if_collisions++; 1528 1529 TSEC_WRITE(sc, TSEC_REG_TSTAT, TSEC_TSTAT_THLT); 1530 } 1531 1532 /* Check receiver errors */ 1533 if (eflags & TSEC_IEVENT_BSY) { 1534 ifp->if_ierrors++; 1535 ifp->if_iqdrops++; 1536 1537 /* Get data from RX buffers */ 1538 tsec_receive_intr_locked(sc, count); 1539 } 1540 1541 if (ifp->if_flags & IFF_DEBUG) 1542 if_printf(ifp, "tsec_error_intr(): event flags: 0x%x\n", 1543 eflags); 1544 1545 if (eflags & TSEC_IEVENT_EBERR) { 1546 if_printf(ifp, "System bus error occurred during" 1547 "DMA transaction (flags: 0x%x)\n", eflags); 1548 tsec_init_locked(sc); 1549 } 1550 1551 if (eflags & TSEC_IEVENT_BABT) 1552 ifp->if_oerrors++; 1553 1554 if (eflags & TSEC_IEVENT_BABR) 1555 ifp->if_ierrors++; 1556} 1557 1558void 1559tsec_error_intr(void *arg) 1560{ 1561 struct tsec_softc *sc = arg; 1562 1563 TSEC_GLOBAL_LOCK(sc); 1564 tsec_error_intr_locked(sc, -1); 1565 TSEC_GLOBAL_UNLOCK(sc); 1566} 1567 1568int 1569tsec_miibus_readreg(device_t dev, int phy, int reg) 1570{ 1571 struct tsec_softc *sc; 1572 uint32_t timeout; 1573 int rv; 1574 1575 sc = device_get_softc(dev); 1576 1577 TSEC_PHY_LOCK(); 1578 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg); 1579 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCOM, 0); 1580 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCOM, TSEC_MIIMCOM_READCYCLE); 1581 1582 timeout = TSEC_READ_RETRY; 1583 while (--timeout && TSEC_PHY_READ(sc, TSEC_REG_MIIMIND) & 1584 (TSEC_MIIMIND_NOTVALID | TSEC_MIIMIND_BUSY)) 1585 DELAY(TSEC_READ_DELAY); 1586 1587 if (timeout == 0) 1588 device_printf(dev, "Timeout while reading from PHY!\n"); 1589 1590 rv = TSEC_PHY_READ(sc, TSEC_REG_MIIMSTAT); 1591 TSEC_PHY_UNLOCK(); 1592 1593 return (rv); 1594} 1595 1596int 1597tsec_miibus_writereg(device_t dev, int phy, int reg, int value) 1598{ 1599 struct tsec_softc *sc; 1600 uint32_t timeout; 1601 1602 sc = device_get_softc(dev); 1603 1604 TSEC_PHY_LOCK(); 1605 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMADD, (phy << 8) | reg); 1606 TSEC_PHY_WRITE(sc, TSEC_REG_MIIMCON, value); 1607 1608 timeout = TSEC_READ_RETRY; 1609 while (--timeout && (TSEC_READ(sc, TSEC_REG_MIIMIND) & 1610 TSEC_MIIMIND_BUSY)) 1611 DELAY(TSEC_READ_DELAY); 1612 TSEC_PHY_UNLOCK(); 1613 1614 if (timeout == 0) 1615 device_printf(dev, "Timeout while writing to PHY!\n"); 1616 1617 return (0); 1618} 1619 1620void 1621tsec_miibus_statchg(device_t dev) 1622{ 1623 struct tsec_softc *sc; 1624 struct mii_data *mii; 1625 uint32_t ecntrl, id, tmp; 1626 int link; 1627 1628 sc = device_get_softc(dev); 1629 mii = sc->tsec_mii; 1630 link = ((mii->mii_media_status & IFM_ACTIVE) ? 1 : 0); 1631 1632 tmp = TSEC_READ(sc, TSEC_REG_MACCFG2) & ~TSEC_MACCFG2_IF; 1633 1634 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) 1635 tmp |= TSEC_MACCFG2_FULLDUPLEX; 1636 else 1637 tmp &= ~TSEC_MACCFG2_FULLDUPLEX; 1638 1639 switch (IFM_SUBTYPE(mii->mii_media_active)) { 1640 case IFM_1000_T: 1641 case IFM_1000_SX: 1642 tmp |= TSEC_MACCFG2_GMII; 1643 sc->tsec_link = link; 1644 break; 1645 case IFM_100_TX: 1646 case IFM_10_T: 1647 tmp |= TSEC_MACCFG2_MII; 1648 sc->tsec_link = link; 1649 break; 1650 case IFM_NONE: 1651 if (link) 1652 device_printf(dev, "No speed selected but link " 1653 "active!\n"); 1654 sc->tsec_link = 0; 1655 return; 1656 default: 1657 sc->tsec_link = 0; 1658 device_printf(dev, "Unknown speed (%d), link %s!\n", 1659 IFM_SUBTYPE(mii->mii_media_active), 1660 ((link) ? "up" : "down")); 1661 return; 1662 } 1663 TSEC_WRITE(sc, TSEC_REG_MACCFG2, tmp); 1664 1665 /* XXX kludge - use circumstantial evidence for reduced mode. */ 1666 id = TSEC_READ(sc, TSEC_REG_ID2); 1667 if (id & 0xffff) { 1668 ecntrl = TSEC_READ(sc, TSEC_REG_ECNTRL) & ~TSEC_ECNTRL_R100M; 1669 ecntrl |= (tmp & TSEC_MACCFG2_MII) ? TSEC_ECNTRL_R100M : 0; 1670 TSEC_WRITE(sc, TSEC_REG_ECNTRL, ecntrl); 1671 } 1672} 1673 1674static void 1675tsec_add_sysctls(struct tsec_softc *sc) 1676{ 1677 struct sysctl_ctx_list *ctx; 1678 struct sysctl_oid_list *children; 1679 struct sysctl_oid *tree; 1680 1681 ctx = device_get_sysctl_ctx(sc->dev); 1682 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)); 1683 tree = SYSCTL_ADD_NODE(ctx, children, OID_AUTO, "int_coal", 1684 CTLFLAG_RD, 0, "TSEC Interrupts coalescing"); 1685 children = SYSCTL_CHILDREN(tree); 1686 1687 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_time", 1688 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_RX, tsec_sysctl_ic_time, 1689 "I", "IC RX time threshold (0-65535)"); 1690 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "rx_count", 1691 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_RX, tsec_sysctl_ic_count, 1692 "I", "IC RX frame count threshold (0-255)"); 1693 1694 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_time", 1695 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_TX, tsec_sysctl_ic_time, 1696 "I", "IC TX time threshold (0-65535)"); 1697 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "tx_count", 1698 CTLTYPE_UINT | CTLFLAG_RW, sc, TSEC_IC_TX, tsec_sysctl_ic_count, 1699 "I", "IC TX frame count threshold (0-255)"); 1700} 1701 1702/* 1703 * With Interrupt Coalescing (IC) active, a transmit/receive frame 1704 * interrupt is raised either upon: 1705 * 1706 * - threshold-defined period of time elapsed, or 1707 * - threshold-defined number of frames is received/transmitted, 1708 * whichever occurs first. 1709 * 1710 * The following sysctls regulate IC behaviour (for TX/RX separately): 1711 * 1712 * dev.tsec.<unit>.int_coal.rx_time 1713 * dev.tsec.<unit>.int_coal.rx_count 1714 * dev.tsec.<unit>.int_coal.tx_time 1715 * dev.tsec.<unit>.int_coal.tx_count 1716 * 1717 * Values: 1718 * 1719 * - 0 for either time or count disables IC on the given TX/RX path 1720 * 1721 * - count: 1-255 (expresses frame count number; note that value of 1 is 1722 * effectively IC off) 1723 * 1724 * - time: 1-65535 (value corresponds to a real time period and is 1725 * expressed in units equivalent to 64 TSEC interface clocks, i.e. one timer 1726 * threshold unit is 26.5 us, 2.56 us, or 512 ns, corresponding to 10 Mbps, 1727 * 100 Mbps, or 1Gbps, respectively. For detailed discussion consult the 1728 * TSEC reference manual. 1729 */ 1730static int 1731tsec_sysctl_ic_time(SYSCTL_HANDLER_ARGS) 1732{ 1733 int error; 1734 uint32_t time; 1735 struct tsec_softc *sc = (struct tsec_softc *)arg1; 1736 1737 time = (arg2 == TSEC_IC_RX) ? sc->rx_ic_time : sc->tx_ic_time; 1738 1739 error = sysctl_handle_int(oidp, &time, 0, req); 1740 if (error != 0) 1741 return (error); 1742 1743 if (time > 65535) 1744 return (EINVAL); 1745 1746 TSEC_IC_LOCK(sc); 1747 if (arg2 == TSEC_IC_RX) { 1748 sc->rx_ic_time = time; 1749 tsec_set_rxic(sc); 1750 } else { 1751 sc->tx_ic_time = time; 1752 tsec_set_txic(sc); 1753 } 1754 TSEC_IC_UNLOCK(sc); 1755 1756 return (0); 1757} 1758 1759static int 1760tsec_sysctl_ic_count(SYSCTL_HANDLER_ARGS) 1761{ 1762 int error; 1763 uint32_t count; 1764 struct tsec_softc *sc = (struct tsec_softc *)arg1; 1765 1766 count = (arg2 == TSEC_IC_RX) ? sc->rx_ic_count : sc->tx_ic_count; 1767 1768 error = sysctl_handle_int(oidp, &count, 0, req); 1769 if (error != 0) 1770 return (error); 1771 1772 if (count > 255) 1773 return (EINVAL); 1774 1775 TSEC_IC_LOCK(sc); 1776 if (arg2 == TSEC_IC_RX) { 1777 sc->rx_ic_count = count; 1778 tsec_set_rxic(sc); 1779 } else { 1780 sc->tx_ic_count = count; 1781 tsec_set_txic(sc); 1782 } 1783 TSEC_IC_UNLOCK(sc); 1784 1785 return (0); 1786} 1787 1788static void 1789tsec_set_rxic(struct tsec_softc *sc) 1790{ 1791 uint32_t rxic_val; 1792 1793 if (sc->rx_ic_count == 0 || sc->rx_ic_time == 0) 1794 /* Disable RX IC */ 1795 rxic_val = 0; 1796 else { 1797 rxic_val = 0x80000000; 1798 rxic_val |= (sc->rx_ic_count << 21); 1799 rxic_val |= sc->rx_ic_time; 1800 } 1801 1802 TSEC_WRITE(sc, TSEC_REG_RXIC, rxic_val); 1803} 1804 1805static void 1806tsec_set_txic(struct tsec_softc *sc) 1807{ 1808 uint32_t txic_val; 1809 1810 if (sc->tx_ic_count == 0 || sc->tx_ic_time == 0) 1811 /* Disable TX IC */ 1812 txic_val = 0; 1813 else { 1814 txic_val = 0x80000000; 1815 txic_val |= (sc->tx_ic_count << 21); 1816 txic_val |= sc->tx_ic_time; 1817 } 1818 1819 TSEC_WRITE(sc, TSEC_REG_TXIC, txic_val); 1820} 1821 1822static void 1823tsec_offload_setup(struct tsec_softc *sc) 1824{ 1825 struct ifnet *ifp = sc->tsec_ifp; 1826 uint32_t reg; 1827 1828 TSEC_GLOBAL_LOCK_ASSERT(sc); 1829 1830 reg = TSEC_READ(sc, TSEC_REG_TCTRL); 1831 reg |= TSEC_TCTRL_IPCSEN | TSEC_TCTRL_TUCSEN; 1832 1833 if (ifp->if_capenable & IFCAP_TXCSUM) 1834 ifp->if_hwassist = TSEC_CHECKSUM_FEATURES; 1835 else 1836 ifp->if_hwassist = 0; 1837 1838 TSEC_WRITE(sc, TSEC_REG_TCTRL, reg); 1839 1840 reg = TSEC_READ(sc, TSEC_REG_RCTRL); 1841 reg &= ~(TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN | TSEC_RCTRL_PRSDEP); 1842 reg |= TSEC_RCTRL_PRSDEP_PARSE_L2 | TSEC_RCTRL_VLEX; 1843 1844 if (ifp->if_capenable & IFCAP_RXCSUM) 1845 reg |= TSEC_RCTRL_IPCSEN | TSEC_RCTRL_TUCSEN | 1846 TSEC_RCTRL_PRSDEP_PARSE_L234; 1847 1848 TSEC_WRITE(sc, TSEC_REG_RCTRL, reg); 1849} 1850 1851 1852static void 1853tsec_offload_process_frame(struct tsec_softc *sc, struct mbuf *m) 1854{ 1855 struct tsec_rx_fcb rx_fcb; 1856 int csum_flags = 0; 1857 int protocol, flags; 1858 1859 TSEC_RECEIVE_LOCK_ASSERT(sc); 1860 1861 m_copydata(m, 0, sizeof(struct tsec_rx_fcb), (caddr_t)(&rx_fcb)); 1862 flags = rx_fcb.flags; 1863 protocol = rx_fcb.protocol; 1864 1865 if (TSEC_RX_FCB_IP_CSUM_CHECKED(flags)) { 1866 csum_flags |= CSUM_IP_CHECKED; 1867 1868 if ((flags & TSEC_RX_FCB_IP_CSUM_ERROR) == 0) 1869 csum_flags |= CSUM_IP_VALID; 1870 } 1871 1872 if ((protocol == IPPROTO_TCP || protocol == IPPROTO_UDP) && 1873 TSEC_RX_FCB_TCP_UDP_CSUM_CHECKED(flags) && 1874 (flags & TSEC_RX_FCB_TCP_UDP_CSUM_ERROR) == 0) { 1875 1876 csum_flags |= CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1877 m->m_pkthdr.csum_data = 0xFFFF; 1878 } 1879 1880 m->m_pkthdr.csum_flags = csum_flags; 1881 1882 if (flags & TSEC_RX_FCB_VLAN) { 1883 m->m_pkthdr.ether_vtag = rx_fcb.vlan; 1884 m->m_flags |= M_VLANTAG; 1885 } 1886 1887 m_adj(m, sizeof(struct tsec_rx_fcb)); 1888} 1889 1890static void 1891tsec_setup_multicast(struct tsec_softc *sc) 1892{ 1893 uint32_t hashtable[8] = { 0, 0, 0, 0, 0, 0, 0, 0 }; 1894 struct ifnet *ifp = sc->tsec_ifp; 1895 struct ifmultiaddr *ifma; 1896 uint32_t h; 1897 int i; 1898 1899 TSEC_GLOBAL_LOCK_ASSERT(sc); 1900 1901 if (ifp->if_flags & IFF_ALLMULTI) { 1902 for (i = 0; i < 8; i++) 1903 TSEC_WRITE(sc, TSEC_REG_GADDR(i), 0xFFFFFFFF); 1904 1905 return; 1906 } 1907 1908 if_maddr_rlock(ifp); 1909 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 1910 1911 if (ifma->ifma_addr->sa_family != AF_LINK) 1912 continue; 1913 1914 h = (ether_crc32_be(LLADDR((struct sockaddr_dl *) 1915 ifma->ifma_addr), ETHER_ADDR_LEN) >> 24) & 0xFF; 1916 1917 hashtable[(h >> 5)] |= 1 << (0x1F - (h & 0x1F)); 1918 } 1919 if_maddr_runlock(ifp); 1920 1921 for (i = 0; i < 8; i++) 1922 TSEC_WRITE(sc, TSEC_REG_GADDR(i), hashtable[i]); 1923} 1924 1925static int 1926tsec_set_mtu(struct tsec_softc *sc, unsigned int mtu) 1927{ 1928 1929 mtu += ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN + ETHER_CRC_LEN; 1930 1931 TSEC_GLOBAL_LOCK_ASSERT(sc); 1932 1933 if (mtu >= TSEC_MIN_FRAME_SIZE && mtu <= TSEC_MAX_FRAME_SIZE) { 1934 TSEC_WRITE(sc, TSEC_REG_MAXFRM, mtu); 1935 return (mtu); 1936 } 1937 1938 return (0); 1939} 1940