siena_sram.c revision 284555 
1/*-
2 * Copyright (c) 2009-2015 Solarflare Communications Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 *    this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 *    this list of conditions and the following disclaimer in the documentation
12 *    and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
29 */
30
31#include <sys/cdefs.h>
32__FBSDID("$FreeBSD: stable/10/sys/dev/sfxge/common/siena_sram.c 284555 2015-06-18 15:46:39Z arybchik $");
33
34#include "efsys.h"
35#include "efx.h"
36#include "efx_impl.h"
37
38#if EFSYS_OPT_SIENA
39
40			void
41siena_sram_init(
42	__in		efx_nic_t *enp)
43{
44	efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
45	efx_oword_t oword;
46	uint32_t rx_base, tx_base;
47
48	EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
49	EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA);
50
51	rx_base = encp->enc_buftbl_limit;
52	tx_base = rx_base + (encp->enc_rxq_limit *
53	    EFX_RXQ_DC_NDESCS(EFX_RXQ_DC_SIZE));
54
55	/* Initialize the transmit descriptor cache */
56	EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_TX_DC_BASE_ADR, tx_base);
57	EFX_BAR_WRITEO(enp, FR_AZ_SRM_TX_DC_CFG_REG, &oword);
58
59	EFX_POPULATE_OWORD_1(oword, FRF_AZ_TX_DC_SIZE, EFX_TXQ_DC_SIZE);
60	EFX_BAR_WRITEO(enp, FR_AZ_TX_DC_CFG_REG, &oword);
61
62	/* Initialize the receive descriptor cache */
63	EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_RX_DC_BASE_ADR, rx_base);
64	EFX_BAR_WRITEO(enp, FR_AZ_SRM_RX_DC_CFG_REG, &oword);
65
66	EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DC_SIZE, EFX_RXQ_DC_SIZE);
67	EFX_BAR_WRITEO(enp, FR_AZ_RX_DC_CFG_REG, &oword);
68
69	/* Set receive descriptor pre-fetch low water mark */
70	EFX_POPULATE_OWORD_1(oword, FRF_AZ_RX_DC_PF_LWM, 56);
71	EFX_BAR_WRITEO(enp, FR_AZ_RX_DC_PF_WM_REG, &oword);
72
73	/* Set the event queue to use for SRAM updates */
74	EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_UPD_EVQ_ID, 0);
75	EFX_BAR_WRITEO(enp, FR_AZ_SRM_UPD_EVQ_REG, &oword);
76}
77
78#if EFSYS_OPT_DIAG
79
80	__checkReturn	int
81siena_sram_test(
82	__in		efx_nic_t *enp,
83	__in		efx_sram_pattern_fn_t func)
84{
85	efx_oword_t oword;
86	efx_qword_t qword;
87	efx_qword_t verify;
88	size_t rows;
89	unsigned int wptr;
90	unsigned int rptr;
91	int rc;
92
93	EFSYS_ASSERT(enp->en_family == EFX_FAMILY_SIENA);
94
95	/* Reconfigure into HALF buffer table mode */
96	EFX_POPULATE_OWORD_1(oword, FRF_AZ_BUF_TBL_MODE, 0);
97	EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_CFG_REG, &oword);
98
99	/*
100	 * Move the descriptor caches up to the top of SRAM, and test
101	 * all of SRAM below them. We only miss out one row here.
102	 */
103	rows = SIENA_SRAM_ROWS - 1;
104	EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_RX_DC_BASE_ADR, rows);
105	EFX_BAR_WRITEO(enp, FR_AZ_SRM_RX_DC_CFG_REG, &oword);
106
107	EFX_POPULATE_OWORD_1(oword, FRF_AZ_SRM_TX_DC_BASE_ADR, rows + 1);
108	EFX_BAR_WRITEO(enp, FR_AZ_SRM_TX_DC_CFG_REG, &oword);
109
110	/*
111	 * Write the pattern through BUF_HALF_TBL. Write
112	 * in 64 entry batches, waiting 1us in between each batch
113	 * to guarantee not to overflow the SRAM fifo
114	 */
115	for (wptr = 0, rptr = 0; wptr < rows; ++wptr) {
116		func(wptr, B_FALSE, &qword);
117		EFX_BAR_TBL_WRITEQ(enp, FR_AZ_BUF_HALF_TBL, wptr, &qword);
118
119		if ((wptr - rptr) < 64 && wptr < rows - 1)
120			continue;
121
122		EFSYS_SPIN(1);
123
124		for (; rptr <= wptr; ++rptr) {
125			func(rptr, B_FALSE, &qword);
126			EFX_BAR_TBL_READQ(enp, FR_AZ_BUF_HALF_TBL, rptr,
127			    &verify);
128
129			if (!EFX_QWORD_IS_EQUAL(verify, qword)) {
130				rc = EFAULT;
131				goto fail1;
132			}
133		}
134	}
135
136	/* And do the same negated */
137	for (wptr = 0, rptr = 0; wptr < rows; ++wptr) {
138		func(wptr, B_TRUE, &qword);
139		EFX_BAR_TBL_WRITEQ(enp, FR_AZ_BUF_HALF_TBL, wptr, &qword);
140
141		if ((wptr - rptr) < 64 && wptr < rows - 1)
142			continue;
143
144		EFSYS_SPIN(1);
145
146		for (; rptr <= wptr; ++rptr) {
147			func(rptr, B_TRUE, &qword);
148			EFX_BAR_TBL_READQ(enp, FR_AZ_BUF_HALF_TBL, rptr,
149			    &verify);
150
151			if (!EFX_QWORD_IS_EQUAL(verify, qword)) {
152				rc = EFAULT;
153				goto fail2;
154			}
155		}
156	}
157
158	/* Restore back to FULL buffer table mode */
159	EFX_POPULATE_OWORD_1(oword, FRF_AZ_BUF_TBL_MODE, 1);
160	EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_CFG_REG, &oword);
161
162	/*
163	 * We don't need to reconfigure SRAM again because the API
164	 * requires efx_nic_fini() to be called after an sram test.
165	 */
166	return (0);
167
168fail2:
169	EFSYS_PROBE(fail2);
170fail1:
171	EFSYS_PROBE1(fail1, int, rc);
172
173	/* Restore back to FULL buffer table mode */
174	EFX_POPULATE_OWORD_1(oword, FRF_AZ_BUF_TBL_MODE, 1);
175	EFX_BAR_WRITEO(enp, FR_AZ_BUF_TBL_CFG_REG, &oword);
176
177	return (rc);
178}
179
180#endif	/* EFSYS_OPT_DIAG */
181
182#endif	/* EFSYS_OPT_SIENA */
183