siena_mac.c revision 284555
1/*- 2 * Copyright (c) 2009-2015 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * The views and conclusions contained in the software and documentation are 27 * those of the authors and should not be interpreted as representing official 28 * policies, either expressed or implied, of the FreeBSD Project. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: stable/10/sys/dev/sfxge/common/siena_mac.c 284555 2015-06-18 15:46:39Z arybchik $"); 33 34#include "efsys.h" 35#include "efx.h" 36#include "efx_impl.h" 37 38#if EFSYS_OPT_SIENA 39 40 __checkReturn int 41siena_mac_poll( 42 __in efx_nic_t *enp, 43 __out efx_link_mode_t *link_modep) 44{ 45 efx_port_t *epp = &(enp->en_port); 46 siena_link_state_t sls; 47 int rc; 48 49 if ((rc = siena_phy_get_link(enp, &sls)) != 0) 50 goto fail1; 51 52 epp->ep_adv_cap_mask = sls.sls_adv_cap_mask; 53 epp->ep_fcntl = sls.sls_fcntl; 54 55 *link_modep = sls.sls_link_mode; 56 57 return (0); 58 59fail1: 60 EFSYS_PROBE1(fail1, int, rc); 61 62 *link_modep = EFX_LINK_UNKNOWN; 63 64 return (rc); 65} 66 67 __checkReturn int 68siena_mac_up( 69 __in efx_nic_t *enp, 70 __out boolean_t *mac_upp) 71{ 72 siena_link_state_t sls; 73 int rc; 74 75 /* 76 * Because Siena doesn't *require* polling, we can't rely on 77 * siena_mac_poll() being executed to populate epp->ep_mac_up. 78 */ 79 if ((rc = siena_phy_get_link(enp, &sls)) != 0) 80 goto fail1; 81 82 *mac_upp = sls.sls_mac_up; 83 84 return (0); 85 86fail1: 87 EFSYS_PROBE1(fail1, int, rc); 88 89 return (rc); 90} 91 92 __checkReturn int 93siena_mac_reconfigure( 94 __in efx_nic_t *enp) 95{ 96 efx_port_t *epp = &(enp->en_port); 97 efx_oword_t multicast_hash[2]; 98 efx_mcdi_req_t req; 99 uint8_t payload[MAX(MAX(MC_CMD_SET_MAC_IN_LEN, 100 MC_CMD_SET_MAC_OUT_LEN), 101 MAX(MC_CMD_SET_MCAST_HASH_IN_LEN, 102 MC_CMD_SET_MCAST_HASH_OUT_LEN))]; 103 unsigned int fcntl; 104 int rc; 105 106 (void) memset(payload, 0, sizeof (payload)); 107 req.emr_cmd = MC_CMD_SET_MAC; 108 req.emr_in_buf = payload; 109 req.emr_in_length = MC_CMD_SET_MAC_IN_LEN; 110 req.emr_out_buf = payload; 111 req.emr_out_length = MC_CMD_SET_MAC_OUT_LEN; 112 113 MCDI_IN_SET_DWORD(req, SET_MAC_IN_MTU, epp->ep_mac_pdu); 114 MCDI_IN_SET_DWORD(req, SET_MAC_IN_DRAIN, epp->ep_mac_drain ? 1 : 0); 115 EFX_MAC_ADDR_COPY(MCDI_IN2(req, uint8_t, SET_MAC_IN_ADDR), 116 epp->ep_mac_addr); 117 MCDI_IN_POPULATE_DWORD_2(req, SET_MAC_IN_REJECT, 118 SET_MAC_IN_REJECT_UNCST, !epp->ep_all_unicst, 119 SET_MAC_IN_REJECT_BRDCST, !epp->ep_brdcst); 120 121 if (epp->ep_fcntl_autoneg) 122 /* efx_fcntl_set() has already set the phy capabilities */ 123 fcntl = MC_CMD_FCNTL_AUTO; 124 else if (epp->ep_fcntl & EFX_FCNTL_RESPOND) 125 fcntl = (epp->ep_fcntl & EFX_FCNTL_GENERATE) 126 ? MC_CMD_FCNTL_BIDIR 127 : MC_CMD_FCNTL_RESPOND; 128 else 129 fcntl = MC_CMD_FCNTL_OFF; 130 131 MCDI_IN_SET_DWORD(req, SET_MAC_IN_FCNTL, fcntl); 132 133 efx_mcdi_execute(enp, &req); 134 135 if (req.emr_rc != 0) { 136 rc = req.emr_rc; 137 goto fail1; 138 } 139 140 /* Push multicast hash */ 141 142 if (epp->ep_all_mulcst) { 143 /* A hash matching all multicast is all 1s */ 144 EFX_SET_OWORD(multicast_hash[0]); 145 EFX_SET_OWORD(multicast_hash[1]); 146 } else if (epp->ep_mulcst) { 147 /* Use the hash set by the multicast list */ 148 multicast_hash[0] = epp->ep_multicst_hash[0]; 149 multicast_hash[1] = epp->ep_multicst_hash[1]; 150 } else { 151 /* A hash matching no traffic is simply 0 */ 152 EFX_ZERO_OWORD(multicast_hash[0]); 153 EFX_ZERO_OWORD(multicast_hash[1]); 154 } 155 156 /* 157 * Broadcast packets go through the multicast hash filter. 158 * The IEEE 802.3 CRC32 of the broadcast address is 0xbe2612ff 159 * so we always add bit 0xff to the mask (bit 0x7f in the 160 * second octword). 161 */ 162 if (epp->ep_brdcst) 163 EFX_SET_OWORD_BIT(multicast_hash[1], 0x7f); 164 165 (void) memset(payload, 0, sizeof (payload)); 166 req.emr_cmd = MC_CMD_SET_MCAST_HASH; 167 req.emr_in_buf = payload; 168 req.emr_in_length = MC_CMD_SET_MCAST_HASH_IN_LEN; 169 req.emr_out_buf = payload; 170 req.emr_out_length = MC_CMD_SET_MCAST_HASH_OUT_LEN; 171 172 memcpy(MCDI_IN2(req, uint8_t, SET_MCAST_HASH_IN_HASH0), 173 multicast_hash, sizeof (multicast_hash)); 174 175 efx_mcdi_execute(enp, &req); 176 177 if (req.emr_rc != 0) { 178 rc = req.emr_rc; 179 goto fail2; 180 } 181 182 return (0); 183 184fail2: 185 EFSYS_PROBE(fail2); 186fail1: 187 EFSYS_PROBE1(fail1, int, rc); 188 189 return (rc); 190} 191 192#if EFSYS_OPT_LOOPBACK 193 194 __checkReturn int 195siena_mac_loopback_set( 196 __in efx_nic_t *enp, 197 __in efx_link_mode_t link_mode, 198 __in efx_loopback_type_t loopback_type) 199{ 200 efx_port_t *epp = &(enp->en_port); 201 efx_phy_ops_t *epop = epp->ep_epop; 202 efx_loopback_type_t old_loopback_type; 203 efx_link_mode_t old_loopback_link_mode; 204 int rc; 205 206 /* The PHY object handles this on Siena */ 207 old_loopback_type = epp->ep_loopback_type; 208 old_loopback_link_mode = epp->ep_loopback_link_mode; 209 epp->ep_loopback_type = loopback_type; 210 epp->ep_loopback_link_mode = link_mode; 211 212 if ((rc = epop->epo_reconfigure(enp)) != 0) 213 goto fail1; 214 215 return (0); 216 217fail1: 218 EFSYS_PROBE(fail2); 219 220 epp->ep_loopback_type = old_loopback_type; 221 epp->ep_loopback_link_mode = old_loopback_link_mode; 222 223 return (rc); 224} 225 226#endif /* EFSYS_OPT_LOOPBACK */ 227 228#if EFSYS_OPT_MAC_STATS 229 230#define SIENA_MAC_STAT_READ(_esmp, _field, _eqp) \ 231 EFSYS_MEM_READQ((_esmp), (_field) * sizeof (efx_qword_t), _eqp) 232 233 __checkReturn int 234siena_mac_stats_update( 235 __in efx_nic_t *enp, 236 __in efsys_mem_t *esmp, 237 __out_ecount(EFX_MAC_NSTATS) efsys_stat_t *stat, 238 __out_opt uint32_t *generationp) 239{ 240 efx_qword_t value; 241 efx_qword_t generation_start; 242 efx_qword_t generation_end; 243 244 _NOTE(ARGUNUSED(enp)) 245 246 /* Read END first so we don't race with the MC */ 247 EFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFX_MAC_STATS_SIZE); 248 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_GENERATION_END, 249 &generation_end); 250 EFSYS_MEM_READ_BARRIER(); 251 252 /* TX */ 253 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_PKTS, &value); 254 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_PKTS]), &value); 255 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_CONTROL_PKTS, &value); 256 EFSYS_STAT_SUBR_QWORD(&(stat[EFX_MAC_TX_PKTS]), &value); 257 258 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_PAUSE_PKTS, &value); 259 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_PAUSE_PKTS]), &value); 260 261 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_UNICAST_PKTS, &value); 262 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_UNICST_PKTS]), &value); 263 264 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_MULTICAST_PKTS, &value); 265 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_MULTICST_PKTS]), &value); 266 267 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BROADCAST_PKTS, &value); 268 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_BRDCST_PKTS]), &value); 269 270 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BYTES, &value); 271 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_OCTETS]), &value); 272 273 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_LT64_PKTS, &value); 274 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_LE_64_PKTS]), &value); 275 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_64_PKTS, &value); 276 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_TX_LE_64_PKTS]), &value); 277 278 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_65_TO_127_PKTS, &value); 279 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_65_TO_127_PKTS]), &value); 280 281 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_128_TO_255_PKTS, &value); 282 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_128_TO_255_PKTS]), &value); 283 284 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_256_TO_511_PKTS, &value); 285 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_256_TO_511_PKTS]), &value); 286 287 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_512_TO_1023_PKTS, &value); 288 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_512_TO_1023_PKTS]), &value); 289 290 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_1024_TO_15XX_PKTS, &value); 291 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_1024_TO_15XX_PKTS]), &value); 292 293 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS, &value); 294 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_GE_15XX_PKTS]), &value); 295 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_GTJUMBO_PKTS, &value); 296 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_TX_GE_15XX_PKTS]), &value); 297 298 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_BAD_FCS_PKTS, &value); 299 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_ERRORS]), &value); 300 301 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS, &value); 302 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_SGL_COL_PKTS]), &value); 303 304 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS, 305 &value); 306 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_MULT_COL_PKTS]), &value); 307 308 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS, 309 &value); 310 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_EX_COL_PKTS]), &value); 311 312 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_LATE_COLLISION_PKTS, &value); 313 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_LATE_COL_PKTS]), &value); 314 315 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_DEFERRED_PKTS, &value); 316 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_DEF_PKTS]), &value); 317 318 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS, 319 &value); 320 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_TX_EX_DEF_PKTS]), &value); 321 322 /* RX */ 323 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BYTES, &value); 324 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_OCTETS]), &value); 325 326 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_PKTS, &value); 327 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_PKTS]), &value); 328 329 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_UNICAST_PKTS, &value); 330 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_UNICST_PKTS]), &value); 331 332 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_MULTICAST_PKTS, &value); 333 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_MULTICST_PKTS]), &value); 334 335 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BROADCAST_PKTS, &value); 336 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_BRDCST_PKTS]), &value); 337 338 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_PAUSE_PKTS, &value); 339 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_PAUSE_PKTS]), &value); 340 341 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_UNDERSIZE_PKTS, &value); 342 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_LE_64_PKTS]), &value); 343 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_64_PKTS, &value); 344 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_RX_LE_64_PKTS]), &value); 345 346 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_65_TO_127_PKTS, &value); 347 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_65_TO_127_PKTS]), &value); 348 349 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_128_TO_255_PKTS, &value); 350 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_128_TO_255_PKTS]), &value); 351 352 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_256_TO_511_PKTS, &value); 353 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_256_TO_511_PKTS]), &value); 354 355 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_512_TO_1023_PKTS, &value); 356 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_512_TO_1023_PKTS]), &value); 357 358 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_1024_TO_15XX_PKTS, &value); 359 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_1024_TO_15XX_PKTS]), &value); 360 361 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS, &value); 362 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_GE_15XX_PKTS]), &value); 363 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_GTJUMBO_PKTS, &value); 364 EFSYS_STAT_INCR_QWORD(&(stat[EFX_MAC_RX_GE_15XX_PKTS]), &value); 365 366 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_BAD_FCS_PKTS, &value); 367 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_FCS_ERRORS]), &value); 368 369 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_OVERFLOW_PKTS, &value); 370 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_DROP_EVENTS]), &value); 371 372 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_FALSE_CARRIER_PKTS, &value); 373 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_FALSE_CARRIER_ERRORS]), &value); 374 375 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS, &value); 376 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_SYMBOL_ERRORS]), &value); 377 378 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_ALIGN_ERROR_PKTS, &value); 379 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_ALIGN_ERRORS]), &value); 380 381 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS, &value); 382 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_INTERNAL_ERRORS]), &value); 383 384 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_JABBER_PKTS, &value); 385 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_JABBER_PKTS]), &value); 386 387 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES01_CHAR_ERR, &value); 388 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE0_CHAR_ERR]), 389 &(value.eq_dword[0])); 390 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE1_CHAR_ERR]), 391 &(value.eq_dword[1])); 392 393 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES23_CHAR_ERR, &value); 394 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE2_CHAR_ERR]), 395 &(value.eq_dword[0])); 396 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE3_CHAR_ERR]), 397 &(value.eq_dword[1])); 398 399 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES01_DISP_ERR, &value); 400 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE0_DISP_ERR]), 401 &(value.eq_dword[0])); 402 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE1_DISP_ERR]), 403 &(value.eq_dword[1])); 404 405 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_LANES23_DISP_ERR, &value); 406 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE2_DISP_ERR]), 407 &(value.eq_dword[0])); 408 EFSYS_STAT_SET_DWORD(&(stat[EFX_MAC_RX_LANE3_DISP_ERR]), 409 &(value.eq_dword[1])); 410 411 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_MATCH_FAULT, &value); 412 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_MATCH_FAULT]), &value); 413 414 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_RX_NODESC_DROPS, &value); 415 EFSYS_STAT_SET_QWORD(&(stat[EFX_MAC_RX_NODESC_DROP_CNT]), &value); 416 417 EFSYS_DMA_SYNC_FOR_KERNEL(esmp, 0, EFX_MAC_STATS_SIZE); 418 EFSYS_MEM_READ_BARRIER(); 419 SIENA_MAC_STAT_READ(esmp, MC_CMD_MAC_GENERATION_START, 420 &generation_start); 421 422 /* Check that we didn't read the stats in the middle of a DMA */ 423 /* Not a good enough check ? */ 424 if (memcmp(&generation_start, &generation_end, 425 sizeof (generation_start))) 426 return (EAGAIN); 427 428 if (generationp) 429 *generationp = EFX_QWORD_FIELD(generation_start, EFX_DWORD_0); 430 431 return (0); 432} 433 434#endif /* EFSYS_OPT_MAC_STATS */ 435 436#endif /* EFSYS_OPT_SIENA */ 437