hunt_impl.h revision 301344 
1/*-
2 * Copyright (c) 2012-2015 Solarflare Communications Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 *    this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 *    this list of conditions and the following disclaimer in the documentation
12 *    and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
29 *
30 * $FreeBSD: stable/10/sys/dev/sfxge/common/hunt_impl.h 301344 2016-06-04 15:24:11Z arybchik $
31 */
32
33#ifndef _SYS_HUNT_IMPL_H
34#define	_SYS_HUNT_IMPL_H
35
36#include "efx.h"
37#include "efx_regs.h"
38#include "efx_regs_ef10.h"
39#include "efx_mcdi.h"
40
41#ifdef	__cplusplus
42extern "C" {
43#endif
44
45/*
46 * FIXME: This is just a power of 2 which fits in an MCDI v1 message, and could
47 * possibly be increased, or the write size reported by newer firmware used
48 * instead.
49 */
50#define	EF10_NVRAM_CHUNK 0x80
51
52/* Alignment requirement for value written to RX WPTR:
53 *  the WPTR must be aligned to an 8 descriptor boundary
54 */
55#define	EF10_RX_WPTR_ALIGN 8
56
57/*
58 * Max byte offset into the packet the TCP header must start for the hardware
59 * to be able to parse the packet correctly.
60 * FIXME: Move to ef10_impl.h when it is included in all driver builds.
61 */
62#define	EF10_TCP_HEADER_OFFSET_LIMIT	208
63
64/* Invalid RSS context handle */
65#define	EF10_RSS_CONTEXT_INVALID	(0xffffffff)
66
67
68/* EV */
69
70	__checkReturn	efx_rc_t
71ef10_ev_init(
72	__in		efx_nic_t *enp);
73
74			void
75ef10_ev_fini(
76	__in		efx_nic_t *enp);
77
78	__checkReturn	efx_rc_t
79ef10_ev_qcreate(
80	__in		efx_nic_t *enp,
81	__in		unsigned int index,
82	__in		efsys_mem_t *esmp,
83	__in		size_t n,
84	__in		uint32_t id,
85	__in		efx_evq_t *eep);
86
87			void
88ef10_ev_qdestroy(
89	__in		efx_evq_t *eep);
90
91	__checkReturn	efx_rc_t
92ef10_ev_qprime(
93	__in		efx_evq_t *eep,
94	__in		unsigned int count);
95
96			void
97ef10_ev_qpost(
98	__in	efx_evq_t *eep,
99	__in	uint16_t data);
100
101	__checkReturn	efx_rc_t
102ef10_ev_qmoderate(
103	__in		efx_evq_t *eep,
104	__in		unsigned int us);
105
106#if EFSYS_OPT_QSTATS
107			void
108ef10_ev_qstats_update(
109	__in				efx_evq_t *eep,
110	__inout_ecount(EV_NQSTATS)	efsys_stat_t *stat);
111#endif /* EFSYS_OPT_QSTATS */
112
113		void
114ef10_ev_rxlabel_init(
115	__in		efx_evq_t *eep,
116	__in		efx_rxq_t *erp,
117	__in		unsigned int label);
118
119		void
120ef10_ev_rxlabel_fini(
121	__in		efx_evq_t *eep,
122	__in		unsigned int label);
123
124/* INTR */
125
126	__checkReturn	efx_rc_t
127ef10_intr_init(
128	__in		efx_nic_t *enp,
129	__in		efx_intr_type_t type,
130	__in		efsys_mem_t *esmp);
131
132			void
133ef10_intr_enable(
134	__in		efx_nic_t *enp);
135
136			void
137ef10_intr_disable(
138	__in		efx_nic_t *enp);
139
140			void
141ef10_intr_disable_unlocked(
142	__in		efx_nic_t *enp);
143
144	__checkReturn	efx_rc_t
145ef10_intr_trigger(
146	__in		efx_nic_t *enp,
147	__in		unsigned int level);
148
149			void
150ef10_intr_status_line(
151	__in		efx_nic_t *enp,
152	__out		boolean_t *fatalp,
153	__out		uint32_t *qmaskp);
154
155			void
156ef10_intr_status_message(
157	__in		efx_nic_t *enp,
158	__in		unsigned int message,
159	__out		boolean_t *fatalp);
160
161			void
162ef10_intr_fatal(
163	__in		efx_nic_t *enp);
164			void
165ef10_intr_fini(
166	__in		efx_nic_t *enp);
167
168/* NIC */
169
170extern	__checkReturn	efx_rc_t
171ef10_nic_probe(
172	__in		efx_nic_t *enp);
173
174extern	__checkReturn	efx_rc_t
175hunt_board_cfg(
176	__in		efx_nic_t *enp);
177
178extern	__checkReturn	efx_rc_t
179ef10_nic_set_drv_limits(
180	__inout		efx_nic_t *enp,
181	__in		efx_drv_limits_t *edlp);
182
183extern	__checkReturn	efx_rc_t
184ef10_nic_get_vi_pool(
185	__in		efx_nic_t *enp,
186	__out		uint32_t *vi_countp);
187
188extern	__checkReturn	efx_rc_t
189ef10_nic_get_bar_region(
190	__in		efx_nic_t *enp,
191	__in		efx_nic_region_t region,
192	__out		uint32_t *offsetp,
193	__out		size_t *sizep);
194
195extern	__checkReturn	efx_rc_t
196ef10_nic_reset(
197	__in		efx_nic_t *enp);
198
199extern	__checkReturn	efx_rc_t
200ef10_nic_init(
201	__in		efx_nic_t *enp);
202
203#if EFSYS_OPT_DIAG
204
205extern	__checkReturn	efx_rc_t
206ef10_nic_register_test(
207	__in		efx_nic_t *enp);
208
209#endif	/* EFSYS_OPT_DIAG */
210
211extern			void
212ef10_nic_fini(
213	__in		efx_nic_t *enp);
214
215extern			void
216ef10_nic_unprobe(
217	__in		efx_nic_t *enp);
218
219
220/* MAC */
221
222extern	__checkReturn	efx_rc_t
223ef10_mac_poll(
224	__in		efx_nic_t *enp,
225	__out		efx_link_mode_t *link_modep);
226
227extern	__checkReturn	efx_rc_t
228ef10_mac_up(
229	__in		efx_nic_t *enp,
230	__out		boolean_t *mac_upp);
231
232extern	__checkReturn	efx_rc_t
233ef10_mac_addr_set(
234	__in	efx_nic_t *enp);
235
236extern	__checkReturn	efx_rc_t
237ef10_mac_pdu_set(
238	__in	efx_nic_t *enp);
239
240extern	__checkReturn	efx_rc_t
241ef10_mac_reconfigure(
242	__in	efx_nic_t *enp);
243
244extern	__checkReturn	efx_rc_t
245ef10_mac_multicast_list_set(
246	__in				efx_nic_t *enp);
247
248extern	__checkReturn	efx_rc_t
249ef10_mac_filter_default_rxq_set(
250	__in		efx_nic_t *enp,
251	__in		efx_rxq_t *erp,
252	__in		boolean_t using_rss);
253
254extern			void
255ef10_mac_filter_default_rxq_clear(
256	__in		efx_nic_t *enp);
257
258#if EFSYS_OPT_LOOPBACK
259
260extern	__checkReturn	efx_rc_t
261ef10_mac_loopback_set(
262	__in		efx_nic_t *enp,
263	__in		efx_link_mode_t link_mode,
264	__in		efx_loopback_type_t loopback_type);
265
266#endif	/* EFSYS_OPT_LOOPBACK */
267
268#if EFSYS_OPT_MAC_STATS
269
270extern	__checkReturn			efx_rc_t
271ef10_mac_stats_update(
272	__in				efx_nic_t *enp,
273	__in				efsys_mem_t *esmp,
274	__inout_ecount(EFX_MAC_NSTATS)	efsys_stat_t *stat,
275	__inout_opt			uint32_t *generationp);
276
277#endif	/* EFSYS_OPT_MAC_STATS */
278
279
280/* MCDI */
281
282#if EFSYS_OPT_MCDI
283
284extern	__checkReturn	efx_rc_t
285ef10_mcdi_init(
286	__in		efx_nic_t *enp,
287	__in		const efx_mcdi_transport_t *mtp);
288
289extern			void
290ef10_mcdi_fini(
291	__in		efx_nic_t *enp);
292
293extern			void
294ef10_mcdi_send_request(
295	__in		efx_nic_t *enp,
296	__in		void *hdrp,
297	__in		size_t hdr_len,
298	__in		void *sdup,
299	__in		size_t sdu_len);
300
301extern	__checkReturn	boolean_t
302ef10_mcdi_poll_response(
303	__in		efx_nic_t *enp);
304
305extern			void
306ef10_mcdi_read_response(
307	__in			efx_nic_t *enp,
308	__out_bcount(length)	void *bufferp,
309	__in			size_t offset,
310	__in			size_t length);
311
312extern			efx_rc_t
313ef10_mcdi_poll_reboot(
314	__in		efx_nic_t *enp);
315
316extern	__checkReturn	efx_rc_t
317ef10_mcdi_feature_supported(
318	__in		efx_nic_t *enp,
319	__in		efx_mcdi_feature_id_t id,
320	__out		boolean_t *supportedp);
321
322#endif /* EFSYS_OPT_MCDI */
323
324/* NVRAM */
325
326#if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
327
328extern	__checkReturn		efx_rc_t
329ef10_nvram_buf_read_tlv(
330	__in				efx_nic_t *enp,
331	__in_bcount(max_seg_size)	caddr_t seg_data,
332	__in				size_t max_seg_size,
333	__in				uint32_t tag,
334	__deref_out_bcount_opt(*sizep)	caddr_t *datap,
335	__out				size_t *sizep);
336
337extern	__checkReturn		efx_rc_t
338ef10_nvram_buf_write_tlv(
339	__inout_bcount(partn_size)	caddr_t partn_data,
340	__in				size_t partn_size,
341	__in				uint32_t tag,
342	__in_bcount(tag_size)		caddr_t tag_data,
343	__in				size_t tag_size,
344	__out				size_t *total_lengthp);
345
346extern	__checkReturn		efx_rc_t
347ef10_nvram_partn_read_tlv(
348	__in				efx_nic_t *enp,
349	__in				uint32_t partn,
350	__in				uint32_t tag,
351	__deref_out_bcount_opt(*sizep)	caddr_t *datap,
352	__out				size_t *sizep);
353
354extern	__checkReturn		efx_rc_t
355ef10_nvram_partn_write_tlv(
356	__in		   	efx_nic_t *enp,
357	__in		    	uint32_t partn,
358	__in		     	uint32_t tag,
359	__in_bcount(size)	caddr_t data,
360	__in			size_t size);
361
362extern	__checkReturn		efx_rc_t
363ef10_nvram_partn_write_segment_tlv(
364	__in			efx_nic_t *enp,
365	__in			uint32_t partn,
366	__in			uint32_t tag,
367	__in_bcount(size)	caddr_t data,
368	__in			size_t size,
369	__in			boolean_t all_segments);
370
371extern	__checkReturn		efx_rc_t
372ef10_nvram_partn_lock(
373	__in			efx_nic_t *enp,
374	__in			uint32_t partn);
375
376extern				void
377ef10_nvram_partn_unlock(
378	__in			efx_nic_t *enp,
379	__in			uint32_t partn);
380
381#endif /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
382
383#if EFSYS_OPT_NVRAM
384
385#if EFSYS_OPT_DIAG
386
387extern	__checkReturn		efx_rc_t
388ef10_nvram_test(
389	__in			efx_nic_t *enp);
390
391#endif	/* EFSYS_OPT_DIAG */
392
393extern	__checkReturn		efx_rc_t
394ef10_nvram_type_to_partn(
395	__in			efx_nic_t *enp,
396	__in			efx_nvram_type_t type,
397	__out			uint32_t *partnp);
398
399extern	__checkReturn		efx_rc_t
400ef10_nvram_partn_size(
401	__in			efx_nic_t *enp,
402	__in			uint32_t partn,
403	__out			size_t *sizep);
404
405extern	__checkReturn		efx_rc_t
406ef10_nvram_partn_rw_start(
407	__in			efx_nic_t *enp,
408	__in			uint32_t partn,
409	__out			size_t *chunk_sizep);
410
411extern	__checkReturn		efx_rc_t
412ef10_nvram_partn_read_mode(
413	__in			efx_nic_t *enp,
414	__in			uint32_t partn,
415	__in			unsigned int offset,
416	__out_bcount(size)	caddr_t data,
417	__in			size_t size,
418	__in			uint32_t mode);
419
420extern	__checkReturn		efx_rc_t
421ef10_nvram_partn_read(
422	__in			efx_nic_t *enp,
423	__in			uint32_t partn,
424	__in			unsigned int offset,
425	__out_bcount(size)	caddr_t data,
426	__in			size_t size);
427
428extern	__checkReturn		efx_rc_t
429ef10_nvram_partn_erase(
430	__in			efx_nic_t *enp,
431	__in			uint32_t partn,
432	__in			unsigned int offset,
433	__in			size_t size);
434
435extern	__checkReturn		efx_rc_t
436ef10_nvram_partn_write(
437	__in			efx_nic_t *enp,
438	__in			uint32_t partn,
439	__in			unsigned int offset,
440	__out_bcount(size)	caddr_t data,
441	__in			size_t size);
442
443extern				void
444ef10_nvram_partn_rw_finish(
445	__in			efx_nic_t *enp,
446	__in			uint32_t partn);
447
448extern	__checkReturn		efx_rc_t
449ef10_nvram_partn_get_version(
450	__in			efx_nic_t *enp,
451	__in			uint32_t partn,
452	__out			uint32_t *subtypep,
453	__out_ecount(4)		uint16_t version[4]);
454
455extern	__checkReturn		efx_rc_t
456ef10_nvram_partn_set_version(
457	__in			efx_nic_t *enp,
458	__in			uint32_t partn,
459	__in_ecount(4)		uint16_t version[4]);
460
461extern	__checkReturn		efx_rc_t
462ef10_nvram_buffer_validate(
463	__in			efx_nic_t *enp,
464	__in			uint32_t partn,
465	__in_bcount(buffer_size)
466				caddr_t bufferp,
467	__in			size_t buffer_size);
468
469extern	__checkReturn		efx_rc_t
470ef10_nvram_buffer_create(
471	__in			efx_nic_t *enp,
472	__in			uint16_t partn_type,
473	__in_bcount(buffer_size)
474				caddr_t bufferp,
475	__in			size_t buffer_size);
476
477extern	__checkReturn		efx_rc_t
478ef10_nvram_buffer_find_item_start(
479	__in_bcount(buffer_size)
480				caddr_t bufferp,
481	__in			size_t buffer_size,
482	__out			uint32_t *startp
483	);
484
485extern	__checkReturn		efx_rc_t
486ef10_nvram_buffer_find_end(
487	__in_bcount(buffer_size)
488				caddr_t bufferp,
489	__in			size_t buffer_size,
490	__in			uint32_t offset,
491	__out			uint32_t *endp
492	);
493
494extern	__checkReturn	__success(return != B_FALSE)	boolean_t
495ef10_nvram_buffer_find_item(
496	__in_bcount(buffer_size)
497				caddr_t bufferp,
498	__in			size_t buffer_size,
499	__in			uint32_t offset,
500	__out			uint32_t *startp,
501	__out			uint32_t *lengthp
502	);
503
504extern	__checkReturn		efx_rc_t
505ef10_nvram_buffer_get_item(
506	__in_bcount(buffer_size)
507				caddr_t bufferp,
508	__in			size_t buffer_size,
509	__in			uint32_t offset,
510	__in			uint32_t length,
511	__out_bcount_part(item_max_size, *lengthp)
512				caddr_t itemp,
513	__in			size_t item_max_size,
514	__out			uint32_t *lengthp
515	);
516
517extern	__checkReturn		efx_rc_t
518ef10_nvram_buffer_insert_item(
519	__in_bcount(buffer_size)
520				caddr_t bufferp,
521	__in			size_t buffer_size,
522	__in			uint32_t offset,
523	__in_bcount(length)	caddr_t keyp,
524	__in			uint32_t length,
525	__out			uint32_t *lengthp
526	);
527
528extern	__checkReturn		efx_rc_t
529ef10_nvram_buffer_delete_item(
530	__in_bcount(buffer_size)
531				caddr_t bufferp,
532	__in			size_t buffer_size,
533	__in			uint32_t offset,
534	__in			uint32_t length,
535	__in			uint32_t end
536	);
537
538extern	__checkReturn		efx_rc_t
539ef10_nvram_buffer_finish(
540	__in_bcount(buffer_size)
541				caddr_t bufferp,
542	__in			size_t buffer_size
543	);
544
545#endif	/* EFSYS_OPT_NVRAM */
546
547
548/* PHY */
549
550typedef struct ef10_link_state_s {
551	uint32_t		els_adv_cap_mask;
552	uint32_t		els_lp_cap_mask;
553	unsigned int		els_fcntl;
554	efx_link_mode_t		els_link_mode;
555#if EFSYS_OPT_LOOPBACK
556	efx_loopback_type_t	els_loopback;
557#endif
558	boolean_t		els_mac_up;
559} ef10_link_state_t;
560
561extern			void
562ef10_phy_link_ev(
563	__in		efx_nic_t *enp,
564	__in		efx_qword_t *eqp,
565	__out		efx_link_mode_t *link_modep);
566
567extern	__checkReturn	efx_rc_t
568ef10_phy_get_link(
569	__in		efx_nic_t *enp,
570	__out		ef10_link_state_t *elsp);
571
572extern	__checkReturn	efx_rc_t
573ef10_phy_power(
574	__in		efx_nic_t *enp,
575	__in		boolean_t on);
576
577extern	__checkReturn	efx_rc_t
578ef10_phy_reconfigure(
579	__in		efx_nic_t *enp);
580
581extern	__checkReturn	efx_rc_t
582ef10_phy_verify(
583	__in		efx_nic_t *enp);
584
585extern	__checkReturn	efx_rc_t
586ef10_phy_oui_get(
587	__in		efx_nic_t *enp,
588	__out		uint32_t *ouip);
589
590#if EFSYS_OPT_PHY_STATS
591
592extern	__checkReturn			efx_rc_t
593ef10_phy_stats_update(
594	__in				efx_nic_t *enp,
595	__in				efsys_mem_t *esmp,
596	__inout_ecount(EFX_PHY_NSTATS)	uint32_t *stat);
597
598#endif	/* EFSYS_OPT_PHY_STATS */
599
600#if EFSYS_OPT_PHY_PROPS
601
602#if EFSYS_OPT_NAMES
603
604extern		const char *
605ef10_phy_prop_name(
606	__in	efx_nic_t *enp,
607	__in	unsigned int id);
608
609#endif	/* EFSYS_OPT_NAMES */
610
611extern	__checkReturn	efx_rc_t
612ef10_phy_prop_get(
613	__in		efx_nic_t *enp,
614	__in		unsigned int id,
615	__in		uint32_t flags,
616	__out		uint32_t *valp);
617
618extern	__checkReturn	efx_rc_t
619ef10_phy_prop_set(
620	__in		efx_nic_t *enp,
621	__in		unsigned int id,
622	__in		uint32_t val);
623
624#endif	/* EFSYS_OPT_PHY_PROPS */
625
626#if EFSYS_OPT_BIST
627
628extern	__checkReturn		efx_rc_t
629hunt_bist_enable_offline(
630	__in			efx_nic_t *enp);
631
632extern	__checkReturn		efx_rc_t
633hunt_bist_start(
634	__in			efx_nic_t *enp,
635	__in			efx_bist_type_t type);
636
637extern	__checkReturn		efx_rc_t
638hunt_bist_poll(
639	__in			efx_nic_t *enp,
640	__in			efx_bist_type_t type,
641	__out			efx_bist_result_t *resultp,
642	__out_opt __drv_when(count > 0, __notnull)
643	uint32_t 	*value_maskp,
644	__out_ecount_opt(count)	__drv_when(count > 0, __notnull)
645	unsigned long	*valuesp,
646	__in			size_t count);
647
648extern				void
649hunt_bist_stop(
650	__in			efx_nic_t *enp,
651	__in			efx_bist_type_t type);
652
653#endif	/* EFSYS_OPT_BIST */
654
655
656/* TX */
657
658extern	__checkReturn	efx_rc_t
659ef10_tx_init(
660	__in		efx_nic_t *enp);
661
662extern			void
663ef10_tx_fini(
664	__in		efx_nic_t *enp);
665
666extern	__checkReturn	efx_rc_t
667ef10_tx_qcreate(
668	__in		efx_nic_t *enp,
669	__in		unsigned int index,
670	__in		unsigned int label,
671	__in		efsys_mem_t *esmp,
672	__in		size_t n,
673	__in		uint32_t id,
674	__in		uint16_t flags,
675	__in		efx_evq_t *eep,
676	__in		efx_txq_t *etp,
677	__out		unsigned int *addedp);
678
679extern		void
680ef10_tx_qdestroy(
681	__in		efx_txq_t *etp);
682
683extern	__checkReturn	efx_rc_t
684ef10_tx_qpost(
685	__in		efx_txq_t *etp,
686	__in_ecount(n)	efx_buffer_t *eb,
687	__in		unsigned int n,
688	__in		unsigned int completed,
689	__inout		unsigned int *addedp);
690
691extern			void
692ef10_tx_qpush(
693	__in		efx_txq_t *etp,
694	__in		unsigned int added,
695	__in		unsigned int pushed);
696
697extern	__checkReturn	efx_rc_t
698ef10_tx_qpace(
699	__in		efx_txq_t *etp,
700	__in		unsigned int ns);
701
702extern	__checkReturn	efx_rc_t
703ef10_tx_qflush(
704	__in		efx_txq_t *etp);
705
706extern			void
707ef10_tx_qenable(
708	__in		efx_txq_t *etp);
709
710extern	__checkReturn	efx_rc_t
711ef10_tx_qpio_enable(
712	__in		efx_txq_t *etp);
713
714extern			void
715ef10_tx_qpio_disable(
716	__in		efx_txq_t *etp);
717
718extern	__checkReturn	efx_rc_t
719ef10_tx_qpio_write(
720	__in			efx_txq_t *etp,
721	__in_ecount(buf_length)	uint8_t *buffer,
722	__in			size_t buf_length,
723	__in                    size_t pio_buf_offset);
724
725extern	__checkReturn	efx_rc_t
726ef10_tx_qpio_post(
727	__in			efx_txq_t *etp,
728	__in			size_t pkt_length,
729	__in			unsigned int completed,
730	__inout			unsigned int *addedp);
731
732extern	__checkReturn	efx_rc_t
733ef10_tx_qdesc_post(
734	__in		efx_txq_t *etp,
735	__in_ecount(n)	efx_desc_t *ed,
736	__in		unsigned int n,
737	__in		unsigned int completed,
738	__inout		unsigned int *addedp);
739
740extern	void
741ef10_tx_qdesc_dma_create(
742	__in	efx_txq_t *etp,
743	__in	efsys_dma_addr_t addr,
744	__in	size_t size,
745	__in	boolean_t eop,
746	__out	efx_desc_t *edp);
747
748extern	void
749ef10_tx_qdesc_tso_create(
750	__in	efx_txq_t *etp,
751	__in	uint16_t ipv4_id,
752	__in	uint32_t tcp_seq,
753	__in	uint8_t  tcp_flags,
754	__out	efx_desc_t *edp);
755
756extern	void
757ef10_tx_qdesc_tso2_create(
758	__in			efx_txq_t *etp,
759	__in			uint16_t ipv4_id,
760	__in			uint32_t tcp_seq,
761	__in			uint16_t tcp_mss,
762	__out_ecount(count)	efx_desc_t *edp,
763	__in			int count);
764
765extern	void
766ef10_tx_qdesc_vlantci_create(
767	__in	efx_txq_t *etp,
768	__in	uint16_t vlan_tci,
769	__out	efx_desc_t *edp);
770
771
772#if EFSYS_OPT_QSTATS
773
774extern			void
775ef10_tx_qstats_update(
776	__in				efx_txq_t *etp,
777	__inout_ecount(TX_NQSTATS)	efsys_stat_t *stat);
778
779#endif /* EFSYS_OPT_QSTATS */
780
781/* PIO */
782
783/* Missing register definitions */
784#ifndef	ER_DZ_TX_PIOBUF_OFST
785#define	ER_DZ_TX_PIOBUF_OFST 0x00001000
786#endif
787#ifndef	ER_DZ_TX_PIOBUF_STEP
788#define	ER_DZ_TX_PIOBUF_STEP 8192
789#endif
790#ifndef	ER_DZ_TX_PIOBUF_ROWS
791#define	ER_DZ_TX_PIOBUF_ROWS 2048
792#endif
793
794#ifndef	ER_DZ_TX_PIOBUF_SIZE
795#define	ER_DZ_TX_PIOBUF_SIZE 2048
796#endif
797
798#define	HUNT_PIOBUF_NBUFS	(16)
799#define	HUNT_PIOBUF_SIZE	(ER_DZ_TX_PIOBUF_SIZE)
800
801#define	HUNT_MIN_PIO_ALLOC_SIZE	(HUNT_PIOBUF_SIZE / 32)
802
803#define	EF10_LEGACY_PF_PRIVILEGE_MASK					\
804	(MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN			|	\
805	MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK			|	\
806	MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD			|	\
807	MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP			|	\
808	MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS		|	\
809	MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING		|	\
810	MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST			|	\
811	MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST			|	\
812	MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST			|	\
813	MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST		|	\
814	MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS)
815
816#define	EF10_LEGACY_VF_PRIVILEGE_MASK	0
817
818typedef uint32_t	efx_piobuf_handle_t;
819
820#define	EFX_PIOBUF_HANDLE_INVALID	((efx_piobuf_handle_t) -1)
821
822extern	__checkReturn	efx_rc_t
823ef10_nic_pio_alloc(
824	__inout		efx_nic_t *enp,
825	__out		uint32_t *bufnump,
826	__out		efx_piobuf_handle_t *handlep,
827	__out		uint32_t *blknump,
828	__out		uint32_t *offsetp,
829	__out		size_t *sizep);
830
831extern	__checkReturn	efx_rc_t
832ef10_nic_pio_free(
833	__inout		efx_nic_t *enp,
834	__in		uint32_t bufnum,
835	__in		uint32_t blknum);
836
837extern	__checkReturn	efx_rc_t
838ef10_nic_pio_link(
839	__inout		efx_nic_t *enp,
840	__in		uint32_t vi_index,
841	__in		efx_piobuf_handle_t handle);
842
843extern	__checkReturn	efx_rc_t
844ef10_nic_pio_unlink(
845	__inout		efx_nic_t *enp,
846	__in		uint32_t vi_index);
847
848
849/* VPD */
850
851#if EFSYS_OPT_VPD
852
853extern	__checkReturn		efx_rc_t
854ef10_vpd_init(
855	__in			efx_nic_t *enp);
856
857extern	__checkReturn		efx_rc_t
858ef10_vpd_size(
859	__in			efx_nic_t *enp,
860	__out			size_t *sizep);
861
862extern	__checkReturn		efx_rc_t
863ef10_vpd_read(
864	__in			efx_nic_t *enp,
865	__out_bcount(size)	caddr_t data,
866	__in			size_t size);
867
868extern	__checkReturn		efx_rc_t
869ef10_vpd_verify(
870	__in			efx_nic_t *enp,
871	__in_bcount(size)	caddr_t data,
872	__in			size_t size);
873
874extern	__checkReturn		efx_rc_t
875ef10_vpd_reinit(
876	__in			efx_nic_t *enp,
877	__in_bcount(size)	caddr_t data,
878	__in			size_t size);
879
880extern	__checkReturn		efx_rc_t
881ef10_vpd_get(
882	__in			efx_nic_t *enp,
883	__in_bcount(size)	caddr_t data,
884	__in			size_t size,
885	__inout			efx_vpd_value_t *evvp);
886
887extern	__checkReturn		efx_rc_t
888ef10_vpd_set(
889	__in			efx_nic_t *enp,
890	__in_bcount(size)	caddr_t data,
891	__in			size_t size,
892	__in			efx_vpd_value_t *evvp);
893
894extern	__checkReturn		efx_rc_t
895ef10_vpd_next(
896	__in			efx_nic_t *enp,
897	__in_bcount(size)	caddr_t data,
898	__in			size_t size,
899	__out			efx_vpd_value_t *evvp,
900	__inout			unsigned int *contp);
901
902extern __checkReturn		efx_rc_t
903ef10_vpd_write(
904	__in			efx_nic_t *enp,
905	__in_bcount(size)	caddr_t data,
906	__in			size_t size);
907
908extern				void
909ef10_vpd_fini(
910	__in			efx_nic_t *enp);
911
912#endif	/* EFSYS_OPT_VPD */
913
914
915/* RX */
916
917extern	__checkReturn	efx_rc_t
918ef10_rx_init(
919	__in		efx_nic_t *enp);
920
921#if EFSYS_OPT_RX_SCATTER
922extern	__checkReturn	efx_rc_t
923ef10_rx_scatter_enable(
924	__in		efx_nic_t *enp,
925	__in		unsigned int buf_size);
926#endif	/* EFSYS_OPT_RX_SCATTER */
927
928
929#if EFSYS_OPT_RX_SCALE
930
931extern	__checkReturn	efx_rc_t
932ef10_rx_scale_mode_set(
933	__in		efx_nic_t *enp,
934	__in		efx_rx_hash_alg_t alg,
935	__in		efx_rx_hash_type_t type,
936	__in		boolean_t insert);
937
938extern	__checkReturn	efx_rc_t
939ef10_rx_scale_key_set(
940	__in		efx_nic_t *enp,
941	__in_ecount(n)	uint8_t *key,
942	__in		size_t n);
943
944extern	__checkReturn	efx_rc_t
945ef10_rx_scale_tbl_set(
946	__in		efx_nic_t *enp,
947	__in_ecount(n)	unsigned int *table,
948	__in		size_t n);
949
950extern	__checkReturn	uint32_t
951ef10_rx_prefix_hash(
952	__in		efx_nic_t *enp,
953	__in		efx_rx_hash_alg_t func,
954	__in		uint8_t *buffer);
955
956#endif /* EFSYS_OPT_RX_SCALE */
957
958extern	__checkReturn	efx_rc_t
959ef10_rx_prefix_pktlen(
960	__in		efx_nic_t *enp,
961	__in		uint8_t *buffer,
962	__out		uint16_t *lengthp);
963
964extern			void
965ef10_rx_qpost(
966	__in		efx_rxq_t *erp,
967	__in_ecount(n)	efsys_dma_addr_t *addrp,
968	__in		size_t size,
969	__in		unsigned int n,
970	__in		unsigned int completed,
971	__in		unsigned int added);
972
973extern			void
974ef10_rx_qpush(
975	__in		efx_rxq_t *erp,
976	__in		unsigned int added,
977	__inout		unsigned int *pushedp);
978
979extern	__checkReturn	efx_rc_t
980ef10_rx_qflush(
981	__in		efx_rxq_t *erp);
982
983extern		void
984ef10_rx_qenable(
985	__in		efx_rxq_t *erp);
986
987extern	__checkReturn	efx_rc_t
988ef10_rx_qcreate(
989	__in		efx_nic_t *enp,
990	__in		unsigned int index,
991	__in		unsigned int label,
992	__in		efx_rxq_type_t type,
993	__in		efsys_mem_t *esmp,
994	__in		size_t n,
995	__in		uint32_t id,
996	__in		efx_evq_t *eep,
997	__in		efx_rxq_t *erp);
998
999extern			void
1000ef10_rx_qdestroy(
1001	__in		efx_rxq_t *erp);
1002
1003extern			void
1004ef10_rx_fini(
1005	__in		efx_nic_t *enp);
1006
1007#if EFSYS_OPT_FILTER
1008
1009typedef struct ef10_filter_handle_s {
1010	uint32_t	efh_lo;
1011	uint32_t	efh_hi;
1012} ef10_filter_handle_t;
1013
1014typedef struct ef10_filter_entry_s {
1015	uintptr_t efe_spec; /* pointer to filter spec plus busy bit */
1016	ef10_filter_handle_t efe_handle;
1017} ef10_filter_entry_t;
1018
1019/*
1020 * BUSY flag indicates that an update is in progress.
1021 * AUTO_OLD flag is used to mark and sweep MAC packet filters.
1022 */
1023#define	EFX_EF10_FILTER_FLAG_BUSY	1U
1024#define	EFX_EF10_FILTER_FLAG_AUTO_OLD	2U
1025#define	EFX_EF10_FILTER_FLAGS		3U
1026
1027/*
1028 * Size of the hash table used by the driver. Doesn't need to be the
1029 * same size as the hardware's table.
1030 */
1031#define	EFX_EF10_FILTER_TBL_ROWS 8192
1032
1033/* Only need to allow for one directed and one unknown unicast filter */
1034#define	EFX_EF10_FILTER_UNICAST_FILTERS_MAX	2
1035
1036/* Allow for the broadcast address to be added to the multicast list */
1037#define	EFX_EF10_FILTER_MULTICAST_FILTERS_MAX	(EFX_MAC_MULTICAST_LIST_MAX + 1)
1038
1039typedef struct ef10_filter_table_s {
1040	ef10_filter_entry_t	eft_entry[EFX_EF10_FILTER_TBL_ROWS];
1041	efx_rxq_t *		eft_default_rxq;
1042	boolean_t 		eft_using_rss;
1043	uint32_t 		eft_unicst_filter_indexes[
1044	    EFX_EF10_FILTER_UNICAST_FILTERS_MAX];
1045	boolean_t		eft_unicst_filter_count;
1046	uint32_t 		eft_mulcst_filter_indexes[
1047	    EFX_EF10_FILTER_MULTICAST_FILTERS_MAX];
1048	uint32_t 		eft_mulcst_filter_count;
1049	boolean_t		eft_using_all_mulcst;
1050} ef10_filter_table_t;
1051
1052	__checkReturn	efx_rc_t
1053ef10_filter_init(
1054	__in		efx_nic_t *enp);
1055
1056			void
1057ef10_filter_fini(
1058	__in		efx_nic_t *enp);
1059
1060	__checkReturn	efx_rc_t
1061ef10_filter_restore(
1062	__in		efx_nic_t *enp);
1063
1064	__checkReturn	efx_rc_t
1065ef10_filter_add(
1066	__in		efx_nic_t *enp,
1067	__inout		efx_filter_spec_t *spec,
1068	__in		boolean_t may_replace);
1069
1070	__checkReturn	efx_rc_t
1071ef10_filter_delete(
1072	__in		efx_nic_t *enp,
1073	__inout		efx_filter_spec_t *spec);
1074
1075extern	__checkReturn	efx_rc_t
1076ef10_filter_supported_filters(
1077	__in		efx_nic_t *enp,
1078	__out		uint32_t *list,
1079	__out		size_t *length);
1080
1081extern	__checkReturn	efx_rc_t
1082ef10_filter_reconfigure(
1083	__in				efx_nic_t *enp,
1084	__in_ecount(6)			uint8_t const *mac_addr,
1085	__in				boolean_t all_unicst,
1086	__in				boolean_t mulcst,
1087	__in				boolean_t all_mulcst,
1088	__in				boolean_t brdcst,
1089	__in_ecount(6*count)		uint8_t const *addrs,
1090	__in				uint32_t count);
1091
1092extern		void
1093ef10_filter_get_default_rxq(
1094	__in		efx_nic_t *enp,
1095	__out		efx_rxq_t **erpp,
1096	__out		boolean_t *using_rss);
1097
1098extern		void
1099ef10_filter_default_rxq_set(
1100	__in		efx_nic_t *enp,
1101	__in		efx_rxq_t *erp,
1102	__in		boolean_t using_rss);
1103
1104extern		void
1105ef10_filter_default_rxq_clear(
1106	__in		efx_nic_t *enp);
1107
1108
1109#endif /* EFSYS_OPT_FILTER */
1110
1111extern	__checkReturn			efx_rc_t
1112efx_mcdi_get_function_info(
1113	__in				efx_nic_t *enp,
1114	__out				uint32_t *pfp,
1115	__out_opt			uint32_t *vfp);
1116
1117extern	__checkReturn		efx_rc_t
1118efx_mcdi_privilege_mask(
1119	__in			efx_nic_t *enp,
1120	__in			uint32_t pf,
1121	__in			uint32_t vf,
1122	__out			uint32_t *maskp);
1123
1124#ifdef	__cplusplus
1125}
1126#endif
1127
1128#endif	/* _SYS_HUNT_IMPL_H */
1129