efx_regs_ef10.h revision 284555
1/*- 2 * Copyright (c) 2007-2015 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * The views and conclusions contained in the software and documentation are 27 * those of the authors and should not be interpreted as representing official 28 * policies, either expressed or implied, of the FreeBSD Project. 29 * 30 * $FreeBSD: stable/10/sys/dev/sfxge/common/efx_regs_ef10.h 284555 2015-06-18 15:46:39Z arybchik $ 31 */ 32 33#ifndef _SYS_EFX_EF10_REGS_H 34#define _SYS_EFX_EF10_REGS_H 35 36#ifdef __cplusplus 37extern "C" { 38#endif 39 40/* 41 * BIU_HW_REV_ID_REG(32bit): 42 * 43 */ 44 45#define ER_DZ_BIU_HW_REV_ID_REG_OFST 0x00000000 46/* hunta0=pcie_pf_bar2 */ 47#define ER_DZ_BIU_HW_REV_ID_REG_RESET 0xeb14face 48 49 50#define ERF_DZ_HW_REV_ID_LBN 0 51#define ERF_DZ_HW_REV_ID_WIDTH 32 52 53 54/* 55 * BIU_MC_SFT_STATUS_REG(32bit): 56 * 57 */ 58 59#define ER_DZ_BIU_MC_SFT_STATUS_REG_OFST 0x00000010 60/* hunta0=pcie_pf_bar2 */ 61#define ER_DZ_BIU_MC_SFT_STATUS_REG_STEP 4 62#define ER_DZ_BIU_MC_SFT_STATUS_REG_ROWS 8 63#define ER_DZ_BIU_MC_SFT_STATUS_REG_RESET 0x1111face 64 65 66#define ERF_DZ_MC_SFT_STATUS_LBN 0 67#define ERF_DZ_MC_SFT_STATUS_WIDTH 32 68 69 70/* 71 * BIU_INT_ISR_REG(32bit): 72 * 73 */ 74 75#define ER_DZ_BIU_INT_ISR_REG_OFST 0x00000090 76/* hunta0=pcie_pf_bar2 */ 77#define ER_DZ_BIU_INT_ISR_REG_RESET 0x0 78 79 80#define ERF_DZ_ISR_REG_LBN 0 81#define ERF_DZ_ISR_REG_WIDTH 32 82 83 84/* 85 * MC_DB_LWRD_REG(32bit): 86 * 87 */ 88 89#define ER_DZ_MC_DB_LWRD_REG_OFST 0x00000200 90/* hunta0=pcie_pf_bar2 */ 91#define ER_DZ_MC_DB_LWRD_REG_RESET 0x0 92 93 94#define ERF_DZ_MC_DOORBELL_L_LBN 0 95#define ERF_DZ_MC_DOORBELL_L_WIDTH 32 96 97 98/* 99 * MC_DB_HWRD_REG(32bit): 100 * 101 */ 102 103#define ER_DZ_MC_DB_HWRD_REG_OFST 0x00000204 104/* hunta0=pcie_pf_bar2 */ 105#define ER_DZ_MC_DB_HWRD_REG_RESET 0x0 106 107 108#define ERF_DZ_MC_DOORBELL_H_LBN 0 109#define ERF_DZ_MC_DOORBELL_H_WIDTH 32 110 111 112/* 113 * EVQ_RPTR_REG(32bit): 114 * 115 */ 116 117#define ER_DZ_EVQ_RPTR_REG_OFST 0x00000400 118/* hunta0=pcie_pf_bar2 */ 119#define ER_DZ_EVQ_RPTR_REG_STEP 8192 120#define ER_DZ_EVQ_RPTR_REG_ROWS 2048 121#define ER_DZ_EVQ_RPTR_REG_RESET 0x0 122 123 124#define ERF_DZ_EVQ_RPTR_VLD_LBN 15 125#define ERF_DZ_EVQ_RPTR_VLD_WIDTH 1 126#define ERF_DZ_EVQ_RPTR_LBN 0 127#define ERF_DZ_EVQ_RPTR_WIDTH 15 128 129 130/* 131 * EVQ_TMR_REG(32bit): 132 * 133 */ 134 135#define ER_DZ_EVQ_TMR_REG_OFST 0x00000420 136/* hunta0=pcie_pf_bar2 */ 137#define ER_DZ_EVQ_TMR_REG_STEP 8192 138#define ER_DZ_EVQ_TMR_REG_ROWS 2048 139#define ER_DZ_EVQ_TMR_REG_RESET 0x0 140 141 142#define ERF_DZ_TC_TIMER_MODE_LBN 14 143#define ERF_DZ_TC_TIMER_MODE_WIDTH 2 144#define ERF_DZ_TC_TIMER_VAL_LBN 0 145#define ERF_DZ_TC_TIMER_VAL_WIDTH 14 146 147 148/* 149 * RX_DESC_UPD_REG(32bit): 150 * 151 */ 152 153#define ER_DZ_RX_DESC_UPD_REG_OFST 0x00000830 154/* hunta0=pcie_pf_bar2 */ 155#define ER_DZ_RX_DESC_UPD_REG_STEP 8192 156#define ER_DZ_RX_DESC_UPD_REG_ROWS 2048 157#define ER_DZ_RX_DESC_UPD_REG_RESET 0x0 158 159 160#define ERF_DZ_RX_DESC_WPTR_LBN 0 161#define ERF_DZ_RX_DESC_WPTR_WIDTH 12 162 163 164/* 165 * TX_DESC_UPD_REG(96bit): 166 * 167 */ 168 169#define ER_DZ_TX_DESC_UPD_REG_OFST 0x00000a10 170/* hunta0=pcie_pf_bar2 */ 171#define ER_DZ_TX_DESC_UPD_REG_STEP 8192 172#define ER_DZ_TX_DESC_UPD_REG_ROWS 2048 173#define ER_DZ_TX_DESC_UPD_REG_RESET 0x0 174 175 176#define ERF_DZ_RSVD_LBN 76 177#define ERF_DZ_RSVD_WIDTH 20 178#define ERF_DZ_TX_DESC_WPTR_LBN 64 179#define ERF_DZ_TX_DESC_WPTR_WIDTH 12 180#define ERF_DZ_TX_DESC_HWORD_LBN 32 181#define ERF_DZ_TX_DESC_HWORD_WIDTH 32 182#define ERF_DZ_TX_DESC_LWORD_LBN 0 183#define ERF_DZ_TX_DESC_LWORD_WIDTH 32 184 185/* 186 * The workaround for bug 35388 requires multiplexing writes through 187 * the ERF_DZ_TX_DESC_WPTR address. 188 * TX_DESC_UPD: 0ppppppppppp (bit 11 lost) 189 * EVQ_RPTR: 1000hhhhhhhh, 1001llllllll (split into high and low bits) 190 * EVQ_TMR: 11mmvvvvvvvv (bits 8:13 of value lost) 191 */ 192#define ER_DD_EVQ_INDIRECT_OFST (ER_DZ_TX_DESC_UPD_REG_OFST + 2 * 4) 193#define ER_DD_EVQ_INDIRECT_STEP ER_DZ_TX_DESC_UPD_REG_STEP 194#define ERF_DD_EVQ_IND_RPTR_FLAGS_LBN 8 195#define ERF_DD_EVQ_IND_RPTR_FLAGS_WIDTH 4 196#define EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH 8 197#define EFE_DD_EVQ_IND_RPTR_FLAGS_LOW 9 198#define ERF_DD_EVQ_IND_RPTR_LBN 0 199#define ERF_DD_EVQ_IND_RPTR_WIDTH 8 200#define ERF_DD_EVQ_IND_TIMER_FLAGS_LBN 10 201#define ERF_DD_EVQ_IND_TIMER_FLAGS_WIDTH 2 202#define EFE_DD_EVQ_IND_TIMER_FLAGS 3 203#define ERF_DD_EVQ_IND_TIMER_MODE_LBN 8 204#define ERF_DD_EVQ_IND_TIMER_MODE_WIDTH 2 205#define ERF_DD_EVQ_IND_TIMER_VAL_LBN 0 206#define ERF_DD_EVQ_IND_TIMER_VAL_WIDTH 8 207 208 209/* ES_DRIVER_EV */ 210#define ESF_DZ_DRV_CODE_LBN 60 211#define ESF_DZ_DRV_CODE_WIDTH 4 212#define ESF_DZ_DRV_SUB_CODE_LBN 56 213#define ESF_DZ_DRV_SUB_CODE_WIDTH 4 214#define ESE_DZ_DRV_TIMER_EV 3 215#define ESE_DZ_DRV_START_UP_EV 2 216#define ESE_DZ_DRV_WAKE_UP_EV 1 217#define ESF_DZ_DRV_SUB_DATA_DW0_LBN 0 218#define ESF_DZ_DRV_SUB_DATA_DW0_WIDTH 32 219#define ESF_DZ_DRV_SUB_DATA_DW1_LBN 32 220#define ESF_DZ_DRV_SUB_DATA_DW1_WIDTH 24 221#define ESF_DZ_DRV_SUB_DATA_LBN 0 222#define ESF_DZ_DRV_SUB_DATA_WIDTH 56 223#define ESF_DZ_DRV_EVQ_ID_LBN 0 224#define ESF_DZ_DRV_EVQ_ID_WIDTH 14 225#define ESF_DZ_DRV_TMR_ID_LBN 0 226#define ESF_DZ_DRV_TMR_ID_WIDTH 14 227 228 229/* ES_EVENT_ENTRY */ 230#define ESF_DZ_EV_CODE_LBN 60 231#define ESF_DZ_EV_CODE_WIDTH 4 232#define ESE_DZ_EV_CODE_MCDI_EV 12 233#define ESE_DZ_EV_CODE_DRIVER_EV 5 234#define ESE_DZ_EV_CODE_TX_EV 2 235#define ESE_DZ_EV_CODE_RX_EV 0 236#define ESE_DZ_OTHER other 237#define ESF_DZ_EV_DATA_DW0_LBN 0 238#define ESF_DZ_EV_DATA_DW0_WIDTH 32 239#define ESF_DZ_EV_DATA_DW1_LBN 32 240#define ESF_DZ_EV_DATA_DW1_WIDTH 28 241#define ESF_DZ_EV_DATA_LBN 0 242#define ESF_DZ_EV_DATA_WIDTH 60 243 244 245/* ES_FF_UMSG_CPU2DL_DESC_FETCH */ 246#define ESF_DZ_C2DDF_DSCR_CACHE_RPTR_LBN 208 247#define ESF_DZ_C2DDF_DSCR_CACHE_RPTR_WIDTH 6 248#define ESF_DZ_C2DDF_QID_LBN 160 249#define ESF_DZ_C2DDF_QID_WIDTH 11 250#define ESF_DZ_C2DDF_DSCR_BASE_PAGE_ID_LBN 64 251#define ESF_DZ_C2DDF_DSCR_BASE_PAGE_ID_WIDTH 18 252#define ESF_DZ_C2DDF_DSCR_HW_RPTR_LBN 48 253#define ESF_DZ_C2DDF_DSCR_HW_RPTR_WIDTH 12 254#define ESF_DZ_C2DDF_DSCR_HW_WPTR_LBN 32 255#define ESF_DZ_C2DDF_DSCR_HW_WPTR_WIDTH 12 256#define ESF_DZ_C2DDF_OID_LBN 16 257#define ESF_DZ_C2DDF_OID_WIDTH 12 258#define ESF_DZ_C2DDF_DSCR_SIZE_LBN 13 259#define ESF_DZ_C2DDF_DSCR_SIZE_WIDTH 3 260#define ESE_DZ_C2DDF_DSCR_SIZE_512 7 261#define ESE_DZ_C2DDF_DSCR_SIZE_1K 6 262#define ESE_DZ_C2DDF_DSCR_SIZE_2K 5 263#define ESE_DZ_C2DDF_DSCR_SIZE_4K 4 264#define ESF_DZ_C2DDF_BIU_ARGS_LBN 0 265#define ESF_DZ_C2DDF_BIU_ARGS_WIDTH 13 266 267 268/* ES_FF_UMSG_CPU2DL_DESC_PUSH */ 269#define ESF_DZ_C2DDP_DSCR_HW_RPTR_LBN 224 270#define ESF_DZ_C2DDP_DSCR_HW_RPTR_WIDTH 12 271#define ESF_DZ_C2DDP_DESC_DW0_LBN 128 272#define ESF_DZ_C2DDP_DESC_DW0_WIDTH 32 273#define ESF_DZ_C2DDP_DESC_DW1_LBN 160 274#define ESF_DZ_C2DDP_DESC_DW1_WIDTH 32 275#define ESF_DZ_C2DDP_DESC_LBN 128 276#define ESF_DZ_C2DDP_DESC_WIDTH 64 277#define ESF_DZ_C2DDP_QID_LBN 64 278#define ESF_DZ_C2DDP_QID_WIDTH 11 279#define ESF_DZ_C2DDP_DSCR_HW_WPTR_LBN 32 280#define ESF_DZ_C2DDP_DSCR_HW_WPTR_WIDTH 12 281#define ESF_DZ_C2DDP_OID_LBN 16 282#define ESF_DZ_C2DDP_OID_WIDTH 12 283#define ESF_DZ_C2DDP_DSCR_SIZE_LBN 0 284#define ESF_DZ_C2DDP_DSCR_SIZE_WIDTH 3 285#define ESE_DZ_C2DDF_DSCR_SIZE_512 7 286#define ESE_DZ_C2DDF_DSCR_SIZE_1K 6 287#define ESE_DZ_C2DDF_DSCR_SIZE_2K 5 288#define ESE_DZ_C2DDF_DSCR_SIZE_4K 4 289 290 291/* ES_FF_UMSG_CPU2DL_GPRD */ 292#define ESF_DZ_C2DG_ENCODED_HOST_ADDR_DW0_LBN 64 293#define ESF_DZ_C2DG_ENCODED_HOST_ADDR_DW0_WIDTH 32 294#define ESF_DZ_C2DG_ENCODED_HOST_ADDR_DW1_LBN 96 295#define ESF_DZ_C2DG_ENCODED_HOST_ADDR_DW1_WIDTH 16 296#define ESF_DZ_C2DG_ENCODED_HOST_ADDR_LBN 64 297#define ESF_DZ_C2DG_ENCODED_HOST_ADDR_WIDTH 48 298#define ESF_DZ_C2DG_SMC_ADDR_LBN 16 299#define ESF_DZ_C2DG_SMC_ADDR_WIDTH 16 300#define ESF_DZ_C2DG_BIU_ARGS_LBN 0 301#define ESF_DZ_C2DG_BIU_ARGS_WIDTH 14 302 303 304/* ES_FF_UMSG_CPU2EV_SOFT */ 305#define ESF_DZ_C2ES_TBD_LBN 0 306#define ESF_DZ_C2ES_TBD_WIDTH 1 307 308 309/* ES_FF_UMSG_CPU2EV_TXCMPLT */ 310#define ESF_DZ_C2ET_EV_SOFT2_LBN 48 311#define ESF_DZ_C2ET_EV_SOFT2_WIDTH 16 312#define ESF_DZ_C2ET_EV_CODE_LBN 42 313#define ESF_DZ_C2ET_EV_CODE_WIDTH 4 314#define ESF_DZ_C2ET_EV_OVERRIDE_HOLDOFF_LBN 41 315#define ESF_DZ_C2ET_EV_OVERRIDE_HOLDOFF_WIDTH 1 316#define ESF_DZ_C2ET_EV_DROP_EVENT_LBN 40 317#define ESF_DZ_C2ET_EV_DROP_EVENT_WIDTH 1 318#define ESF_DZ_C2ET_EV_CAN_MERGE_LBN 39 319#define ESF_DZ_C2ET_EV_CAN_MERGE_WIDTH 1 320#define ESF_DZ_C2ET_EV_SOFT1_LBN 32 321#define ESF_DZ_C2ET_EV_SOFT1_WIDTH 7 322#define ESF_DZ_C2ET_DSCR_IDX_LBN 16 323#define ESF_DZ_C2ET_DSCR_IDX_WIDTH 16 324#define ESF_DZ_C2ET_EV_QID_LBN 5 325#define ESF_DZ_C2ET_EV_QID_WIDTH 11 326#define ESF_DZ_C2ET_EV_QLABEL_LBN 0 327#define ESF_DZ_C2ET_EV_QLABEL_WIDTH 5 328 329 330/* ES_FF_UMSG_CPU2RXDP_INGR_BUFOP */ 331#define ESF_DZ_C2RIB_EV_DISABLE_LBN 191 332#define ESF_DZ_C2RIB_EV_DISABLE_WIDTH 1 333#define ESF_DZ_C2RIB_EV_SOFT_LBN 188 334#define ESF_DZ_C2RIB_EV_SOFT_WIDTH 3 335#define ESF_DZ_C2RIB_EV_DESC_PTR_LBN 176 336#define ESF_DZ_C2RIB_EV_DESC_PTR_WIDTH 12 337#define ESF_DZ_C2RIB_EV_ARG1_LBN 160 338#define ESF_DZ_C2RIB_EV_ARG1_WIDTH 16 339#define ESF_DZ_C2RIB_ENCODED_HOST_ADDR_DW0_LBN 64 340#define ESF_DZ_C2RIB_ENCODED_HOST_ADDR_DW0_WIDTH 32 341#define ESF_DZ_C2RIB_ENCODED_HOST_ADDR_DW1_LBN 96 342#define ESF_DZ_C2RIB_ENCODED_HOST_ADDR_DW1_WIDTH 16 343#define ESF_DZ_C2RIB_ENCODED_HOST_ADDR_LBN 64 344#define ESF_DZ_C2RIB_ENCODED_HOST_ADDR_WIDTH 48 345#define ESF_DZ_C2RIB_BIU_ARGS_LBN 16 346#define ESF_DZ_C2RIB_BIU_ARGS_WIDTH 13 347#define ESF_DZ_C2RIB_EV_QID_LBN 5 348#define ESF_DZ_C2RIB_EV_QID_WIDTH 11 349#define ESF_DZ_C2RIB_EV_QLABEL_LBN 0 350#define ESF_DZ_C2RIB_EV_QLABEL_WIDTH 5 351 352 353/* ES_FF_UMSG_CPU2RXDP_INGR_PDISP */ 354#define ESF_DZ_C2RIP_BUF_LEN_LBN 240 355#define ESF_DZ_C2RIP_BUF_LEN_WIDTH 16 356#define ESF_DZ_C2RIP_ENCODED_HOST_ADDR_DW0_LBN 192 357#define ESF_DZ_C2RIP_ENCODED_HOST_ADDR_DW0_WIDTH 32 358#define ESF_DZ_C2RIP_ENCODED_HOST_ADDR_DW1_LBN 224 359#define ESF_DZ_C2RIP_ENCODED_HOST_ADDR_DW1_WIDTH 16 360#define ESF_DZ_C2RIP_ENCODED_HOST_ADDR_LBN 192 361#define ESF_DZ_C2RIP_ENCODED_HOST_ADDR_WIDTH 48 362#define ESF_DZ_C2RIP_EV_DISABLE_LBN 191 363#define ESF_DZ_C2RIP_EV_DISABLE_WIDTH 1 364#define ESF_DZ_C2RIP_EV_SOFT_LBN 188 365#define ESF_DZ_C2RIP_EV_SOFT_WIDTH 3 366#define ESF_DZ_C2RIP_EV_DESC_PTR_LBN 176 367#define ESF_DZ_C2RIP_EV_DESC_PTR_WIDTH 12 368#define ESF_DZ_C2RIP_EV_ARG1_LBN 160 369#define ESF_DZ_C2RIP_EV_ARG1_WIDTH 16 370#define ESF_DZ_C2RIP_UPD_CRC_MODE_LBN 157 371#define ESF_DZ_C2RIP_UPD_CRC_MODE_WIDTH 3 372#define ESE_DZ_C2RIP_FCOIP_FCOE 4 373#define ESE_DZ_C2RIP_ISCSI_HDR_AND_PYLD 3 374#define ESE_DZ_C2RIP_ISCSI_HDR 2 375#define ESE_DZ_C2RIP_FCOE 1 376#define ESE_DZ_C2RIP_OFF 0 377#define ESF_DZ_C2RIP_BIU_ARGS_LBN 144 378#define ESF_DZ_C2RIP_BIU_ARGS_WIDTH 13 379#define ESF_DZ_C2RIP_EV_QID_LBN 133 380#define ESF_DZ_C2RIP_EV_QID_WIDTH 11 381#define ESF_DZ_C2RIP_EV_QLABEL_LBN 128 382#define ESF_DZ_C2RIP_EV_QLABEL_WIDTH 5 383#define ESF_DZ_C2RIP_PEDIT_DELTA_LBN 104 384#define ESF_DZ_C2RIP_PEDIT_DELTA_WIDTH 8 385#define ESF_DZ_C2RIP_PYLOAD_OFST_LBN 96 386#define ESF_DZ_C2RIP_PYLOAD_OFST_WIDTH 8 387#define ESF_DZ_C2RIP_L4_HDR_OFST_LBN 88 388#define ESF_DZ_C2RIP_L4_HDR_OFST_WIDTH 8 389#define ESF_DZ_C2RIP_L3_HDR_OFST_LBN 80 390#define ESF_DZ_C2RIP_L3_HDR_OFST_WIDTH 8 391#define ESF_DZ_C2RIP_IS_UDP_LBN 69 392#define ESF_DZ_C2RIP_IS_UDP_WIDTH 1 393#define ESF_DZ_C2RIP_IS_TCP_LBN 68 394#define ESF_DZ_C2RIP_IS_TCP_WIDTH 1 395#define ESF_DZ_C2RIP_IS_IPV6_LBN 67 396#define ESF_DZ_C2RIP_IS_IPV6_WIDTH 1 397#define ESF_DZ_C2RIP_IS_IPV4_LBN 66 398#define ESF_DZ_C2RIP_IS_IPV4_WIDTH 1 399#define ESF_DZ_C2RIP_IS_FCOE_LBN 65 400#define ESF_DZ_C2RIP_IS_FCOE_WIDTH 1 401#define ESF_DZ_C2RIP_PARSE_INCOMP_LBN 64 402#define ESF_DZ_C2RIP_PARSE_INCOMP_WIDTH 1 403#define ESF_DZ_C2RIP_FINFO_WRD3_LBN 48 404#define ESF_DZ_C2RIP_FINFO_WRD3_WIDTH 16 405#define ESF_DZ_C2RIP_FINFO_WRD2_LBN 32 406#define ESF_DZ_C2RIP_FINFO_WRD2_WIDTH 16 407#define ESF_DZ_C2RIP_FINFO_WRD1_LBN 16 408#define ESF_DZ_C2RIP_FINFO_WRD1_WIDTH 16 409#define ESF_DZ_C2RIP_FINFO_SRCDST_LBN 0 410#define ESF_DZ_C2RIP_FINFO_SRCDST_WIDTH 16 411 412 413/* ES_FF_UMSG_CPU2RXDP_INGR_SOFT */ 414#define ESF_DZ_C2RIS_SOFT3_LBN 48 415#define ESF_DZ_C2RIS_SOFT3_WIDTH 16 416#define ESF_DZ_C2RIS_SOFT2_LBN 32 417#define ESF_DZ_C2RIS_SOFT2_WIDTH 16 418#define ESF_DZ_C2RIS_SOFT1_LBN 16 419#define ESF_DZ_C2RIS_SOFT1_WIDTH 16 420#define ESF_DZ_C2RIS_SOFT0_LBN 0 421#define ESF_DZ_C2RIS_SOFT0_WIDTH 16 422 423 424/* ES_FF_UMSG_CPU2SMC_BUFLKUP */ 425#define ESF_DZ_C2SB_PAGE_ID_LBN 16 426#define ESF_DZ_C2SB_PAGE_ID_WIDTH 18 427#define ESF_DZ_C2SB_EXP_PAGE_ID_LBN 0 428#define ESF_DZ_C2SB_EXP_PAGE_ID_WIDTH 12 429 430 431/* ES_FF_UMSG_CPU2SMC_DESCOP */ 432#define ESF_DZ_C2SD_LEN_LBN 112 433#define ESF_DZ_C2SD_LEN_WIDTH 14 434#define ESF_DZ_C2SD_ENCODED_HOST_ADDR_DW0_LBN 64 435#define ESF_DZ_C2SD_ENCODED_HOST_ADDR_DW0_WIDTH 32 436#define ESF_DZ_C2SD_ENCODED_HOST_ADDR_DW1_LBN 96 437#define ESF_DZ_C2SD_ENCODED_HOST_ADDR_DW1_WIDTH 16 438#define ESF_DZ_C2SD_ENCODED_HOST_ADDR_LBN 64 439#define ESF_DZ_C2SD_ENCODED_HOST_ADDR_WIDTH 48 440#define ESF_DZ_C2SD_OFFSET_LBN 80 441#define ESF_DZ_C2SD_OFFSET_WIDTH 8 442#define ESF_DZ_C2SD_QID_LBN 32 443#define ESF_DZ_C2SD_QID_WIDTH 11 444#define ESF_DZ_C2SD_CONT_LBN 16 445#define ESF_DZ_C2SD_CONT_WIDTH 1 446#define ESF_DZ_C2SD_TYPE_LBN 0 447#define ESF_DZ_C2SD_TYPE_WIDTH 1 448 449 450/* ES_FF_UMSG_CPU2SMC_GPOP */ 451#define ESF_DZ_C2SG_DATA_DW0_LBN 64 452#define ESF_DZ_C2SG_DATA_DW0_WIDTH 32 453#define ESF_DZ_C2SG_DATA_DW1_LBN 96 454#define ESF_DZ_C2SG_DATA_DW1_WIDTH 32 455#define ESF_DZ_C2SG_DATA_LBN 64 456#define ESF_DZ_C2SG_DATA_WIDTH 64 457#define ESF_DZ_C2SG_SOFT_LBN 48 458#define ESF_DZ_C2SG_SOFT_WIDTH 4 459#define ESF_DZ_C2SG_REFLECT_LBN 32 460#define ESF_DZ_C2SG_REFLECT_WIDTH 1 461#define ESF_DZ_C2SG_ADDR_LBN 0 462#define ESF_DZ_C2SG_ADDR_WIDTH 16 463 464 465/* ES_FF_UMSG_CPU2TXDP_DMA_BUFREQ */ 466#define ESF_DZ_C2TDB_BUF_LEN_LBN 176 467#define ESF_DZ_C2TDB_BUF_LEN_WIDTH 16 468#define ESF_DZ_C2TDB_ENCODED_HOST_ADDR_DW0_LBN 128 469#define ESF_DZ_C2TDB_ENCODED_HOST_ADDR_DW0_WIDTH 32 470#define ESF_DZ_C2TDB_ENCODED_HOST_ADDR_DW1_LBN 160 471#define ESF_DZ_C2TDB_ENCODED_HOST_ADDR_DW1_WIDTH 16 472#define ESF_DZ_C2TDB_ENCODED_HOST_ADDR_LBN 128 473#define ESF_DZ_C2TDB_ENCODED_HOST_ADDR_WIDTH 48 474#define ESF_DZ_C2TDB_SOFT_LBN 112 475#define ESF_DZ_C2TDB_SOFT_WIDTH 14 476#define ESF_DZ_C2TDB_DESC_IDX_LBN 96 477#define ESF_DZ_C2TDB_DESC_IDX_WIDTH 16 478#define ESF_DZ_C2TDB_UPD_CRC_MODE_LBN 93 479#define ESF_DZ_C2TDB_UPD_CRC_MODE_WIDTH 3 480#define ESE_DZ_C2RIP_FCOIP_FCOE 4 481#define ESE_DZ_C2RIP_ISCSI_HDR_AND_PYLD 3 482#define ESE_DZ_C2RIP_ISCSI_HDR 2 483#define ESE_DZ_C2RIP_FCOE 1 484#define ESE_DZ_C2RIP_OFF 0 485#define ESF_DZ_C2TDB_BIU_ARGS_LBN 80 486#define ESF_DZ_C2TDB_BIU_ARGS_WIDTH 13 487#define ESF_DZ_C2TDB_CONT_LBN 64 488#define ESF_DZ_C2TDB_CONT_WIDTH 1 489#define ESF_DZ_C2TDB_FINFO_WRD3_LBN 48 490#define ESF_DZ_C2TDB_FINFO_WRD3_WIDTH 16 491#define ESF_DZ_C2TDB_FINFO_WRD2_LBN 32 492#define ESF_DZ_C2TDB_FINFO_WRD2_WIDTH 16 493#define ESF_DZ_C2TDB_FINFO_WRD1_LBN 16 494#define ESF_DZ_C2TDB_FINFO_WRD1_WIDTH 16 495#define ESF_DZ_C2TDB_FINFO_SRCDST_LBN 0 496#define ESF_DZ_C2TDB_FINFO_SRCDST_WIDTH 16 497 498 499/* ES_FF_UMSG_CPU2TXDP_DMA_PKTABORT */ 500#define ESF_DZ_C2TDP_SOFT_LBN 48 501#define ESF_DZ_C2TDP_SOFT_WIDTH 14 502#define ESF_DZ_C2TDP_DESC_IDX_LBN 32 503#define ESF_DZ_C2TDP_DESC_IDX_WIDTH 16 504#define ESF_DZ_C2TDP_BIU_ARGS_LBN 16 505#define ESF_DZ_C2TDP_BIU_ARGS_WIDTH 14 506 507 508/* ES_FF_UMSG_CPU2TXDP_DMA_SOFT */ 509#define ESF_DZ_C2TDS_SOFT3_LBN 48 510#define ESF_DZ_C2TDS_SOFT3_WIDTH 16 511#define ESF_DZ_C2TDS_SOFT2_LBN 32 512#define ESF_DZ_C2TDS_SOFT2_WIDTH 16 513#define ESF_DZ_C2TDS_SOFT1_LBN 16 514#define ESF_DZ_C2TDS_SOFT1_WIDTH 16 515#define ESF_DZ_C2TDS_SOFT0_LBN 0 516#define ESF_DZ_C2TDS_SOFT0_WIDTH 16 517 518 519/* ES_FF_UMSG_CPU2TXDP_EGR */ 520#define ESF_DZ_C2TE_RMON_SOFT_LBN 240 521#define ESF_DZ_C2TE_RMON_SOFT_WIDTH 1 522#define ESF_DZ_C2TE_VLAN_PRIO_LBN 224 523#define ESF_DZ_C2TE_VLAN_PRIO_WIDTH 3 524#define ESF_DZ_C2TE_VLAN_LBN 208 525#define ESF_DZ_C2TE_VLAN_WIDTH 1 526#define ESF_DZ_C2TE_QID_LBN 192 527#define ESF_DZ_C2TE_QID_WIDTH 11 528#define ESF_DZ_C2TE_PEDIT_DELTA_LBN 168 529#define ESF_DZ_C2TE_PEDIT_DELTA_WIDTH 8 530#define ESF_DZ_C2TE_PYLOAD_OFST_LBN 160 531#define ESF_DZ_C2TE_PYLOAD_OFST_WIDTH 8 532#define ESF_DZ_C2TE_L4_HDR_OFST_LBN 152 533#define ESF_DZ_C2TE_L4_HDR_OFST_WIDTH 8 534#define ESF_DZ_C2TE_L3_HDR_OFST_LBN 144 535#define ESF_DZ_C2TE_L3_HDR_OFST_WIDTH 8 536#define ESF_DZ_C2TE_IS_UDP_LBN 133 537#define ESF_DZ_C2TE_IS_UDP_WIDTH 1 538#define ESF_DZ_C2TE_IS_TCP_LBN 132 539#define ESF_DZ_C2TE_IS_TCP_WIDTH 1 540#define ESF_DZ_C2TE_IS_IPV6_LBN 131 541#define ESF_DZ_C2TE_IS_IPV6_WIDTH 1 542#define ESF_DZ_C2TE_IS_IPV4_LBN 130 543#define ESF_DZ_C2TE_IS_IPV4_WIDTH 1 544#define ESF_DZ_C2TE_IS_FCOE_LBN 129 545#define ESF_DZ_C2TE_IS_FCOE_WIDTH 1 546#define ESF_DZ_C2TE_PARSE_INCOMP_LBN 128 547#define ESF_DZ_C2TE_PARSE_INCOMP_WIDTH 1 548#define ESF_DZ_C2TE_UPD_CRC_MODE_LBN 98 549#define ESF_DZ_C2TE_UPD_CRC_MODE_WIDTH 3 550#define ESE_DZ_C2RIP_FCOIP_FCOE 4 551#define ESE_DZ_C2RIP_ISCSI_HDR_AND_PYLD 3 552#define ESE_DZ_C2RIP_ISCSI_HDR 2 553#define ESE_DZ_C2RIP_FCOE 1 554#define ESE_DZ_C2RIP_OFF 0 555#define ESF_DZ_C2TE_UPD_TCPUDPCSUM_MODE_LBN 97 556#define ESF_DZ_C2TE_UPD_TCPUDPCSUM_MODE_WIDTH 1 557#define ESF_DZ_C2TE_UPD_IPCSUM_MODE_LBN 96 558#define ESF_DZ_C2TE_UPD_IPCSUM_MODE_WIDTH 1 559#define ESF_DZ_C2TE_PKT_LEN_LBN 64 560#define ESF_DZ_C2TE_PKT_LEN_WIDTH 16 561#define ESF_DZ_C2TE_FINFO_WRD3_LBN 48 562#define ESF_DZ_C2TE_FINFO_WRD3_WIDTH 16 563#define ESF_DZ_C2TE_FINFO_WRD2_LBN 32 564#define ESF_DZ_C2TE_FINFO_WRD2_WIDTH 16 565#define ESF_DZ_C2TE_FINFO_WRD1_LBN 16 566#define ESF_DZ_C2TE_FINFO_WRD1_WIDTH 16 567#define ESF_DZ_C2TE_FINFO_SRCDST_LBN 0 568#define ESF_DZ_C2TE_FINFO_SRCDST_WIDTH 16 569 570 571/* ES_FF_UMSG_CPU2TXDP_EGR_SOFT */ 572#define ESF_DZ_C2TES_SOFT3_LBN 48 573#define ESF_DZ_C2TES_SOFT3_WIDTH 16 574#define ESF_DZ_C2TES_SOFT2_LBN 32 575#define ESF_DZ_C2TES_SOFT2_WIDTH 16 576#define ESF_DZ_C2TES_SOFT1_LBN 16 577#define ESF_DZ_C2TES_SOFT1_WIDTH 16 578#define ESF_DZ_C2TES_SOFT0_LBN 0 579#define ESF_DZ_C2TES_SOFT0_WIDTH 16 580 581 582/* ES_FF_UMSG_DL2CPU_DESC_FETCH */ 583#define ESF_DZ_D2CDF_REFL_DSCR_HW_WPTR_LBN 64 584#define ESF_DZ_D2CDF_REFL_DSCR_HW_WPTR_WIDTH 12 585#define ESF_DZ_D2CDF_FAIL_LBN 48 586#define ESF_DZ_D2CDF_FAIL_WIDTH 1 587#define ESF_DZ_D2CDF_QID_LBN 32 588#define ESF_DZ_D2CDF_QID_WIDTH 11 589#define ESF_DZ_D2CDF_NUM_DESC_LBN 16 590#define ESF_DZ_D2CDF_NUM_DESC_WIDTH 7 591#define ESF_DZ_D2CDF_NEW_DSCR_HW_RPTR_LBN 0 592#define ESF_DZ_D2CDF_NEW_DSCR_HW_RPTR_WIDTH 12 593 594 595/* ES_FF_UMSG_DL2CPU_GPRD */ 596#define ESF_DZ_D2CG_BIU_ARGS_LBN 0 597#define ESF_DZ_D2CG_BIU_ARGS_WIDTH 14 598 599 600/* ES_FF_UMSG_DPCPU_PACER_TXQ_D_R_I_REQ */ 601#define ESF_DZ_FRM_LEN_LBN 16 602#define ESF_DZ_FRM_LEN_WIDTH 15 603#define ESF_DZ_TXQ_ID_LBN 0 604#define ESF_DZ_TXQ_ID_WIDTH 10 605 606 607/* ES_FF_UMSG_PACER_BKT_TBL_RD_REQ */ 608#define ESF_DZ_BKT_ID_LBN 0 609#define ESF_DZ_BKT_ID_WIDTH 10 610 611 612/* ES_FF_UMSG_PACER_BKT_TBL_RD_RSP */ 613#define ESF_DZ_DUE_TIME_LBN 80 614#define ESF_DZ_DUE_TIME_WIDTH 16 615#define ESF_DZ_LAST_FILL_TIME_LBN 64 616#define ESF_DZ_LAST_FILL_TIME_WIDTH 16 617#define ESF_DZ_RATE_REC_LBN 48 618#define ESF_DZ_RATE_REC_WIDTH 16 619#define ESF_DZ_RATE_LBN 32 620#define ESF_DZ_RATE_WIDTH 16 621#define ESF_DZ_FILL_LEVEL_LBN 16 622#define ESF_DZ_FILL_LEVEL_WIDTH 16 623#define ESF_DZ_IDLE_LBN 15 624#define ESF_DZ_IDLE_WIDTH 1 625#define ESF_DZ_USED_LBN 14 626#define ESF_DZ_USED_WIDTH 1 627#define ESF_DZ_MAX_FILL_REG_LBN 12 628#define ESF_DZ_MAX_FILL_REG_WIDTH 2 629#define ESF_DZ_BKT_ID_LBN 0 630#define ESF_DZ_BKT_ID_WIDTH 10 631 632 633/* ES_FF_UMSG_PACER_BKT_TBL_WR_REQ */ 634#define ESF_DZ_RATE_REC_LBN 48 635#define ESF_DZ_RATE_REC_WIDTH 16 636#define ESF_DZ_RATE_LBN 32 637#define ESF_DZ_RATE_WIDTH 16 638#define ESF_DZ_FILL_LEVEL_LBN 16 639#define ESF_DZ_FILL_LEVEL_WIDTH 16 640#define ESF_DZ_IDLE_LBN 15 641#define ESF_DZ_IDLE_WIDTH 1 642#define ESF_DZ_USED_LBN 14 643#define ESF_DZ_USED_WIDTH 1 644#define ESF_DZ_MAX_FILL_REG_LBN 12 645#define ESF_DZ_MAX_FILL_REG_WIDTH 2 646#define ESF_DZ_BKT_ID_LBN 0 647#define ESF_DZ_BKT_ID_WIDTH 10 648 649 650/* ES_FF_UMSG_PACER_TXQ_TBL_RD_REQ */ 651#define ESF_DZ_TXQ_ID_LBN 0 652#define ESF_DZ_TXQ_ID_WIDTH 10 653 654 655/* ES_FF_UMSG_PACER_TXQ_TBL_RD_RSP */ 656#define ESF_DZ_MAX_BKT2_LBN 112 657#define ESF_DZ_MAX_BKT2_WIDTH 10 658#define ESF_DZ_MAX_BKT1_LBN 96 659#define ESF_DZ_MAX_BKT1_WIDTH 10 660#define ESF_DZ_MAX_BKT0_LBN 80 661#define ESF_DZ_MAX_BKT0_WIDTH 10 662#define ESF_DZ_MIN_BKT_LBN 64 663#define ESF_DZ_MIN_BKT_WIDTH 10 664#define ESF_DZ_LABEL_LBN 48 665#define ESF_DZ_LABEL_WIDTH 4 666#define ESF_DZ_PQ_FLAGS_LBN 32 667#define ESF_DZ_PQ_FLAGS_WIDTH 3 668#define ESF_DZ_DSBL_LBN 16 669#define ESF_DZ_DSBL_WIDTH 1 670#define ESF_DZ_TXQ_ID_LBN 0 671#define ESF_DZ_TXQ_ID_WIDTH 10 672 673 674/* ES_FF_UMSG_PACER_TXQ_TBL_WR_REQ */ 675#define ESF_DZ_MAX_BKT2_LBN 112 676#define ESF_DZ_MAX_BKT2_WIDTH 10 677#define ESF_DZ_MAX_BKT1_LBN 96 678#define ESF_DZ_MAX_BKT1_WIDTH 10 679#define ESF_DZ_MAX_BKT0_LBN 80 680#define ESF_DZ_MAX_BKT0_WIDTH 10 681#define ESF_DZ_MIN_BKT_LBN 64 682#define ESF_DZ_MIN_BKT_WIDTH 10 683#define ESF_DZ_LABEL_LBN 48 684#define ESF_DZ_LABEL_WIDTH 4 685#define ESF_DZ_PQ_FLAGS_LBN 32 686#define ESF_DZ_PQ_FLAGS_WIDTH 3 687#define ESF_DZ_DSBL_LBN 16 688#define ESF_DZ_DSBL_WIDTH 1 689#define ESF_DZ_TXQ_ID_LBN 0 690#define ESF_DZ_TXQ_ID_WIDTH 10 691 692 693/* ES_FF_UMSG_PE */ 694#define ESF_DZ_PE_PKT_OFST_LBN 47 695#define ESF_DZ_PE_PKT_OFST_WIDTH 17 696#define ESF_DZ_PE_PEDIT_DELTA_LBN 40 697#define ESF_DZ_PE_PEDIT_DELTA_WIDTH 8 698#define ESF_DZ_PE_PYLOAD_OFST_LBN 32 699#define ESF_DZ_PE_PYLOAD_OFST_WIDTH 8 700#define ESF_DZ_PE_L4_HDR_OFST_LBN 24 701#define ESF_DZ_PE_L4_HDR_OFST_WIDTH 8 702#define ESF_DZ_PE_L3_HDR_OFST_LBN 16 703#define ESF_DZ_PE_L3_HDR_OFST_WIDTH 8 704#define ESF_DZ_PE_HAVE_UDP_HDR_LBN 5 705#define ESF_DZ_PE_HAVE_UDP_HDR_WIDTH 1 706#define ESF_DZ_PE_HAVE_TCP_HDR_LBN 4 707#define ESF_DZ_PE_HAVE_TCP_HDR_WIDTH 1 708#define ESF_DZ_PE_HAVE_IPV6_HDR_LBN 3 709#define ESF_DZ_PE_HAVE_IPV6_HDR_WIDTH 1 710#define ESF_DZ_PE_HAVE_IPV4_HDR_LBN 2 711#define ESF_DZ_PE_HAVE_IPV4_HDR_WIDTH 1 712#define ESF_DZ_PE_HAVE_FCOE_LBN 1 713#define ESF_DZ_PE_HAVE_FCOE_WIDTH 1 714#define ESF_DZ_PE_PARSE_INCOMP_LBN 0 715#define ESF_DZ_PE_PARSE_INCOMP_WIDTH 1 716 717 718/* ES_FF_UMSG_RXDP_EGR2CPU_SOFT */ 719#define ESF_DZ_RE2CS_SOFT3_LBN 48 720#define ESF_DZ_RE2CS_SOFT3_WIDTH 16 721#define ESF_DZ_RE2CS_SOFT2_LBN 32 722#define ESF_DZ_RE2CS_SOFT2_WIDTH 16 723#define ESF_DZ_RE2CS_SOFT1_LBN 16 724#define ESF_DZ_RE2CS_SOFT1_WIDTH 16 725#define ESF_DZ_RE2CS_SOFT0_LBN 0 726#define ESF_DZ_RE2CS_SOFT0_WIDTH 16 727 728 729/* ES_FF_UMSG_RXDP_INGR2CPU */ 730#define ESF_DZ_RI2C_QUEUE_ID_LBN 224 731#define ESF_DZ_RI2C_QUEUE_ID_WIDTH 11 732#define ESF_DZ_RI2C_LEN_LBN 208 733#define ESF_DZ_RI2C_LEN_WIDTH 16 734#define ESF_DZ_RI2C_L4_CLASS_LBN 205 735#define ESF_DZ_RI2C_L4_CLASS_WIDTH 3 736#define ESF_DZ_RI2C_L3_CLASS_LBN 202 737#define ESF_DZ_RI2C_L3_CLASS_WIDTH 3 738#define ESF_DZ_RI2C_ETHTAG_CLASS_LBN 199 739#define ESF_DZ_RI2C_ETHTAG_CLASS_WIDTH 3 740#define ESF_DZ_RI2C_ETHBASE_CLASS_LBN 196 741#define ESF_DZ_RI2C_ETHBASE_CLASS_WIDTH 3 742#define ESF_DZ_RI2C_MAC_CLASS_LBN 195 743#define ESF_DZ_RI2C_MAC_CLASS_WIDTH 1 744#define ESF_DZ_RI2C_PKT_OFST_LBN 176 745#define ESF_DZ_RI2C_PKT_OFST_WIDTH 16 746#define ESF_DZ_RI2C_PEDIT_DELTA_LBN 168 747#define ESF_DZ_RI2C_PEDIT_DELTA_WIDTH 8 748#define ESF_DZ_RI2C_PYLOAD_OFST_LBN 160 749#define ESF_DZ_RI2C_PYLOAD_OFST_WIDTH 8 750#define ESF_DZ_RI2C_L4_HDR_OFST_LBN 152 751#define ESF_DZ_RI2C_L4_HDR_OFST_WIDTH 8 752#define ESF_DZ_RI2C_L3_HDR_OFST_LBN 144 753#define ESF_DZ_RI2C_L3_HDR_OFST_WIDTH 8 754#define ESF_DZ_RI2C_HAVE_UDP_HDR_LBN 133 755#define ESF_DZ_RI2C_HAVE_UDP_HDR_WIDTH 1 756#define ESF_DZ_RI2C_HAVE_TCP_HDR_LBN 132 757#define ESF_DZ_RI2C_HAVE_TCP_HDR_WIDTH 1 758#define ESF_DZ_RI2C_HAVE_IPV6_HDR_LBN 131 759#define ESF_DZ_RI2C_HAVE_IPV6_HDR_WIDTH 1 760#define ESF_DZ_RI2C_HAVE_IPV4_HDR_LBN 130 761#define ESF_DZ_RI2C_HAVE_IPV4_HDR_WIDTH 1 762#define ESF_DZ_RI2C_HAVE_FCOE_LBN 129 763#define ESF_DZ_RI2C_HAVE_FCOE_WIDTH 1 764#define ESF_DZ_RI2C_PARSE_INCOMP_LBN 128 765#define ESF_DZ_RI2C_PARSE_INCOMP_WIDTH 1 766#define ESF_DZ_RI2C_EFINFO_WRD3_LBN 112 767#define ESF_DZ_RI2C_EFINFO_WRD3_WIDTH 16 768#define ESF_DZ_RI2C_EFINFO_WRD2_LBN 96 769#define ESF_DZ_RI2C_EFINFO_WRD2_WIDTH 16 770#define ESF_DZ_RI2C_EFINFO_WRD1_LBN 80 771#define ESF_DZ_RI2C_EFINFO_WRD1_WIDTH 16 772#define ESF_DZ_RI2C_EFINFO_WRD0_LBN 64 773#define ESF_DZ_RI2C_EFINFO_WRD0_WIDTH 16 774#define ESF_DZ_RI2C_FINFO_WRD3_LBN 48 775#define ESF_DZ_RI2C_FINFO_WRD3_WIDTH 16 776#define ESF_DZ_RI2C_FINFO_WRD2_LBN 32 777#define ESF_DZ_RI2C_FINFO_WRD2_WIDTH 16 778#define ESF_DZ_RI2C_FINFO_WRD1_LBN 16 779#define ESF_DZ_RI2C_FINFO_WRD1_WIDTH 16 780#define ESF_DZ_RI2C_FINFO_SRCDST_LBN 0 781#define ESF_DZ_RI2C_FINFO_SRCDST_WIDTH 16 782 783 784/* ES_FF_UMSG_SMC2CPU_BUFLKUP */ 785#define ESF_DZ_S2CB_ENCODED_PAGE_ADDR_DW0_LBN 0 786#define ESF_DZ_S2CB_ENCODED_PAGE_ADDR_DW0_WIDTH 32 787#define ESF_DZ_S2CB_ENCODED_PAGE_ADDR_DW1_LBN 32 788#define ESF_DZ_S2CB_ENCODED_PAGE_ADDR_DW1_WIDTH 16 789#define ESF_DZ_S2CB_ENCODED_PAGE_ADDR_LBN 0 790#define ESF_DZ_S2CB_ENCODED_PAGE_ADDR_WIDTH 48 791#define ESF_DZ_S2CB_FAIL_LBN 32 792#define ESF_DZ_S2CB_FAIL_WIDTH 1 793 794 795/* ES_FF_UMSG_SMC2CPU_DESCRD */ 796#define ESF_DZ_S2CD_BUF_LEN_LBN 112 797#define ESF_DZ_S2CD_BUF_LEN_WIDTH 14 798#define ESF_DZ_S2CD_ENCODED_HOST_ADDR_DW0_LBN 64 799#define ESF_DZ_S2CD_ENCODED_HOST_ADDR_DW0_WIDTH 32 800#define ESF_DZ_S2CD_ENCODED_HOST_ADDR_DW1_LBN 96 801#define ESF_DZ_S2CD_ENCODED_HOST_ADDR_DW1_WIDTH 16 802#define ESF_DZ_S2CD_ENCODED_HOST_ADDR_LBN 64 803#define ESF_DZ_S2CD_ENCODED_HOST_ADDR_WIDTH 48 804#define ESF_DZ_S2CD_CONT_LBN 16 805#define ESF_DZ_S2CD_CONT_WIDTH 1 806#define ESF_DZ_S2CD_TYPE_LBN 0 807#define ESF_DZ_S2CD_TYPE_WIDTH 1 808 809 810/* ES_FF_UMSG_SMC2CPU_GPRD */ 811#define ESF_DZ_S2CG_DATA_DW0_LBN 64 812#define ESF_DZ_S2CG_DATA_DW0_WIDTH 32 813#define ESF_DZ_S2CG_DATA_DW1_LBN 96 814#define ESF_DZ_S2CG_DATA_DW1_WIDTH 32 815#define ESF_DZ_S2CG_DATA_LBN 64 816#define ESF_DZ_S2CG_DATA_WIDTH 64 817#define ESF_DZ_S2CG_SOFT_LBN 48 818#define ESF_DZ_S2CG_SOFT_WIDTH 4 819#define ESF_DZ_S2CG_FAIL_LBN 32 820#define ESF_DZ_S2CG_FAIL_WIDTH 1 821 822 823/* ES_FF_UMSG_TXDP_DMA2CPU_PKTRDY */ 824#define ESF_DZ_TD2CP_L4_CLASS_LBN 250 825#define ESF_DZ_TD2CP_L4_CLASS_WIDTH 3 826#define ESF_DZ_TD2CP_L3_CLASS_LBN 247 827#define ESF_DZ_TD2CP_L3_CLASS_WIDTH 3 828#define ESF_DZ_TD2CP_ETHTAG_CLASS_LBN 244 829#define ESF_DZ_TD2CP_ETHTAG_CLASS_WIDTH 3 830#define ESF_DZ_TD2CP_ETHBASE_CLASS_LBN 241 831#define ESF_DZ_TD2CP_ETHBASE_CLASS_WIDTH 3 832#define ESF_DZ_TD2CP_MAC_CLASS_LBN 240 833#define ESF_DZ_TD2CP_MAC_CLASS_WIDTH 1 834#define ESF_DZ_TD2CP_PCIE_ERR_OR_ABORT_LBN 239 835#define ESF_DZ_TD2CP_PCIE_ERR_OR_ABORT_WIDTH 1 836#define ESF_DZ_TD2CP_PKT_ABORT_LBN 238 837#define ESF_DZ_TD2CP_PKT_ABORT_WIDTH 1 838#define ESF_DZ_TD2CP_SOFT_LBN 224 839#define ESF_DZ_TD2CP_SOFT_WIDTH 14 840#define ESF_DZ_TD2CP_DESC_IDX_LBN 208 841#define ESF_DZ_TD2CP_DESC_IDX_WIDTH 16 842#define ESF_DZ_TD2CP_PKT_LEN_LBN 192 843#define ESF_DZ_TD2CP_PKT_LEN_WIDTH 16 844#define ESF_DZ_TD2CP_PKT_OFFST_OR_FIRST_DESC_IDX_LBN 176 845#define ESF_DZ_TD2CP_PKT_OFFST_OR_FIRST_DESC_IDX_WIDTH 7 846#define ESF_DZ_TD2CP_PEDIT_DELTA_LBN 168 847#define ESF_DZ_TD2CP_PEDIT_DELTA_WIDTH 8 848#define ESF_DZ_TD2CP_PYLOAD_OFST_LBN 160 849#define ESF_DZ_TD2CP_PYLOAD_OFST_WIDTH 8 850#define ESF_DZ_TD2CP_L4_HDR_OFST_LBN 152 851#define ESF_DZ_TD2CP_L4_HDR_OFST_WIDTH 8 852#define ESF_DZ_TD2CP_L3_HDR_OFST_LBN 144 853#define ESF_DZ_TD2CP_L3_HDR_OFST_WIDTH 8 854#define ESF_DZ_TD2CP_IS_UDP_LBN 133 855#define ESF_DZ_TD2CP_IS_UDP_WIDTH 1 856#define ESF_DZ_TD2CP_IS_TCP_LBN 132 857#define ESF_DZ_TD2CP_IS_TCP_WIDTH 1 858#define ESF_DZ_TD2CP_IS_IPV6_LBN 131 859#define ESF_DZ_TD2CP_IS_IPV6_WIDTH 1 860#define ESF_DZ_TD2CP_IS_IPV4_LBN 130 861#define ESF_DZ_TD2CP_IS_IPV4_WIDTH 1 862#define ESF_DZ_TD2CP_IS_FCOE_LBN 129 863#define ESF_DZ_TD2CP_IS_FCOE_WIDTH 1 864#define ESF_DZ_TD2CP_PARSE_INCOMP_LBN 128 865#define ESF_DZ_TD2CP_PARSE_INCOMP_WIDTH 1 866#define ESF_DZ_TD2CP_EFINFO_WRD3_LBN 112 867#define ESF_DZ_TD2CP_EFINFO_WRD3_WIDTH 16 868#define ESF_DZ_TD2CP_EFINFO_WRD2_LBN 96 869#define ESF_DZ_TD2CP_EFINFO_WRD2_WIDTH 16 870#define ESF_DZ_TD2CP_EFINFO_WRD1_LBN 80 871#define ESF_DZ_TD2CP_EFINFO_WRD1_WIDTH 16 872#define ESF_DZ_TD2CP_EFINFO_WRD0_LBN 64 873#define ESF_DZ_TD2CP_EFINFO_WRD0_WIDTH 16 874#define ESF_DZ_TD2CP_FINFO_WRD3_LBN 48 875#define ESF_DZ_TD2CP_FINFO_WRD3_WIDTH 16 876#define ESF_DZ_TD2CP_FINFO_WRD2_LBN 32 877#define ESF_DZ_TD2CP_FINFO_WRD2_WIDTH 16 878#define ESF_DZ_TD2CP_FINFO_WRD1_LBN 16 879#define ESF_DZ_TD2CP_FINFO_WRD1_WIDTH 16 880#define ESF_DZ_TD2CP_FINFO_SRCDST_LBN 0 881#define ESF_DZ_TD2CP_FINFO_SRCDST_WIDTH 16 882 883 884/* ES_FF_UMSG_TXDP_DMA2CPU_SOFT */ 885#define ESF_DZ_TD2CS_SOFT3_LBN 48 886#define ESF_DZ_TD2CS_SOFT3_WIDTH 16 887#define ESF_DZ_TD2CS_SOFT2_LBN 32 888#define ESF_DZ_TD2CS_SOFT2_WIDTH 16 889#define ESF_DZ_TD2CS_SOFT1_LBN 16 890#define ESF_DZ_TD2CS_SOFT1_WIDTH 16 891#define ESF_DZ_TD2CS_SOFT0_LBN 0 892#define ESF_DZ_TD2CS_SOFT0_WIDTH 16 893 894 895/* ES_FF_UMSG_TXDP_EGR2CPU_SOFT */ 896#define ESF_DZ_TE2CS_SOFT3_LBN 48 897#define ESF_DZ_TE2CS_SOFT3_WIDTH 16 898#define ESF_DZ_TE2CS_SOFT2_LBN 32 899#define ESF_DZ_TE2CS_SOFT2_WIDTH 16 900#define ESF_DZ_TE2CS_SOFT1_LBN 16 901#define ESF_DZ_TE2CS_SOFT1_WIDTH 16 902#define ESF_DZ_TE2CS_SOFT0_LBN 0 903#define ESF_DZ_TE2CS_SOFT0_WIDTH 16 904 905 906/* ES_FF_UMSG_VICTL2CPU */ 907#define ESF_DZ_V2C_DESC_WORD3_LBN 112 908#define ESF_DZ_V2C_DESC_WORD3_WIDTH 17 909#define ESF_DZ_V2C_DESC_WORD2_LBN 96 910#define ESF_DZ_V2C_DESC_WORD2_WIDTH 16 911#define ESF_DZ_V2C_DESC_WORD1_LBN 80 912#define ESF_DZ_V2C_DESC_WORD1_WIDTH 16 913#define ESF_DZ_V2C_DESC_WORD0_LBN 64 914#define ESF_DZ_V2C_DESC_WORD0_WIDTH 16 915#define ESF_DZ_V2C_NEW_DSCR_WPTR_LBN 32 916#define ESF_DZ_V2C_NEW_DSCR_WPTR_WIDTH 12 917#define ESF_DZ_V2C_DESC_PUSH_LBN 16 918#define ESF_DZ_V2C_DESC_PUSH_WIDTH 1 919 920 921/* ES_LUE_DB_MATCH_ENTRY */ 922#define ESF_DZ_LUE_DSCRMNTR_LBN 140 923#define ESF_DZ_LUE_DSCRMNTR_WIDTH 6 924#define ESF_DZ_LUE_MATCH_VAL_DW0_LBN 44 925#define ESF_DZ_LUE_MATCH_VAL_DW0_WIDTH 32 926#define ESF_DZ_LUE_MATCH_VAL_DW1_LBN 76 927#define ESF_DZ_LUE_MATCH_VAL_DW1_WIDTH 32 928#define ESF_DZ_LUE_MATCH_VAL_DW2_LBN 108 929#define ESF_DZ_LUE_MATCH_VAL_DW2_WIDTH 32 930#define ESF_DZ_LUE_MATCH_VAL_LBN 44 931#define ESF_DZ_LUE_MATCH_VAL_WIDTH 96 932#define ESF_DZ_LUE_ME_SOFT_LBN 35 933#define ESF_DZ_LUE_ME_SOFT_WIDTH 9 934#define ESF_DZ_LUE_TX_MCAST_LBN 33 935#define ESF_DZ_LUE_TX_MCAST_WIDTH 2 936#define ESF_DZ_LUE_TX_DOMAIN_LBN 25 937#define ESF_DZ_LUE_TX_DOMAIN_WIDTH 8 938#define ESF_DZ_LUE_RX_MCAST_LBN 24 939#define ESF_DZ_LUE_RX_MCAST_WIDTH 1 940#define ESE_DZ_LUE_MULTI 1 941#define ESE_DZ_LUE_SINGLE 0 942#define ESF_DZ_LUE_RCPNTR_LBN 0 943#define ESF_DZ_LUE_RCPNTR_WIDTH 24 944 945 946/* ES_LUE_DB_NONMATCH_ENTRY */ 947#define ESF_DZ_LUE_DSCRMNTR_LBN 140 948#define ESF_DZ_LUE_DSCRMNTR_WIDTH 6 949#define ESF_DZ_LUE_TERMINAL_LBN 139 950#define ESF_DZ_LUE_TERMINAL_WIDTH 1 951#define ESF_DZ_LUE_LAST_LBN 138 952#define ESF_DZ_LUE_LAST_WIDTH 1 953#define ESF_DZ_LUE_NE_SOFT_LBN 137 954#define ESF_DZ_LUE_NE_SOFT_WIDTH 1 955#define ESF_DZ_LUE_RCPNTR_NUM_LBN 134 956#define ESF_DZ_LUE_RCPNTR_NUM_WIDTH 3 957#define ESF_DZ_LUE_RCPNTR0_LBN 110 958#define ESF_DZ_LUE_RCPNTR0_WIDTH 24 959#define ESF_DZ_LUE_RCPNTR1_LBN 86 960#define ESF_DZ_LUE_RCPNTR1_WIDTH 24 961#define ESF_DZ_LUE_RCPNTR2_LBN 62 962#define ESF_DZ_LUE_RCPNTR2_WIDTH 24 963#define ESF_DZ_LUE_RCPNTR3_LBN 38 964#define ESF_DZ_LUE_RCPNTR3_WIDTH 24 965#define ESF_DZ_LUE_RCPNTR4_LBN 14 966#define ESF_DZ_LUE_RCPNTR4_WIDTH 24 967#define ESF_DZ_LUE_RCPNTR_NE_PTR_LBN 0 968#define ESF_DZ_LUE_RCPNTR_NE_PTR_WIDTH 14 969 970 971/* ES_LUE_MC_DIRECT_REQUEST_MSG */ 972#define ESF_DZ_MC2L_DR_PAD_DW0_LBN 22 973#define ESF_DZ_MC2L_DR_PAD_DW0_WIDTH 32 974#define ESF_DZ_MC2L_DR_PAD_DW1_LBN 54 975#define ESF_DZ_MC2L_DR_PAD_DW1_WIDTH 32 976#define ESF_DZ_MC2L_DR_PAD_DW2_LBN 86 977#define ESF_DZ_MC2L_DR_PAD_DW2_WIDTH 32 978#define ESF_DZ_MC2L_DR_PAD_DW3_LBN 118 979#define ESF_DZ_MC2L_DR_PAD_DW3_WIDTH 32 980#define ESF_DZ_MC2L_DR_PAD_DW4_LBN 150 981#define ESF_DZ_MC2L_DR_PAD_DW4_WIDTH 18 982#define ESF_DZ_MC2L_DR_PAD_LBN 22 983#define ESF_DZ_MC2L_DR_PAD_WIDTH 146 984#define ESF_DZ_MC2L_DR_ADDR_LBN 8 985#define ESF_DZ_MC2L_DR_ADDR_WIDTH 14 986#define ESF_DZ_MC2L_DR_THREAD_ID_LBN 5 987#define ESF_DZ_MC2L_DR_THREAD_ID_WIDTH 3 988#define ESF_DZ_MC2L_DR_CLIENT_ID_LBN 2 989#define ESF_DZ_MC2L_DR_CLIENT_ID_WIDTH 3 990#define ESF_DZ_MC2L_DR_OP_LBN 0 991#define ESF_DZ_MC2L_DR_OP_WIDTH 2 992#define ESE_DZ_LUE_GP_WR 3 993#define ESE_DZ_LUE_GP_RD 2 994#define ESE_DZ_LUE_DIR_REQ 1 995#define ESE_DZ_LUE_MATCH_REQ 0 996 997 998/* ES_LUE_MC_DIRECT_RESPONSE_MSG */ 999#define ESF_DZ_L2MC_DR_PAD_LBN 146 1000#define ESF_DZ_L2MC_DR_PAD_WIDTH 8 1001#define ESF_DZ_L2MC_DR_RCPNT_PTR_LBN 132 1002#define ESF_DZ_L2MC_DR_RCPNT_PTR_WIDTH 14 1003#define ESF_DZ_L2MC_DR_RCPNT4_LBN 108 1004#define ESF_DZ_L2MC_DR_RCPNT4_WIDTH 24 1005#define ESF_DZ_L2MC_DR_RCPNT3_LBN 84 1006#define ESF_DZ_L2MC_DR_RCPNT3_WIDTH 24 1007#define ESF_DZ_L2MC_DR_RCPNT2_LBN 60 1008#define ESF_DZ_L2MC_DR_RCPNT2_WIDTH 24 1009#define ESF_DZ_L2MC_DR_RCPNT1_LBN 36 1010#define ESF_DZ_L2MC_DR_RCPNT1_WIDTH 24 1011#define ESF_DZ_L2MC_DR_RCPNT0_LBN 12 1012#define ESF_DZ_L2MC_DR_RCPNT0_WIDTH 24 1013#define ESF_DZ_L2MC_DR_RCPNT_NUM_LBN 9 1014#define ESF_DZ_L2MC_DR_RCPNT_NUM_WIDTH 3 1015#define ESF_DZ_L2MC_DR_LAST_LBN 8 1016#define ESF_DZ_L2MC_DR_LAST_WIDTH 1 1017#define ESF_DZ_L2MC_DR_THREAD_ID_LBN 5 1018#define ESF_DZ_L2MC_DR_THREAD_ID_WIDTH 3 1019#define ESF_DZ_L2MC_DR_CLIENT_ID_LBN 2 1020#define ESF_DZ_L2MC_DR_CLIENT_ID_WIDTH 3 1021#define ESF_DZ_L2MC_DR_OP_LBN 0 1022#define ESF_DZ_L2MC_DR_OP_WIDTH 2 1023#define ESE_DZ_LUE_GP_WR 3 1024#define ESE_DZ_LUE_GP_RD 2 1025#define ESE_DZ_LUE_DIR_REQ 1 1026#define ESE_DZ_LUE_MATCH_REQ 0 1027 1028 1029/* ES_LUE_MC_GP_RD_REQUEST_MSG */ 1030#define ESF_DZ_MC2L_GPR_PAD_DW0_LBN 22 1031#define ESF_DZ_MC2L_GPR_PAD_DW0_WIDTH 32 1032#define ESF_DZ_MC2L_GPR_PAD_DW1_LBN 54 1033#define ESF_DZ_MC2L_GPR_PAD_DW1_WIDTH 32 1034#define ESF_DZ_MC2L_GPR_PAD_DW2_LBN 86 1035#define ESF_DZ_MC2L_GPR_PAD_DW2_WIDTH 32 1036#define ESF_DZ_MC2L_GPR_PAD_DW3_LBN 118 1037#define ESF_DZ_MC2L_GPR_PAD_DW3_WIDTH 32 1038#define ESF_DZ_MC2L_GPR_PAD_DW4_LBN 150 1039#define ESF_DZ_MC2L_GPR_PAD_DW4_WIDTH 18 1040#define ESF_DZ_MC2L_GPR_PAD_LBN 22 1041#define ESF_DZ_MC2L_GPR_PAD_WIDTH 146 1042#define ESF_DZ_MC2L_GPR_ADDR_LBN 8 1043#define ESF_DZ_MC2L_GPR_ADDR_WIDTH 14 1044#define ESF_DZ_MC2L_GPR_THREAD_ID_LBN 5 1045#define ESF_DZ_MC2L_GPR_THREAD_ID_WIDTH 3 1046#define ESF_DZ_MC2L_GPR_CLIENT_ID_LBN 2 1047#define ESF_DZ_MC2L_GPR_CLIENT_ID_WIDTH 3 1048#define ESF_DZ_MC2L_GPR_OP_LBN 0 1049#define ESF_DZ_MC2L_GPR_OP_WIDTH 2 1050#define ESE_DZ_LUE_GP_WR 3 1051#define ESE_DZ_LUE_GP_RD 2 1052#define ESE_DZ_LUE_DIR_REQ 1 1053#define ESE_DZ_LUE_MATCH_REQ 0 1054 1055 1056/* ES_LUE_MC_GP_RD_RESPONSE_MSG */ 1057#define ESF_DZ_L2MC_GPR_DATA_DW0_LBN 8 1058#define ESF_DZ_L2MC_GPR_DATA_DW0_WIDTH 32 1059#define ESF_DZ_L2MC_GPR_DATA_DW1_LBN 40 1060#define ESF_DZ_L2MC_GPR_DATA_DW1_WIDTH 32 1061#define ESF_DZ_L2MC_GPR_DATA_DW2_LBN 72 1062#define ESF_DZ_L2MC_GPR_DATA_DW2_WIDTH 32 1063#define ESF_DZ_L2MC_GPR_DATA_DW3_LBN 104 1064#define ESF_DZ_L2MC_GPR_DATA_DW3_WIDTH 32 1065#define ESF_DZ_L2MC_GPR_DATA_DW4_LBN 136 1066#define ESF_DZ_L2MC_GPR_DATA_DW4_WIDTH 18 1067#define ESF_DZ_L2MC_GPR_DATA_LBN 8 1068#define ESF_DZ_L2MC_GPR_DATA_WIDTH 146 1069#define ESF_DZ_L2MC_GPR_THREAD_ID_LBN 5 1070#define ESF_DZ_L2MC_GPR_THREAD_ID_WIDTH 3 1071#define ESF_DZ_L2MC_GPR_CLIENT_ID_LBN 2 1072#define ESF_DZ_L2MC_GPR_CLIENT_ID_WIDTH 3 1073#define ESF_DZ_L2MC_GPR_OP_LBN 0 1074#define ESF_DZ_L2MC_GPR_OP_WIDTH 2 1075#define ESE_DZ_LUE_GP_WR 3 1076#define ESE_DZ_LUE_GP_RD 2 1077#define ESE_DZ_LUE_DIR_REQ 1 1078#define ESE_DZ_LUE_MATCH_REQ 0 1079 1080 1081/* ES_LUE_MC_GP_WR_REQUEST_MSG */ 1082#define ESF_DZ_MC2L_GPW_DATA_DW0_LBN 22 1083#define ESF_DZ_MC2L_GPW_DATA_DW0_WIDTH 32 1084#define ESF_DZ_MC2L_GPW_DATA_DW1_LBN 54 1085#define ESF_DZ_MC2L_GPW_DATA_DW1_WIDTH 32 1086#define ESF_DZ_MC2L_GPW_DATA_DW2_LBN 86 1087#define ESF_DZ_MC2L_GPW_DATA_DW2_WIDTH 32 1088#define ESF_DZ_MC2L_GPW_DATA_DW3_LBN 118 1089#define ESF_DZ_MC2L_GPW_DATA_DW3_WIDTH 32 1090#define ESF_DZ_MC2L_GPW_DATA_DW4_LBN 150 1091#define ESF_DZ_MC2L_GPW_DATA_DW4_WIDTH 18 1092#define ESF_DZ_MC2L_GPW_DATA_LBN 22 1093#define ESF_DZ_MC2L_GPW_DATA_WIDTH 146 1094#define ESF_DZ_MC2L_GPW_ADDR_LBN 8 1095#define ESF_DZ_MC2L_GPW_ADDR_WIDTH 14 1096#define ESF_DZ_MC2L_GPW_THREAD_ID_LBN 5 1097#define ESF_DZ_MC2L_GPW_THREAD_ID_WIDTH 3 1098#define ESF_DZ_MC2L_GPW_CLIENT_ID_LBN 2 1099#define ESF_DZ_MC2L_GPW_CLIENT_ID_WIDTH 3 1100#define ESF_DZ_MC2L_GPW_OP_LBN 0 1101#define ESF_DZ_MC2L_GPW_OP_WIDTH 2 1102#define ESE_DZ_LUE_GP_WR 3 1103#define ESE_DZ_LUE_GP_RD 2 1104#define ESE_DZ_LUE_DIR_REQ 1 1105#define ESE_DZ_LUE_MATCH_REQ 0 1106 1107 1108/* ES_LUE_MC_MATCH_REQUEST_MSG */ 1109#define ESF_DZ_MC2L_MR_PAD_LBN 137 1110#define ESF_DZ_MC2L_MR_PAD_WIDTH 31 1111#define ESF_DZ_MC2L_MR_HASH2_LBN 124 1112#define ESF_DZ_MC2L_MR_HASH2_WIDTH 13 1113#define ESF_DZ_MC2L_MR_HASH1_LBN 110 1114#define ESF_DZ_MC2L_MR_HASH1_WIDTH 14 1115#define ESF_DZ_MC2L_MR_MATCH_BITS_DW0_LBN 14 1116#define ESF_DZ_MC2L_MR_MATCH_BITS_DW0_WIDTH 32 1117#define ESF_DZ_MC2L_MR_MATCH_BITS_DW1_LBN 46 1118#define ESF_DZ_MC2L_MR_MATCH_BITS_DW1_WIDTH 32 1119#define ESF_DZ_MC2L_MR_MATCH_BITS_DW2_LBN 78 1120#define ESF_DZ_MC2L_MR_MATCH_BITS_DW2_WIDTH 32 1121#define ESF_DZ_MC2L_MR_MATCH_BITS_LBN 14 1122#define ESF_DZ_MC2L_MR_MATCH_BITS_WIDTH 96 1123#define ESF_DZ_MC2L_MR_DSCRMNTR_LBN 8 1124#define ESF_DZ_MC2L_MR_DSCRMNTR_WIDTH 6 1125#define ESF_DZ_MC2L_MR_THREAD_ID_LBN 5 1126#define ESF_DZ_MC2L_MR_THREAD_ID_WIDTH 3 1127#define ESF_DZ_MC2L_MR_CLIENT_ID_LBN 2 1128#define ESF_DZ_MC2L_MR_CLIENT_ID_WIDTH 3 1129#define ESF_DZ_MC2L_MR_OP_LBN 0 1130#define ESF_DZ_MC2L_MR_OP_WIDTH 2 1131#define ESE_DZ_LUE_GP_WR 3 1132#define ESE_DZ_LUE_GP_RD 2 1133#define ESE_DZ_LUE_DIR_REQ 1 1134#define ESE_DZ_LUE_MATCH_REQ 0 1135 1136 1137/* ES_LUE_MC_MATCH_RESPONSE_MSG */ 1138#define ESF_DZ_L2MC_MR_PAD_DW0_LBN 53 1139#define ESF_DZ_L2MC_MR_PAD_DW0_WIDTH 32 1140#define ESF_DZ_L2MC_MR_PAD_DW1_LBN 85 1141#define ESF_DZ_L2MC_MR_PAD_DW1_WIDTH 32 1142#define ESF_DZ_L2MC_MR_PAD_DW2_LBN 117 1143#define ESF_DZ_L2MC_MR_PAD_DW2_WIDTH 32 1144#define ESF_DZ_L2MC_MR_PAD_DW3_LBN 149 1145#define ESF_DZ_L2MC_MR_PAD_DW3_WIDTH 5 1146#define ESF_DZ_L2MC_MR_PAD_LBN 53 1147#define ESF_DZ_L2MC_MR_PAD_WIDTH 101 1148#define ESF_DZ_L2MC_MR_LUE_RCPNT_LBN 29 1149#define ESF_DZ_L2MC_MR_LUE_RCPNT_WIDTH 24 1150#define ESF_DZ_L2MC_MR_RX_MCAST_LBN 28 1151#define ESF_DZ_L2MC_MR_RX_MCAST_WIDTH 1 1152#define ESF_DZ_L2MC_MR_TX_DOMAIN_LBN 20 1153#define ESF_DZ_L2MC_MR_TX_DOMAIN_WIDTH 8 1154#define ESF_DZ_L2MC_MR_TX_MCAST_LBN 18 1155#define ESF_DZ_L2MC_MR_TX_MCAST_WIDTH 2 1156#define ESF_DZ_L2MC_MR_SOFT_LBN 9 1157#define ESF_DZ_L2MC_MR_SOFT_WIDTH 9 1158#define ESF_DZ_L2MC_MR_MATCH_LBN 8 1159#define ESF_DZ_L2MC_MR_MATCH_WIDTH 1 1160#define ESF_DZ_L2MC_MR_THREAD_ID_LBN 5 1161#define ESF_DZ_L2MC_MR_THREAD_ID_WIDTH 3 1162#define ESF_DZ_L2MC_MR_CLIENT_ID_LBN 2 1163#define ESF_DZ_L2MC_MR_CLIENT_ID_WIDTH 3 1164#define ESF_DZ_L2MC_MR_OP_LBN 0 1165#define ESF_DZ_L2MC_MR_OP_WIDTH 2 1166#define ESE_DZ_LUE_GP_WR 3 1167#define ESE_DZ_LUE_GP_RD 2 1168#define ESE_DZ_LUE_DIR_REQ 1 1169#define ESE_DZ_LUE_MATCH_REQ 0 1170 1171 1172/* ES_LUE_MSG_BASE_REQ */ 1173#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW0_LBN 8 1174#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW0_WIDTH 32 1175#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW1_LBN 40 1176#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW1_WIDTH 32 1177#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW2_LBN 72 1178#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW2_WIDTH 32 1179#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW3_LBN 104 1180#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW3_WIDTH 32 1181#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW4_LBN 136 1182#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_DW4_WIDTH 32 1183#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_LBN 8 1184#define ESF_DZ_LUE_HW_REQ_BASE_REQ_MSG_DATA_WIDTH 160 1185#define ESF_DZ_LUE_HW_REQ_BASE_THREAD_ID_LBN 5 1186#define ESF_DZ_LUE_HW_REQ_BASE_THREAD_ID_WIDTH 3 1187#define ESF_DZ_LUE_HW_REQ_BASE_CLIENT_ID_LBN 2 1188#define ESF_DZ_LUE_HW_REQ_BASE_CLIENT_ID_WIDTH 3 1189#define ESE_DZ_LUE_MC_ID 7 1190#define ESE_DZ_LUE_MATCH_REQ_FIFO_ID 3 1191#define ESE_DZ_LUE_TX_DICPU_ID 1 1192#define ESE_DZ_LUE_RX_DICPU_ID 0 1193#define ESF_DZ_LUE_HW_REQ_BASE_OP_LBN 0 1194#define ESF_DZ_LUE_HW_REQ_BASE_OP_WIDTH 2 1195#define ESE_DZ_LUE_GP_WR 3 1196#define ESE_DZ_LUE_GP_RD 2 1197#define ESE_DZ_LUE_DIR_REQ 1 1198#define ESE_DZ_LUE_MATCH_REQ 0 1199 1200 1201/* ES_LUE_MSG_BASE_RESP */ 1202#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW0_LBN 8 1203#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW0_WIDTH 32 1204#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW1_LBN 40 1205#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW1_WIDTH 32 1206#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW2_LBN 72 1207#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW2_WIDTH 32 1208#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW3_LBN 104 1209#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW3_WIDTH 32 1210#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW4_LBN 136 1211#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_DW4_WIDTH 18 1212#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_LBN 8 1213#define ESF_DZ_LUE_HW_RSP_BASE_RSP_DATA_WIDTH 146 1214#define ESF_DZ_LUE_HW_RSP_BASE_THREAD_ID_LBN 5 1215#define ESF_DZ_LUE_HW_RSP_BASE_THREAD_ID_WIDTH 3 1216#define ESF_DZ_LUE_HW_RSP_BASE_CLIENT_ID_LBN 2 1217#define ESF_DZ_LUE_HW_RSP_BASE_CLIENT_ID_WIDTH 3 1218#define ESE_DZ_LUE_MC_ID 7 1219#define ESE_DZ_LUE_MATCH_REQ_FIFO_ID 3 1220#define ESE_DZ_LUE_TX_DICPU_ID 1 1221#define ESE_DZ_LUE_RX_DICPU_ID 0 1222#define ESF_DZ_LUE_HW_RSP_BASE_OP_LBN 0 1223#define ESF_DZ_LUE_HW_RSP_BASE_OP_WIDTH 2 1224#define ESE_DZ_LUE_GP_WR 3 1225#define ESE_DZ_LUE_GP_RD 2 1226#define ESE_DZ_LUE_DIR_REQ 1 1227#define ESE_DZ_LUE_MATCH_REQ 0 1228 1229 1230/* ES_LUE_MSG_DIRECT_REQ */ 1231#define ESF_DZ_LUE_HW_REQ_DIR_ADDR_LBN 8 1232#define ESF_DZ_LUE_HW_REQ_DIR_ADDR_WIDTH 14 1233#define ESF_DZ_LUE_HW_REQ_DIR_THREAD_ID_LBN 5 1234#define ESF_DZ_LUE_HW_REQ_DIR_THREAD_ID_WIDTH 3 1235#define ESF_DZ_LUE_HW_REQ_DIR_CLIENT_ID_LBN 2 1236#define ESF_DZ_LUE_HW_REQ_DIR_CLIENT_ID_WIDTH 3 1237#define ESE_DZ_LUE_MC_ID 7 1238#define ESE_DZ_LUE_MATCH_REQ_FIFO_ID 3 1239#define ESE_DZ_LUE_TX_DICPU_ID 1 1240#define ESE_DZ_LUE_RX_DICPU_ID 0 1241#define ESF_DZ_LUE_HW_REQ_DIR_OP_LBN 0 1242#define ESF_DZ_LUE_HW_REQ_DIR_OP_WIDTH 2 1243#define ESE_DZ_LUE_GP_WR 3 1244#define ESE_DZ_LUE_GP_RD 2 1245#define ESE_DZ_LUE_DIR_REQ 1 1246#define ESE_DZ_LUE_MATCH_REQ 0 1247 1248 1249/* ES_LUE_MSG_DIRECT_RESP */ 1250#define ESF_DZ_LUE_HW_RSP_DIR_RCPNT_PTR_LBN 132 1251#define ESF_DZ_LUE_HW_RSP_DIR_RCPNT_PTR_WIDTH 14 1252#define ESF_DZ_LUE_HW_RSP_DIR_RCPNT4_LBN 108 1253#define ESF_DZ_LUE_HW_RSP_DIR_RCPNT4_WIDTH 24 1254#define ESF_DZ_LUE_HW_RSP_DIR_RCPNT3_LBN 84 1255#define ESF_DZ_LUE_HW_RSP_DIR_RCPNT3_WIDTH 24 1256#define ESF_DZ_LUE_HW_RSP_DIR_RCPNT2_LBN 60 1257#define ESF_DZ_LUE_HW_RSP_DIR_RCPNT2_WIDTH 24 1258#define ESF_DZ_LUE_HW_RSP_DIR_RCPNT1_LBN 36 1259#define ESF_DZ_LUE_HW_RSP_DIR_RCPNT1_WIDTH 24 1260#define ESF_DZ_LUE_HW_RSP_DIR_RCPNT0_LBN 12 1261#define ESF_DZ_LUE_HW_RSP_DIR_RCPNT0_WIDTH 24 1262#define ESF_DZ_LUE_HW_RSP_DIR_RCPNT_NUM_LBN 9 1263#define ESF_DZ_LUE_HW_RSP_DIR_RCPNT_NUM_WIDTH 3 1264#define ESF_DZ_LUE_HW_RSP_DIR_LAST_LBN 8 1265#define ESF_DZ_LUE_HW_RSP_DIR_LAST_WIDTH 1 1266#define ESF_DZ_LUE_HW_RSP_DIR_THREAD_ID_LBN 5 1267#define ESF_DZ_LUE_HW_RSP_DIR_THREAD_ID_WIDTH 3 1268#define ESF_DZ_LUE_HW_RSP_DIR_CLIENT_ID_LBN 2 1269#define ESF_DZ_LUE_HW_RSP_DIR_CLIENT_ID_WIDTH 3 1270#define ESE_DZ_LUE_MC_ID 7 1271#define ESE_DZ_LUE_MATCH_REQ_FIFO_ID 3 1272#define ESE_DZ_LUE_TX_DICPU_ID 1 1273#define ESE_DZ_LUE_RX_DICPU_ID 0 1274#define ESF_DZ_LUE_HW_RSP_DIR_OP_LBN 0 1275#define ESF_DZ_LUE_HW_RSP_DIR_OP_WIDTH 2 1276#define ESE_DZ_LUE_GP_WR 3 1277#define ESE_DZ_LUE_GP_RD 2 1278#define ESE_DZ_LUE_DIR_REQ 1 1279#define ESE_DZ_LUE_MATCH_REQ 0 1280 1281 1282/* ES_LUE_MSG_GP_RD_REQ */ 1283#define ESF_DZ_LUE_HW_REQ_GPRD_ADDR_LBN 8 1284#define ESF_DZ_LUE_HW_REQ_GPRD_ADDR_WIDTH 14 1285#define ESF_DZ_LUE_HW_REQ_GPRD_THREAD_ID_LBN 5 1286#define ESF_DZ_LUE_HW_REQ_GPRD_THREAD_ID_WIDTH 3 1287#define ESF_DZ_LUE_HW_REQ_GPRD_CLIENT_ID_LBN 2 1288#define ESF_DZ_LUE_HW_REQ_GPRD_CLIENT_ID_WIDTH 3 1289#define ESE_DZ_LUE_MC_ID 7 1290#define ESE_DZ_LUE_MATCH_REQ_FIFO_ID 3 1291#define ESE_DZ_LUE_TX_DICPU_ID 1 1292#define ESE_DZ_LUE_RX_DICPU_ID 0 1293#define ESF_DZ_LUE_HW_REQ_GPRD_OP_LBN 0 1294#define ESF_DZ_LUE_HW_REQ_GPRD_OP_WIDTH 2 1295#define ESE_DZ_LUE_GP_WR 3 1296#define ESE_DZ_LUE_GP_RD 2 1297#define ESE_DZ_LUE_DIR_REQ 1 1298#define ESE_DZ_LUE_MATCH_REQ 0 1299 1300 1301/* ES_LUE_MSG_GP_RD_RESP */ 1302#define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW0_LBN 8 1303#define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW0_WIDTH 32 1304#define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW1_LBN 40 1305#define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW1_WIDTH 32 1306#define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW2_LBN 72 1307#define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW2_WIDTH 32 1308#define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW3_LBN 104 1309#define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW3_WIDTH 32 1310#define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW4_LBN 136 1311#define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_DW4_WIDTH 18 1312#define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_LBN 8 1313#define ESF_DZ_LUE_HW_RSP_GPRD_LUE_DATA_WIDTH 146 1314#define ESF_DZ_LUE_HW_RSP_GPRD_THREAD_ID_LBN 5 1315#define ESF_DZ_LUE_HW_RSP_GPRD_THREAD_ID_WIDTH 3 1316#define ESF_DZ_LUE_HW_RSP_GPRD_CLIENT_ID_LBN 2 1317#define ESF_DZ_LUE_HW_RSP_GPRD_CLIENT_ID_WIDTH 3 1318#define ESE_DZ_LUE_MC_ID 7 1319#define ESE_DZ_LUE_MATCH_REQ_FIFO_ID 3 1320#define ESE_DZ_LUE_TX_DICPU_ID 1 1321#define ESE_DZ_LUE_RX_DICPU_ID 0 1322#define ESF_DZ_LUE_HW_RSP_GPRD_OP_LBN 0 1323#define ESF_DZ_LUE_HW_RSP_GPRD_OP_WIDTH 2 1324#define ESE_DZ_LUE_GP_WR 3 1325#define ESE_DZ_LUE_GP_RD 2 1326#define ESE_DZ_LUE_DIR_REQ 1 1327#define ESE_DZ_LUE_MATCH_REQ 0 1328 1329 1330/* ES_LUE_MSG_GP_WR_REQ */ 1331#define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW0_LBN 22 1332#define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW0_WIDTH 32 1333#define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW1_LBN 54 1334#define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW1_WIDTH 32 1335#define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW2_LBN 86 1336#define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW2_WIDTH 32 1337#define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW3_LBN 118 1338#define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW3_WIDTH 32 1339#define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW4_LBN 150 1340#define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_DW4_WIDTH 18 1341#define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_LBN 22 1342#define ESF_DZ_LUE_HW_REQ_GPWR_LUE_DATA_WIDTH 146 1343#define ESF_DZ_LUE_HW_REQ_GPWR_ADDR_LBN 8 1344#define ESF_DZ_LUE_HW_REQ_GPWR_ADDR_WIDTH 14 1345#define ESF_DZ_LUE_HW_REQ_GPWR_THREAD_ID_LBN 5 1346#define ESF_DZ_LUE_HW_REQ_GPWR_THREAD_ID_WIDTH 3 1347#define ESF_DZ_LUE_HW_REQ_GPWR_CLIENT_ID_LBN 2 1348#define ESF_DZ_LUE_HW_REQ_GPWR_CLIENT_ID_WIDTH 3 1349#define ESE_DZ_LUE_MC_ID 7 1350#define ESE_DZ_LUE_MATCH_REQ_FIFO_ID 3 1351#define ESE_DZ_LUE_TX_DICPU_ID 1 1352#define ESE_DZ_LUE_RX_DICPU_ID 0 1353#define ESF_DZ_LUE_HW_REQ_GPWR_OP_LBN 0 1354#define ESF_DZ_LUE_HW_REQ_GPWR_OP_WIDTH 2 1355#define ESE_DZ_LUE_GP_WR 3 1356#define ESE_DZ_LUE_GP_RD 2 1357#define ESE_DZ_LUE_DIR_REQ 1 1358#define ESE_DZ_LUE_MATCH_REQ 0 1359 1360 1361/* ES_LUE_MSG_MATCH_REQ */ 1362#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_REQ_COUNT_LBN 137 1363#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_REQ_COUNT_WIDTH 8 1364#define ESF_DZ_LUE_HW_REQ_MATCH_HASH2_LBN 124 1365#define ESF_DZ_LUE_HW_REQ_MATCH_HASH2_WIDTH 13 1366#define ESF_DZ_LUE_HW_REQ_MATCH_HASH1_LBN 110 1367#define ESF_DZ_LUE_HW_REQ_MATCH_HASH1_WIDTH 14 1368#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW0_LBN 14 1369#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW0_WIDTH 32 1370#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW1_LBN 46 1371#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW1_WIDTH 32 1372#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW2_LBN 78 1373#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_DW2_WIDTH 32 1374#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_LBN 14 1375#define ESF_DZ_LUE_HW_REQ_MATCH_MATCH_BITS_WIDTH 96 1376#define ESF_DZ_LUE_HW_REQ_MATCH_DSCRMNTR_LBN 8 1377#define ESF_DZ_LUE_HW_REQ_MATCH_DSCRMNTR_WIDTH 6 1378#define ESF_DZ_LUE_HW_REQ_MATCH_THREAD_ID_LBN 5 1379#define ESF_DZ_LUE_HW_REQ_MATCH_THREAD_ID_WIDTH 3 1380#define ESF_DZ_LUE_HW_REQ_MATCH_CLIENT_ID_LBN 2 1381#define ESF_DZ_LUE_HW_REQ_MATCH_CLIENT_ID_WIDTH 3 1382#define ESE_DZ_LUE_MC_ID 7 1383#define ESE_DZ_LUE_MATCH_REQ_FIFO_ID 3 1384#define ESE_DZ_LUE_TX_DICPU_ID 1 1385#define ESE_DZ_LUE_RX_DICPU_ID 0 1386#define ESF_DZ_LUE_HW_REQ_MATCH_OP_LBN 0 1387#define ESF_DZ_LUE_HW_REQ_MATCH_OP_WIDTH 2 1388#define ESE_DZ_LUE_GP_WR 3 1389#define ESE_DZ_LUE_GP_RD 2 1390#define ESE_DZ_LUE_DIR_REQ 1 1391#define ESE_DZ_LUE_MATCH_REQ 0 1392 1393 1394/* ES_LUE_MSG_MATCH_RESP */ 1395#define ESF_DZ_LUE_HW_RSP_MATCH_LUE_RCPNT_LBN 29 1396#define ESF_DZ_LUE_HW_RSP_MATCH_LUE_RCPNT_WIDTH 24 1397#define ESF_DZ_LUE_HW_RSP_MATCH_RX_MCAST_LBN 28 1398#define ESF_DZ_LUE_HW_RSP_MATCH_RX_MCAST_WIDTH 1 1399#define ESF_DZ_LUE_HW_RSP_MATCH_TX_DOMAIN_LBN 20 1400#define ESF_DZ_LUE_HW_RSP_MATCH_TX_DOMAIN_WIDTH 8 1401#define ESF_DZ_LUE_HW_RSP_MATCH_TX_MCAST_LBN 18 1402#define ESF_DZ_LUE_HW_RSP_MATCH_TX_MCAST_WIDTH 2 1403#define ESF_DZ_LUE_HW_RSP_MATCH_SOFT_LBN 9 1404#define ESF_DZ_LUE_HW_RSP_MATCH_SOFT_WIDTH 9 1405#define ESF_DZ_LUE_HW_RSP_MATCH_MATCH_LBN 8 1406#define ESF_DZ_LUE_HW_RSP_MATCH_MATCH_WIDTH 1 1407#define ESF_DZ_LUE_HW_RSP_MATCH_THREAD_ID_LBN 5 1408#define ESF_DZ_LUE_HW_RSP_MATCH_THREAD_ID_WIDTH 3 1409#define ESF_DZ_LUE_HW_RSP_MATCH_CLIENT_ID_LBN 2 1410#define ESF_DZ_LUE_HW_RSP_MATCH_CLIENT_ID_WIDTH 3 1411#define ESE_DZ_LUE_MC_ID 7 1412#define ESE_DZ_LUE_MATCH_REQ_FIFO_ID 3 1413#define ESE_DZ_LUE_TX_DICPU_ID 1 1414#define ESE_DZ_LUE_RX_DICPU_ID 0 1415#define ESF_DZ_LUE_HW_RSP_MATCH_OP_LBN 0 1416#define ESF_DZ_LUE_HW_RSP_MATCH_OP_WIDTH 2 1417#define ESE_DZ_LUE_GP_WR 3 1418#define ESE_DZ_LUE_GP_RD 2 1419#define ESE_DZ_LUE_DIR_REQ 1 1420#define ESE_DZ_LUE_MATCH_REQ 0 1421 1422 1423/* ES_LUE_RCPNTR_TYPE */ 1424#define ESF_DZ_LUE_RXQ_LBN 14 1425#define ESF_DZ_LUE_RXQ_WIDTH 10 1426#define ESF_DZ_LUE_RSS_INFO_LBN 8 1427#define ESF_DZ_LUE_RSS_INFO_WIDTH 6 1428#define ESF_DZ_LUE_DEST_LBN 5 1429#define ESF_DZ_LUE_DEST_WIDTH 3 1430#define ESF_DZ_LUE_SOFT_LBN 0 1431#define ESF_DZ_LUE_SOFT_WIDTH 5 1432 1433 1434/* ES_LUE_UMSG_LU2DI_HASH_RESP */ 1435#define ESF_DZ_L2DHR_LASTREC_ENTRY_STATUS_LBN 50 1436#define ESF_DZ_L2DHR_LASTREC_ENTRY_STATUS_WIDTH 1 1437#define ESF_DZ_L2DHR_MULTITYPE_STATUS_LBN 50 1438#define ESF_DZ_L2DHR_MULTITYPE_STATUS_WIDTH 1 1439#define ESF_DZ_L2DHR_LASTREC_STATUS_LBN 49 1440#define ESF_DZ_L2DHR_LASTREC_STATUS_WIDTH 1 1441#define ESF_DZ_L2DHR_MATCH_STATUS_LBN 48 1442#define ESF_DZ_L2DHR_MATCH_STATUS_WIDTH 1 1443#define ESF_DZ_L2DHR_HASH_LBN 0 1444#define ESF_DZ_L2DHR_HASH_WIDTH 32 1445 1446 1447/* ES_LUE_UMSG_LU2DI_RXLU_MULTI_MATCH_RESP */ 1448#define ESF_DZ_L2DRMMR_SOFT_LBN 112 1449#define ESF_DZ_L2DRMMR_SOFT_WIDTH 9 1450#define ESF_DZ_L2DRMMR_RCPNTR_PTR_LBN 96 1451#define ESF_DZ_L2DRMMR_RCPNTR_PTR_WIDTH 14 1452#define ESF_DZ_L2DRMMR_TX_MCAST_LBN 80 1453#define ESF_DZ_L2DRMMR_TX_MCAST_WIDTH 2 1454#define ESF_DZ_L2DRMMR_MULTITYPE_STATUS_LBN 67 1455#define ESF_DZ_L2DRMMR_MULTITYPE_STATUS_WIDTH 1 1456#define ESF_DZ_L2DRMMR_LASTREC_ENTRY_STATUS_LBN 66 1457#define ESF_DZ_L2DRMMR_LASTREC_ENTRY_STATUS_WIDTH 1 1458#define ESF_DZ_L2DRMMR_LASTREC_STATUS_LBN 65 1459#define ESF_DZ_L2DRMMR_LASTREC_STATUS_WIDTH 1 1460#define ESF_DZ_L2DRMMR_MATCH_STATUS_LBN 64 1461#define ESF_DZ_L2DRMMR_MATCH_STATUS_WIDTH 1 1462 1463 1464/* ES_LUE_UMSG_LU2DI_RXLU_MULTI_RECORD_RESP */ 1465#define ESF_DZ_L2DRMRR_SOFT_LBN 112 1466#define ESF_DZ_L2DRMRR_SOFT_WIDTH 9 1467#define ESF_DZ_L2DRMRR_RCPNTR_PTR_LBN 96 1468#define ESF_DZ_L2DRMRR_RCPNTR_PTR_WIDTH 14 1469#define ESF_DZ_L2DRMRR_RCPNTR_NUM_LBN 80 1470#define ESF_DZ_L2DRMRR_RCPNTR_NUM_WIDTH 3 1471#define ESF_DZ_L2DRMRR_MULTITYPE_STATUS_LBN 67 1472#define ESF_DZ_L2DRMRR_MULTITYPE_STATUS_WIDTH 1 1473#define ESF_DZ_L2DRMRR_LASTREC_ENTRY_STATUS_LBN 66 1474#define ESF_DZ_L2DRMRR_LASTREC_ENTRY_STATUS_WIDTH 1 1475#define ESF_DZ_L2DRMRR_LASTREC_STATUS_LBN 65 1476#define ESF_DZ_L2DRMRR_LASTREC_STATUS_WIDTH 1 1477#define ESF_DZ_L2DRMRR_MATCH_STATUS_LBN 64 1478#define ESF_DZ_L2DRMRR_MATCH_STATUS_WIDTH 1 1479#define ESF_DZ_L2DRMRR_RCPNTR_SOFT_LBN 48 1480#define ESF_DZ_L2DRMRR_RCPNTR_SOFT_WIDTH 6 1481#define ESF_DZ_L2DRMRR_RCPNTR_RSS_INFO_LBN 32 1482#define ESF_DZ_L2DRMRR_RCPNTR_RSS_INFO_WIDTH 5 1483#define ESF_DZ_L2DRMRR_RCPNTR_RXQ_LBN 16 1484#define ESF_DZ_L2DRMRR_RCPNTR_RXQ_WIDTH 10 1485#define ESF_DZ_L2DRMRR_HOST_LBN 7 1486#define ESF_DZ_L2DRMRR_HOST_WIDTH 1 1487#define ESF_DZ_L2DRMRR_MC_LBN 6 1488#define ESF_DZ_L2DRMRR_MC_WIDTH 1 1489#define ESF_DZ_L2DRMRR_PORT0_MAC_LBN 5 1490#define ESF_DZ_L2DRMRR_PORT0_MAC_WIDTH 1 1491#define ESF_DZ_L2DRMRR_PORT1_MAC_LBN 4 1492#define ESF_DZ_L2DRMRR_PORT1_MAC_WIDTH 1 1493 1494 1495/* ES_LUE_UMSG_LU2DI_RXLU_SINGLE_MATCH_RESP */ 1496#define ESF_DZ_L2DRSMR_MULTITYPE_STATUS_LBN 67 1497#define ESF_DZ_L2DRSMR_MULTITYPE_STATUS_WIDTH 1 1498#define ESF_DZ_L2DRSMR_LASTREC_ENTRY_STATUS_LBN 66 1499#define ESF_DZ_L2DRSMR_LASTREC_ENTRY_STATUS_WIDTH 1 1500#define ESF_DZ_L2DRSMR_LASTREC_STATUS_LBN 65 1501#define ESF_DZ_L2DRSMR_LASTREC_STATUS_WIDTH 1 1502#define ESF_DZ_L2DRSMR_MATCH_STATUS_LBN 64 1503#define ESF_DZ_L2DRSMR_MATCH_STATUS_WIDTH 1 1504#define ESF_DZ_L2DRSMR_RCPNTR_SOFT_LBN 48 1505#define ESF_DZ_L2DRSMR_RCPNTR_SOFT_WIDTH 6 1506#define ESF_DZ_L2DRSMR_RCPNTR_RSS_INFO_LBN 32 1507#define ESF_DZ_L2DRSMR_RCPNTR_RSS_INFO_WIDTH 5 1508#define ESF_DZ_L2DRSMR_RCPNTR_RXQ_LBN 16 1509#define ESF_DZ_L2DRSMR_RCPNTR_RXQ_WIDTH 10 1510#define ESF_DZ_L2DRSMR_HOST_LBN 7 1511#define ESF_DZ_L2DRSMR_HOST_WIDTH 1 1512#define ESF_DZ_L2DRSMR_MC_LBN 6 1513#define ESF_DZ_L2DRSMR_MC_WIDTH 1 1514#define ESF_DZ_L2DRSMR_PORT0_MAC_LBN 5 1515#define ESF_DZ_L2DRSMR_PORT0_MAC_WIDTH 1 1516#define ESF_DZ_L2DRSMR_PORT1_MAC_LBN 4 1517#define ESF_DZ_L2DRSMR_PORT1_MAC_WIDTH 1 1518 1519 1520/* ES_LUE_UMSG_LU2DI_TXLU_MATCH_RESP */ 1521#define ESF_DZ_L2DTMR_RCPNTR_SOFT_LBN 112 1522#define ESF_DZ_L2DTMR_RCPNTR_SOFT_WIDTH 6 1523#define ESF_DZ_L2DTMR_RCPNTR_RSS_INFO_LBN 96 1524#define ESF_DZ_L2DTMR_RCPNTR_RSS_INFO_WIDTH 5 1525#define ESF_DZ_L2DTMR_RCPNTR__RXQ_LBN 80 1526#define ESF_DZ_L2DTMR_RCPNTR__RXQ_WIDTH 10 1527#define ESF_DZ_L2DTMR_MULTITYPE_STATUS_LBN 67 1528#define ESF_DZ_L2DTMR_MULTITYPE_STATUS_WIDTH 1 1529#define ESF_DZ_L2DTMR_LASTREC_ENTRY_STATUS_LBN 66 1530#define ESF_DZ_L2DTMR_LASTREC_ENTRY_STATUS_WIDTH 1 1531#define ESF_DZ_L2DTMR_LASTREC_STATUS_LBN 65 1532#define ESF_DZ_L2DTMR_LASTREC_STATUS_WIDTH 1 1533#define ESF_DZ_L2DTMR_MATCH_STATUS_LBN 64 1534#define ESF_DZ_L2DTMR_MATCH_STATUS_WIDTH 1 1535#define ESF_DZ_L2DTMR_ME_SOFT_LBN 48 1536#define ESF_DZ_L2DTMR_ME_SOFT_WIDTH 9 1537#define ESF_DZ_L2DTMR_TX_MCAST_LBN 32 1538#define ESF_DZ_L2DTMR_TX_MCAST_WIDTH 2 1539#define ESF_DZ_L2DTMR_TX_DOMAIN_LBN 16 1540#define ESF_DZ_L2DTMR_TX_DOMAIN_WIDTH 8 1541#define ESF_DZ_L2DTMR_PORT1_MAC_LBN 6 1542#define ESF_DZ_L2DTMR_PORT1_MAC_WIDTH 1 1543#define ESF_DZ_L2DTMR_PMEM_LBN 6 1544#define ESF_DZ_L2DTMR_PMEM_WIDTH 1 1545#define ESF_DZ_L2DTMR_PORT0_MAC_LBN 5 1546#define ESF_DZ_L2DTMR_PORT0_MAC_WIDTH 1 1547 1548 1549/* ES_MC_EVENT */ 1550#define ESF_DZ_MC_CODE_LBN 60 1551#define ESF_DZ_MC_CODE_WIDTH 4 1552#define ESF_DZ_MC_OVERRIDE_HOLDOFF_LBN 59 1553#define ESF_DZ_MC_OVERRIDE_HOLDOFF_WIDTH 1 1554#define ESF_DZ_MC_DROP_EVENT_LBN 58 1555#define ESF_DZ_MC_DROP_EVENT_WIDTH 1 1556#define ESF_DZ_MC_SOFT_DW0_LBN 0 1557#define ESF_DZ_MC_SOFT_DW0_WIDTH 32 1558#define ESF_DZ_MC_SOFT_DW1_LBN 32 1559#define ESF_DZ_MC_SOFT_DW1_WIDTH 26 1560#define ESF_DZ_MC_SOFT_LBN 0 1561#define ESF_DZ_MC_SOFT_WIDTH 58 1562 1563 1564/* ES_MC_XGMAC_FLTR_RULE_DEF */ 1565#define ESF_DZ_MC_XFRC_MODE_LBN 416 1566#define ESF_DZ_MC_XFRC_MODE_WIDTH 1 1567#define ESE_DZ_MC_XFRC_MODE_LAYERED 1 1568#define ESE_DZ_MC_XFRC_MODE_SIMPLE 0 1569#define ESF_DZ_MC_XFRC_HASH_LBN 384 1570#define ESF_DZ_MC_XFRC_HASH_WIDTH 32 1571#define ESF_DZ_MC_XFRC_LAYER4_BYTE_MASK_DW0_LBN 256 1572#define ESF_DZ_MC_XFRC_LAYER4_BYTE_MASK_DW0_WIDTH 32 1573#define ESF_DZ_MC_XFRC_LAYER4_BYTE_MASK_DW1_LBN 288 1574#define ESF_DZ_MC_XFRC_LAYER4_BYTE_MASK_DW1_WIDTH 32 1575#define ESF_DZ_MC_XFRC_LAYER4_BYTE_MASK_DW2_LBN 320 1576#define ESF_DZ_MC_XFRC_LAYER4_BYTE_MASK_DW2_WIDTH 32 1577#define ESF_DZ_MC_XFRC_LAYER4_BYTE_MASK_DW3_LBN 352 1578#define ESF_DZ_MC_XFRC_LAYER4_BYTE_MASK_DW3_WIDTH 32 1579#define ESF_DZ_MC_XFRC_LAYER4_BYTE_MASK_LBN 256 1580#define ESF_DZ_MC_XFRC_LAYER4_BYTE_MASK_WIDTH 128 1581#define ESF_DZ_MC_XFRC_LAYER3_BYTE_MASK_DW0_LBN 128 1582#define ESF_DZ_MC_XFRC_LAYER3_BYTE_MASK_DW0_WIDTH 32 1583#define ESF_DZ_MC_XFRC_LAYER3_BYTE_MASK_DW1_LBN 160 1584#define ESF_DZ_MC_XFRC_LAYER3_BYTE_MASK_DW1_WIDTH 32 1585#define ESF_DZ_MC_XFRC_LAYER3_BYTE_MASK_DW2_LBN 192 1586#define ESF_DZ_MC_XFRC_LAYER3_BYTE_MASK_DW2_WIDTH 32 1587#define ESF_DZ_MC_XFRC_LAYER3_BYTE_MASK_DW3_LBN 224 1588#define ESF_DZ_MC_XFRC_LAYER3_BYTE_MASK_DW3_WIDTH 32 1589#define ESF_DZ_MC_XFRC_LAYER3_BYTE_MASK_LBN 128 1590#define ESF_DZ_MC_XFRC_LAYER3_BYTE_MASK_WIDTH 128 1591#define ESF_DZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_DW0_LBN 0 1592#define ESF_DZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_DW0_WIDTH 32 1593#define ESF_DZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_DW1_LBN 32 1594#define ESF_DZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_DW1_WIDTH 32 1595#define ESF_DZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_DW2_LBN 64 1596#define ESF_DZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_DW2_WIDTH 32 1597#define ESF_DZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_DW3_LBN 96 1598#define ESF_DZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_DW3_WIDTH 32 1599#define ESF_DZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_LBN 0 1600#define ESF_DZ_MC_XFRC_LAYER2_OR_SIMPLE_BYTE_MASK_WIDTH 128 1601 1602 1603/* ES_RX_EVENT */ 1604#define ESF_DZ_RX_CODE_LBN 60 1605#define ESF_DZ_RX_CODE_WIDTH 4 1606#define ESF_DZ_RX_OVERRIDE_HOLDOFF_LBN 59 1607#define ESF_DZ_RX_OVERRIDE_HOLDOFF_WIDTH 1 1608#define ESF_DZ_RX_DROP_EVENT_LBN 58 1609#define ESF_DZ_RX_DROP_EVENT_WIDTH 1 1610#define ESF_DZ_RX_EV_RSVD2_LBN 54 1611#define ESF_DZ_RX_EV_RSVD2_WIDTH 4 1612#define ESF_DZ_RX_EV_SOFT2_LBN 52 1613#define ESF_DZ_RX_EV_SOFT2_WIDTH 2 1614#define ESF_DZ_RX_DSC_PTR_LBITS_LBN 48 1615#define ESF_DZ_RX_DSC_PTR_LBITS_WIDTH 4 1616#define ESF_DZ_RX_L4_CLASS_LBN 45 1617#define ESF_DZ_RX_L4_CLASS_WIDTH 3 1618#define ESE_DZ_L4_CLASS_RSVD7 7 1619#define ESE_DZ_L4_CLASS_RSVD6 6 1620#define ESE_DZ_L4_CLASS_RSVD5 5 1621#define ESE_DZ_L4_CLASS_RSVD4 4 1622#define ESE_DZ_L4_CLASS_RSVD3 3 1623#define ESE_DZ_L4_CLASS_UDP 2 1624#define ESE_DZ_L4_CLASS_TCP 1 1625#define ESE_DZ_L4_CLASS_UNKNOWN 0 1626#define ESF_DZ_RX_L3_CLASS_LBN 42 1627#define ESF_DZ_RX_L3_CLASS_WIDTH 3 1628#define ESE_DZ_L3_CLASS_RSVD7 7 1629#define ESE_DZ_L3_CLASS_IP6_FRAG 6 1630#define ESE_DZ_L3_CLASS_ARP 5 1631#define ESE_DZ_L3_CLASS_IP4_FRAG 4 1632#define ESE_DZ_L3_CLASS_FCOE 3 1633#define ESE_DZ_L3_CLASS_IP6 2 1634#define ESE_DZ_L3_CLASS_IP4 1 1635#define ESE_DZ_L3_CLASS_UNKNOWN 0 1636#define ESF_DZ_RX_ETH_TAG_CLASS_LBN 39 1637#define ESF_DZ_RX_ETH_TAG_CLASS_WIDTH 3 1638#define ESE_DZ_ETH_TAG_CLASS_RSVD7 7 1639#define ESE_DZ_ETH_TAG_CLASS_RSVD6 6 1640#define ESE_DZ_ETH_TAG_CLASS_RSVD5 5 1641#define ESE_DZ_ETH_TAG_CLASS_RSVD4 4 1642#define ESE_DZ_ETH_TAG_CLASS_RSVD3 3 1643#define ESE_DZ_ETH_TAG_CLASS_VLAN2 2 1644#define ESE_DZ_ETH_TAG_CLASS_VLAN1 1 1645#define ESE_DZ_ETH_TAG_CLASS_NONE 0 1646#define ESF_DZ_RX_ETH_BASE_CLASS_LBN 36 1647#define ESF_DZ_RX_ETH_BASE_CLASS_WIDTH 3 1648#define ESE_DZ_ETH_BASE_CLASS_LLC_SNAP 2 1649#define ESE_DZ_ETH_BASE_CLASS_LLC 1 1650#define ESE_DZ_ETH_BASE_CLASS_ETH2 0 1651#define ESF_DZ_RX_MAC_CLASS_LBN 35 1652#define ESF_DZ_RX_MAC_CLASS_WIDTH 1 1653#define ESE_DZ_MAC_CLASS_MCAST 1 1654#define ESE_DZ_MAC_CLASS_UCAST 0 1655#define ESF_DZ_RX_EV_SOFT1_LBN 32 1656#define ESF_DZ_RX_EV_SOFT1_WIDTH 3 1657#define ESF_DZ_RX_EV_RSVD1_LBN 31 1658#define ESF_DZ_RX_EV_RSVD1_WIDTH 1 1659#define ESF_DZ_RX_ABORT_LBN 30 1660#define ESF_DZ_RX_ABORT_WIDTH 1 1661#define ESF_DZ_RX_ECC_ERR_LBN 29 1662#define ESF_DZ_RX_ECC_ERR_WIDTH 1 1663#define ESF_DZ_RX_CRC1_ERR_LBN 28 1664#define ESF_DZ_RX_CRC1_ERR_WIDTH 1 1665#define ESF_DZ_RX_CRC0_ERR_LBN 27 1666#define ESF_DZ_RX_CRC0_ERR_WIDTH 1 1667#define ESF_DZ_RX_TCPUDP_CKSUM_ERR_LBN 26 1668#define ESF_DZ_RX_TCPUDP_CKSUM_ERR_WIDTH 1 1669#define ESF_DZ_RX_IPCKSUM_ERR_LBN 25 1670#define ESF_DZ_RX_IPCKSUM_ERR_WIDTH 1 1671#define ESF_DZ_RX_ECRC_ERR_LBN 24 1672#define ESF_DZ_RX_ECRC_ERR_WIDTH 1 1673#define ESF_DZ_RX_QLABEL_LBN 16 1674#define ESF_DZ_RX_QLABEL_WIDTH 5 1675#define ESF_DZ_RX_PARSE_INCOMPLETE_LBN 15 1676#define ESF_DZ_RX_PARSE_INCOMPLETE_WIDTH 1 1677#define ESF_DZ_RX_CONT_LBN 14 1678#define ESF_DZ_RX_CONT_WIDTH 1 1679#define ESF_DZ_RX_BYTES_LBN 0 1680#define ESF_DZ_RX_BYTES_WIDTH 14 1681 1682 1683/* ES_RX_KER_DESC */ 1684#define ESF_DZ_RX_KER_RESERVED_LBN 62 1685#define ESF_DZ_RX_KER_RESERVED_WIDTH 2 1686#define ESF_DZ_RX_KER_BYTE_CNT_LBN 48 1687#define ESF_DZ_RX_KER_BYTE_CNT_WIDTH 14 1688#define ESF_DZ_RX_KER_BUF_ADDR_DW0_LBN 0 1689#define ESF_DZ_RX_KER_BUF_ADDR_DW0_WIDTH 32 1690#define ESF_DZ_RX_KER_BUF_ADDR_DW1_LBN 32 1691#define ESF_DZ_RX_KER_BUF_ADDR_DW1_WIDTH 16 1692#define ESF_DZ_RX_KER_BUF_ADDR_LBN 0 1693#define ESF_DZ_RX_KER_BUF_ADDR_WIDTH 48 1694 1695 1696/* ES_RX_USER_DESC */ 1697#define ESF_DZ_RX_USR_RESERVED_LBN 62 1698#define ESF_DZ_RX_USR_RESERVED_WIDTH 2 1699#define ESF_DZ_RX_USR_BYTE_CNT_LBN 48 1700#define ESF_DZ_RX_USR_BYTE_CNT_WIDTH 14 1701#define ESF_DZ_RX_USR_BUF_PAGE_SIZE_LBN 44 1702#define ESF_DZ_RX_USR_BUF_PAGE_SIZE_WIDTH 4 1703#define ESE_DZ_USR_BUF_PAGE_SZ_4MB 10 1704#define ESE_DZ_USR_BUF_PAGE_SZ_1MB 8 1705#define ESE_DZ_USR_BUF_PAGE_SZ_64KB 4 1706#define ESE_DZ_USR_BUF_PAGE_SZ_4KB 0 1707#define ESF_DZ_RX_USR_BUF_ID_OFFSET_DW0_LBN 0 1708#define ESF_DZ_RX_USR_BUF_ID_OFFSET_DW0_WIDTH 32 1709#define ESF_DZ_RX_USR_BUF_ID_OFFSET_DW1_LBN 32 1710#define ESF_DZ_RX_USR_BUF_ID_OFFSET_DW1_WIDTH 12 1711#define ESF_DZ_RX_USR_BUF_ID_OFFSET_LBN 0 1712#define ESF_DZ_RX_USR_BUF_ID_OFFSET_WIDTH 44 1713#define ESF_DZ_RX_USR_4KBPS_BUF_ID_LBN 12 1714#define ESF_DZ_RX_USR_4KBPS_BUF_ID_WIDTH 32 1715#define ESF_DZ_RX_USR_64KBPS_BUF_ID_LBN 16 1716#define ESF_DZ_RX_USR_64KBPS_BUF_ID_WIDTH 28 1717#define ESF_DZ_RX_USR_1MBPS_BUF_ID_LBN 20 1718#define ESF_DZ_RX_USR_1MBPS_BUF_ID_WIDTH 24 1719#define ESF_DZ_RX_USR_4MBPS_BUF_ID_LBN 22 1720#define ESF_DZ_RX_USR_4MBPS_BUF_ID_WIDTH 22 1721#define ESF_DZ_RX_USR_4MBPS_BYTE_OFFSET_LBN 0 1722#define ESF_DZ_RX_USR_4MBPS_BYTE_OFFSET_WIDTH 22 1723#define ESF_DZ_RX_USR_1MBPS_BYTE_OFFSET_LBN 0 1724#define ESF_DZ_RX_USR_1MBPS_BYTE_OFFSET_WIDTH 20 1725#define ESF_DZ_RX_USR_64KBPS_BYTE_OFFSET_LBN 0 1726#define ESF_DZ_RX_USR_64KBPS_BYTE_OFFSET_WIDTH 16 1727#define ESF_DZ_RX_USR_4KBPS_BYTE_OFFSET_LBN 0 1728#define ESF_DZ_RX_USR_4KBPS_BYTE_OFFSET_WIDTH 12 1729 1730 1731/* ES_RX_U_QSTATE_TBL0_ENTRY */ 1732#define ESF_DZ_RX_U_DC_FILL_LBN 112 1733#define ESF_DZ_RX_U_DC_FILL_WIDTH 7 1734#define ESF_DZ_RX_U_SOFT7_B1R1_0_LBN 112 1735#define ESF_DZ_RX_U_SOFT7_B1R1_0_WIDTH 7 1736#define ESF_DZ_RX_U_DSCR_HW_RPTR_LBN 96 1737#define ESF_DZ_RX_U_DSCR_HW_RPTR_WIDTH 12 1738#define ESF_DZ_RX_U_SOFT12_B1R2_0_LBN 96 1739#define ESF_DZ_RX_U_SOFT12_B1R2_0_WIDTH 12 1740#define ESF_DZ_RX_U_DC_RPTR_LBN 80 1741#define ESF_DZ_RX_U_DC_RPTR_WIDTH 6 1742#define ESF_DZ_RX_U_SOFT6_B1R1_0_LBN 80 1743#define ESF_DZ_RX_U_SOFT6_B1R1_0_WIDTH 6 1744#define ESF_DZ_RX_U_NOTIFY_PENDING_LBN 70 1745#define ESF_DZ_RX_U_NOTIFY_PENDING_WIDTH 1 1746#define ESF_DZ_RX_U_SOFT1_B1R0_6_LBN 70 1747#define ESF_DZ_RX_U_SOFT1_B1R0_6_WIDTH 1 1748#define ESF_DZ_RX_U_DATA_ACTIVE_LBN 69 1749#define ESF_DZ_RX_U_DATA_ACTIVE_WIDTH 1 1750#define ESF_DZ_RX_U_SOFT1_B1R0_5_LBN 69 1751#define ESF_DZ_RX_U_SOFT1_B1R0_5_WIDTH 1 1752#define ESF_DZ_RX_U_FAST_PATH_LBN 68 1753#define ESF_DZ_RX_U_FAST_PATH_WIDTH 1 1754#define ESF_DZ_RX_U_SOFT1_B1R0_4_LBN 68 1755#define ESF_DZ_RX_U_SOFT1_B1R0_4_WIDTH 1 1756#define ESF_DZ_RX_U_CHAIN_LBN 67 1757#define ESF_DZ_RX_U_CHAIN_WIDTH 1 1758#define ESF_DZ_RX_U_SOFT1_B1R0_3_LBN 67 1759#define ESF_DZ_RX_U_SOFT1_B1R0_3_WIDTH 1 1760#define ESF_DZ_RX_U_DESC_ACTIVE_LBN 66 1761#define ESF_DZ_RX_U_DESC_ACTIVE_WIDTH 1 1762#define ESF_DZ_RX_U_SOFT1_B1R0_2_LBN 66 1763#define ESF_DZ_RX_U_SOFT1_B1R0_2_WIDTH 1 1764#define ESF_DZ_RX_U_TIMESTAMP_LBN 65 1765#define ESF_DZ_RX_U_TIMESTAMP_WIDTH 1 1766#define ESF_DZ_RX_U_SOFT1_B1R0_1_LBN 65 1767#define ESF_DZ_RX_U_SOFT1_B1R0_1_WIDTH 1 1768#define ESF_DZ_RX_U_Q_ENABLE_LBN 64 1769#define ESF_DZ_RX_U_Q_ENABLE_WIDTH 1 1770#define ESF_DZ_RX_U_SOFT1_B1R0_0_LBN 64 1771#define ESF_DZ_RX_U_SOFT1_B1R0_0_WIDTH 1 1772#define ESF_DZ_RX_U_UPD_CRC_MODE_LBN 29 1773#define ESF_DZ_RX_U_UPD_CRC_MODE_WIDTH 3 1774#define ESE_DZ_C2RIP_FCOIP_MPA 5 1775#define ESE_DZ_C2RIP_FCOIP_FCOE 4 1776#define ESE_DZ_C2RIP_ISCSI_HDR_AND_PYLD 3 1777#define ESE_DZ_C2RIP_ISCSI_HDR 2 1778#define ESE_DZ_C2RIP_FCOE 1 1779#define ESE_DZ_C2RIP_OFF 0 1780#define ESF_DZ_RX_U_SOFT16_B0R1_LBN 16 1781#define ESF_DZ_RX_U_SOFT16_B0R1_WIDTH 16 1782#define ESF_DZ_RX_U_BIU_ARGS_LBN 16 1783#define ESF_DZ_RX_U_BIU_ARGS_WIDTH 13 1784#define ESF_DZ_RX_U_EV_QID_LBN 5 1785#define ESF_DZ_RX_U_EV_QID_WIDTH 11 1786#define ESF_DZ_RX_U_SOFT16_B0R0_LBN 0 1787#define ESF_DZ_RX_U_SOFT16_B0R0_WIDTH 16 1788#define ESF_DZ_RX_U_EV_QLABEL_LBN 0 1789#define ESF_DZ_RX_U_EV_QLABEL_WIDTH 5 1790 1791 1792/* ES_RX_U_QSTATE_TBL1_ENTRY */ 1793#define ESF_DZ_RX_U_DSCR_BASE_PAGE_ID_LBN 64 1794#define ESF_DZ_RX_U_DSCR_BASE_PAGE_ID_WIDTH 18 1795#define ESF_DZ_RX_U_SOFT18_B1R0_0_LBN 64 1796#define ESF_DZ_RX_U_SOFT18_B1R0_0_WIDTH 18 1797#define ESF_DZ_RX_U_QST1_SPARE_LBN 53 1798#define ESF_DZ_RX_U_QST1_SPARE_WIDTH 11 1799#define ESF_DZ_RX_U_SOFT16_B0R3_0_LBN 48 1800#define ESF_DZ_RX_U_SOFT16_B0R3_0_WIDTH 16 1801#define ESF_DZ_RX_U_NO_FLUSH_LBN 52 1802#define ESF_DZ_RX_U_NO_FLUSH_WIDTH 1 1803#define ESF_DZ_RX_U_HDR_SPLIT_LBN 51 1804#define ESF_DZ_RX_U_HDR_SPLIT_WIDTH 1 1805#define ESF_DZ_RX_U_DOORBELL_ENABLED_LBN 50 1806#define ESF_DZ_RX_U_DOORBELL_ENABLED_WIDTH 1 1807#define ESF_DZ_RX_U_WORK_PENDING_LBN 49 1808#define ESF_DZ_RX_U_WORK_PENDING_WIDTH 1 1809#define ESF_DZ_RX_U_ERROR_LBN 48 1810#define ESF_DZ_RX_U_ERROR_WIDTH 1 1811#define ESF_DZ_RX_U_DSCR_SW_WPTR_LBN 32 1812#define ESF_DZ_RX_U_DSCR_SW_WPTR_WIDTH 12 1813#define ESF_DZ_RX_U_SOFT12_B0R2_0_LBN 32 1814#define ESF_DZ_RX_U_SOFT12_B0R2_0_WIDTH 12 1815#define ESF_DZ_RX_U_OWNER_ID_LBN 16 1816#define ESF_DZ_RX_U_OWNER_ID_WIDTH 12 1817#define ESF_DZ_RX_U_SOFT12_B0R1_0_LBN 16 1818#define ESF_DZ_RX_U_SOFT12_B0R1_0_WIDTH 12 1819#define ESF_DZ_RX_U_DSCR_SIZE_LBN 0 1820#define ESF_DZ_RX_U_DSCR_SIZE_WIDTH 3 1821#define ESE_DZ_RX_DSCR_SIZE_512 7 1822#define ESE_DZ_RX_DSCR_SIZE_1K 6 1823#define ESE_DZ_RX_DSCR_SIZE_2K 5 1824#define ESE_DZ_RX_DSCR_SIZE_4K 4 1825#define ESF_DZ_RX_U_SOFT3_B0R0_0_LBN 0 1826#define ESF_DZ_RX_U_SOFT3_B0R0_0_WIDTH 3 1827 1828 1829/* ES_SGMII_DEV_PTNR_ABILITY_1000BX_MD */ 1830#define ESF_DZ_SGMII_DPA_NXT_PG_LBN 15 1831#define ESF_DZ_SGMII_DPA_NXT_PG_WIDTH 1 1832#define ESF_DZ_SGMII_DPA_ACK_LBN 14 1833#define ESF_DZ_SGMII_DPA_ACK_WIDTH 1 1834#define ESF_DZ_SGMII_DPA_REMOTE_FLT_LBN 12 1835#define ESF_DZ_SGMII_DPA_REMOTE_FLT_WIDTH 2 1836#define ESE_DZ_SGMII_DPA_RF_AN_ERR 3 1837#define ESE_DZ_SGMII_DPA_RF_OFFLINE 2 1838#define ESE_DZ_SGMII_DPA_RF_LINK_FAIL 1 1839#define ESE_DZ_SGMII_DPA_RF_NONE 0 1840#define ESF_DZ_SGMII_DPA_PS_LBN 7 1841#define ESF_DZ_SGMII_DPA_PS_WIDTH 2 1842#define ESF_DZ_SGMII_DPA_HD_LBN 6 1843#define ESF_DZ_SGMII_DPA_HD_WIDTH 1 1844#define ESF_DZ_SGMII_DPA_FD_LBN 5 1845#define ESF_DZ_SGMII_DPA_FD_WIDTH 1 1846 1847 1848/* ES_SGMII_DEV_PTNR_ABILITY_SGMII_MD */ 1849#define ESF_DZ_SGMII_DPA_CPR_LINK_STATE_LBN 15 1850#define ESF_DZ_SGMII_DPA_CPR_LINK_STATE_WIDTH 1 1851#define ESF_DZ_SGMII_DPA_ACK_LBN 14 1852#define ESF_DZ_SGMII_DPA_ACK_WIDTH 1 1853#define ESF_DZ_SGMII_CPR_BPLX_STS_LBN 12 1854#define ESF_DZ_SGMII_CPR_BPLX_STS_WIDTH 1 1855#define ESF_DZ_SGMII_DPA_COPPER_SPEED_LBN 10 1856#define ESF_DZ_SGMII_DPA_COPPER_SPEED_WIDTH 2 1857#define ESE_DZ_SGMII_DPA_CPR_1GBS 2 1858#define ESE_DZ_SGMII_DPA_CPR_100MBS 1 1859#define ESE_DZ_SGMII_DPA_CPR_10MBS 0 1860 1861 1862/* ES_SMC_BUFTBL_CNTRL_ENTRY */ 1863#define ESF_DZ_SMC_SW_CNTXT_DW0_LBN 16 1864#define ESF_DZ_SMC_SW_CNTXT_DW0_WIDTH 32 1865#define ESF_DZ_SMC_SW_CNTXT_DW1_LBN 48 1866#define ESF_DZ_SMC_SW_CNTXT_DW1_WIDTH 24 1867#define ESF_DZ_SMC_SW_CNTXT_LBN 16 1868#define ESF_DZ_SMC_SW_CNTXT_WIDTH 56 1869#define ESF_DZ_SMC_PAGE_SIZE_LBN 12 1870#define ESF_DZ_SMC_PAGE_SIZE_WIDTH 4 1871#define ESF_DZ_SMC_OWNER_ID_LBN 0 1872#define ESF_DZ_SMC_OWNER_ID_WIDTH 12 1873 1874 1875/* ES_SMC_BUFTBL_TRANSL_ENTRY */ 1876#define ESF_DZ_SMC_PAGE_INDEX0_DW0_LBN 36 1877#define ESF_DZ_SMC_PAGE_INDEX0_DW0_WIDTH 32 1878#define ESF_DZ_SMC_PAGE_INDEX0_DW1_LBN 68 1879#define ESF_DZ_SMC_PAGE_INDEX0_DW1_WIDTH 4 1880#define ESF_DZ_SMC_PAGE_INDEX0_LBN 36 1881#define ESF_DZ_SMC_PAGE_INDEX0_WIDTH 36 1882#define ESF_DZ_SMC_PAGE_INDEX1_DW0_LBN 0 1883#define ESF_DZ_SMC_PAGE_INDEX1_DW0_WIDTH 32 1884#define ESF_DZ_SMC_PAGE_INDEX1_DW1_LBN 32 1885#define ESF_DZ_SMC_PAGE_INDEX1_DW1_WIDTH 4 1886#define ESF_DZ_SMC_PAGE_INDEX1_LBN 0 1887#define ESF_DZ_SMC_PAGE_INDEX1_WIDTH 36 1888 1889 1890/* ES_SMC_DSCR_CACHE_ENTRY */ 1891#define ESF_DZ_SMC_BTE_PAD_LBN 64 1892#define ESF_DZ_SMC_BTE_PAD_WIDTH 8 1893#define ESF_DZ_SMC_DSCR_DW0_LBN 0 1894#define ESF_DZ_SMC_DSCR_DW0_WIDTH 32 1895#define ESF_DZ_SMC_DSCR_DW1_LBN 32 1896#define ESF_DZ_SMC_DSCR_DW1_WIDTH 32 1897#define ESF_DZ_SMC_DSCR_LBN 0 1898#define ESF_DZ_SMC_DSCR_WIDTH 64 1899 1900 1901/* ES_SMC_GEN_STORAGE_ENTRY */ 1902#define ESF_DZ_SMC_DATA_DW0_LBN 0 1903#define ESF_DZ_SMC_DATA_DW0_WIDTH 32 1904#define ESF_DZ_SMC_DATA_DW1_LBN 32 1905#define ESF_DZ_SMC_DATA_DW1_WIDTH 32 1906#define ESF_DZ_SMC_DATA_DW2_LBN 64 1907#define ESF_DZ_SMC_DATA_DW2_WIDTH 8 1908#define ESF_DZ_SMC_DATA_LBN 0 1909#define ESF_DZ_SMC_DATA_WIDTH 72 1910 1911 1912/* ES_SMC_MSG_BASE_REQ */ 1913#define ESF_DZ_MC2S_BASE_REQ_MSG_DATA_DW0_LBN 11 1914#define ESF_DZ_MC2S_BASE_REQ_MSG_DATA_DW0_WIDTH 32 1915#define ESF_DZ_MC2S_BASE_REQ_MSG_DATA_DW1_LBN 43 1916#define ESF_DZ_MC2S_BASE_REQ_MSG_DATA_DW1_WIDTH 32 1917#define ESF_DZ_MC2S_BASE_REQ_MSG_DATA_DW2_LBN 75 1918#define ESF_DZ_MC2S_BASE_REQ_MSG_DATA_DW2_WIDTH 26 1919#define ESF_DZ_MC2S_BASE_REQ_MSG_DATA_LBN 11 1920#define ESF_DZ_MC2S_BASE_REQ_MSG_DATA_WIDTH 90 1921#define ESF_DZ_MC2S_BASE_SOFT_LBN 7 1922#define ESF_DZ_MC2S_BASE_SOFT_WIDTH 4 1923#define ESF_DZ_MC2S_BASE_CLIENT_ID_LBN 3 1924#define ESF_DZ_MC2S_BASE_CLIENT_ID_WIDTH 4 1925#define ESE_DZ_SMC_MACRO_ENGINE_ID 15 1926#define ESE_DZ_SMC_TX_DICPU_ID 14 1927#define ESE_DZ_SMC_RX_DICPU_ID 13 1928#define ESE_DZ_SMC_MC_ID 12 1929#define ESE_DZ_SMC_DL_ID 10 1930#define ESE_DZ_SMC_EV_ID 8 1931#define ESE_DZ_SMC_TX_DPCPU1_ID 5 1932#define ESE_DZ_SMC_TX_DPCPU0_ID 4 1933#define ESE_DZ_SMC_RX_DPCPU_ID 0 1934#define ESF_DZ_MC2S_BASE_OP_LBN 0 1935#define ESF_DZ_MC2S_BASE_OP_WIDTH 3 1936#define ESE_DZ_SMC_REQ_WR 4 1937#define ESE_DZ_SMC_RESP_WR 4 1938#define ESE_DZ_SMC_REQ_RD 3 1939#define ESE_DZ_SMC_RESP_RD 3 1940#define ESE_DZ_SMC_REQ_DSCR_WRITE 2 1941#define ESE_DZ_SMC_RESP_DSCR_WRITE 2 1942#define ESE_DZ_SMC_REQ_DSCR_READ 1 1943#define ESE_DZ_SMC_RESP_DSCR_READ 1 1944#define ESE_DZ_SMC_REQ_BUFTBL_LOOKUP 0 1945#define ESE_DZ_SMC_RESP_BUFTBL_LOOKUP 0 1946 1947 1948/* ES_SMC_MSG_BUFTBL_LOOKUP_REQ */ 1949#define ESF_DZ_MC2S_BL_BUF_ID_LBN 28 1950#define ESF_DZ_MC2S_BL_BUF_ID_WIDTH 18 1951#define ESF_DZ_MC2S_BL_EXP_PAGE_SIZE_LBN 24 1952#define ESF_DZ_MC2S_BL_EXP_PAGE_SIZE_WIDTH 4 1953#define ESE_DZ_SMC_PAGE_SIZE_4M 10 1954#define ESE_DZ_SMC_PAGE_SIZE_1M 8 1955#define ESE_DZ_SMC_PAGE_SIZE_64K 4 1956#define ESE_DZ_SMC_PAGE_SIZE_4K 0 1957#define ESF_DZ_MC2S_BL_EXP_OWNER_ID_LBN 12 1958#define ESF_DZ_MC2S_BL_EXP_OWNER_ID_WIDTH 12 1959#define ESF_DZ_MC2S_BL_REFLECT_LBN 11 1960#define ESF_DZ_MC2S_BL_REFLECT_WIDTH 1 1961#define ESF_DZ_MC2S_BL_SOFT_LBN 7 1962#define ESF_DZ_MC2S_BL_SOFT_WIDTH 4 1963#define ESF_DZ_MC2S_BL_CLIENT_ID_LBN 3 1964#define ESF_DZ_MC2S_BL_CLIENT_ID_WIDTH 4 1965#define ESE_DZ_SMC_MACRO_ENGINE_ID 15 1966#define ESE_DZ_SMC_TX_DICPU_ID 14 1967#define ESE_DZ_SMC_RX_DICPU_ID 13 1968#define ESE_DZ_SMC_MC_ID 12 1969#define ESE_DZ_SMC_DL_ID 10 1970#define ESE_DZ_SMC_EV_ID 8 1971#define ESE_DZ_SMC_TX_DPCPU1_ID 5 1972#define ESE_DZ_SMC_TX_DPCPU0_ID 4 1973#define ESE_DZ_SMC_RX_DPCPU_ID 0 1974#define ESF_DZ_MC2S_BL_OP_LBN 0 1975#define ESF_DZ_MC2S_BL_OP_WIDTH 3 1976#define ESE_DZ_SMC_REQ_WR 4 1977#define ESE_DZ_SMC_REQ_RD 3 1978#define ESE_DZ_SMC_REQ_DSCR_WRITE 2 1979#define ESE_DZ_SMC_REQ_DSCR_READ 1 1980#define ESE_DZ_SMC_REQ_BUFTBL_LOOKUP 0 1981 1982 1983/* ES_SMC_MSG_BUFTBL_LOOKUP_RESP */ 1984#define ESF_DZ_S2MC_BL_BUFTBL_ENTRY_DW0_LBN 12 1985#define ESF_DZ_S2MC_BL_BUFTBL_ENTRY_DW0_WIDTH 32 1986#define ESF_DZ_S2MC_BL_BUFTBL_ENTRY_DW1_LBN 44 1987#define ESF_DZ_S2MC_BL_BUFTBL_ENTRY_DW1_WIDTH 4 1988#define ESF_DZ_S2MC_BL_BUFTBL_ENTRY_LBN 12 1989#define ESF_DZ_S2MC_BL_BUFTBL_ENTRY_WIDTH 36 1990#define ESF_DZ_S2MC_BL_FAIL_LBN 11 1991#define ESF_DZ_S2MC_BL_FAIL_WIDTH 1 1992#define ESF_DZ_S2MC_BL_SOFT_LBN 7 1993#define ESF_DZ_S2MC_BL_SOFT_WIDTH 4 1994#define ESF_DZ_S2MC_BL_CLIENT_ID_LBN 3 1995#define ESF_DZ_S2MC_BL_CLIENT_ID_WIDTH 4 1996#define ESE_DZ_SMC_MACRO_ENGINE_ID 15 1997#define ESE_DZ_SMC_TX_DICPU_ID 14 1998#define ESE_DZ_SMC_RX_DICPU_ID 13 1999#define ESE_DZ_SMC_MC_ID 12 2000#define ESE_DZ_SMC_DL_ID 10 2001#define ESE_DZ_SMC_EV_ID 8 2002#define ESE_DZ_SMC_TX_DPCPU1_ID 5 2003#define ESE_DZ_SMC_TX_DPCPU0_ID 4 2004#define ESE_DZ_SMC_RX_DPCPU_ID 0 2005#define ESF_DZ_S2MC_BL_OP_LBN 0 2006#define ESF_DZ_S2MC_BL_OP_WIDTH 3 2007#define ESE_DZ_SMC_REQ_WR 4 2008#define ESE_DZ_SMC_REQ_RD 3 2009#define ESE_DZ_SMC_REQ_DSCR_WRITE 2 2010#define ESE_DZ_SMC_REQ_DSCR_READ 1 2011#define ESE_DZ_SMC_REQ_BUFTBL_LOOKUP 0 2012 2013 2014/* ES_SMC_MSG_DSCR_RD_REQ */ 2015#define ESF_DZ_MC2S_DR_DSCR_OFST_LBN 24 2016#define ESF_DZ_MC2S_DR_DSCR_OFST_WIDTH 6 2017#define ESF_DZ_MC2S_DR_QID_LBN 13 2018#define ESF_DZ_MC2S_DR_QID_WIDTH 11 2019#define ESF_DZ_MC2S_DR_IS_TX_LBN 12 2020#define ESF_DZ_MC2S_DR_IS_TX_WIDTH 1 2021#define ESF_DZ_MC2S_DR_REFLECT_LBN 11 2022#define ESF_DZ_MC2S_DR_REFLECT_WIDTH 1 2023#define ESF_DZ_MC2S_DR_SOFT_LBN 7 2024#define ESF_DZ_MC2S_DR_SOFT_WIDTH 4 2025#define ESF_DZ_MC2S_DR_CLIENT_ID_LBN 3 2026#define ESF_DZ_MC2S_DR_CLIENT_ID_WIDTH 4 2027#define ESE_DZ_SMC_MACRO_ENGINE_ID 15 2028#define ESE_DZ_SMC_TX_DICPU_ID 14 2029#define ESE_DZ_SMC_RX_DICPU_ID 13 2030#define ESE_DZ_SMC_MC_ID 12 2031#define ESE_DZ_SMC_DL_ID 10 2032#define ESE_DZ_SMC_EV_ID 8 2033#define ESE_DZ_SMC_TX_DPCPU1_ID 5 2034#define ESE_DZ_SMC_TX_DPCPU0_ID 4 2035#define ESE_DZ_SMC_RX_DPCPU_ID 0 2036#define ESF_DZ_MC2S_DR_OP_LBN 0 2037#define ESF_DZ_MC2S_DR_OP_WIDTH 3 2038#define ESE_DZ_SMC_REQ_WR 4 2039#define ESE_DZ_SMC_REQ_RD 3 2040#define ESE_DZ_SMC_REQ_DSCR_WRITE 2 2041#define ESE_DZ_SMC_REQ_DSCR_READ 1 2042#define ESE_DZ_SMC_REQ_BUFTBL_LOOKUP 0 2043 2044 2045/* ES_SMC_MSG_DSCR_RD_RESP */ 2046#define ESF_DZ_S2MC_DR_DSCR_DW0_LBN 12 2047#define ESF_DZ_S2MC_DR_DSCR_DW0_WIDTH 32 2048#define ESF_DZ_S2MC_DR_DSCR_DW1_LBN 44 2049#define ESF_DZ_S2MC_DR_DSCR_DW1_WIDTH 32 2050#define ESF_DZ_S2MC_DR_DSCR_LBN 12 2051#define ESF_DZ_S2MC_DR_DSCR_WIDTH 64 2052#define ESF_DZ_S2MC_DR_FAIL_LBN 11 2053#define ESF_DZ_S2MC_DR_FAIL_WIDTH 1 2054#define ESF_DZ_S2MC_DR_SOFT_LBN 7 2055#define ESF_DZ_S2MC_DR_SOFT_WIDTH 4 2056#define ESF_DZ_S2MC_DR_CLIENT_ID_LBN 3 2057#define ESF_DZ_S2MC_DR_CLIENT_ID_WIDTH 4 2058#define ESE_DZ_SMC_MACRO_ENGINE_ID 15 2059#define ESE_DZ_SMC_TX_DICPU_ID 14 2060#define ESE_DZ_SMC_RX_DICPU_ID 13 2061#define ESE_DZ_SMC_MC_ID 12 2062#define ESE_DZ_SMC_DL_ID 10 2063#define ESE_DZ_SMC_EV_ID 8 2064#define ESE_DZ_SMC_TX_DPCPU1_ID 5 2065#define ESE_DZ_SMC_TX_DPCPU0_ID 4 2066#define ESE_DZ_SMC_RX_DPCPU_ID 0 2067#define ESF_DZ_S2MC_DR_OP_LBN 0 2068#define ESF_DZ_S2MC_DR_OP_WIDTH 3 2069#define ESE_DZ_SMC_REQ_WR 4 2070#define ESE_DZ_SMC_REQ_RD 3 2071#define ESE_DZ_SMC_REQ_DSCR_WRITE 2 2072#define ESE_DZ_SMC_REQ_DSCR_READ 1 2073#define ESE_DZ_SMC_REQ_BUFTBL_LOOKUP 0 2074 2075 2076/* ES_SMC_MSG_DSCR_WR_REQ */ 2077#define ESF_DZ_MC2S_DW_DSCR_DW0_LBN 30 2078#define ESF_DZ_MC2S_DW_DSCR_DW0_WIDTH 32 2079#define ESF_DZ_MC2S_DW_DSCR_DW1_LBN 62 2080#define ESF_DZ_MC2S_DW_DSCR_DW1_WIDTH 32 2081#define ESF_DZ_MC2S_DW_DSCR_LBN 30 2082#define ESF_DZ_MC2S_DW_DSCR_WIDTH 64 2083#define ESF_DZ_MC2S_DW_DSCR_OFST_LBN 24 2084#define ESF_DZ_MC2S_DW_DSCR_OFST_WIDTH 6 2085#define ESF_DZ_MC2S_DW_QID_LBN 13 2086#define ESF_DZ_MC2S_DW_QID_WIDTH 11 2087#define ESF_DZ_MC2S_DW_IS_TX_LBN 12 2088#define ESF_DZ_MC2S_DW_IS_TX_WIDTH 1 2089#define ESF_DZ_MC2S_DW_REFLECT_LBN 11 2090#define ESF_DZ_MC2S_DW_REFLECT_WIDTH 1 2091#define ESF_DZ_MC2S_DW_SOFT_LBN 7 2092#define ESF_DZ_MC2S_DW_SOFT_WIDTH 4 2093#define ESF_DZ_MC2S_DW_CLIENT_ID_LBN 3 2094#define ESF_DZ_MC2S_DW_CLIENT_ID_WIDTH 4 2095#define ESE_DZ_SMC_MACRO_ENGINE_ID 15 2096#define ESE_DZ_SMC_TX_DICPU_ID 14 2097#define ESE_DZ_SMC_RX_DICPU_ID 13 2098#define ESE_DZ_SMC_MC_ID 12 2099#define ESE_DZ_SMC_DL_ID 10 2100#define ESE_DZ_SMC_EV_ID 8 2101#define ESE_DZ_SMC_TX_DPCPU1_ID 5 2102#define ESE_DZ_SMC_TX_DPCPU0_ID 4 2103#define ESE_DZ_SMC_RX_DPCPU_ID 0 2104#define ESF_DZ_MC2S_DW_OP_LBN 0 2105#define ESF_DZ_MC2S_DW_OP_WIDTH 3 2106#define ESE_DZ_SMC_REQ_WR 4 2107#define ESE_DZ_SMC_REQ_RD 3 2108#define ESE_DZ_SMC_REQ_DSCR_WRITE 2 2109#define ESE_DZ_SMC_REQ_DSCR_READ 1 2110#define ESE_DZ_SMC_REQ_BUFTBL_LOOKUP 0 2111 2112 2113/* ES_SMC_MSG_DSCR_WR_RESP */ 2114#define ESF_DZ_S2MC_DW_FAIL_LBN 11 2115#define ESF_DZ_S2MC_DW_FAIL_WIDTH 1 2116#define ESF_DZ_S2MC_DW_SOFT_LBN 7 2117#define ESF_DZ_S2MC_DW_SOFT_WIDTH 4 2118#define ESF_DZ_S2MC_DW_CLIENT_ID_LBN 3 2119#define ESF_DZ_S2MC_DW_CLIENT_ID_WIDTH 4 2120#define ESE_DZ_SMC_MACRO_ENGINE_ID 15 2121#define ESE_DZ_SMC_TX_DICPU_ID 14 2122#define ESE_DZ_SMC_RX_DICPU_ID 13 2123#define ESE_DZ_SMC_MC_ID 12 2124#define ESE_DZ_SMC_DL_ID 10 2125#define ESE_DZ_SMC_EV_ID 8 2126#define ESE_DZ_SMC_TX_DPCPU1_ID 5 2127#define ESE_DZ_SMC_TX_DPCPU0_ID 4 2128#define ESE_DZ_SMC_RX_DPCPU_ID 0 2129#define ESF_DZ_S2MC_DW_OP_LBN 0 2130#define ESF_DZ_S2MC_DW_OP_WIDTH 3 2131#define ESE_DZ_SMC_REQ_WR 4 2132#define ESE_DZ_SMC_REQ_RD 3 2133#define ESE_DZ_SMC_REQ_DSCR_WRITE 2 2134#define ESE_DZ_SMC_REQ_DSCR_READ 1 2135#define ESE_DZ_SMC_REQ_BUFTBL_LOOKUP 0 2136 2137 2138/* ES_SMC_MSG_RD_REQ */ 2139#define ESF_DZ_MC2S_RD_ADDR_LBN 12 2140#define ESF_DZ_MC2S_RD_ADDR_WIDTH 17 2141#define ESF_DZ_MC2S_RD_REFLECT_LBN 11 2142#define ESF_DZ_MC2S_RD_REFLECT_WIDTH 1 2143#define ESF_DZ_MC2S_RD_SOFT_LBN 7 2144#define ESF_DZ_MC2S_RD_SOFT_WIDTH 4 2145#define ESF_DZ_MC2S_RD_CLIENT_ID_LBN 3 2146#define ESF_DZ_MC2S_RD_CLIENT_ID_WIDTH 4 2147#define ESE_DZ_SMC_MACRO_ENGINE_ID 15 2148#define ESE_DZ_SMC_TX_DICPU_ID 14 2149#define ESE_DZ_SMC_RX_DICPU_ID 13 2150#define ESE_DZ_SMC_MC_ID 12 2151#define ESE_DZ_SMC_DL_ID 10 2152#define ESE_DZ_SMC_EV_ID 8 2153#define ESE_DZ_SMC_TX_DPCPU1_ID 5 2154#define ESE_DZ_SMC_TX_DPCPU0_ID 4 2155#define ESE_DZ_SMC_RX_DPCPU_ID 0 2156#define ESF_DZ_MC2S_RD_OP_LBN 0 2157#define ESF_DZ_MC2S_RD_OP_WIDTH 3 2158#define ESE_DZ_SMC_REQ_WR 4 2159#define ESE_DZ_SMC_REQ_RD 3 2160#define ESE_DZ_SMC_REQ_DSCR_WRITE 2 2161#define ESE_DZ_SMC_REQ_DSCR_READ 1 2162#define ESE_DZ_SMC_REQ_BUFTBL_LOOKUP 0 2163 2164 2165/* ES_SMC_MSG_RD_RESP */ 2166#define ESF_DZ_S2MC_RD_DATA_DW0_LBN 12 2167#define ESF_DZ_S2MC_RD_DATA_DW0_WIDTH 32 2168#define ESF_DZ_S2MC_RD_DATA_DW1_LBN 44 2169#define ESF_DZ_S2MC_RD_DATA_DW1_WIDTH 32 2170#define ESF_DZ_S2MC_RD_DATA_DW2_LBN 76 2171#define ESF_DZ_S2MC_RD_DATA_DW2_WIDTH 8 2172#define ESF_DZ_S2MC_RD_DATA_LBN 12 2173#define ESF_DZ_S2MC_RD_DATA_WIDTH 72 2174#define ESF_DZ_S2MC_RD_FAIL_LBN 11 2175#define ESF_DZ_S2MC_RD_FAIL_WIDTH 1 2176#define ESF_DZ_S2MC_RD_SOFT_LBN 7 2177#define ESF_DZ_S2MC_RD_SOFT_WIDTH 4 2178#define ESF_DZ_S2MC_RD_CLIENT_ID_LBN 3 2179#define ESF_DZ_S2MC_RD_CLIENT_ID_WIDTH 4 2180#define ESE_DZ_SMC_MACRO_ENGINE_ID 15 2181#define ESE_DZ_SMC_TX_DICPU_ID 14 2182#define ESE_DZ_SMC_RX_DICPU_ID 13 2183#define ESE_DZ_SMC_MC_ID 12 2184#define ESE_DZ_SMC_DL_ID 10 2185#define ESE_DZ_SMC_EV_ID 8 2186#define ESE_DZ_SMC_TX_DPCPU1_ID 5 2187#define ESE_DZ_SMC_TX_DPCPU0_ID 4 2188#define ESE_DZ_SMC_RX_DPCPU_ID 0 2189#define ESF_DZ_S2MC_RD_OP_LBN 0 2190#define ESF_DZ_S2MC_RD_OP_WIDTH 3 2191#define ESE_DZ_SMC_REQ_WR 4 2192#define ESE_DZ_SMC_REQ_RD 3 2193#define ESE_DZ_SMC_REQ_DSCR_WRITE 2 2194#define ESE_DZ_SMC_REQ_DSCR_READ 1 2195#define ESE_DZ_SMC_REQ_BUFTBL_LOOKUP 0 2196 2197 2198/* ES_SMC_MSG_RESP */ 2199#define ESF_DZ_S2MC_BASE_RSP_DATA_DW0_LBN 12 2200#define ESF_DZ_S2MC_BASE_RSP_DATA_DW0_WIDTH 32 2201#define ESF_DZ_S2MC_BASE_RSP_DATA_DW1_LBN 44 2202#define ESF_DZ_S2MC_BASE_RSP_DATA_DW1_WIDTH 32 2203#define ESF_DZ_S2MC_BASE_RSP_DATA_DW2_LBN 76 2204#define ESF_DZ_S2MC_BASE_RSP_DATA_DW2_WIDTH 8 2205#define ESF_DZ_S2MC_BASE_RSP_DATA_LBN 12 2206#define ESF_DZ_S2MC_BASE_RSP_DATA_WIDTH 72 2207#define ESF_DZ_S2MC_BASE_FAIL_LBN 11 2208#define ESF_DZ_S2MC_BASE_FAIL_WIDTH 1 2209#define ESF_DZ_S2MC_BASE_SOFT_LBN 7 2210#define ESF_DZ_S2MC_BASE_SOFT_WIDTH 4 2211#define ESF_DZ_S2MC_BASE_CLIENT_ID_LBN 3 2212#define ESF_DZ_S2MC_BASE_CLIENT_ID_WIDTH 4 2213#define ESE_DZ_SMC_MACRO_ENGINE_ID 15 2214#define ESE_DZ_SMC_TX_DICPU_ID 14 2215#define ESE_DZ_SMC_RX_DICPU_ID 13 2216#define ESE_DZ_SMC_MC_ID 12 2217#define ESE_DZ_SMC_DL_ID 10 2218#define ESE_DZ_SMC_EV_ID 8 2219#define ESE_DZ_SMC_TX_DPCPU1_ID 5 2220#define ESE_DZ_SMC_TX_DPCPU0_ID 4 2221#define ESE_DZ_SMC_RX_DPCPU_ID 0 2222#define ESF_DZ_S2MC_BASE_OP_LBN 0 2223#define ESF_DZ_S2MC_BASE_OP_WIDTH 3 2224#define ESE_DZ_SMC_REQ_WR 4 2225#define ESE_DZ_SMC_REQ_RD 3 2226#define ESE_DZ_SMC_REQ_DSCR_WRITE 2 2227#define ESE_DZ_SMC_REQ_DSCR_READ 1 2228#define ESE_DZ_SMC_REQ_BUFTBL_LOOKUP 0 2229 2230 2231/* ES_SMC_MSG_WR_REQ */ 2232#define ESF_DZ_MC2S_WR_DATA_DW0_LBN 29 2233#define ESF_DZ_MC2S_WR_DATA_DW0_WIDTH 32 2234#define ESF_DZ_MC2S_WR_DATA_DW1_LBN 61 2235#define ESF_DZ_MC2S_WR_DATA_DW1_WIDTH 32 2236#define ESF_DZ_MC2S_WR_DATA_DW2_LBN 93 2237#define ESF_DZ_MC2S_WR_DATA_DW2_WIDTH 8 2238#define ESF_DZ_MC2S_WR_DATA_LBN 29 2239#define ESF_DZ_MC2S_WR_DATA_WIDTH 72 2240#define ESF_DZ_MC2S_WR_ADDR_LBN 12 2241#define ESF_DZ_MC2S_WR_ADDR_WIDTH 17 2242#define ESF_DZ_MC2S_WR_REFLECT_LBN 11 2243#define ESF_DZ_MC2S_WR_REFLECT_WIDTH 1 2244#define ESF_DZ_MC2S_WR_SOFT_LBN 7 2245#define ESF_DZ_MC2S_WR_SOFT_WIDTH 4 2246#define ESF_DZ_MC2S_WR_CLIENT_ID_LBN 3 2247#define ESF_DZ_MC2S_WR_CLIENT_ID_WIDTH 4 2248#define ESE_DZ_SMC_MACRO_ENGINE_ID 15 2249#define ESE_DZ_SMC_TX_DICPU_ID 14 2250#define ESE_DZ_SMC_RX_DICPU_ID 13 2251#define ESE_DZ_SMC_MC_ID 12 2252#define ESE_DZ_SMC_DL_ID 10 2253#define ESE_DZ_SMC_EV_ID 8 2254#define ESE_DZ_SMC_TX_DPCPU1_ID 5 2255#define ESE_DZ_SMC_TX_DPCPU0_ID 4 2256#define ESE_DZ_SMC_RX_DPCPU_ID 0 2257#define ESF_DZ_MC2S_WR_OP_LBN 0 2258#define ESF_DZ_MC2S_WR_OP_WIDTH 3 2259#define ESE_DZ_SMC_REQ_WR 4 2260#define ESE_DZ_SMC_REQ_RD 3 2261#define ESE_DZ_SMC_REQ_DSCR_WRITE 2 2262#define ESE_DZ_SMC_REQ_DSCR_READ 1 2263#define ESE_DZ_SMC_REQ_BUFTBL_LOOKUP 0 2264 2265 2266/* ES_SMC_MSG_WR_RESP */ 2267#define ESF_DZ_S2MC_WR_FAIL_LBN 11 2268#define ESF_DZ_S2MC_WR_FAIL_WIDTH 1 2269#define ESF_DZ_S2MC_WR_SOFT_LBN 7 2270#define ESF_DZ_S2MC_WR_SOFT_WIDTH 4 2271#define ESF_DZ_S2MC_WR_CLIENT_ID_LBN 3 2272#define ESF_DZ_S2MC_WR_CLIENT_ID_WIDTH 4 2273#define ESE_DZ_SMC_MACRO_ENGINE_ID 15 2274#define ESE_DZ_SMC_TX_DICPU_ID 14 2275#define ESE_DZ_SMC_RX_DICPU_ID 13 2276#define ESE_DZ_SMC_MC_ID 12 2277#define ESE_DZ_SMC_DL_ID 10 2278#define ESE_DZ_SMC_EV_ID 8 2279#define ESE_DZ_SMC_TX_DPCPU1_ID 5 2280#define ESE_DZ_SMC_TX_DPCPU0_ID 4 2281#define ESE_DZ_SMC_RX_DPCPU_ID 0 2282#define ESF_DZ_S2MC_WR_OP_LBN 0 2283#define ESF_DZ_S2MC_WR_OP_WIDTH 3 2284#define ESE_DZ_SMC_REQ_WR 4 2285#define ESE_DZ_SMC_REQ_RD 3 2286#define ESE_DZ_SMC_REQ_DSCR_WRITE 2 2287#define ESE_DZ_SMC_REQ_DSCR_READ 1 2288#define ESE_DZ_SMC_REQ_BUFTBL_LOOKUP 0 2289 2290 2291/* ES_TX_CSUM_TSTAMP_DESC */ 2292#define ESF_DZ_TX_DESC_IS_OPT_LBN 63 2293#define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 2294#define ESF_DZ_TX_OPTION_TYPE_LBN 60 2295#define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 2296#define ESE_DZ_TX_OPTION_DESC_TSO 7 2297#define ESE_DZ_TX_OPTION_DESC_VLAN 6 2298#define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 2299#define ESF_DZ_TX_TIMESTAMP_LBN 5 2300#define ESF_DZ_TX_TIMESTAMP_WIDTH 1 2301#define ESF_DZ_TX_OPTION_CRC_MODE_LBN 2 2302#define ESF_DZ_TX_OPTION_CRC_MODE_WIDTH 3 2303#define ESE_DZ_TX_OPTION_CRC_FCOIP_MPA 5 2304#define ESE_DZ_TX_OPTION_CRC_FCOIP_FCOE 4 2305#define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR_AND_PYLD 3 2306#define ESE_DZ_TX_OPTION_CRC_ISCSI_HDR 2 2307#define ESE_DZ_TX_OPTION_CRC_FCOE 1 2308#define ESE_DZ_TX_OPTION_CRC_OFF 0 2309#define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_LBN 1 2310#define ESF_DZ_TX_OPTION_UDP_TCP_CSUM_WIDTH 1 2311#define ESF_DZ_TX_OPTION_IP_CSUM_LBN 0 2312#define ESF_DZ_TX_OPTION_IP_CSUM_WIDTH 1 2313 2314 2315/* ES_TX_EVENT */ 2316#define ESF_DZ_TX_CODE_LBN 60 2317#define ESF_DZ_TX_CODE_WIDTH 4 2318#define ESF_DZ_TX_OVERRIDE_HOLDOFF_LBN 59 2319#define ESF_DZ_TX_OVERRIDE_HOLDOFF_WIDTH 1 2320#define ESF_DZ_TX_DROP_EVENT_LBN 58 2321#define ESF_DZ_TX_DROP_EVENT_WIDTH 1 2322#define ESF_DZ_TX_EV_RSVD_LBN 48 2323#define ESF_DZ_TX_EV_RSVD_WIDTH 10 2324#define ESF_DZ_TX_SOFT2_LBN 32 2325#define ESF_DZ_TX_SOFT2_WIDTH 16 2326#define ESF_DZ_TX_CAN_MERGE_LBN 31 2327#define ESF_DZ_TX_CAN_MERGE_WIDTH 1 2328#define ESF_DZ_TX_SOFT1_LBN 24 2329#define ESF_DZ_TX_SOFT1_WIDTH 7 2330#define ESF_DZ_TX_QLABEL_LBN 16 2331#define ESF_DZ_TX_QLABEL_WIDTH 5 2332#define ESF_DZ_TX_DESCR_INDX_LBN 0 2333#define ESF_DZ_TX_DESCR_INDX_WIDTH 16 2334 2335 2336/* ES_TX_KER_DESC */ 2337#define ESF_DZ_TX_KER_TYPE_LBN 63 2338#define ESF_DZ_TX_KER_TYPE_WIDTH 1 2339#define ESF_DZ_TX_KER_CONT_LBN 62 2340#define ESF_DZ_TX_KER_CONT_WIDTH 1 2341#define ESF_DZ_TX_KER_BYTE_CNT_LBN 48 2342#define ESF_DZ_TX_KER_BYTE_CNT_WIDTH 14 2343#define ESF_DZ_TX_KER_BUF_ADDR_DW0_LBN 0 2344#define ESF_DZ_TX_KER_BUF_ADDR_DW0_WIDTH 32 2345#define ESF_DZ_TX_KER_BUF_ADDR_DW1_LBN 32 2346#define ESF_DZ_TX_KER_BUF_ADDR_DW1_WIDTH 16 2347#define ESF_DZ_TX_KER_BUF_ADDR_LBN 0 2348#define ESF_DZ_TX_KER_BUF_ADDR_WIDTH 48 2349 2350 2351/* ES_TX_PIO_DESC */ 2352#define ESF_DZ_TX_PIO_TYPE_LBN 63 2353#define ESF_DZ_TX_PIO_TYPE_WIDTH 1 2354#define ESF_DZ_TX_PIO_OPT_LBN 60 2355#define ESF_DZ_TX_PIO_OPT_WIDTH 3 2356#define ESF_DZ_TX_PIO_CONT_LBN 59 2357#define ESF_DZ_TX_PIO_CONT_WIDTH 1 2358#define ESF_DZ_TX_PIO_BYTE_CNT_LBN 32 2359#define ESF_DZ_TX_PIO_BYTE_CNT_WIDTH 12 2360#define ESF_DZ_TX_PIO_BUF_ADDR_LBN 0 2361#define ESF_DZ_TX_PIO_BUF_ADDR_WIDTH 12 2362 2363 2364/* ES_TX_TSO_DESC */ 2365#define ESF_DZ_TX_DESC_IS_OPT_LBN 63 2366#define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 2367#define ESF_DZ_TX_OPTION_TYPE_LBN 60 2368#define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 2369#define ESE_DZ_TX_OPTION_DESC_TSO 7 2370#define ESE_DZ_TX_OPTION_DESC_VLAN 6 2371#define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 2372#define ESF_DZ_TX_TSO_TCP_FLAGS_LBN 48 2373#define ESF_DZ_TX_TSO_TCP_FLAGS_WIDTH 8 2374#define ESF_DZ_TX_TSO_IP_ID_LBN 32 2375#define ESF_DZ_TX_TSO_IP_ID_WIDTH 16 2376#define ESF_DZ_TX_TSO_TCP_SEQNO_LBN 0 2377#define ESF_DZ_TX_TSO_TCP_SEQNO_WIDTH 32 2378 2379 2380/* ES_TX_USER_DESC */ 2381#define ESF_DZ_TX_USR_TYPE_LBN 63 2382#define ESF_DZ_TX_USR_TYPE_WIDTH 1 2383#define ESF_DZ_TX_USR_CONT_LBN 62 2384#define ESF_DZ_TX_USR_CONT_WIDTH 1 2385#define ESF_DZ_TX_USR_BYTE_CNT_LBN 48 2386#define ESF_DZ_TX_USR_BYTE_CNT_WIDTH 14 2387#define ESF_DZ_TX_USR_BUF_PAGE_SIZE_LBN 44 2388#define ESF_DZ_TX_USR_BUF_PAGE_SIZE_WIDTH 4 2389#define ESE_DZ_USR_BUF_PAGE_SZ_4MB 10 2390#define ESE_DZ_USR_BUF_PAGE_SZ_1MB 8 2391#define ESE_DZ_USR_BUF_PAGE_SZ_64KB 4 2392#define ESE_DZ_USR_BUF_PAGE_SZ_4KB 0 2393#define ESF_DZ_TX_USR_BUF_ID_OFFSET_DW0_LBN 0 2394#define ESF_DZ_TX_USR_BUF_ID_OFFSET_DW0_WIDTH 32 2395#define ESF_DZ_TX_USR_BUF_ID_OFFSET_DW1_LBN 32 2396#define ESF_DZ_TX_USR_BUF_ID_OFFSET_DW1_WIDTH 12 2397#define ESF_DZ_TX_USR_BUF_ID_OFFSET_LBN 0 2398#define ESF_DZ_TX_USR_BUF_ID_OFFSET_WIDTH 44 2399#define ESF_DZ_TX_USR_4KBPS_BUF_ID_LBN 12 2400#define ESF_DZ_TX_USR_4KBPS_BUF_ID_WIDTH 32 2401#define ESF_DZ_TX_USR_64KBPS_BUF_ID_LBN 16 2402#define ESF_DZ_TX_USR_64KBPS_BUF_ID_WIDTH 28 2403#define ESF_DZ_TX_USR_1MBPS_BUF_ID_LBN 20 2404#define ESF_DZ_TX_USR_1MBPS_BUF_ID_WIDTH 24 2405#define ESF_DZ_TX_USR_4MBPS_BUF_ID_LBN 22 2406#define ESF_DZ_TX_USR_4MBPS_BUF_ID_WIDTH 22 2407#define ESF_DZ_TX_USR_4MBPS_BYTE_OFFSET_LBN 0 2408#define ESF_DZ_TX_USR_4MBPS_BYTE_OFFSET_WIDTH 22 2409#define ESF_DZ_TX_USR_1MBPS_BYTE_OFFSET_LBN 0 2410#define ESF_DZ_TX_USR_1MBPS_BYTE_OFFSET_WIDTH 20 2411#define ESF_DZ_TX_USR_64KBPS_BYTE_OFFSET_LBN 0 2412#define ESF_DZ_TX_USR_64KBPS_BYTE_OFFSET_WIDTH 16 2413#define ESF_DZ_TX_USR_4KBPS_BYTE_OFFSET_LBN 0 2414#define ESF_DZ_TX_USR_4KBPS_BYTE_OFFSET_WIDTH 12 2415 2416 2417/* ES_TX_U_QSTATE_TBL0_ENTRY */ 2418#define ESF_DZ_TX_U_DC_FILL_LBN 112 2419#define ESF_DZ_TX_U_DC_FILL_WIDTH 7 2420#define ESF_DZ_TX_U_SOFT7_B1R3_LBN 112 2421#define ESF_DZ_TX_U_SOFT7_B1R3_WIDTH 7 2422#define ESF_DZ_TX_U_DSCR_HW_RPTR_LBN 96 2423#define ESF_DZ_TX_U_DSCR_HW_RPTR_WIDTH 12 2424#define ESF_DZ_TX_U_SOFT12_B1R2_LBN 96 2425#define ESF_DZ_TX_U_SOFT12_B1R2_WIDTH 12 2426#define ESF_DZ_TX_U_DC_RPTR_LBN 80 2427#define ESF_DZ_TX_U_DC_RPTR_WIDTH 6 2428#define ESF_DZ_TX_U_SOFT6_B1R1_LBN 80 2429#define ESF_DZ_TX_U_SOFT6_B1R1_WIDTH 6 2430#define ESF_DZ_TX_U_CNTAG_LBN 68 2431#define ESF_DZ_TX_U_CNTAG_WIDTH 1 2432#define ESF_DZ_TX_U_SOFT5_B1R0_LBN 64 2433#define ESF_DZ_TX_U_SOFT5_B1R0_WIDTH 5 2434#define ESF_DZ_TX_U_TIMESTAMP_LBN 67 2435#define ESF_DZ_TX_U_TIMESTAMP_WIDTH 1 2436#define ESF_DZ_TX_U_PREFETCH_ACTIVE_LBN 66 2437#define ESF_DZ_TX_U_PREFETCH_ACTIVE_WIDTH 1 2438#define ESF_DZ_TX_U_PREFETCH_PENDING_LBN 65 2439#define ESF_DZ_TX_U_PREFETCH_PENDING_WIDTH 1 2440#define ESF_DZ_TX_U_DOORBELL_ENABLED_LBN 64 2441#define ESF_DZ_TX_U_DOORBELL_ENABLED_WIDTH 1 2442#define ESF_DZ_TX_U_UPD_UDPTCP_CSUM_MODE_LBN 33 2443#define ESF_DZ_TX_U_UPD_UDPTCP_CSUM_MODE_WIDTH 1 2444#define ESF_DZ_TX_U_SOFT2_B0R2_LBN 32 2445#define ESF_DZ_TX_U_SOFT2_B0R2_WIDTH 2 2446#define ESF_DZ_TX_U_UPD_IP_CSUM_MODE_LBN 32 2447#define ESF_DZ_TX_U_UPD_IP_CSUM_MODE_WIDTH 1 2448#define ESF_DZ_TX_U_UPD_CRC_MODE_LBN 29 2449#define ESF_DZ_TX_U_UPD_CRC_MODE_WIDTH 3 2450#define ESE_DZ_C2RIP_FCOIP_MPA 5 2451#define ESE_DZ_C2RIP_FCOIP_FCOE 4 2452#define ESE_DZ_C2RIP_ISCSI_HDR_AND_PYLD 3 2453#define ESE_DZ_C2RIP_ISCSI_HDR 2 2454#define ESE_DZ_C2RIP_FCOE 1 2455#define ESE_DZ_C2RIP_OFF 0 2456#define ESF_DZ_TX_U_SOFT16_B0R1_LBN 16 2457#define ESF_DZ_TX_U_SOFT16_B0R1_WIDTH 16 2458#define ESF_DZ_TX_U_BIU_ARGS_LBN 16 2459#define ESF_DZ_TX_U_BIU_ARGS_WIDTH 13 2460#define ESF_DZ_TX_U_EV_QID_LBN 5 2461#define ESF_DZ_TX_U_EV_QID_WIDTH 11 2462#define ESF_DZ_TX_U_SOFT16_B0R0_LBN 0 2463#define ESF_DZ_TX_U_SOFT16_B0R0_WIDTH 16 2464#define ESF_DZ_TX_U_EV_QLABEL_LBN 0 2465#define ESF_DZ_TX_U_EV_QLABEL_WIDTH 5 2466 2467 2468/* ES_TX_U_QSTATE_TBL1_ENTRY */ 2469#define ESF_DZ_TX_U_DSCR_BASE_PAGE_ID_LBN 64 2470#define ESF_DZ_TX_U_DSCR_BASE_PAGE_ID_WIDTH 18 2471#define ESF_DZ_TX_U_SOFT18_B1R0_LBN 64 2472#define ESF_DZ_TX_U_SOFT18_B1R0_WIDTH 18 2473#define ESF_DZ_TX_U_SOFT16_B0R3_LBN 48 2474#define ESF_DZ_TX_U_SOFT16_B0R3_WIDTH 16 2475#define ESF_DZ_TX_U_EMERGENCY_FETCH_FAILED_LBN 56 2476#define ESF_DZ_TX_U_EMERGENCY_FETCH_FAILED_WIDTH 1 2477#define ESF_DZ_TX_U_PACER_BYPASS_OK_LBN 55 2478#define ESF_DZ_TX_U_PACER_BYPASS_OK_WIDTH 1 2479#define ESF_DZ_TX_U_STALE_DL_FETCH_LBN 54 2480#define ESF_DZ_TX_U_STALE_DL_FETCH_WIDTH 1 2481#define ESF_DZ_TX_U_ROLLBACK_IDX_REACHED_LBN 52 2482#define ESF_DZ_TX_U_ROLLBACK_IDX_REACHED_WIDTH 1 2483#define ESF_DZ_TX_U_ROLLBACK_ACTIVE_LBN 51 2484#define ESF_DZ_TX_U_ROLLBACK_ACTIVE_WIDTH 1 2485#define ESF_DZ_TX_U_QUEUE_PAUSED_LBN 50 2486#define ESF_DZ_TX_U_QUEUE_PAUSED_WIDTH 1 2487#define ESF_DZ_TX_U_QUEUE_ENABLED_LBN 49 2488#define ESF_DZ_TX_U_QUEUE_ENABLED_WIDTH 1 2489#define ESF_DZ_TX_U_FLUSH_PENDING_LBN 48 2490#define ESF_DZ_TX_U_FLUSH_PENDING_WIDTH 1 2491#define ESF_DZ_TX_U_DSCR_HW_WPTR_LBN 32 2492#define ESF_DZ_TX_U_DSCR_HW_WPTR_WIDTH 12 2493#define ESF_DZ_TX_U_SOFT12_B0R2_LBN 32 2494#define ESF_DZ_TX_U_SOFT12_B0R2_WIDTH 12 2495#define ESF_DZ_TX_U_OWNER_ID_LBN 16 2496#define ESF_DZ_TX_U_OWNER_ID_WIDTH 12 2497#define ESF_DZ_TX_U_SOFT12_B0R1_LBN 16 2498#define ESF_DZ_TX_U_SOFT12_B0R1_WIDTH 12 2499#define ESF_DZ_TX_U_DSCR_SIZE_LBN 13 2500#define ESF_DZ_TX_U_DSCR_SIZE_WIDTH 3 2501#define ESF_DZ_TX_U_SOFT3_B0R0_LBN 0 2502#define ESF_DZ_TX_U_SOFT3_B0R0_WIDTH 3 2503 2504 2505/* ES_TX_U_QSTATE_TBL2_ENTRY */ 2506#define ESF_DZ_TX_FINFO_WRD3_LBN 48 2507#define ESF_DZ_TX_FINFO_WRD3_WIDTH 16 2508#define ESF_DZ_TX_FINFO_WRD2_LBN 32 2509#define ESF_DZ_TX_FINFO_WRD2_WIDTH 16 2510#define ESF_DZ_TX_FINFO_WRD1_LBN 16 2511#define ESF_DZ_TX_FINFO_WRD1_WIDTH 16 2512#define ESF_DZ_TX_FINFO_SRCDST_LBN 0 2513#define ESF_DZ_TX_FINFO_SRCDST_WIDTH 16 2514 2515 2516/* ES_TX_VLAN_DESC */ 2517#define ESF_DZ_TX_DESC_IS_OPT_LBN 63 2518#define ESF_DZ_TX_DESC_IS_OPT_WIDTH 1 2519#define ESF_DZ_TX_OPTION_TYPE_LBN 60 2520#define ESF_DZ_TX_OPTION_TYPE_WIDTH 3 2521#define ESE_DZ_TX_OPTION_DESC_TSO 7 2522#define ESE_DZ_TX_OPTION_DESC_VLAN 6 2523#define ESE_DZ_TX_OPTION_DESC_CRC_CSUM 0 2524#define ESF_DZ_TX_VLAN_OP_LBN 32 2525#define ESF_DZ_TX_VLAN_OP_WIDTH 2 2526#define ESF_DZ_TX_VLAN_TAG2_LBN 16 2527#define ESF_DZ_TX_VLAN_TAG2_WIDTH 16 2528#define ESF_DZ_TX_VLAN_TAG1_LBN 0 2529#define ESF_DZ_TX_VLAN_TAG1_WIDTH 16 2530 2531 2532/* ES_b2t_cpl_rsp */ 2533#define ESF_DZ_B2T_CPL_RSP_CPL_ECC_LBN 284 2534#define ESF_DZ_B2T_CPL_RSP_CPL_ECC_WIDTH 32 2535#define ESF_DZ_B2T_CPL_RSP_CPL_EOT_LBN 283 2536#define ESF_DZ_B2T_CPL_RSP_CPL_EOT_WIDTH 1 2537#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW0_LBN 27 2538#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW0_WIDTH 32 2539#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW1_LBN 59 2540#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW1_WIDTH 32 2541#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW2_LBN 91 2542#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW2_WIDTH 32 2543#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW3_LBN 123 2544#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW3_WIDTH 32 2545#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW4_LBN 155 2546#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW4_WIDTH 32 2547#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW5_LBN 187 2548#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW5_WIDTH 32 2549#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW6_LBN 219 2550#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW6_WIDTH 32 2551#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW7_LBN 251 2552#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_DW7_WIDTH 32 2553#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_LBN 27 2554#define ESF_DZ_B2T_CPL_RSP_CPL_DATA_WIDTH 256 2555#define ESF_DZ_B2T_CPL_RSP_CPL_ERROR_LBN 26 2556#define ESF_DZ_B2T_CPL_RSP_CPL_ERROR_WIDTH 1 2557#define ESF_DZ_B2T_CPL_RSP_CPL_LAST_LBN 25 2558#define ESF_DZ_B2T_CPL_RSP_CPL_LAST_WIDTH 1 2559#define ESF_DZ_B2T_CPL_RSP_CPL_TAG_LBN 19 2560#define ESF_DZ_B2T_CPL_RSP_CPL_TAG_WIDTH 6 2561#define ESF_DZ_B2T_CPL_RSP_CPL_LEN_LBN 7 2562#define ESF_DZ_B2T_CPL_RSP_CPL_LEN_WIDTH 12 2563#define ESF_DZ_B2T_CPL_RSP_CPL_ADRS_LBN 0 2564#define ESF_DZ_B2T_CPL_RSP_CPL_ADRS_WIDTH 7 2565 2566 2567/* ES_fltr_info_wrd_mac_to_rx */ 2568#define ESF_DZ_FLTR_INFO_MAC_TO_RX_RESERVED2_LBN 112 2569#define ESF_DZ_FLTR_INFO_MAC_TO_RX_RESERVED2_WIDTH 16 2570#define ESF_DZ_FLTR_INFO_MAC_TO_RX_TIMESTAMP2_LBN 96 2571#define ESF_DZ_FLTR_INFO_MAC_TO_RX_TIMESTAMP2_WIDTH 16 2572#define ESF_DZ_FLTR_INFO_MAC_TO_RX_TIMESTAMP1_LBN 80 2573#define ESF_DZ_FLTR_INFO_MAC_TO_RX_TIMESTAMP1_WIDTH 16 2574#define ESF_DZ_FLTR_INFO_MAC_TO_RX_TIMESTAMP0_LBN 64 2575#define ESF_DZ_FLTR_INFO_MAC_TO_RX_TIMESTAMP0_WIDTH 16 2576#define ESF_DZ_FLTR_INFO_MAC_TO_RX_RESERVED1_LBN 48 2577#define ESF_DZ_FLTR_INFO_MAC_TO_RX_RESERVED1_WIDTH 16 2578#define ESF_DZ_FLTR_INFO_MAC_TO_RX_IPSEC_SA_LBN 32 2579#define ESF_DZ_FLTR_INFO_MAC_TO_RX_IPSEC_SA_WIDTH 16 2580#define ESF_DZ_FLTR_INFO_MAC_TO_RX_RESERVED0_LBN 8 2581#define ESF_DZ_FLTR_INFO_MAC_TO_RX_RESERVED0_WIDTH 24 2582#define ESF_DZ_FLTR_INFO_MAC_TO_RX_IPSEC_LBN 7 2583#define ESF_DZ_FLTR_INFO_MAC_TO_RX_IPSEC_WIDTH 1 2584#define ESF_DZ_FLTR_INFO_MAC_TO_RX_PRIORITY_LBN 4 2585#define ESF_DZ_FLTR_INFO_MAC_TO_RX_PRIORITY_WIDTH 3 2586#define ESF_DZ_FLTR_INFO_MAC_TO_RX_SRC_LBN 0 2587#define ESF_DZ_FLTR_INFO_MAC_TO_RX_SRC_WIDTH 4 2588 2589 2590/* ES_fltr_info_wrd_mc_pdma */ 2591#define ESF_DZ_FLTR_INFO_MC_PDMA_FLTR_OUT_LBN 64 2592#define ESF_DZ_FLTR_INFO_MC_PDMA_FLTR_OUT_WIDTH 16 2593#define ESE_DZ_FLTR_MULTICAST_VLAN 512 2594#define ESE_DZ_FLTR_MAC_VLAN 256 2595#define ESE_DZ_FLTR_STRUCTURED7 128 2596#define ESE_DZ_FLTR_STRUCTURED6 64 2597#define ESE_DZ_FLTR_STRUCTURED5 32 2598#define ESE_DZ_FLTR_STRUCTURED4 16 2599#define ESE_DZ_FLTR_STRUCTURED3 8 2600#define ESE_DZ_FLTR_STRUCTURED2 4 2601#define ESE_DZ_FLTR_STRUCTURED1 2 2602#define ESE_DZ_FLTR_STRUCTURED0 1 2603#define ESF_DZ_FLTR_INFO_MC_PDMA_TIMESTAMP_DW0_LBN 16 2604#define ESF_DZ_FLTR_INFO_MC_PDMA_TIMESTAMP_DW0_WIDTH 32 2605#define ESF_DZ_FLTR_INFO_MC_PDMA_TIMESTAMP_DW1_LBN 48 2606#define ESF_DZ_FLTR_INFO_MC_PDMA_TIMESTAMP_DW1_WIDTH 16 2607#define ESF_DZ_FLTR_INFO_MC_PDMA_TIMESTAMP_LBN 16 2608#define ESF_DZ_FLTR_INFO_MC_PDMA_TIMESTAMP_WIDTH 48 2609#define ESF_DZ_FLTR_INFO_MC_PDMA_DST_LBN 8 2610#define ESF_DZ_FLTR_INFO_MC_PDMA_DST_WIDTH 8 2611#define ESE_DZ_DST_NCSI 64 2612#define ESE_DZ_DST_PORT0 32 2613#define ESE_DZ_DST_PORT1 16 2614#define ESE_DZ_DST_PORT0_IPSEC 8 2615#define ESE_DZ_DST_PORT1_IPSEC 4 2616#define ESE_DZ_DST_PM 2 2617#define ESE_DZ_DST_TIMESTAMP 1 2618#define ESF_DZ_FLTR_INFO_MC_PDMA_PRIORITY_LBN 4 2619#define ESF_DZ_FLTR_INFO_MC_PDMA_PRIORITY_WIDTH 4 2620#define ESF_DZ_FLTR_INFO_MC_PDMA_SRC_LBN 0 2621#define ESF_DZ_FLTR_INFO_MC_PDMA_SRC_WIDTH 4 2622 2623 2624/* ES_fltr_info_wrd_rxdi_to_rxdp */ 2625#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_INNER_VLAN_LBN 112 2626#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_INNER_VLAN_WIDTH 16 2627#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_OUTER_VLAN_LBN 96 2628#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_OUTER_VLAN_WIDTH 16 2629#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_THASH1_LBN 80 2630#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_THASH1_WIDTH 16 2631#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_THASH0_LBN 64 2632#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_THASH0_WIDTH 16 2633#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_TIMESTAMP1_LBN 48 2634#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_TIMESTAMP1_WIDTH 16 2635#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_TIMESTAMP0_LBN 32 2636#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_TIMESTAMP0_WIDTH 16 2637#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_CNP_LBN 31 2638#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_CNP_WIDTH 1 2639#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_IVP_LBN 30 2640#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_IVP_WIDTH 1 2641#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_OVP_LBN 29 2642#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_OVP_WIDTH 1 2643#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_ST2_LBN 28 2644#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_ST2_WIDTH 1 2645#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_ST1_LBN 27 2646#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_ST1_WIDTH 1 2647#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_ST0_LBN 26 2648#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_ST0_WIDTH 1 2649#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_RX_QID_LBN 16 2650#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_RX_QID_WIDTH 10 2651#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_HOST_LBN 15 2652#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_HOST_WIDTH 1 2653#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_MC_LBN 14 2654#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_MC_WIDTH 1 2655#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_P0_LBN 13 2656#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_P0_WIDTH 1 2657#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_P1_LBN 12 2658#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_P1_WIDTH 1 2659#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_RESERVED1_LBN 11 2660#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_RESERVED1_WIDTH 1 2661#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_CRF_LBN 10 2662#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_DST_CRF_WIDTH 1 2663#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_RESERVED0_LBN 9 2664#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_RESERVED0_WIDTH 1 2665#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_REPLAY_LBN 8 2666#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_REPLAY_WIDTH 1 2667#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_IPSEC_LBN 7 2668#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_IPSEC_WIDTH 1 2669#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_PRIORITY_LBN 4 2670#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_PRIORITY_WIDTH 3 2671#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_SRC_LBN 0 2672#define ESF_DZ_FLTR_INFO_RXDI_TO_RXDP_SRC_WIDTH 4 2673 2674 2675/* ES_fltr_info_wrd_rxdp_to_host */ 2676#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RESERVED3_LBN 33 2677#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RESERVED3_WIDTH 31 2678#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RMON_SOFT_LBN 32 2679#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RMON_SOFT_WIDTH 1 2680#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RESERVED2_LBN 27 2681#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RESERVED2_WIDTH 5 2682#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RX_QID_LBN 16 2683#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RX_QID_WIDTH 11 2684#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_HOST_LBN 15 2685#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_HOST_WIDTH 1 2686#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_MC_LBN 14 2687#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_MC_WIDTH 1 2688#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_P0_LBN 13 2689#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_P0_WIDTH 1 2690#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_P1_LBN 12 2691#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_P1_WIDTH 1 2692#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RESERVED1_LBN 11 2693#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RESERVED1_WIDTH 1 2694#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_CRF_LBN 10 2695#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_DST_CRF_WIDTH 1 2696#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RESERVED0_LBN 9 2697#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_RESERVED0_WIDTH 1 2698#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_REPLAY_LBN 8 2699#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_REPLAY_WIDTH 1 2700#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_IPSEC_LBN 7 2701#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_IPSEC_WIDTH 1 2702#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_PRIORITY_LBN 4 2703#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_PRIORITY_WIDTH 3 2704#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_SRC_LBN 0 2705#define ESF_DZ_FLTR_INFO_RXDP_TO_HOST_SRC_WIDTH 4 2706 2707 2708/* ES_fltr_info_wrd_tx_to_mac */ 2709#define ESF_DZ_FLTR_INFO_TX_TO_MAC_PRV_LBN 63 2710#define ESF_DZ_FLTR_INFO_TX_TO_MAC_PRV_WIDTH 1 2711#define ESF_DZ_FLTR_INFO_TX_TO_MAC_LB_LBN 62 2712#define ESF_DZ_FLTR_INFO_TX_TO_MAC_LB_WIDTH 1 2713#define ESF_DZ_FLTR_INFO_TX_TO_MAC_MS0_LBN 61 2714#define ESF_DZ_FLTR_INFO_TX_TO_MAC_MS0_WIDTH 1 2715#define ESF_DZ_FLTR_INFO_TX_TO_MAC_MS1_LBN 60 2716#define ESF_DZ_FLTR_INFO_TX_TO_MAC_MS1_WIDTH 1 2717#define ESF_DZ_FLTR_INFO_TX_TO_MAC_NDI_LBN 59 2718#define ESF_DZ_FLTR_INFO_TX_TO_MAC_NDI_WIDTH 1 2719#define ESF_DZ_FLTR_INFO_TX_TO_MAC_RESERVED2_LBN 48 2720#define ESF_DZ_FLTR_INFO_TX_TO_MAC_RESERVED2_WIDTH 11 2721#define ESF_DZ_FLTR_INFO_TX_TO_MAC_IPSEC_SA_LBN 32 2722#define ESF_DZ_FLTR_INFO_TX_TO_MAC_IPSEC_SA_WIDTH 16 2723#define ESF_DZ_FLTR_INFO_TX_TO_MAC_TX_STACK_ID_LBN 24 2724#define ESF_DZ_FLTR_INFO_TX_TO_MAC_TX_STACK_ID_WIDTH 8 2725#define ESF_DZ_FLTR_INFO_TX_TO_MAC_TX_DOMAIN_LBN 16 2726#define ESF_DZ_FLTR_INFO_TX_TO_MAC_TX_DOMAIN_WIDTH 8 2727#define ESF_DZ_FLTR_INFO_TX_TO_MAC_RESERVED1_LBN 14 2728#define ESF_DZ_FLTR_INFO_TX_TO_MAC_RESERVED1_WIDTH 2 2729#define ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_P0_LBN 13 2730#define ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_P0_WIDTH 1 2731#define ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_P1_LBN 12 2732#define ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_P1_WIDTH 1 2733#define ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_IP0_LBN 11 2734#define ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_IP0_WIDTH 1 2735#define ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_IP1_LBN 10 2736#define ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_IP1_WIDTH 1 2737#define ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_PM_LBN 9 2738#define ESF_DZ_FLTR_INFO_TX_TO_MAC_DST_PM_WIDTH 1 2739#define ESF_DZ_FLTR_INFO_TX_TO_MAC_RESERVED0_LBN 8 2740#define ESF_DZ_FLTR_INFO_TX_TO_MAC_RESERVED0_WIDTH 1 2741#define ESF_DZ_FLTR_INFO_TX_TO_MAC_IPSEC_LBN 7 2742#define ESF_DZ_FLTR_INFO_TX_TO_MAC_IPSEC_WIDTH 1 2743#define ESF_DZ_FLTR_INFO_TX_TO_MAC_PRIORITY_LBN 4 2744#define ESF_DZ_FLTR_INFO_TX_TO_MAC_PRIORITY_WIDTH 3 2745#define ESF_DZ_FLTR_INFO_TX_TO_MAC_SRC_LBN 0 2746#define ESF_DZ_FLTR_INFO_TX_TO_MAC_SRC_WIDTH 4 2747 2748 2749/* ES_fltr_info_wrd_txdi_to_txdp */ 2750#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_INNER_VLAN_LBN 112 2751#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_INNER_VLAN_WIDTH 16 2752#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_OUTER_VLAN_LBN 96 2753#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_OUTER_VLAN_WIDTH 16 2754#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_CNP_LBN 95 2755#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_CNP_WIDTH 1 2756#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_IVP_LBN 94 2757#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_IVP_WIDTH 1 2758#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_OVP_LBN 93 2759#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_OVP_WIDTH 1 2760#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_RESERVED4_LBN 90 2761#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_RESERVED4_WIDTH 3 2762#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_QID_LBN 80 2763#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_QID_WIDTH 10 2764#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_VRI_LBN 79 2765#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_VRI_WIDTH 1 2766#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_RESERVED3_LBN 78 2767#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_RESERVED3_WIDTH 1 2768#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_MTU_DIV4_LBN 66 2769#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_MTU_DIV4_WIDTH 12 2770#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_VRI_OP_LBN 64 2771#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_VRI_OP_WIDTH 2 2772#define ESE_DZ_VRI_OP_INSERT_REPLACE 3 2773#define ESE_DZ_VRI_OP_INSERT_INSERT 2 2774#define ESE_DZ_VRI_OP_REPLACE 1 2775#define ESE_DZ_VRI_OP_INSERT 0 2776#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_PRV_LBN 63 2777#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_PRV_WIDTH 1 2778#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_LB_LBN 62 2779#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_LB_WIDTH 1 2780#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_MS0_LBN 61 2781#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_MS0_WIDTH 1 2782#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_MS1_LBN 60 2783#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_MS1_WIDTH 1 2784#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_NDI_LBN 59 2785#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_NDI_WIDTH 1 2786#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_TXDP_CONTEXT_OUT_LBN 48 2787#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_TXDP_CONTEXT_OUT_WIDTH 11 2788#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_IPSEC_SA_LBN 32 2789#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_IPSEC_SA_WIDTH 16 2790#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_TX_STACK_ID_LBN 24 2791#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_TX_STACK_ID_WIDTH 8 2792#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_TX_DOMAIN_LBN 16 2793#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_TX_DOMAIN_WIDTH 8 2794#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_RESERVED1_LBN 14 2795#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_RESERVED1_WIDTH 2 2796#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_P0_LBN 13 2797#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_P0_WIDTH 1 2798#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_P1_LBN 12 2799#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_P1_WIDTH 1 2800#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_IP0_LBN 11 2801#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_IP0_WIDTH 1 2802#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_IP1_LBN 10 2803#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_IP1_WIDTH 1 2804#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_PM_LBN 9 2805#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_DST_PM_WIDTH 1 2806#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_RESERVED0_LBN 8 2807#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_RESERVED0_WIDTH 1 2808#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_IPSEC_LBN 7 2809#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_IPSEC_WIDTH 1 2810#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_PRIORITY_LBN 4 2811#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_PRIORITY_WIDTH 3 2812#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_SRC_LBN 0 2813#define ESF_DZ_FLTR_INFO_TXDI_TO_TXDP_SRC_WIDTH 4 2814 2815 2816/* ES_fltr_info_wrd_txdp_to_txdi */ 2817#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_VLAN_OP_LBN 62 2818#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_VLAN_OP_WIDTH 2 2819#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_RESERVED1_LBN 58 2820#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_RESERVED1_WIDTH 4 2821#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_TX_QID_LBN 48 2822#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_TX_QID_WIDTH 10 2823#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_INNER_VLAN_LBN 32 2824#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_INNER_VLAN_WIDTH 16 2825#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_OUTER_VLAN_LBN 16 2826#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_OUTER_VLAN_WIDTH 16 2827#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_TXDP_CONTEXT_IN_LBN 5 2828#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_TXDP_CONTEXT_IN_WIDTH 11 2829#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_RESERVED0_LBN 4 2830#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_RESERVED0_WIDTH 1 2831#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_SRC_LBN 0 2832#define ESF_DZ_FLTR_INFO_TXDP_TO_TXDI_SRC_WIDTH 4 2833 2834 2835/* ES_nwk_ev_merge_blk_cmd */ 2836#define ESF_DZ_EV_MERGE_BLK_COMMAND_OP_LBN 28 2837#define ESF_DZ_EV_MERGE_BLK_COMMAND_OP_WIDTH 4 2838#define ESE_DZ_EV_MERGE_BLK_COMMAND_OP_FLUSH 2 2839#define ESE_DZ_EV_MERGE_BLK_COMMAND_OP_ENABLE 1 2840#define ESE_DZ_EV_MERGE_BLK_COMMAND_OP_DISABLE 0 2841#define ESF_DZ_EV_MERGE_BLK_COMMAND_BUSY_LBN 31 2842#define ESF_DZ_EV_MERGE_BLK_COMMAND_BUSY_WIDTH 1 2843#define ESF_DZ_EV_MERGE_BLK_COMMAND_EVQ_IDX_LBN 0 2844#define ESF_DZ_EV_MERGE_BLK_COMMAND_EVQ_IDX_WIDTH 11 2845 2846 2847/* ES_txpm2ini_cpl_rsp */ 2848#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_ECC_LBN 284 2849#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_ECC_WIDTH 32 2850#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_EOT_LBN 283 2851#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_EOT_WIDTH 1 2852#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW0_LBN 27 2853#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW0_WIDTH 32 2854#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW1_LBN 59 2855#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW1_WIDTH 32 2856#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW2_LBN 91 2857#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW2_WIDTH 32 2858#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW3_LBN 123 2859#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW3_WIDTH 32 2860#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW4_LBN 155 2861#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW4_WIDTH 32 2862#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW5_LBN 187 2863#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW5_WIDTH 32 2864#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW6_LBN 219 2865#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW6_WIDTH 32 2866#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW7_LBN 251 2867#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_DW7_WIDTH 32 2868#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_LBN 27 2869#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_DATA_WIDTH 256 2870#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_ERROR_LBN 26 2871#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_ERROR_WIDTH 1 2872#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_LAST_LBN 25 2873#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_LAST_WIDTH 1 2874#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_TAG_LBN 19 2875#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_TAG_WIDTH 6 2876#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_LEN_LBN 7 2877#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_LEN_WIDTH 12 2878#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_ADRS_LBN 0 2879#define ESF_DZ_TXPM2INI_CPL_RSP_CPL_ADRS_WIDTH 7 2880 2881 2882 2883/* Enum INI_OP */ 2884#define ESE_DZ_RD_COMPL 0x3 2885#define ESE_DZ_NOP 0x2 2886#define ESE_DZ_WR 0x1 2887#define ESE_DZ_RD 0x0 2888 2889/* Enum INT_OP */ 2890#define ESE_DZ_LEGACY 0x2 2891#define ESE_DZ_MSI 0x1 2892#define ESE_DZ_MSIX 0x0 2893 2894/* Enum MC_PDMA_BUFFER_ID */ 2895#define ESE_DZ_MC_PDMA_BUFFER_ALL 4 2896#define ESE_DZ_MC_PDMA_BUFFER_RXDP 3 2897#define ESE_DZ_MC_PDMA_BUFFER_NCSI 2 2898#define ESE_DZ_MC_PDMA_BUFFER_NWPORT1 1 2899#define ESE_DZ_MC_PDMA_BUFFER_NWPORT0 0 2900 2901/* Enum MC_PDMA_INTERFACE_ID */ 2902#define ESE_DZ_MC_PDMA_INTERFACE_RXDP 3 2903#define ESE_DZ_MC_PDMA_INTERFACE_NCSI 2 2904#define ESE_DZ_MC_PDMA_INTERFACE_NWPORT1 1 2905#define ESE_DZ_MC_PDMA_INTERFACE_NWPORT0 0 2906 2907/* Enum PKT_STRM_CTL */ 2908#define ESE_DZ_EOP_TRUNC 0x3 2909#define ESE_DZ_EOP_CRC_ERR 0x2 2910#define ESE_DZ_EOP 0x1 2911#define ESE_DZ_NOOP 0x0 2912 2913/* Enum PM_EPI_PKT_MARKER */ 2914#define ESE_DZ_PM_EPI_LST 0x3 2915#define ESE_DZ_PM_EPI_OBL 0x2 2916#define ESE_DZ_PM_EPI_TBL 0x1 2917#define ESE_DZ_PM_EPI_MDL 0x0 2918 2919/* Enum PM_IPI_TO_PM_MM_COMMAND */ 2920#define ESE_DZ_FREE_CHAIN 0x3 2921#define ESE_DZ_FREE_BUFFER 0x2 2922#define ESE_DZ_ADD_BUFFER 0x1 2923#define ESE_DZ_PM_MM_NOOP 0x0 2924 2925/* Enum PM_MA_TO_PM_EPI_COMMAND */ 2926#define ESE_DZ_FROM_PORT_D 0x4 2927#define ESE_DZ_FROM_PORT_C 0x3 2928#define ESE_DZ_FROM_PORT_B 0x2 2929#define ESE_DZ_FROM_PORT_A 0x1 2930#define ESE_DZ_PM_EPI_NOOP 0x0 2931 2932/* Enum PM_MA_TO_PM_IPI_COMMAND */ 2933#define ESE_DZ_TO_PORT_D 0x4 2934#define ESE_DZ_TO_PORT_C 0x3 2935#define ESE_DZ_TO_PORT_B 0x2 2936#define ESE_DZ_TO_PORT_A 0x1 2937#define ESE_DZ_PM_IPI_NOOP 0x0 2938#ifdef __cplusplus 2939} 2940#endif 2941 2942#endif /* _SYS_EFX_EF10_REGS_H */ 2943