efx_regs.h revision 284555
1/*- 2 * Copyright (c) 2007-2015 Solarflare Communications Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are met: 7 * 8 * 1. Redistributions of source code must retain the above copyright notice, 9 * this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright notice, 11 * this list of conditions and the following disclaimer in the documentation 12 * and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR 18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * The views and conclusions contained in the software and documentation are 27 * those of the authors and should not be interpreted as representing official 28 * policies, either expressed or implied, of the FreeBSD Project. 29 * 30 * $FreeBSD: stable/10/sys/dev/sfxge/common/efx_regs.h 284555 2015-06-18 15:46:39Z arybchik $ 31 */ 32 33#ifndef _SYS_EFX_REGS_H 34#define _SYS_EFX_REGS_H 35 36 37#ifdef __cplusplus 38extern "C" { 39#endif 40 41 42/************************************************************************** 43 * 44 * Falcon/Siena registers and descriptors 45 * 46 ************************************************************************** 47 */ 48 49/* 50 * FR_AB_EE_VPD_CFG0_REG_SF(128bit): 51 * SPI/VPD configuration register 0 52 */ 53#define FR_AB_EE_VPD_CFG0_REG_SF_OFST 0x00000300 54/* falcona0,falconb0=eeprom_flash */ 55/* 56 * FR_AB_EE_VPD_CFG0_REG(128bit): 57 * SPI/VPD configuration register 0 58 */ 59#define FR_AB_EE_VPD_CFG0_REG_OFST 0x00000140 60/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 61 62#define FRF_AB_EE_SF_FASTRD_EN_LBN 127 63#define FRF_AB_EE_SF_FASTRD_EN_WIDTH 1 64#define FRF_AB_EE_SF_CLOCK_DIV_LBN 120 65#define FRF_AB_EE_SF_CLOCK_DIV_WIDTH 7 66#define FRF_AB_EE_VPD_WIP_POLL_LBN 119 67#define FRF_AB_EE_VPD_WIP_POLL_WIDTH 1 68#define FRF_AB_EE_EE_CLOCK_DIV_LBN 112 69#define FRF_AB_EE_EE_CLOCK_DIV_WIDTH 7 70#define FRF_AB_EE_EE_WR_TMR_VALUE_LBN 96 71#define FRF_AB_EE_EE_WR_TMR_VALUE_WIDTH 16 72#define FRF_AB_EE_VPDW_LENGTH_LBN 80 73#define FRF_AB_EE_VPDW_LENGTH_WIDTH 15 74#define FRF_AB_EE_VPDW_BASE_LBN 64 75#define FRF_AB_EE_VPDW_BASE_WIDTH 15 76#define FRF_AB_EE_VPD_WR_CMD_EN_LBN 56 77#define FRF_AB_EE_VPD_WR_CMD_EN_WIDTH 8 78#define FRF_AB_EE_VPD_BASE_LBN 32 79#define FRF_AB_EE_VPD_BASE_WIDTH 24 80#define FRF_AB_EE_VPD_LENGTH_LBN 16 81#define FRF_AB_EE_VPD_LENGTH_WIDTH 15 82#define FRF_AB_EE_VPD_AD_SIZE_LBN 8 83#define FRF_AB_EE_VPD_AD_SIZE_WIDTH 5 84#define FRF_AB_EE_VPD_ACCESS_ON_LBN 5 85#define FRF_AB_EE_VPD_ACCESS_ON_WIDTH 1 86#define FRF_AB_EE_VPD_ACCESS_BLOCK_LBN 4 87#define FRF_AB_EE_VPD_ACCESS_BLOCK_WIDTH 1 88#define FRF_AB_EE_VPD_DEV_SF_SEL_LBN 2 89#define FRF_AB_EE_VPD_DEV_SF_SEL_WIDTH 1 90#define FRF_AB_EE_VPD_EN_AD9_MODE_LBN 1 91#define FRF_AB_EE_VPD_EN_AD9_MODE_WIDTH 1 92#define FRF_AB_EE_VPD_EN_LBN 0 93#define FRF_AB_EE_VPD_EN_WIDTH 1 94 95 96/* 97 * FR_AB_PCIE_SD_CTL0123_REG_SF(128bit): 98 * PCIE SerDes control register 0 to 3 99 */ 100#define FR_AB_PCIE_SD_CTL0123_REG_SF_OFST 0x00000320 101/* falcona0,falconb0=eeprom_flash */ 102/* 103 * FR_AB_PCIE_SD_CTL0123_REG(128bit): 104 * PCIE SerDes control register 0 to 3 105 */ 106#define FR_AB_PCIE_SD_CTL0123_REG_OFST 0x00000320 107/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 108 109#define FRF_AB_PCIE_TESTSIG_H_LBN 96 110#define FRF_AB_PCIE_TESTSIG_H_WIDTH 19 111#define FRF_AB_PCIE_TESTSIG_L_LBN 64 112#define FRF_AB_PCIE_TESTSIG_L_WIDTH 19 113#define FRF_AB_PCIE_OFFSET_LBN 56 114#define FRF_AB_PCIE_OFFSET_WIDTH 8 115#define FRF_AB_PCIE_OFFSETEN_H_LBN 55 116#define FRF_AB_PCIE_OFFSETEN_H_WIDTH 1 117#define FRF_AB_PCIE_OFFSETEN_L_LBN 54 118#define FRF_AB_PCIE_OFFSETEN_L_WIDTH 1 119#define FRF_AB_PCIE_HIVMODE_H_LBN 53 120#define FRF_AB_PCIE_HIVMODE_H_WIDTH 1 121#define FRF_AB_PCIE_HIVMODE_L_LBN 52 122#define FRF_AB_PCIE_HIVMODE_L_WIDTH 1 123#define FRF_AB_PCIE_PARRESET_H_LBN 51 124#define FRF_AB_PCIE_PARRESET_H_WIDTH 1 125#define FRF_AB_PCIE_PARRESET_L_LBN 50 126#define FRF_AB_PCIE_PARRESET_L_WIDTH 1 127#define FRF_AB_PCIE_LPBKWDRV_H_LBN 49 128#define FRF_AB_PCIE_LPBKWDRV_H_WIDTH 1 129#define FRF_AB_PCIE_LPBKWDRV_L_LBN 48 130#define FRF_AB_PCIE_LPBKWDRV_L_WIDTH 1 131#define FRF_AB_PCIE_LPBK_LBN 40 132#define FRF_AB_PCIE_LPBK_WIDTH 8 133#define FRF_AB_PCIE_PARLPBK_LBN 32 134#define FRF_AB_PCIE_PARLPBK_WIDTH 8 135#define FRF_AB_PCIE_RXTERMADJ_H_LBN 30 136#define FRF_AB_PCIE_RXTERMADJ_H_WIDTH 2 137#define FRF_AB_PCIE_RXTERMADJ_L_LBN 28 138#define FRF_AB_PCIE_RXTERMADJ_L_WIDTH 2 139#define FFE_AB_PCIE_RXTERMADJ_MIN15PCNT 3 140#define FFE_AB_PCIE_RXTERMADJ_PL10PCNT 2 141#define FFE_AB_PCIE_RXTERMADJ_MIN17PCNT 1 142#define FFE_AB_PCIE_RXTERMADJ_NOMNL 0 143#define FRF_AB_PCIE_TXTERMADJ_H_LBN 26 144#define FRF_AB_PCIE_TXTERMADJ_H_WIDTH 2 145#define FRF_AB_PCIE_TXTERMADJ_L_LBN 24 146#define FRF_AB_PCIE_TXTERMADJ_L_WIDTH 2 147#define FFE_AB_PCIE_TXTERMADJ_MIN15PCNT 3 148#define FFE_AB_PCIE_TXTERMADJ_PL10PCNT 2 149#define FFE_AB_PCIE_TXTERMADJ_MIN17PCNT 1 150#define FFE_AB_PCIE_TXTERMADJ_NOMNL 0 151#define FRF_AB_PCIE_RXEQCTL_H_LBN 18 152#define FRF_AB_PCIE_RXEQCTL_H_WIDTH 2 153#define FRF_AB_PCIE_RXEQCTL_L_LBN 16 154#define FRF_AB_PCIE_RXEQCTL_L_WIDTH 2 155#define FFE_AB_PCIE_RXEQCTL_OFF_ALT 3 156#define FFE_AB_PCIE_RXEQCTL_OFF 2 157#define FFE_AB_PCIE_RXEQCTL_MIN 1 158#define FFE_AB_PCIE_RXEQCTL_MAX 0 159#define FRF_AB_PCIE_HIDRV_LBN 8 160#define FRF_AB_PCIE_HIDRV_WIDTH 8 161#define FRF_AB_PCIE_LODRV_LBN 0 162#define FRF_AB_PCIE_LODRV_WIDTH 8 163 164 165/* 166 * FR_AB_PCIE_SD_CTL45_REG_SF(128bit): 167 * PCIE SerDes control register 4 and 5 168 */ 169#define FR_AB_PCIE_SD_CTL45_REG_SF_OFST 0x00000330 170/* falcona0,falconb0=eeprom_flash */ 171/* 172 * FR_AB_PCIE_SD_CTL45_REG(128bit): 173 * PCIE SerDes control register 4 and 5 174 */ 175#define FR_AB_PCIE_SD_CTL45_REG_OFST 0x00000330 176/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 177 178#define FRF_AB_PCIE_DTX7_LBN 60 179#define FRF_AB_PCIE_DTX7_WIDTH 4 180#define FRF_AB_PCIE_DTX6_LBN 56 181#define FRF_AB_PCIE_DTX6_WIDTH 4 182#define FRF_AB_PCIE_DTX5_LBN 52 183#define FRF_AB_PCIE_DTX5_WIDTH 4 184#define FRF_AB_PCIE_DTX4_LBN 48 185#define FRF_AB_PCIE_DTX4_WIDTH 4 186#define FRF_AB_PCIE_DTX3_LBN 44 187#define FRF_AB_PCIE_DTX3_WIDTH 4 188#define FRF_AB_PCIE_DTX2_LBN 40 189#define FRF_AB_PCIE_DTX2_WIDTH 4 190#define FRF_AB_PCIE_DTX1_LBN 36 191#define FRF_AB_PCIE_DTX1_WIDTH 4 192#define FRF_AB_PCIE_DTX0_LBN 32 193#define FRF_AB_PCIE_DTX0_WIDTH 4 194#define FRF_AB_PCIE_DEQ7_LBN 28 195#define FRF_AB_PCIE_DEQ7_WIDTH 4 196#define FRF_AB_PCIE_DEQ6_LBN 24 197#define FRF_AB_PCIE_DEQ6_WIDTH 4 198#define FRF_AB_PCIE_DEQ5_LBN 20 199#define FRF_AB_PCIE_DEQ5_WIDTH 4 200#define FRF_AB_PCIE_DEQ4_LBN 16 201#define FRF_AB_PCIE_DEQ4_WIDTH 4 202#define FRF_AB_PCIE_DEQ3_LBN 12 203#define FRF_AB_PCIE_DEQ3_WIDTH 4 204#define FRF_AB_PCIE_DEQ2_LBN 8 205#define FRF_AB_PCIE_DEQ2_WIDTH 4 206#define FRF_AB_PCIE_DEQ1_LBN 4 207#define FRF_AB_PCIE_DEQ1_WIDTH 4 208#define FRF_AB_PCIE_DEQ0_LBN 0 209#define FRF_AB_PCIE_DEQ0_WIDTH 4 210 211 212/* 213 * FR_AB_PCIE_PCS_CTL_STAT_REG_SF(128bit): 214 * PCIE PCS control and status register 215 */ 216#define FR_AB_PCIE_PCS_CTL_STAT_REG_SF_OFST 0x00000340 217/* falcona0,falconb0=eeprom_flash */ 218/* 219 * FR_AB_PCIE_PCS_CTL_STAT_REG(128bit): 220 * PCIE PCS control and status register 221 */ 222#define FR_AB_PCIE_PCS_CTL_STAT_REG_OFST 0x00000340 223/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 224 225#define FRF_AB_PCIE_PRBSERRCOUNT0_H_LBN 52 226#define FRF_AB_PCIE_PRBSERRCOUNT0_H_WIDTH 4 227#define FRF_AB_PCIE_PRBSERRCOUNT0_L_LBN 48 228#define FRF_AB_PCIE_PRBSERRCOUNT0_L_WIDTH 4 229#define FRF_AB_PCIE_PRBSERR_LBN 40 230#define FRF_AB_PCIE_PRBSERR_WIDTH 8 231#define FRF_AB_PCIE_PRBSERRH0_LBN 32 232#define FRF_AB_PCIE_PRBSERRH0_WIDTH 8 233#define FRF_AB_PCIE_FASTINIT_H_LBN 15 234#define FRF_AB_PCIE_FASTINIT_H_WIDTH 1 235#define FRF_AB_PCIE_FASTINIT_L_LBN 14 236#define FRF_AB_PCIE_FASTINIT_L_WIDTH 1 237#define FRF_AB_PCIE_CTCDISABLE_H_LBN 13 238#define FRF_AB_PCIE_CTCDISABLE_H_WIDTH 1 239#define FRF_AB_PCIE_CTCDISABLE_L_LBN 12 240#define FRF_AB_PCIE_CTCDISABLE_L_WIDTH 1 241#define FRF_AB_PCIE_PRBSSYNC_H_LBN 11 242#define FRF_AB_PCIE_PRBSSYNC_H_WIDTH 1 243#define FRF_AB_PCIE_PRBSSYNC_L_LBN 10 244#define FRF_AB_PCIE_PRBSSYNC_L_WIDTH 1 245#define FRF_AB_PCIE_PRBSERRACK_H_LBN 9 246#define FRF_AB_PCIE_PRBSERRACK_H_WIDTH 1 247#define FRF_AB_PCIE_PRBSERRACK_L_LBN 8 248#define FRF_AB_PCIE_PRBSERRACK_L_WIDTH 1 249#define FRF_AB_PCIE_PRBSSEL_LBN 0 250#define FRF_AB_PCIE_PRBSSEL_WIDTH 8 251 252 253/* 254 * FR_AB_HW_INIT_REG_SF(128bit): 255 * Hardware initialization register 256 */ 257#define FR_AB_HW_INIT_REG_SF_OFST 0x00000350 258/* falcona0,falconb0=eeprom_flash */ 259/* 260 * FR_AZ_HW_INIT_REG(128bit): 261 * Hardware initialization register 262 */ 263#define FR_AZ_HW_INIT_REG_OFST 0x000000c0 264/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 265 266#define FRF_BB_BDMRD_CPLF_FULL_LBN 124 267#define FRF_BB_BDMRD_CPLF_FULL_WIDTH 1 268#define FRF_BB_PCIE_CPL_TIMEOUT_CTRL_LBN 121 269#define FRF_BB_PCIE_CPL_TIMEOUT_CTRL_WIDTH 3 270#define FRF_CZ_TX_MRG_TAGS_LBN 120 271#define FRF_CZ_TX_MRG_TAGS_WIDTH 1 272#define FRF_AZ_TRGT_MASK_ALL_LBN 100 273#define FRF_AZ_TRGT_MASK_ALL_WIDTH 1 274#define FRF_AZ_DOORBELL_DROP_LBN 92 275#define FRF_AZ_DOORBELL_DROP_WIDTH 8 276#define FRF_AB_TX_RREQ_MASK_EN_LBN 76 277#define FRF_AB_TX_RREQ_MASK_EN_WIDTH 1 278#define FRF_AB_PE_EIDLE_DIS_LBN 75 279#define FRF_AB_PE_EIDLE_DIS_WIDTH 1 280#define FRF_AZ_FC_BLOCKING_EN_LBN 45 281#define FRF_AZ_FC_BLOCKING_EN_WIDTH 1 282#define FRF_AZ_B2B_REQ_EN_LBN 44 283#define FRF_AZ_B2B_REQ_EN_WIDTH 1 284#define FRF_AZ_POST_WR_MASK_LBN 40 285#define FRF_AZ_POST_WR_MASK_WIDTH 4 286#define FRF_AZ_TLP_TC_LBN 34 287#define FRF_AZ_TLP_TC_WIDTH 3 288#define FRF_AZ_TLP_ATTR_LBN 32 289#define FRF_AZ_TLP_ATTR_WIDTH 2 290#define FRF_AB_INTB_VEC_LBN 24 291#define FRF_AB_INTB_VEC_WIDTH 5 292#define FRF_AB_INTA_VEC_LBN 16 293#define FRF_AB_INTA_VEC_WIDTH 5 294#define FRF_AZ_WD_TIMER_LBN 8 295#define FRF_AZ_WD_TIMER_WIDTH 8 296#define FRF_AZ_US_DISABLE_LBN 5 297#define FRF_AZ_US_DISABLE_WIDTH 1 298#define FRF_AZ_TLP_EP_LBN 4 299#define FRF_AZ_TLP_EP_WIDTH 1 300#define FRF_AZ_ATTR_SEL_LBN 3 301#define FRF_AZ_ATTR_SEL_WIDTH 1 302#define FRF_AZ_TD_SEL_LBN 1 303#define FRF_AZ_TD_SEL_WIDTH 1 304#define FRF_AZ_TLP_TD_LBN 0 305#define FRF_AZ_TLP_TD_WIDTH 1 306 307 308/* 309 * FR_AB_NIC_STAT_REG_SF(128bit): 310 * NIC status register 311 */ 312#define FR_AB_NIC_STAT_REG_SF_OFST 0x00000360 313/* falcona0,falconb0=eeprom_flash */ 314/* 315 * FR_AB_NIC_STAT_REG(128bit): 316 * NIC status register 317 */ 318#define FR_AB_NIC_STAT_REG_OFST 0x00000200 319/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 320 321#define FRF_BB_AER_DIS_LBN 34 322#define FRF_BB_AER_DIS_WIDTH 1 323#define FRF_BB_EE_STRAP_EN_LBN 31 324#define FRF_BB_EE_STRAP_EN_WIDTH 1 325#define FRF_BB_EE_STRAP_LBN 24 326#define FRF_BB_EE_STRAP_WIDTH 4 327#define FRF_BB_REVISION_ID_LBN 17 328#define FRF_BB_REVISION_ID_WIDTH 7 329#define FRF_AB_ONCHIP_SRAM_LBN 16 330#define FRF_AB_ONCHIP_SRAM_WIDTH 1 331#define FRF_AB_SF_PRST_LBN 9 332#define FRF_AB_SF_PRST_WIDTH 1 333#define FRF_AB_EE_PRST_LBN 8 334#define FRF_AB_EE_PRST_WIDTH 1 335#define FRF_AB_ATE_MODE_LBN 3 336#define FRF_AB_ATE_MODE_WIDTH 1 337#define FRF_AB_STRAP_PINS_LBN 0 338#define FRF_AB_STRAP_PINS_WIDTH 3 339 340 341/* 342 * FR_AB_GLB_CTL_REG_SF(128bit): 343 * Global control register 344 */ 345#define FR_AB_GLB_CTL_REG_SF_OFST 0x00000370 346/* falcona0,falconb0=eeprom_flash */ 347/* 348 * FR_AB_GLB_CTL_REG(128bit): 349 * Global control register 350 */ 351#define FR_AB_GLB_CTL_REG_OFST 0x00000220 352/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 353 354#define FRF_AB_EXT_PHY_RST_CTL_LBN 63 355#define FRF_AB_EXT_PHY_RST_CTL_WIDTH 1 356#define FRF_AB_XAUI_SD_RST_CTL_LBN 62 357#define FRF_AB_XAUI_SD_RST_CTL_WIDTH 1 358#define FRF_AB_PCIE_SD_RST_CTL_LBN 61 359#define FRF_AB_PCIE_SD_RST_CTL_WIDTH 1 360#define FRF_AA_PCIX_RST_CTL_LBN 60 361#define FRF_AA_PCIX_RST_CTL_WIDTH 1 362#define FRF_BB_BIU_RST_CTL_LBN 60 363#define FRF_BB_BIU_RST_CTL_WIDTH 1 364#define FRF_AB_PCIE_STKY_RST_CTL_LBN 59 365#define FRF_AB_PCIE_STKY_RST_CTL_WIDTH 1 366#define FRF_AB_PCIE_NSTKY_RST_CTL_LBN 58 367#define FRF_AB_PCIE_NSTKY_RST_CTL_WIDTH 1 368#define FRF_AB_PCIE_CORE_RST_CTL_LBN 57 369#define FRF_AB_PCIE_CORE_RST_CTL_WIDTH 1 370#define FRF_AB_XGRX_RST_CTL_LBN 56 371#define FRF_AB_XGRX_RST_CTL_WIDTH 1 372#define FRF_AB_XGTX_RST_CTL_LBN 55 373#define FRF_AB_XGTX_RST_CTL_WIDTH 1 374#define FRF_AB_EM_RST_CTL_LBN 54 375#define FRF_AB_EM_RST_CTL_WIDTH 1 376#define FRF_AB_EV_RST_CTL_LBN 53 377#define FRF_AB_EV_RST_CTL_WIDTH 1 378#define FRF_AB_SR_RST_CTL_LBN 52 379#define FRF_AB_SR_RST_CTL_WIDTH 1 380#define FRF_AB_RX_RST_CTL_LBN 51 381#define FRF_AB_RX_RST_CTL_WIDTH 1 382#define FRF_AB_TX_RST_CTL_LBN 50 383#define FRF_AB_TX_RST_CTL_WIDTH 1 384#define FRF_AB_EE_RST_CTL_LBN 49 385#define FRF_AB_EE_RST_CTL_WIDTH 1 386#define FRF_AB_CS_RST_CTL_LBN 48 387#define FRF_AB_CS_RST_CTL_WIDTH 1 388#define FRF_AB_HOT_RST_CTL_LBN 40 389#define FRF_AB_HOT_RST_CTL_WIDTH 2 390#define FRF_AB_RST_EXT_PHY_LBN 31 391#define FRF_AB_RST_EXT_PHY_WIDTH 1 392#define FRF_AB_RST_XAUI_SD_LBN 30 393#define FRF_AB_RST_XAUI_SD_WIDTH 1 394#define FRF_AB_RST_PCIE_SD_LBN 29 395#define FRF_AB_RST_PCIE_SD_WIDTH 1 396#define FRF_AA_RST_PCIX_LBN 28 397#define FRF_AA_RST_PCIX_WIDTH 1 398#define FRF_BB_RST_BIU_LBN 28 399#define FRF_BB_RST_BIU_WIDTH 1 400#define FRF_AB_RST_PCIE_STKY_LBN 27 401#define FRF_AB_RST_PCIE_STKY_WIDTH 1 402#define FRF_AB_RST_PCIE_NSTKY_LBN 26 403#define FRF_AB_RST_PCIE_NSTKY_WIDTH 1 404#define FRF_AB_RST_PCIE_CORE_LBN 25 405#define FRF_AB_RST_PCIE_CORE_WIDTH 1 406#define FRF_AB_RST_XGRX_LBN 24 407#define FRF_AB_RST_XGRX_WIDTH 1 408#define FRF_AB_RST_XGTX_LBN 23 409#define FRF_AB_RST_XGTX_WIDTH 1 410#define FRF_AB_RST_EM_LBN 22 411#define FRF_AB_RST_EM_WIDTH 1 412#define FRF_AB_RST_EV_LBN 21 413#define FRF_AB_RST_EV_WIDTH 1 414#define FRF_AB_RST_SR_LBN 20 415#define FRF_AB_RST_SR_WIDTH 1 416#define FRF_AB_RST_RX_LBN 19 417#define FRF_AB_RST_RX_WIDTH 1 418#define FRF_AB_RST_TX_LBN 18 419#define FRF_AB_RST_TX_WIDTH 1 420#define FRF_AB_RST_SF_LBN 17 421#define FRF_AB_RST_SF_WIDTH 1 422#define FRF_AB_RST_CS_LBN 16 423#define FRF_AB_RST_CS_WIDTH 1 424#define FRF_AB_INT_RST_DUR_LBN 4 425#define FRF_AB_INT_RST_DUR_WIDTH 3 426#define FRF_AB_EXT_PHY_RST_DUR_LBN 1 427#define FRF_AB_EXT_PHY_RST_DUR_WIDTH 3 428#define FFE_AB_EXT_PHY_RST_DUR_10240US 7 429#define FFE_AB_EXT_PHY_RST_DUR_5120US 6 430#define FFE_AB_EXT_PHY_RST_DUR_2560US 5 431#define FFE_AB_EXT_PHY_RST_DUR_1280US 4 432#define FFE_AB_EXT_PHY_RST_DUR_640US 3 433#define FFE_AB_EXT_PHY_RST_DUR_320US 2 434#define FFE_AB_EXT_PHY_RST_DUR_160US 1 435#define FFE_AB_EXT_PHY_RST_DUR_80US 0 436#define FRF_AB_SWRST_LBN 0 437#define FRF_AB_SWRST_WIDTH 1 438 439 440/* 441 * FR_AZ_IOM_IND_ADR_REG(32bit): 442 * IO-mapped indirect access address register 443 */ 444#define FR_AZ_IOM_IND_ADR_REG_OFST 0x00000000 445/* falcona0,falconb0,sienaa0=net_func_bar0 */ 446 447#define FRF_AZ_IOM_AUTO_ADR_INC_EN_LBN 24 448#define FRF_AZ_IOM_AUTO_ADR_INC_EN_WIDTH 1 449#define FRF_AZ_IOM_IND_ADR_LBN 0 450#define FRF_AZ_IOM_IND_ADR_WIDTH 24 451 452 453/* 454 * FR_AZ_IOM_IND_DAT_REG(32bit): 455 * IO-mapped indirect access data register 456 */ 457#define FR_AZ_IOM_IND_DAT_REG_OFST 0x00000004 458/* falcona0,falconb0,sienaa0=net_func_bar0 */ 459 460#define FRF_AZ_IOM_IND_DAT_LBN 0 461#define FRF_AZ_IOM_IND_DAT_WIDTH 32 462 463 464/* 465 * FR_AZ_ADR_REGION_REG(128bit): 466 * Address region register 467 */ 468#define FR_AZ_ADR_REGION_REG_OFST 0x00000000 469/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 470 471#define FRF_AZ_ADR_REGION3_LBN 96 472#define FRF_AZ_ADR_REGION3_WIDTH 18 473#define FRF_AZ_ADR_REGION2_LBN 64 474#define FRF_AZ_ADR_REGION2_WIDTH 18 475#define FRF_AZ_ADR_REGION1_LBN 32 476#define FRF_AZ_ADR_REGION1_WIDTH 18 477#define FRF_AZ_ADR_REGION0_LBN 0 478#define FRF_AZ_ADR_REGION0_WIDTH 18 479 480 481/* 482 * FR_AZ_INT_EN_REG_KER(128bit): 483 * Kernel driver Interrupt enable register 484 */ 485#define FR_AZ_INT_EN_REG_KER_OFST 0x00000010 486/* falcona0,falconb0,sienaa0=net_func_bar2 */ 487 488#define FRF_AZ_KER_INT_LEVE_SEL_LBN 8 489#define FRF_AZ_KER_INT_LEVE_SEL_WIDTH 6 490#define FRF_AZ_KER_INT_CHAR_LBN 4 491#define FRF_AZ_KER_INT_CHAR_WIDTH 1 492#define FRF_AZ_KER_INT_KER_LBN 3 493#define FRF_AZ_KER_INT_KER_WIDTH 1 494#define FRF_AZ_DRV_INT_EN_KER_LBN 0 495#define FRF_AZ_DRV_INT_EN_KER_WIDTH 1 496 497 498/* 499 * FR_AZ_INT_EN_REG_CHAR(128bit): 500 * Char Driver interrupt enable register 501 */ 502#define FR_AZ_INT_EN_REG_CHAR_OFST 0x00000020 503/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 504 505#define FRF_AZ_CHAR_INT_LEVE_SEL_LBN 8 506#define FRF_AZ_CHAR_INT_LEVE_SEL_WIDTH 6 507#define FRF_AZ_CHAR_INT_CHAR_LBN 4 508#define FRF_AZ_CHAR_INT_CHAR_WIDTH 1 509#define FRF_AZ_CHAR_INT_KER_LBN 3 510#define FRF_AZ_CHAR_INT_KER_WIDTH 1 511#define FRF_AZ_DRV_INT_EN_CHAR_LBN 0 512#define FRF_AZ_DRV_INT_EN_CHAR_WIDTH 1 513 514 515/* 516 * FR_AZ_INT_ADR_REG_KER(128bit): 517 * Interrupt host address for Kernel driver 518 */ 519#define FR_AZ_INT_ADR_REG_KER_OFST 0x00000030 520/* falcona0,falconb0,sienaa0=net_func_bar2 */ 521 522#define FRF_AZ_NORM_INT_VEC_DIS_KER_LBN 64 523#define FRF_AZ_NORM_INT_VEC_DIS_KER_WIDTH 1 524#define FRF_AZ_INT_ADR_KER_LBN 0 525#define FRF_AZ_INT_ADR_KER_WIDTH 64 526#define FRF_AZ_INT_ADR_KER_DW0_LBN 0 527#define FRF_AZ_INT_ADR_KER_DW0_WIDTH 32 528#define FRF_AZ_INT_ADR_KER_DW1_LBN 32 529#define FRF_AZ_INT_ADR_KER_DW1_WIDTH 32 530 531 532/* 533 * FR_AZ_INT_ADR_REG_CHAR(128bit): 534 * Interrupt host address for Char driver 535 */ 536#define FR_AZ_INT_ADR_REG_CHAR_OFST 0x00000040 537/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 538 539#define FRF_AZ_NORM_INT_VEC_DIS_CHAR_LBN 64 540#define FRF_AZ_NORM_INT_VEC_DIS_CHAR_WIDTH 1 541#define FRF_AZ_INT_ADR_CHAR_LBN 0 542#define FRF_AZ_INT_ADR_CHAR_WIDTH 64 543#define FRF_AZ_INT_ADR_CHAR_DW0_LBN 0 544#define FRF_AZ_INT_ADR_CHAR_DW0_WIDTH 32 545#define FRF_AZ_INT_ADR_CHAR_DW1_LBN 32 546#define FRF_AZ_INT_ADR_CHAR_DW1_WIDTH 32 547 548 549/* 550 * FR_AA_INT_ACK_KER(32bit): 551 * Kernel interrupt acknowledge register 552 */ 553#define FR_AA_INT_ACK_KER_OFST 0x00000050 554/* falcona0=net_func_bar2 */ 555 556#define FRF_AA_INT_ACK_KER_FIELD_LBN 0 557#define FRF_AA_INT_ACK_KER_FIELD_WIDTH 32 558 559 560/* 561 * FR_BZ_INT_ISR0_REG(128bit): 562 * Function 0 Interrupt Acknowlege Status register 563 */ 564#define FR_BZ_INT_ISR0_REG_OFST 0x00000090 565/* falconb0,sienaa0=net_func_bar2 */ 566 567#define FRF_BZ_INT_ISR_REG_LBN 0 568#define FRF_BZ_INT_ISR_REG_WIDTH 64 569#define FRF_BZ_INT_ISR_REG_DW0_LBN 0 570#define FRF_BZ_INT_ISR_REG_DW0_WIDTH 32 571#define FRF_BZ_INT_ISR_REG_DW1_LBN 32 572#define FRF_BZ_INT_ISR_REG_DW1_WIDTH 32 573 574 575/* 576 * FR_AB_EE_SPI_HCMD_REG(128bit): 577 * SPI host command register 578 */ 579#define FR_AB_EE_SPI_HCMD_REG_OFST 0x00000100 580/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 581 582#define FRF_AB_EE_SPI_HCMD_CMD_EN_LBN 31 583#define FRF_AB_EE_SPI_HCMD_CMD_EN_WIDTH 1 584#define FRF_AB_EE_WR_TIMER_ACTIVE_LBN 28 585#define FRF_AB_EE_WR_TIMER_ACTIVE_WIDTH 1 586#define FRF_AB_EE_SPI_HCMD_SF_SEL_LBN 24 587#define FRF_AB_EE_SPI_HCMD_SF_SEL_WIDTH 1 588#define FRF_AB_EE_SPI_HCMD_DABCNT_LBN 16 589#define FRF_AB_EE_SPI_HCMD_DABCNT_WIDTH 5 590#define FRF_AB_EE_SPI_HCMD_READ_LBN 15 591#define FRF_AB_EE_SPI_HCMD_READ_WIDTH 1 592#define FRF_AB_EE_SPI_HCMD_DUBCNT_LBN 12 593#define FRF_AB_EE_SPI_HCMD_DUBCNT_WIDTH 2 594#define FRF_AB_EE_SPI_HCMD_ADBCNT_LBN 8 595#define FRF_AB_EE_SPI_HCMD_ADBCNT_WIDTH 2 596#define FRF_AB_EE_SPI_HCMD_ENC_LBN 0 597#define FRF_AB_EE_SPI_HCMD_ENC_WIDTH 8 598 599 600/* 601 * FR_CZ_USR_EV_CFG(32bit): 602 * User Level Event Configuration register 603 */ 604#define FR_CZ_USR_EV_CFG_OFST 0x00000100 605/* sienaa0=net_func_bar2 */ 606 607#define FRF_CZ_USREV_DIS_LBN 16 608#define FRF_CZ_USREV_DIS_WIDTH 1 609#define FRF_CZ_DFLT_EVQ_LBN 0 610#define FRF_CZ_DFLT_EVQ_WIDTH 10 611 612 613/* 614 * FR_AB_EE_SPI_HADR_REG(128bit): 615 * SPI host address register 616 */ 617#define FR_AB_EE_SPI_HADR_REG_OFST 0x00000110 618/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 619 620#define FRF_AB_EE_SPI_HADR_DUBYTE_LBN 24 621#define FRF_AB_EE_SPI_HADR_DUBYTE_WIDTH 8 622#define FRF_AB_EE_SPI_HADR_ADR_LBN 0 623#define FRF_AB_EE_SPI_HADR_ADR_WIDTH 24 624 625 626/* 627 * FR_AB_EE_SPI_HDATA_REG(128bit): 628 * SPI host data register 629 */ 630#define FR_AB_EE_SPI_HDATA_REG_OFST 0x00000120 631/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 632 633#define FRF_AB_EE_SPI_HDATA3_LBN 96 634#define FRF_AB_EE_SPI_HDATA3_WIDTH 32 635#define FRF_AB_EE_SPI_HDATA2_LBN 64 636#define FRF_AB_EE_SPI_HDATA2_WIDTH 32 637#define FRF_AB_EE_SPI_HDATA1_LBN 32 638#define FRF_AB_EE_SPI_HDATA1_WIDTH 32 639#define FRF_AB_EE_SPI_HDATA0_LBN 0 640#define FRF_AB_EE_SPI_HDATA0_WIDTH 32 641 642 643/* 644 * FR_AB_EE_BASE_PAGE_REG(128bit): 645 * Expansion ROM base mirror register 646 */ 647#define FR_AB_EE_BASE_PAGE_REG_OFST 0x00000130 648/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 649 650#define FRF_AB_EE_EXPROM_MASK_LBN 16 651#define FRF_AB_EE_EXPROM_MASK_WIDTH 13 652#define FRF_AB_EE_EXP_ROM_WINDOW_BASE_LBN 0 653#define FRF_AB_EE_EXP_ROM_WINDOW_BASE_WIDTH 13 654 655 656/* 657 * FR_AB_EE_VPD_SW_CNTL_REG(128bit): 658 * VPD access SW control register 659 */ 660#define FR_AB_EE_VPD_SW_CNTL_REG_OFST 0x00000150 661/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 662 663#define FRF_AB_EE_VPD_CYCLE_PENDING_LBN 31 664#define FRF_AB_EE_VPD_CYCLE_PENDING_WIDTH 1 665#define FRF_AB_EE_VPD_CYC_WRITE_LBN 28 666#define FRF_AB_EE_VPD_CYC_WRITE_WIDTH 1 667#define FRF_AB_EE_VPD_CYC_ADR_LBN 0 668#define FRF_AB_EE_VPD_CYC_ADR_WIDTH 15 669 670 671/* 672 * FR_AB_EE_VPD_SW_DATA_REG(128bit): 673 * VPD access SW data register 674 */ 675#define FR_AB_EE_VPD_SW_DATA_REG_OFST 0x00000160 676/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 677 678#define FRF_AB_EE_VPD_CYC_DAT_LBN 0 679#define FRF_AB_EE_VPD_CYC_DAT_WIDTH 32 680 681 682/* 683 * FR_BB_PCIE_CORE_INDIRECT_REG(64bit): 684 * Indirect Access to PCIE Core registers 685 */ 686#define FR_BB_PCIE_CORE_INDIRECT_REG_OFST 0x000001f0 687/* falconb0=net_func_bar2 */ 688 689#define FRF_BB_PCIE_CORE_TARGET_DATA_LBN 32 690#define FRF_BB_PCIE_CORE_TARGET_DATA_WIDTH 32 691#define FRF_BB_PCIE_CORE_INDIRECT_ACCESS_DIR_LBN 15 692#define FRF_BB_PCIE_CORE_INDIRECT_ACCESS_DIR_WIDTH 1 693#define FRF_BB_PCIE_CORE_TARGET_REG_ADRS_LBN 0 694#define FRF_BB_PCIE_CORE_TARGET_REG_ADRS_WIDTH 12 695 696 697/* 698 * FR_AB_GPIO_CTL_REG(128bit): 699 * GPIO control register 700 */ 701#define FR_AB_GPIO_CTL_REG_OFST 0x00000210 702/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 703 704#define FRF_AB_GPIO15_OEN_LBN 63 705#define FRF_AB_GPIO15_OEN_WIDTH 1 706#define FRF_AB_GPIO14_OEN_LBN 62 707#define FRF_AB_GPIO14_OEN_WIDTH 1 708#define FRF_AB_GPIO13_OEN_LBN 61 709#define FRF_AB_GPIO13_OEN_WIDTH 1 710#define FRF_AB_GPIO12_OEN_LBN 60 711#define FRF_AB_GPIO12_OEN_WIDTH 1 712#define FRF_AB_GPIO11_OEN_LBN 59 713#define FRF_AB_GPIO11_OEN_WIDTH 1 714#define FRF_AB_GPIO10_OEN_LBN 58 715#define FRF_AB_GPIO10_OEN_WIDTH 1 716#define FRF_AB_GPIO9_OEN_LBN 57 717#define FRF_AB_GPIO9_OEN_WIDTH 1 718#define FRF_AB_GPIO8_OEN_LBN 56 719#define FRF_AB_GPIO8_OEN_WIDTH 1 720#define FRF_AB_GPIO15_OUT_LBN 55 721#define FRF_AB_GPIO15_OUT_WIDTH 1 722#define FRF_AB_GPIO14_OUT_LBN 54 723#define FRF_AB_GPIO14_OUT_WIDTH 1 724#define FRF_AB_GPIO13_OUT_LBN 53 725#define FRF_AB_GPIO13_OUT_WIDTH 1 726#define FRF_AB_GPIO12_OUT_LBN 52 727#define FRF_AB_GPIO12_OUT_WIDTH 1 728#define FRF_AB_GPIO11_OUT_LBN 51 729#define FRF_AB_GPIO11_OUT_WIDTH 1 730#define FRF_AB_GPIO10_OUT_LBN 50 731#define FRF_AB_GPIO10_OUT_WIDTH 1 732#define FRF_AB_GPIO9_OUT_LBN 49 733#define FRF_AB_GPIO9_OUT_WIDTH 1 734#define FRF_AB_GPIO8_OUT_LBN 48 735#define FRF_AB_GPIO8_OUT_WIDTH 1 736#define FRF_AB_GPIO15_IN_LBN 47 737#define FRF_AB_GPIO15_IN_WIDTH 1 738#define FRF_AB_GPIO14_IN_LBN 46 739#define FRF_AB_GPIO14_IN_WIDTH 1 740#define FRF_AB_GPIO13_IN_LBN 45 741#define FRF_AB_GPIO13_IN_WIDTH 1 742#define FRF_AB_GPIO12_IN_LBN 44 743#define FRF_AB_GPIO12_IN_WIDTH 1 744#define FRF_AB_GPIO11_IN_LBN 43 745#define FRF_AB_GPIO11_IN_WIDTH 1 746#define FRF_AB_GPIO10_IN_LBN 42 747#define FRF_AB_GPIO10_IN_WIDTH 1 748#define FRF_AB_GPIO9_IN_LBN 41 749#define FRF_AB_GPIO9_IN_WIDTH 1 750#define FRF_AB_GPIO8_IN_LBN 40 751#define FRF_AB_GPIO8_IN_WIDTH 1 752#define FRF_AB_GPIO15_PWRUP_VALUE_LBN 39 753#define FRF_AB_GPIO15_PWRUP_VALUE_WIDTH 1 754#define FRF_AB_GPIO14_PWRUP_VALUE_LBN 38 755#define FRF_AB_GPIO14_PWRUP_VALUE_WIDTH 1 756#define FRF_AB_GPIO13_PWRUP_VALUE_LBN 37 757#define FRF_AB_GPIO13_PWRUP_VALUE_WIDTH 1 758#define FRF_AB_GPIO12_PWRUP_VALUE_LBN 36 759#define FRF_AB_GPIO12_PWRUP_VALUE_WIDTH 1 760#define FRF_AB_GPIO11_PWRUP_VALUE_LBN 35 761#define FRF_AB_GPIO11_PWRUP_VALUE_WIDTH 1 762#define FRF_AB_GPIO10_PWRUP_VALUE_LBN 34 763#define FRF_AB_GPIO10_PWRUP_VALUE_WIDTH 1 764#define FRF_AB_GPIO9_PWRUP_VALUE_LBN 33 765#define FRF_AB_GPIO9_PWRUP_VALUE_WIDTH 1 766#define FRF_AB_GPIO8_PWRUP_VALUE_LBN 32 767#define FRF_AB_GPIO8_PWRUP_VALUE_WIDTH 1 768#define FRF_BB_CLK156_OUT_EN_LBN 31 769#define FRF_BB_CLK156_OUT_EN_WIDTH 1 770#define FRF_BB_USE_NIC_CLK_LBN 30 771#define FRF_BB_USE_NIC_CLK_WIDTH 1 772#define FRF_AB_GPIO5_OEN_LBN 29 773#define FRF_AB_GPIO5_OEN_WIDTH 1 774#define FRF_AB_GPIO4_OEN_LBN 28 775#define FRF_AB_GPIO4_OEN_WIDTH 1 776#define FRF_AB_GPIO3_OEN_LBN 27 777#define FRF_AB_GPIO3_OEN_WIDTH 1 778#define FRF_AB_GPIO2_OEN_LBN 26 779#define FRF_AB_GPIO2_OEN_WIDTH 1 780#define FRF_AB_GPIO1_OEN_LBN 25 781#define FRF_AB_GPIO1_OEN_WIDTH 1 782#define FRF_AB_GPIO0_OEN_LBN 24 783#define FRF_AB_GPIO0_OEN_WIDTH 1 784#define FRF_AB_GPIO5_OUT_LBN 21 785#define FRF_AB_GPIO5_OUT_WIDTH 1 786#define FRF_AB_GPIO4_OUT_LBN 20 787#define FRF_AB_GPIO4_OUT_WIDTH 1 788#define FRF_AB_GPIO3_OUT_LBN 19 789#define FRF_AB_GPIO3_OUT_WIDTH 1 790#define FRF_AB_GPIO2_OUT_LBN 18 791#define FRF_AB_GPIO2_OUT_WIDTH 1 792#define FRF_AB_GPIO1_OUT_LBN 17 793#define FRF_AB_GPIO1_OUT_WIDTH 1 794#define FRF_AB_GPIO0_OUT_LBN 16 795#define FRF_AB_GPIO0_OUT_WIDTH 1 796#define FRF_AB_GPIO5_IN_LBN 13 797#define FRF_AB_GPIO5_IN_WIDTH 1 798#define FRF_AB_GPIO4_IN_LBN 12 799#define FRF_AB_GPIO4_IN_WIDTH 1 800#define FRF_AB_GPIO3_IN_LBN 11 801#define FRF_AB_GPIO3_IN_WIDTH 1 802#define FRF_AB_GPIO2_IN_LBN 10 803#define FRF_AB_GPIO2_IN_WIDTH 1 804#define FRF_AB_GPIO1_IN_LBN 9 805#define FRF_AB_GPIO1_IN_WIDTH 1 806#define FRF_AB_GPIO0_IN_LBN 8 807#define FRF_AB_GPIO0_IN_WIDTH 1 808#define FRF_AB_GPIO5_PWRUP_VALUE_LBN 5 809#define FRF_AB_GPIO5_PWRUP_VALUE_WIDTH 1 810#define FRF_AB_GPIO4_PWRUP_VALUE_LBN 4 811#define FRF_AB_GPIO4_PWRUP_VALUE_WIDTH 1 812#define FRF_AB_GPIO3_PWRUP_VALUE_LBN 3 813#define FRF_AB_GPIO3_PWRUP_VALUE_WIDTH 1 814#define FRF_AB_GPIO2_PWRUP_VALUE_LBN 2 815#define FRF_AB_GPIO2_PWRUP_VALUE_WIDTH 1 816#define FRF_AB_GPIO1_PWRUP_VALUE_LBN 1 817#define FRF_AB_GPIO1_PWRUP_VALUE_WIDTH 1 818#define FRF_AB_GPIO0_PWRUP_VALUE_LBN 0 819#define FRF_AB_GPIO0_PWRUP_VALUE_WIDTH 1 820 821 822/* 823 * FR_AZ_FATAL_INTR_REG_KER(128bit): 824 * Fatal interrupt register for Kernel 825 */ 826#define FR_AZ_FATAL_INTR_REG_KER_OFST 0x00000230 827/* falcona0,falconb0,sienaa0=net_func_bar2 */ 828 829#define FRF_CZ_SRAM_PERR_INT_P_KER_EN_LBN 44 830#define FRF_CZ_SRAM_PERR_INT_P_KER_EN_WIDTH 1 831#define FRF_AB_PCI_BUSERR_INT_KER_EN_LBN 43 832#define FRF_AB_PCI_BUSERR_INT_KER_EN_WIDTH 1 833#define FRF_CZ_MBU_PERR_INT_KER_EN_LBN 43 834#define FRF_CZ_MBU_PERR_INT_KER_EN_WIDTH 1 835#define FRF_AZ_SRAM_OOB_INT_KER_EN_LBN 42 836#define FRF_AZ_SRAM_OOB_INT_KER_EN_WIDTH 1 837#define FRF_AZ_BUFID_OOB_INT_KER_EN_LBN 41 838#define FRF_AZ_BUFID_OOB_INT_KER_EN_WIDTH 1 839#define FRF_AZ_MEM_PERR_INT_KER_EN_LBN 40 840#define FRF_AZ_MEM_PERR_INT_KER_EN_WIDTH 1 841#define FRF_AZ_RBUF_OWN_INT_KER_EN_LBN 39 842#define FRF_AZ_RBUF_OWN_INT_KER_EN_WIDTH 1 843#define FRF_AZ_TBUF_OWN_INT_KER_EN_LBN 38 844#define FRF_AZ_TBUF_OWN_INT_KER_EN_WIDTH 1 845#define FRF_AZ_RDESCQ_OWN_INT_KER_EN_LBN 37 846#define FRF_AZ_RDESCQ_OWN_INT_KER_EN_WIDTH 1 847#define FRF_AZ_TDESCQ_OWN_INT_KER_EN_LBN 36 848#define FRF_AZ_TDESCQ_OWN_INT_KER_EN_WIDTH 1 849#define FRF_AZ_EVQ_OWN_INT_KER_EN_LBN 35 850#define FRF_AZ_EVQ_OWN_INT_KER_EN_WIDTH 1 851#define FRF_AZ_EVF_OFLO_INT_KER_EN_LBN 34 852#define FRF_AZ_EVF_OFLO_INT_KER_EN_WIDTH 1 853#define FRF_AZ_ILL_ADR_INT_KER_EN_LBN 33 854#define FRF_AZ_ILL_ADR_INT_KER_EN_WIDTH 1 855#define FRF_AZ_SRM_PERR_INT_KER_EN_LBN 32 856#define FRF_AZ_SRM_PERR_INT_KER_EN_WIDTH 1 857#define FRF_CZ_SRAM_PERR_INT_P_KER_LBN 12 858#define FRF_CZ_SRAM_PERR_INT_P_KER_WIDTH 1 859#define FRF_AB_PCI_BUSERR_INT_KER_LBN 11 860#define FRF_AB_PCI_BUSERR_INT_KER_WIDTH 1 861#define FRF_CZ_MBU_PERR_INT_KER_LBN 11 862#define FRF_CZ_MBU_PERR_INT_KER_WIDTH 1 863#define FRF_AZ_SRAM_OOB_INT_KER_LBN 10 864#define FRF_AZ_SRAM_OOB_INT_KER_WIDTH 1 865#define FRF_AZ_BUFID_DC_OOB_INT_KER_LBN 9 866#define FRF_AZ_BUFID_DC_OOB_INT_KER_WIDTH 1 867#define FRF_AZ_MEM_PERR_INT_KER_LBN 8 868#define FRF_AZ_MEM_PERR_INT_KER_WIDTH 1 869#define FRF_AZ_RBUF_OWN_INT_KER_LBN 7 870#define FRF_AZ_RBUF_OWN_INT_KER_WIDTH 1 871#define FRF_AZ_TBUF_OWN_INT_KER_LBN 6 872#define FRF_AZ_TBUF_OWN_INT_KER_WIDTH 1 873#define FRF_AZ_RDESCQ_OWN_INT_KER_LBN 5 874#define FRF_AZ_RDESCQ_OWN_INT_KER_WIDTH 1 875#define FRF_AZ_TDESCQ_OWN_INT_KER_LBN 4 876#define FRF_AZ_TDESCQ_OWN_INT_KER_WIDTH 1 877#define FRF_AZ_EVQ_OWN_INT_KER_LBN 3 878#define FRF_AZ_EVQ_OWN_INT_KER_WIDTH 1 879#define FRF_AZ_EVF_OFLO_INT_KER_LBN 2 880#define FRF_AZ_EVF_OFLO_INT_KER_WIDTH 1 881#define FRF_AZ_ILL_ADR_INT_KER_LBN 1 882#define FRF_AZ_ILL_ADR_INT_KER_WIDTH 1 883#define FRF_AZ_SRM_PERR_INT_KER_LBN 0 884#define FRF_AZ_SRM_PERR_INT_KER_WIDTH 1 885 886 887/* 888 * FR_AZ_FATAL_INTR_REG_CHAR(128bit): 889 * Fatal interrupt register for Char 890 */ 891#define FR_AZ_FATAL_INTR_REG_CHAR_OFST 0x00000240 892/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 893 894#define FRF_CZ_SRAM_PERR_INT_P_CHAR_EN_LBN 44 895#define FRF_CZ_SRAM_PERR_INT_P_CHAR_EN_WIDTH 1 896#define FRF_AB_PCI_BUSERR_INT_CHAR_EN_LBN 43 897#define FRF_AB_PCI_BUSERR_INT_CHAR_EN_WIDTH 1 898#define FRF_CZ_MBU_PERR_INT_CHAR_EN_LBN 43 899#define FRF_CZ_MBU_PERR_INT_CHAR_EN_WIDTH 1 900#define FRF_AZ_SRAM_OOB_INT_CHAR_EN_LBN 42 901#define FRF_AZ_SRAM_OOB_INT_CHAR_EN_WIDTH 1 902#define FRF_AZ_BUFID_OOB_INT_CHAR_EN_LBN 41 903#define FRF_AZ_BUFID_OOB_INT_CHAR_EN_WIDTH 1 904#define FRF_AZ_MEM_PERR_INT_CHAR_EN_LBN 40 905#define FRF_AZ_MEM_PERR_INT_CHAR_EN_WIDTH 1 906#define FRF_AZ_RBUF_OWN_INT_CHAR_EN_LBN 39 907#define FRF_AZ_RBUF_OWN_INT_CHAR_EN_WIDTH 1 908#define FRF_AZ_TBUF_OWN_INT_CHAR_EN_LBN 38 909#define FRF_AZ_TBUF_OWN_INT_CHAR_EN_WIDTH 1 910#define FRF_AZ_RDESCQ_OWN_INT_CHAR_EN_LBN 37 911#define FRF_AZ_RDESCQ_OWN_INT_CHAR_EN_WIDTH 1 912#define FRF_AZ_TDESCQ_OWN_INT_CHAR_EN_LBN 36 913#define FRF_AZ_TDESCQ_OWN_INT_CHAR_EN_WIDTH 1 914#define FRF_AZ_EVQ_OWN_INT_CHAR_EN_LBN 35 915#define FRF_AZ_EVQ_OWN_INT_CHAR_EN_WIDTH 1 916#define FRF_AZ_EVF_OFLO_INT_CHAR_EN_LBN 34 917#define FRF_AZ_EVF_OFLO_INT_CHAR_EN_WIDTH 1 918#define FRF_AZ_ILL_ADR_INT_CHAR_EN_LBN 33 919#define FRF_AZ_ILL_ADR_INT_CHAR_EN_WIDTH 1 920#define FRF_AZ_SRM_PERR_INT_CHAR_EN_LBN 32 921#define FRF_AZ_SRM_PERR_INT_CHAR_EN_WIDTH 1 922#define FRF_CZ_SRAM_PERR_INT_P_CHAR_LBN 12 923#define FRF_CZ_SRAM_PERR_INT_P_CHAR_WIDTH 1 924#define FRF_AB_PCI_BUSERR_INT_CHAR_LBN 11 925#define FRF_AB_PCI_BUSERR_INT_CHAR_WIDTH 1 926#define FRF_CZ_MBU_PERR_INT_CHAR_LBN 11 927#define FRF_CZ_MBU_PERR_INT_CHAR_WIDTH 1 928#define FRF_AZ_SRAM_OOB_INT_CHAR_LBN 10 929#define FRF_AZ_SRAM_OOB_INT_CHAR_WIDTH 1 930#define FRF_AZ_BUFID_DC_OOB_INT_CHAR_LBN 9 931#define FRF_AZ_BUFID_DC_OOB_INT_CHAR_WIDTH 1 932#define FRF_AZ_MEM_PERR_INT_CHAR_LBN 8 933#define FRF_AZ_MEM_PERR_INT_CHAR_WIDTH 1 934#define FRF_AZ_RBUF_OWN_INT_CHAR_LBN 7 935#define FRF_AZ_RBUF_OWN_INT_CHAR_WIDTH 1 936#define FRF_AZ_TBUF_OWN_INT_CHAR_LBN 6 937#define FRF_AZ_TBUF_OWN_INT_CHAR_WIDTH 1 938#define FRF_AZ_RDESCQ_OWN_INT_CHAR_LBN 5 939#define FRF_AZ_RDESCQ_OWN_INT_CHAR_WIDTH 1 940#define FRF_AZ_TDESCQ_OWN_INT_CHAR_LBN 4 941#define FRF_AZ_TDESCQ_OWN_INT_CHAR_WIDTH 1 942#define FRF_AZ_EVQ_OWN_INT_CHAR_LBN 3 943#define FRF_AZ_EVQ_OWN_INT_CHAR_WIDTH 1 944#define FRF_AZ_EVF_OFLO_INT_CHAR_LBN 2 945#define FRF_AZ_EVF_OFLO_INT_CHAR_WIDTH 1 946#define FRF_AZ_ILL_ADR_INT_CHAR_LBN 1 947#define FRF_AZ_ILL_ADR_INT_CHAR_WIDTH 1 948#define FRF_AZ_SRM_PERR_INT_CHAR_LBN 0 949#define FRF_AZ_SRM_PERR_INT_CHAR_WIDTH 1 950 951 952/* 953 * FR_AZ_DP_CTRL_REG(128bit): 954 * Datapath control register 955 */ 956#define FR_AZ_DP_CTRL_REG_OFST 0x00000250 957/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 958 959#define FRF_AZ_FLS_EVQ_ID_LBN 0 960#define FRF_AZ_FLS_EVQ_ID_WIDTH 12 961 962 963/* 964 * FR_AZ_MEM_STAT_REG(128bit): 965 * Memory status register 966 */ 967#define FR_AZ_MEM_STAT_REG_OFST 0x00000260 968/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 969 970#define FRF_AB_MEM_PERR_VEC_LBN 53 971#define FRF_AB_MEM_PERR_VEC_WIDTH 40 972#define FRF_AB_MEM_PERR_VEC_DW0_LBN 53 973#define FRF_AB_MEM_PERR_VEC_DW0_WIDTH 32 974#define FRF_AB_MEM_PERR_VEC_DW1_LBN 85 975#define FRF_AB_MEM_PERR_VEC_DW1_WIDTH 6 976#define FRF_AB_MBIST_CORR_LBN 38 977#define FRF_AB_MBIST_CORR_WIDTH 15 978#define FRF_AB_MBIST_ERR_LBN 0 979#define FRF_AB_MBIST_ERR_WIDTH 40 980#define FRF_AB_MBIST_ERR_DW0_LBN 0 981#define FRF_AB_MBIST_ERR_DW0_WIDTH 32 982#define FRF_AB_MBIST_ERR_DW1_LBN 32 983#define FRF_AB_MBIST_ERR_DW1_WIDTH 6 984#define FRF_CZ_MEM_PERR_VEC_LBN 0 985#define FRF_CZ_MEM_PERR_VEC_WIDTH 35 986#define FRF_CZ_MEM_PERR_VEC_DW0_LBN 0 987#define FRF_CZ_MEM_PERR_VEC_DW0_WIDTH 32 988#define FRF_CZ_MEM_PERR_VEC_DW1_LBN 32 989#define FRF_CZ_MEM_PERR_VEC_DW1_WIDTH 3 990 991 992/* 993 * FR_PORT0_CS_DEBUG_REG(128bit): 994 * Debug register 995 */ 996 997#define FR_AZ_CS_DEBUG_REG_OFST 0x00000270 998/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 999 1000#define FRF_AB_GLB_DEBUG2_SEL_LBN 50 1001#define FRF_AB_GLB_DEBUG2_SEL_WIDTH 3 1002#define FRF_AB_DEBUG_BLK_SEL2_LBN 47 1003#define FRF_AB_DEBUG_BLK_SEL2_WIDTH 3 1004#define FRF_AB_DEBUG_BLK_SEL1_LBN 44 1005#define FRF_AB_DEBUG_BLK_SEL1_WIDTH 3 1006#define FRF_AB_DEBUG_BLK_SEL0_LBN 41 1007#define FRF_AB_DEBUG_BLK_SEL0_WIDTH 3 1008#define FRF_CZ_CS_PORT_NUM_LBN 40 1009#define FRF_CZ_CS_PORT_NUM_WIDTH 2 1010#define FRF_AB_MISC_DEBUG_ADDR_LBN 36 1011#define FRF_AB_MISC_DEBUG_ADDR_WIDTH 5 1012#define FRF_CZ_CS_RESERVED_LBN 36 1013#define FRF_CZ_CS_RESERVED_WIDTH 4 1014#define FRF_AB_SERDES_DEBUG_ADDR_LBN 31 1015#define FRF_AB_SERDES_DEBUG_ADDR_WIDTH 5 1016#define FRF_CZ_CS_PORT_FPE_DW0_LBN 1 1017#define FRF_CZ_CS_PORT_FPE_DW0_WIDTH 32 1018#define FRF_CZ_CS_PORT_FPE_DW1_LBN 33 1019#define FRF_CZ_CS_PORT_FPE_DW1_WIDTH 3 1020#define FRF_CZ_CS_PORT_FPE_LBN 1 1021#define FRF_CZ_CS_PORT_FPE_WIDTH 35 1022#define FRF_AB_EM_DEBUG_ADDR_LBN 26 1023#define FRF_AB_EM_DEBUG_ADDR_WIDTH 5 1024#define FRF_AB_SR_DEBUG_ADDR_LBN 21 1025#define FRF_AB_SR_DEBUG_ADDR_WIDTH 5 1026#define FRF_AB_EV_DEBUG_ADDR_LBN 16 1027#define FRF_AB_EV_DEBUG_ADDR_WIDTH 5 1028#define FRF_AB_RX_DEBUG_ADDR_LBN 11 1029#define FRF_AB_RX_DEBUG_ADDR_WIDTH 5 1030#define FRF_AB_TX_DEBUG_ADDR_LBN 6 1031#define FRF_AB_TX_DEBUG_ADDR_WIDTH 5 1032#define FRF_AB_CS_BIU_DEBUG_ADDR_LBN 1 1033#define FRF_AB_CS_BIU_DEBUG_ADDR_WIDTH 5 1034#define FRF_AZ_CS_DEBUG_EN_LBN 0 1035#define FRF_AZ_CS_DEBUG_EN_WIDTH 1 1036 1037 1038/* 1039 * FR_AZ_DRIVER_REG(128bit): 1040 * Driver scratch register [0-7] 1041 */ 1042#define FR_AZ_DRIVER_REG_OFST 0x00000280 1043/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1044#define FR_AZ_DRIVER_REG_STEP 16 1045#define FR_AZ_DRIVER_REG_ROWS 8 1046 1047#define FRF_AZ_DRIVER_DW0_LBN 0 1048#define FRF_AZ_DRIVER_DW0_WIDTH 32 1049 1050 1051/* 1052 * FR_AZ_ALTERA_BUILD_REG(128bit): 1053 * Altera build register 1054 */ 1055#define FR_AZ_ALTERA_BUILD_REG_OFST 0x00000300 1056/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1057 1058#define FRF_AZ_ALTERA_BUILD_VER_LBN 0 1059#define FRF_AZ_ALTERA_BUILD_VER_WIDTH 32 1060 1061 1062/* 1063 * FR_AZ_CSR_SPARE_REG(128bit): 1064 * Spare register 1065 */ 1066#define FR_AZ_CSR_SPARE_REG_OFST 0x00000310 1067/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1068 1069#define FRF_AZ_MEM_PERR_EN_TX_DATA_LBN 72 1070#define FRF_AZ_MEM_PERR_EN_TX_DATA_WIDTH 2 1071#define FRF_AZ_MEM_PERR_EN_LBN 64 1072#define FRF_AZ_MEM_PERR_EN_WIDTH 38 1073#define FRF_AZ_MEM_PERR_EN_DW0_LBN 64 1074#define FRF_AZ_MEM_PERR_EN_DW0_WIDTH 32 1075#define FRF_AZ_MEM_PERR_EN_DW1_LBN 96 1076#define FRF_AZ_MEM_PERR_EN_DW1_WIDTH 6 1077#define FRF_AZ_CSR_SPARE_BITS_LBN 0 1078#define FRF_AZ_CSR_SPARE_BITS_WIDTH 32 1079 1080 1081/* 1082 * FR_BZ_DEBUG_DATA_OUT_REG(128bit): 1083 * Live Debug and Debug 2 out ports 1084 */ 1085#define FR_BZ_DEBUG_DATA_OUT_REG_OFST 0x00000350 1086/* falconb0,sienaa0=net_func_bar2 */ 1087 1088#define FRF_BZ_DEBUG2_PORT_LBN 25 1089#define FRF_BZ_DEBUG2_PORT_WIDTH 15 1090#define FRF_BZ_DEBUG1_PORT_LBN 0 1091#define FRF_BZ_DEBUG1_PORT_WIDTH 25 1092 1093 1094/* 1095 * FR_BZ_EVQ_RPTR_REGP0(32bit): 1096 * Event queue read pointer register 1097 */ 1098#define FR_BZ_EVQ_RPTR_REGP0_OFST 0x00000400 1099/* falconb0,sienaa0=net_func_bar2 */ 1100#define FR_BZ_EVQ_RPTR_REGP0_STEP 8192 1101#define FR_BZ_EVQ_RPTR_REGP0_ROWS 1024 1102/* 1103 * FR_AA_EVQ_RPTR_REG_KER(32bit): 1104 * Event queue read pointer register 1105 */ 1106#define FR_AA_EVQ_RPTR_REG_KER_OFST 0x00011b00 1107/* falcona0=net_func_bar2 */ 1108#define FR_AA_EVQ_RPTR_REG_KER_STEP 4 1109#define FR_AA_EVQ_RPTR_REG_KER_ROWS 4 1110/* 1111 * FR_AZ_EVQ_RPTR_REG(32bit): 1112 * Event queue read pointer register 1113 */ 1114#define FR_AZ_EVQ_RPTR_REG_OFST 0x00fa0000 1115/* falconb0=net_func_bar2,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1116#define FR_AZ_EVQ_RPTR_REG_STEP 16 1117#define FR_AB_EVQ_RPTR_REG_ROWS 4096 1118#define FR_CZ_EVQ_RPTR_REG_ROWS 1024 1119/* 1120 * FR_BB_EVQ_RPTR_REGP123(32bit): 1121 * Event queue read pointer register 1122 */ 1123#define FR_BB_EVQ_RPTR_REGP123_OFST 0x01000400 1124/* falconb0=net_func_bar2 */ 1125#define FR_BB_EVQ_RPTR_REGP123_STEP 8192 1126#define FR_BB_EVQ_RPTR_REGP123_ROWS 3072 1127 1128#define FRF_AZ_EVQ_RPTR_VLD_LBN 15 1129#define FRF_AZ_EVQ_RPTR_VLD_WIDTH 1 1130#define FRF_AZ_EVQ_RPTR_LBN 0 1131#define FRF_AZ_EVQ_RPTR_WIDTH 15 1132 1133 1134/* 1135 * FR_BZ_TIMER_COMMAND_REGP0(128bit): 1136 * Timer Command Registers 1137 */ 1138#define FR_BZ_TIMER_COMMAND_REGP0_OFST 0x00000420 1139/* falconb0,sienaa0=net_func_bar2 */ 1140#define FR_BZ_TIMER_COMMAND_REGP0_STEP 8192 1141#define FR_BZ_TIMER_COMMAND_REGP0_ROWS 1024 1142/* 1143 * FR_AA_TIMER_COMMAND_REG_KER(128bit): 1144 * Timer Command Registers 1145 */ 1146#define FR_AA_TIMER_COMMAND_REG_KER_OFST 0x00000420 1147/* falcona0=net_func_bar2 */ 1148#define FR_AA_TIMER_COMMAND_REG_KER_STEP 8192 1149#define FR_AA_TIMER_COMMAND_REG_KER_ROWS 4 1150/* 1151 * FR_AB_TIMER_COMMAND_REGP123(128bit): 1152 * Timer Command Registers 1153 */ 1154#define FR_AB_TIMER_COMMAND_REGP123_OFST 0x01000420 1155/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 1156#define FR_AB_TIMER_COMMAND_REGP123_STEP 8192 1157#define FR_AB_TIMER_COMMAND_REGP123_ROWS 3072 1158/* 1159 * FR_AA_TIMER_COMMAND_REGP0(128bit): 1160 * Timer Command Registers 1161 */ 1162#define FR_AA_TIMER_COMMAND_REGP0_OFST 0x00008420 1163/* falcona0=char_func_bar0 */ 1164#define FR_AA_TIMER_COMMAND_REGP0_STEP 8192 1165#define FR_AA_TIMER_COMMAND_REGP0_ROWS 1020 1166 1167#define FRF_CZ_TC_TIMER_MODE_LBN 14 1168#define FRF_CZ_TC_TIMER_MODE_WIDTH 2 1169#define FRF_AB_TC_TIMER_MODE_LBN 12 1170#define FRF_AB_TC_TIMER_MODE_WIDTH 2 1171#define FRF_CZ_TC_TIMER_VAL_LBN 0 1172#define FRF_CZ_TC_TIMER_VAL_WIDTH 14 1173#define FRF_AB_TC_TIMER_VAL_LBN 0 1174#define FRF_AB_TC_TIMER_VAL_WIDTH 12 1175 1176 1177/* 1178 * FR_AZ_DRV_EV_REG(128bit): 1179 * Driver generated event register 1180 */ 1181#define FR_AZ_DRV_EV_REG_OFST 0x00000440 1182/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1183 1184#define FRF_AZ_DRV_EV_QID_LBN 64 1185#define FRF_AZ_DRV_EV_QID_WIDTH 12 1186#define FRF_AZ_DRV_EV_DATA_LBN 0 1187#define FRF_AZ_DRV_EV_DATA_WIDTH 64 1188#define FRF_AZ_DRV_EV_DATA_DW0_LBN 0 1189#define FRF_AZ_DRV_EV_DATA_DW0_WIDTH 32 1190#define FRF_AZ_DRV_EV_DATA_DW1_LBN 32 1191#define FRF_AZ_DRV_EV_DATA_DW1_WIDTH 32 1192 1193 1194/* 1195 * FR_AZ_EVQ_CTL_REG(128bit): 1196 * Event queue control register 1197 */ 1198#define FR_AZ_EVQ_CTL_REG_OFST 0x00000450 1199/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1200 1201#define FRF_CZ_RX_EVQ_WAKEUP_MASK_LBN 15 1202#define FRF_CZ_RX_EVQ_WAKEUP_MASK_WIDTH 10 1203#define FRF_BB_RX_EVQ_WAKEUP_MASK_LBN 15 1204#define FRF_BB_RX_EVQ_WAKEUP_MASK_WIDTH 6 1205#define FRF_AZ_EVQ_OWNERR_CTL_LBN 14 1206#define FRF_AZ_EVQ_OWNERR_CTL_WIDTH 1 1207#define FRF_AZ_EVQ_FIFO_AF_TH_LBN 7 1208#define FRF_AZ_EVQ_FIFO_AF_TH_WIDTH 7 1209#define FRF_AZ_EVQ_FIFO_NOTAF_TH_LBN 0 1210#define FRF_AZ_EVQ_FIFO_NOTAF_TH_WIDTH 7 1211 1212 1213/* 1214 * FR_AZ_EVQ_CNT1_REG(128bit): 1215 * Event counter 1 register 1216 */ 1217#define FR_AZ_EVQ_CNT1_REG_OFST 0x00000460 1218/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1219 1220#define FRF_AZ_EVQ_CNT_PRE_FIFO_LBN 120 1221#define FRF_AZ_EVQ_CNT_PRE_FIFO_WIDTH 7 1222#define FRF_AZ_EVQ_CNT_TOBIU_LBN 100 1223#define FRF_AZ_EVQ_CNT_TOBIU_WIDTH 20 1224#define FRF_AZ_EVQ_TX_REQ_CNT_LBN 80 1225#define FRF_AZ_EVQ_TX_REQ_CNT_WIDTH 20 1226#define FRF_AZ_EVQ_RX_REQ_CNT_LBN 60 1227#define FRF_AZ_EVQ_RX_REQ_CNT_WIDTH 20 1228#define FRF_AZ_EVQ_EM_REQ_CNT_LBN 40 1229#define FRF_AZ_EVQ_EM_REQ_CNT_WIDTH 20 1230#define FRF_AZ_EVQ_CSR_REQ_CNT_LBN 20 1231#define FRF_AZ_EVQ_CSR_REQ_CNT_WIDTH 20 1232#define FRF_AZ_EVQ_ERR_REQ_CNT_LBN 0 1233#define FRF_AZ_EVQ_ERR_REQ_CNT_WIDTH 20 1234 1235 1236/* 1237 * FR_AZ_EVQ_CNT2_REG(128bit): 1238 * Event counter 2 register 1239 */ 1240#define FR_AZ_EVQ_CNT2_REG_OFST 0x00000470 1241/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1242 1243#define FRF_AZ_EVQ_UPD_REQ_CNT_LBN 104 1244#define FRF_AZ_EVQ_UPD_REQ_CNT_WIDTH 20 1245#define FRF_AZ_EVQ_CLR_REQ_CNT_LBN 84 1246#define FRF_AZ_EVQ_CLR_REQ_CNT_WIDTH 20 1247#define FRF_AZ_EVQ_RDY_CNT_LBN 80 1248#define FRF_AZ_EVQ_RDY_CNT_WIDTH 4 1249#define FRF_AZ_EVQ_WU_REQ_CNT_LBN 60 1250#define FRF_AZ_EVQ_WU_REQ_CNT_WIDTH 20 1251#define FRF_AZ_EVQ_WET_REQ_CNT_LBN 40 1252#define FRF_AZ_EVQ_WET_REQ_CNT_WIDTH 20 1253#define FRF_AZ_EVQ_INIT_REQ_CNT_LBN 20 1254#define FRF_AZ_EVQ_INIT_REQ_CNT_WIDTH 20 1255#define FRF_AZ_EVQ_TM_REQ_CNT_LBN 0 1256#define FRF_AZ_EVQ_TM_REQ_CNT_WIDTH 20 1257 1258 1259/* 1260 * FR_CZ_USR_EV_REG(32bit): 1261 * Event mailbox register 1262 */ 1263#define FR_CZ_USR_EV_REG_OFST 0x00000540 1264/* sienaa0=net_func_bar2 */ 1265#define FR_CZ_USR_EV_REG_STEP 8192 1266#define FR_CZ_USR_EV_REG_ROWS 1024 1267 1268#define FRF_CZ_USR_EV_DATA_LBN 0 1269#define FRF_CZ_USR_EV_DATA_WIDTH 32 1270 1271 1272/* 1273 * FR_AZ_BUF_TBL_CFG_REG(128bit): 1274 * Buffer table configuration register 1275 */ 1276#define FR_AZ_BUF_TBL_CFG_REG_OFST 0x00000600 1277/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1278 1279#define FRF_AZ_BUF_TBL_MODE_LBN 3 1280#define FRF_AZ_BUF_TBL_MODE_WIDTH 1 1281 1282 1283/* 1284 * FR_AZ_SRM_RX_DC_CFG_REG(128bit): 1285 * SRAM receive descriptor cache configuration register 1286 */ 1287#define FR_AZ_SRM_RX_DC_CFG_REG_OFST 0x00000610 1288/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1289 1290#define FRF_AZ_SRM_CLK_TMP_EN_LBN 21 1291#define FRF_AZ_SRM_CLK_TMP_EN_WIDTH 1 1292#define FRF_AZ_SRM_RX_DC_BASE_ADR_LBN 0 1293#define FRF_AZ_SRM_RX_DC_BASE_ADR_WIDTH 21 1294 1295 1296/* 1297 * FR_AZ_SRM_TX_DC_CFG_REG(128bit): 1298 * SRAM transmit descriptor cache configuration register 1299 */ 1300#define FR_AZ_SRM_TX_DC_CFG_REG_OFST 0x00000620 1301/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1302 1303#define FRF_AZ_SRM_TX_DC_BASE_ADR_LBN 0 1304#define FRF_AZ_SRM_TX_DC_BASE_ADR_WIDTH 21 1305 1306 1307/* 1308 * FR_AZ_SRM_CFG_REG(128bit): 1309 * SRAM configuration register 1310 */ 1311#define FR_AZ_SRM_CFG_REG_SF_OFST 0x00000380 1312/* falcona0,falconb0=eeprom_flash */ 1313/* 1314 * FR_AZ_SRM_CFG_REG(128bit): 1315 * SRAM configuration register 1316 */ 1317#define FR_AZ_SRM_CFG_REG_OFST 0x00000630 1318/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1319 1320#define FRF_AZ_SRM_OOB_ADR_INTEN_LBN 5 1321#define FRF_AZ_SRM_OOB_ADR_INTEN_WIDTH 1 1322#define FRF_AZ_SRM_OOB_BUF_INTEN_LBN 4 1323#define FRF_AZ_SRM_OOB_BUF_INTEN_WIDTH 1 1324#define FRF_AZ_SRM_INIT_EN_LBN 3 1325#define FRF_AZ_SRM_INIT_EN_WIDTH 1 1326#define FRF_AZ_SRM_NUM_BANK_LBN 2 1327#define FRF_AZ_SRM_NUM_BANK_WIDTH 1 1328#define FRF_AZ_SRM_BANK_SIZE_LBN 0 1329#define FRF_AZ_SRM_BANK_SIZE_WIDTH 2 1330 1331 1332/* 1333 * FR_AZ_BUF_TBL_UPD_REG(128bit): 1334 * Buffer table update register 1335 */ 1336#define FR_AZ_BUF_TBL_UPD_REG_OFST 0x00000650 1337/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1338 1339#define FRF_AZ_BUF_UPD_CMD_LBN 63 1340#define FRF_AZ_BUF_UPD_CMD_WIDTH 1 1341#define FRF_AZ_BUF_CLR_CMD_LBN 62 1342#define FRF_AZ_BUF_CLR_CMD_WIDTH 1 1343#define FRF_AZ_BUF_CLR_END_ID_LBN 32 1344#define FRF_AZ_BUF_CLR_END_ID_WIDTH 20 1345#define FRF_AZ_BUF_CLR_START_ID_LBN 0 1346#define FRF_AZ_BUF_CLR_START_ID_WIDTH 20 1347 1348 1349/* 1350 * FR_AZ_SRM_UPD_EVQ_REG(128bit): 1351 * Buffer table update register 1352 */ 1353#define FR_AZ_SRM_UPD_EVQ_REG_OFST 0x00000660 1354/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1355 1356#define FRF_AZ_SRM_UPD_EVQ_ID_LBN 0 1357#define FRF_AZ_SRM_UPD_EVQ_ID_WIDTH 12 1358 1359 1360/* 1361 * FR_AZ_SRAM_PARITY_REG(128bit): 1362 * SRAM parity register. 1363 */ 1364#define FR_AZ_SRAM_PARITY_REG_OFST 0x00000670 1365/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1366 1367#define FRF_CZ_BYPASS_ECC_LBN 3 1368#define FRF_CZ_BYPASS_ECC_WIDTH 1 1369#define FRF_CZ_SEC_INT_LBN 2 1370#define FRF_CZ_SEC_INT_WIDTH 1 1371#define FRF_CZ_FORCE_SRAM_DOUBLE_ERR_LBN 1 1372#define FRF_CZ_FORCE_SRAM_DOUBLE_ERR_WIDTH 1 1373#define FRF_CZ_FORCE_SRAM_SINGLE_ERR_LBN 0 1374#define FRF_CZ_FORCE_SRAM_SINGLE_ERR_WIDTH 1 1375#define FRF_AB_FORCE_SRAM_PERR_LBN 0 1376#define FRF_AB_FORCE_SRAM_PERR_WIDTH 1 1377 1378 1379/* 1380 * FR_AZ_RX_CFG_REG(128bit): 1381 * Receive configuration register 1382 */ 1383#define FR_AZ_RX_CFG_REG_OFST 0x00000800 1384/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1385 1386#define FRF_CZ_RX_HDR_SPLIT_EN_LBN 71 1387#define FRF_CZ_RX_HDR_SPLIT_EN_WIDTH 1 1388#define FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_LBN 62 1389#define FRF_CZ_RX_HDR_SPLIT_PLD_BUF_SIZE_WIDTH 9 1390#define FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_LBN 53 1391#define FRF_CZ_RX_HDR_SPLIT_HDR_BUF_SIZE_WIDTH 9 1392#define FRF_CZ_RX_PRE_RFF_IPG_LBN 49 1393#define FRF_CZ_RX_PRE_RFF_IPG_WIDTH 4 1394#define FRF_BZ_RX_TCP_SUP_LBN 48 1395#define FRF_BZ_RX_TCP_SUP_WIDTH 1 1396#define FRF_BZ_RX_INGR_EN_LBN 47 1397#define FRF_BZ_RX_INGR_EN_WIDTH 1 1398#define FRF_BZ_RX_IP_HASH_LBN 46 1399#define FRF_BZ_RX_IP_HASH_WIDTH 1 1400#define FRF_BZ_RX_HASH_ALG_LBN 45 1401#define FRF_BZ_RX_HASH_ALG_WIDTH 1 1402#define FRF_BZ_RX_HASH_INSRT_HDR_LBN 44 1403#define FRF_BZ_RX_HASH_INSRT_HDR_WIDTH 1 1404#define FRF_BZ_RX_DESC_PUSH_EN_LBN 43 1405#define FRF_BZ_RX_DESC_PUSH_EN_WIDTH 1 1406#define FRF_BZ_RX_RDW_PATCH_EN_LBN 42 1407#define FRF_BZ_RX_RDW_PATCH_EN_WIDTH 1 1408#define FRF_BB_RX_PCI_BURST_SIZE_LBN 39 1409#define FRF_BB_RX_PCI_BURST_SIZE_WIDTH 3 1410#define FRF_BZ_RX_OWNERR_CTL_LBN 38 1411#define FRF_BZ_RX_OWNERR_CTL_WIDTH 1 1412#define FRF_BZ_RX_XON_TX_TH_LBN 33 1413#define FRF_BZ_RX_XON_TX_TH_WIDTH 5 1414#define FRF_AA_RX_DESC_PUSH_EN_LBN 35 1415#define FRF_AA_RX_DESC_PUSH_EN_WIDTH 1 1416#define FRF_AA_RX_RDW_PATCH_EN_LBN 34 1417#define FRF_AA_RX_RDW_PATCH_EN_WIDTH 1 1418#define FRF_AA_RX_PCI_BURST_SIZE_LBN 31 1419#define FRF_AA_RX_PCI_BURST_SIZE_WIDTH 3 1420#define FRF_BZ_RX_XOFF_TX_TH_LBN 28 1421#define FRF_BZ_RX_XOFF_TX_TH_WIDTH 5 1422#define FRF_AA_RX_OWNERR_CTL_LBN 30 1423#define FRF_AA_RX_OWNERR_CTL_WIDTH 1 1424#define FRF_AA_RX_XON_TX_TH_LBN 25 1425#define FRF_AA_RX_XON_TX_TH_WIDTH 5 1426#define FRF_BZ_RX_USR_BUF_SIZE_LBN 19 1427#define FRF_BZ_RX_USR_BUF_SIZE_WIDTH 9 1428#define FRF_AA_RX_XOFF_TX_TH_LBN 20 1429#define FRF_AA_RX_XOFF_TX_TH_WIDTH 5 1430#define FRF_AA_RX_USR_BUF_SIZE_LBN 11 1431#define FRF_AA_RX_USR_BUF_SIZE_WIDTH 9 1432#define FRF_BZ_RX_XON_MAC_TH_LBN 10 1433#define FRF_BZ_RX_XON_MAC_TH_WIDTH 9 1434#define FRF_AA_RX_XON_MAC_TH_LBN 6 1435#define FRF_AA_RX_XON_MAC_TH_WIDTH 5 1436#define FRF_BZ_RX_XOFF_MAC_TH_LBN 1 1437#define FRF_BZ_RX_XOFF_MAC_TH_WIDTH 9 1438#define FRF_AA_RX_XOFF_MAC_TH_LBN 1 1439#define FRF_AA_RX_XOFF_MAC_TH_WIDTH 5 1440#define FRF_AZ_RX_XOFF_MAC_EN_LBN 0 1441#define FRF_AZ_RX_XOFF_MAC_EN_WIDTH 1 1442 1443 1444/* 1445 * FR_AZ_RX_FILTER_CTL_REG(128bit): 1446 * Receive filter control registers 1447 */ 1448#define FR_AZ_RX_FILTER_CTL_REG_OFST 0x00000810 1449/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1450 1451#define FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT_LBN 94 1452#define FRF_CZ_ETHERNET_WILDCARD_SEARCH_LIMIT_WIDTH 8 1453#define FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT_LBN 86 1454#define FRF_CZ_ETHERNET_FULL_SEARCH_LIMIT_WIDTH 8 1455#define FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES_LBN 85 1456#define FRF_CZ_RX_FILTER_ALL_VLAN_ETHERTYPES_WIDTH 1 1457#define FRF_CZ_RX_VLAN_MATCH_ETHERTYPE_LBN 69 1458#define FRF_CZ_RX_VLAN_MATCH_ETHERTYPE_WIDTH 16 1459#define FRF_CZ_MULTICAST_NOMATCH_Q_ID_LBN 57 1460#define FRF_CZ_MULTICAST_NOMATCH_Q_ID_WIDTH 12 1461#define FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED_LBN 56 1462#define FRF_CZ_MULTICAST_NOMATCH_RSS_ENABLED_WIDTH 1 1463#define FRF_CZ_MULTICAST_NOMATCH_IP_OVERRIDE_LBN 55 1464#define FRF_CZ_MULTICAST_NOMATCH_IP_OVERRIDE_WIDTH 1 1465#define FRF_CZ_UNICAST_NOMATCH_Q_ID_LBN 43 1466#define FRF_CZ_UNICAST_NOMATCH_Q_ID_WIDTH 12 1467#define FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED_LBN 42 1468#define FRF_CZ_UNICAST_NOMATCH_RSS_ENABLED_WIDTH 1 1469#define FRF_CZ_UNICAST_NOMATCH_IP_OVERRIDE_LBN 41 1470#define FRF_CZ_UNICAST_NOMATCH_IP_OVERRIDE_WIDTH 1 1471#define FRF_BZ_SCATTER_ENBL_NO_MATCH_Q_LBN 40 1472#define FRF_BZ_SCATTER_ENBL_NO_MATCH_Q_WIDTH 1 1473#define FRF_AZ_UDP_FULL_SRCH_LIMIT_LBN 32 1474#define FRF_AZ_UDP_FULL_SRCH_LIMIT_WIDTH 8 1475#define FRF_AZ_NUM_KER_LBN 24 1476#define FRF_AZ_NUM_KER_WIDTH 2 1477#define FRF_AZ_UDP_WILD_SRCH_LIMIT_LBN 16 1478#define FRF_AZ_UDP_WILD_SRCH_LIMIT_WIDTH 8 1479#define FRF_AZ_TCP_WILD_SRCH_LIMIT_LBN 8 1480#define FRF_AZ_TCP_WILD_SRCH_LIMIT_WIDTH 8 1481#define FRF_AZ_TCP_FULL_SRCH_LIMIT_LBN 0 1482#define FRF_AZ_TCP_FULL_SRCH_LIMIT_WIDTH 8 1483 1484 1485/* 1486 * FR_AZ_RX_FLUSH_DESCQ_REG(128bit): 1487 * Receive flush descriptor queue register 1488 */ 1489#define FR_AZ_RX_FLUSH_DESCQ_REG_OFST 0x00000820 1490/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1491 1492#define FRF_AZ_RX_FLUSH_DESCQ_CMD_LBN 24 1493#define FRF_AZ_RX_FLUSH_DESCQ_CMD_WIDTH 1 1494#define FRF_AZ_RX_FLUSH_DESCQ_LBN 0 1495#define FRF_AZ_RX_FLUSH_DESCQ_WIDTH 12 1496 1497 1498/* 1499 * FR_BZ_RX_DESC_UPD_REGP0(128bit): 1500 * Receive descriptor update register. 1501 */ 1502#define FR_BZ_RX_DESC_UPD_REGP0_OFST 0x00000830 1503/* falconb0,sienaa0=net_func_bar2 */ 1504#define FR_BZ_RX_DESC_UPD_REGP0_STEP 8192 1505#define FR_BZ_RX_DESC_UPD_REGP0_ROWS 1024 1506/* 1507 * FR_AA_RX_DESC_UPD_REG_KER(128bit): 1508 * Receive descriptor update register. 1509 */ 1510#define FR_AA_RX_DESC_UPD_REG_KER_OFST 0x00000830 1511/* falcona0=net_func_bar2 */ 1512#define FR_AA_RX_DESC_UPD_REG_KER_STEP 8192 1513#define FR_AA_RX_DESC_UPD_REG_KER_ROWS 4 1514/* 1515 * FR_AB_RX_DESC_UPD_REGP123(128bit): 1516 * Receive descriptor update register. 1517 */ 1518#define FR_AB_RX_DESC_UPD_REGP123_OFST 0x01000830 1519/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 1520#define FR_AB_RX_DESC_UPD_REGP123_STEP 8192 1521#define FR_AB_RX_DESC_UPD_REGP123_ROWS 3072 1522/* 1523 * FR_AA_RX_DESC_UPD_REGP0(128bit): 1524 * Receive descriptor update register. 1525 */ 1526#define FR_AA_RX_DESC_UPD_REGP0_OFST 0x00008830 1527/* falcona0=char_func_bar0 */ 1528#define FR_AA_RX_DESC_UPD_REGP0_STEP 8192 1529#define FR_AA_RX_DESC_UPD_REGP0_ROWS 1020 1530 1531#define FRF_AZ_RX_DESC_WPTR_LBN 96 1532#define FRF_AZ_RX_DESC_WPTR_WIDTH 12 1533#define FRF_AZ_RX_DESC_PUSH_CMD_LBN 95 1534#define FRF_AZ_RX_DESC_PUSH_CMD_WIDTH 1 1535#define FRF_AZ_RX_DESC_LBN 0 1536#define FRF_AZ_RX_DESC_WIDTH 64 1537#define FRF_AZ_RX_DESC_DW0_LBN 0 1538#define FRF_AZ_RX_DESC_DW0_WIDTH 32 1539#define FRF_AZ_RX_DESC_DW1_LBN 32 1540#define FRF_AZ_RX_DESC_DW1_WIDTH 32 1541 1542 1543/* 1544 * FR_AZ_RX_DC_CFG_REG(128bit): 1545 * Receive descriptor cache configuration register 1546 */ 1547#define FR_AZ_RX_DC_CFG_REG_OFST 0x00000840 1548/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1549 1550#define FRF_AZ_RX_MAX_PF_LBN 2 1551#define FRF_AZ_RX_MAX_PF_WIDTH 2 1552#define FRF_AZ_RX_DC_SIZE_LBN 0 1553#define FRF_AZ_RX_DC_SIZE_WIDTH 2 1554#define FFE_AZ_RX_DC_SIZE_64 3 1555#define FFE_AZ_RX_DC_SIZE_32 2 1556#define FFE_AZ_RX_DC_SIZE_16 1 1557#define FFE_AZ_RX_DC_SIZE_8 0 1558 1559 1560/* 1561 * FR_AZ_RX_DC_PF_WM_REG(128bit): 1562 * Receive descriptor cache pre-fetch watermark register 1563 */ 1564#define FR_AZ_RX_DC_PF_WM_REG_OFST 0x00000850 1565/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1566 1567#define FRF_AZ_RX_DC_PF_HWM_LBN 6 1568#define FRF_AZ_RX_DC_PF_HWM_WIDTH 6 1569#define FRF_AZ_RX_DC_PF_LWM_LBN 0 1570#define FRF_AZ_RX_DC_PF_LWM_WIDTH 6 1571 1572 1573/* 1574 * FR_BZ_RX_RSS_TKEY_REG(128bit): 1575 * RSS Toeplitz hash key 1576 */ 1577#define FR_BZ_RX_RSS_TKEY_REG_OFST 0x00000860 1578/* falconb0,sienaa0=net_func_bar2 */ 1579 1580#define FRF_BZ_RX_RSS_TKEY_LBN 96 1581#define FRF_BZ_RX_RSS_TKEY_WIDTH 32 1582#define FRF_BZ_RX_RSS_TKEY_DW3_LBN 96 1583#define FRF_BZ_RX_RSS_TKEY_DW3_WIDTH 32 1584#define FRF_BZ_RX_RSS_TKEY_DW2_LBN 64 1585#define FRF_BZ_RX_RSS_TKEY_DW2_WIDTH 32 1586#define FRF_BZ_RX_RSS_TKEY_DW1_LBN 32 1587#define FRF_BZ_RX_RSS_TKEY_DW1_WIDTH 32 1588#define FRF_BZ_RX_RSS_TKEY_DW0_LBN 0 1589#define FRF_BZ_RX_RSS_TKEY_DW0_WIDTH 32 1590 1591 1592/* 1593 * FR_AZ_RX_NODESC_DROP_REG(128bit): 1594 * Receive dropped packet counter register 1595 */ 1596#define FR_AZ_RX_NODESC_DROP_REG_OFST 0x00000880 1597/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1598 1599#define FRF_AZ_RX_NODESC_DROP_CNT_LBN 0 1600#define FRF_AZ_RX_NODESC_DROP_CNT_WIDTH 16 1601 1602 1603/* 1604 * FR_AZ_RX_SELF_RST_REG(128bit): 1605 * Receive self reset register 1606 */ 1607#define FR_AZ_RX_SELF_RST_REG_OFST 0x00000890 1608/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1609 1610#define FRF_AZ_RX_ISCSI_DIS_LBN 17 1611#define FRF_AZ_RX_ISCSI_DIS_WIDTH 1 1612#define FRF_AB_RX_SW_RST_REG_LBN 16 1613#define FRF_AB_RX_SW_RST_REG_WIDTH 1 1614#define FRF_AB_RX_SELF_RST_EN_LBN 8 1615#define FRF_AB_RX_SELF_RST_EN_WIDTH 1 1616#define FRF_AZ_RX_MAX_PF_LAT_LBN 4 1617#define FRF_AZ_RX_MAX_PF_LAT_WIDTH 4 1618#define FRF_AZ_RX_MAX_LU_LAT_LBN 0 1619#define FRF_AZ_RX_MAX_LU_LAT_WIDTH 4 1620 1621 1622/* 1623 * FR_AZ_RX_DEBUG_REG(128bit): 1624 * undocumented register 1625 */ 1626#define FR_AZ_RX_DEBUG_REG_OFST 0x000008a0 1627/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1628 1629#define FRF_AZ_RX_DEBUG_LBN 0 1630#define FRF_AZ_RX_DEBUG_WIDTH 64 1631#define FRF_AZ_RX_DEBUG_DW0_LBN 0 1632#define FRF_AZ_RX_DEBUG_DW0_WIDTH 32 1633#define FRF_AZ_RX_DEBUG_DW1_LBN 32 1634#define FRF_AZ_RX_DEBUG_DW1_WIDTH 32 1635 1636 1637/* 1638 * FR_AZ_RX_PUSH_DROP_REG(128bit): 1639 * Receive descriptor push dropped counter register 1640 */ 1641#define FR_AZ_RX_PUSH_DROP_REG_OFST 0x000008b0 1642/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1643 1644#define FRF_AZ_RX_PUSH_DROP_CNT_LBN 0 1645#define FRF_AZ_RX_PUSH_DROP_CNT_WIDTH 32 1646 1647 1648/* 1649 * FR_CZ_RX_RSS_IPV6_REG1(128bit): 1650 * IPv6 RSS Toeplitz hash key low bytes 1651 */ 1652#define FR_CZ_RX_RSS_IPV6_REG1_OFST 0x000008d0 1653/* sienaa0=net_func_bar2 */ 1654 1655#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_LBN 0 1656#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_WIDTH 128 1657#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW0_LBN 0 1658#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW0_WIDTH 32 1659#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW1_LBN 32 1660#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW1_WIDTH 32 1661#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW2_LBN 64 1662#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW2_WIDTH 32 1663#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW3_LBN 96 1664#define FRF_CZ_RX_RSS_IPV6_TKEY_LO_DW3_WIDTH 32 1665 1666 1667/* 1668 * FR_CZ_RX_RSS_IPV6_REG2(128bit): 1669 * IPv6 RSS Toeplitz hash key middle bytes 1670 */ 1671#define FR_CZ_RX_RSS_IPV6_REG2_OFST 0x000008e0 1672/* sienaa0=net_func_bar2 */ 1673 1674#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_LBN 0 1675#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_WIDTH 128 1676#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW0_LBN 0 1677#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW0_WIDTH 32 1678#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW1_LBN 32 1679#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW1_WIDTH 32 1680#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW2_LBN 64 1681#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW2_WIDTH 32 1682#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW3_LBN 96 1683#define FRF_CZ_RX_RSS_IPV6_TKEY_MID_DW3_WIDTH 32 1684 1685 1686/* 1687 * FR_CZ_RX_RSS_IPV6_REG3(128bit): 1688 * IPv6 RSS Toeplitz hash key upper bytes and IPv6 RSS settings 1689 */ 1690#define FR_CZ_RX_RSS_IPV6_REG3_OFST 0x000008f0 1691/* sienaa0=net_func_bar2 */ 1692 1693#define FRF_CZ_RX_RSS_IPV6_THASH_ENABLE_LBN 66 1694#define FRF_CZ_RX_RSS_IPV6_THASH_ENABLE_WIDTH 1 1695#define FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE_LBN 65 1696#define FRF_CZ_RX_RSS_IPV6_IP_THASH_ENABLE_WIDTH 1 1697#define FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS_LBN 64 1698#define FRF_CZ_RX_RSS_IPV6_TCP_SUPPRESS_WIDTH 1 1699#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_LBN 0 1700#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_WIDTH 64 1701#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW0_LBN 0 1702#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW0_WIDTH 32 1703#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW1_LBN 32 1704#define FRF_CZ_RX_RSS_IPV6_TKEY_HI_DW1_WIDTH 32 1705 1706 1707/* 1708 * FR_AZ_TX_FLUSH_DESCQ_REG(128bit): 1709 * Transmit flush descriptor queue register 1710 */ 1711#define FR_AZ_TX_FLUSH_DESCQ_REG_OFST 0x00000a00 1712/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1713 1714#define FRF_AZ_TX_FLUSH_DESCQ_CMD_LBN 12 1715#define FRF_AZ_TX_FLUSH_DESCQ_CMD_WIDTH 1 1716#define FRF_AZ_TX_FLUSH_DESCQ_LBN 0 1717#define FRF_AZ_TX_FLUSH_DESCQ_WIDTH 12 1718 1719 1720/* 1721 * FR_BZ_TX_DESC_UPD_REGP0(128bit): 1722 * Transmit descriptor update register. 1723 */ 1724#define FR_BZ_TX_DESC_UPD_REGP0_OFST 0x00000a10 1725/* falconb0,sienaa0=net_func_bar2 */ 1726#define FR_BZ_TX_DESC_UPD_REGP0_STEP 8192 1727#define FR_BZ_TX_DESC_UPD_REGP0_ROWS 1024 1728/* 1729 * FR_AA_TX_DESC_UPD_REG_KER(128bit): 1730 * Transmit descriptor update register. 1731 */ 1732#define FR_AA_TX_DESC_UPD_REG_KER_OFST 0x00000a10 1733/* falcona0=net_func_bar2 */ 1734#define FR_AA_TX_DESC_UPD_REG_KER_STEP 8192 1735#define FR_AA_TX_DESC_UPD_REG_KER_ROWS 8 1736/* 1737 * FR_AB_TX_DESC_UPD_REGP123(128bit): 1738 * Transmit descriptor update register. 1739 */ 1740#define FR_AB_TX_DESC_UPD_REGP123_OFST 0x01000a10 1741/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 1742#define FR_AB_TX_DESC_UPD_REGP123_STEP 8192 1743#define FR_AB_TX_DESC_UPD_REGP123_ROWS 3072 1744/* 1745 * FR_AA_TX_DESC_UPD_REGP0(128bit): 1746 * Transmit descriptor update register. 1747 */ 1748#define FR_AA_TX_DESC_UPD_REGP0_OFST 0x00008a10 1749/* falcona0=char_func_bar0 */ 1750#define FR_AA_TX_DESC_UPD_REGP0_STEP 8192 1751#define FR_AA_TX_DESC_UPD_REGP0_ROWS 1020 1752 1753#define FRF_AZ_TX_DESC_WPTR_LBN 96 1754#define FRF_AZ_TX_DESC_WPTR_WIDTH 12 1755#define FRF_AZ_TX_DESC_PUSH_CMD_LBN 95 1756#define FRF_AZ_TX_DESC_PUSH_CMD_WIDTH 1 1757#define FRF_AZ_TX_DESC_LBN 0 1758#define FRF_AZ_TX_DESC_WIDTH 95 1759#define FRF_AZ_TX_DESC_DW0_LBN 0 1760#define FRF_AZ_TX_DESC_DW0_WIDTH 32 1761#define FRF_AZ_TX_DESC_DW1_LBN 32 1762#define FRF_AZ_TX_DESC_DW1_WIDTH 32 1763#define FRF_AZ_TX_DESC_DW2_LBN 64 1764#define FRF_AZ_TX_DESC_DW2_WIDTH 31 1765 1766 1767/* 1768 * FR_AZ_TX_DC_CFG_REG(128bit): 1769 * Transmit descriptor cache configuration register 1770 */ 1771#define FR_AZ_TX_DC_CFG_REG_OFST 0x00000a20 1772/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1773 1774#define FRF_AZ_TX_DC_SIZE_LBN 0 1775#define FRF_AZ_TX_DC_SIZE_WIDTH 2 1776#define FFE_AZ_TX_DC_SIZE_32 2 1777#define FFE_AZ_TX_DC_SIZE_16 1 1778#define FFE_AZ_TX_DC_SIZE_8 0 1779 1780 1781/* 1782 * FR_AA_TX_CHKSM_CFG_REG(128bit): 1783 * Transmit checksum configuration register 1784 */ 1785#define FR_AA_TX_CHKSM_CFG_REG_OFST 0x00000a30 1786/* falcona0=net_func_bar2,falcona0=char_func_bar0 */ 1787 1788#define FRF_AA_TX_Q_CHKSM_DIS_96_127_LBN 96 1789#define FRF_AA_TX_Q_CHKSM_DIS_96_127_WIDTH 32 1790#define FRF_AA_TX_Q_CHKSM_DIS_64_95_LBN 64 1791#define FRF_AA_TX_Q_CHKSM_DIS_64_95_WIDTH 32 1792#define FRF_AA_TX_Q_CHKSM_DIS_32_63_LBN 32 1793#define FRF_AA_TX_Q_CHKSM_DIS_32_63_WIDTH 32 1794#define FRF_AA_TX_Q_CHKSM_DIS_0_31_LBN 0 1795#define FRF_AA_TX_Q_CHKSM_DIS_0_31_WIDTH 32 1796 1797 1798/* 1799 * FR_AZ_TX_CFG_REG(128bit): 1800 * Transmit configuration register 1801 */ 1802#define FR_AZ_TX_CFG_REG_OFST 0x00000a50 1803/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1804 1805#define FRF_CZ_TX_CONT_LOOKUP_THRESH_RANGE_LBN 114 1806#define FRF_CZ_TX_CONT_LOOKUP_THRESH_RANGE_WIDTH 8 1807#define FRF_CZ_TX_FILTER_TEST_MODE_BIT_LBN 113 1808#define FRF_CZ_TX_FILTER_TEST_MODE_BIT_WIDTH 1 1809#define FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE_LBN 105 1810#define FRF_CZ_TX_ETH_FILTER_WILD_SEARCH_RANGE_WIDTH 8 1811#define FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE_LBN 97 1812#define FRF_CZ_TX_ETH_FILTER_FULL_SEARCH_RANGE_WIDTH 8 1813#define FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE_LBN 89 1814#define FRF_CZ_TX_UDPIP_FILTER_WILD_SEARCH_RANGE_WIDTH 8 1815#define FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE_LBN 81 1816#define FRF_CZ_TX_UDPIP_FILTER_FULL_SEARCH_RANGE_WIDTH 8 1817#define FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE_LBN 73 1818#define FRF_CZ_TX_TCPIP_FILTER_WILD_SEARCH_RANGE_WIDTH 8 1819#define FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE_LBN 65 1820#define FRF_CZ_TX_TCPIP_FILTER_FULL_SEARCH_RANGE_WIDTH 8 1821#define FRF_CZ_TX_FILTER_ALL_VLAN_ETHERTYPES_BIT_LBN 64 1822#define FRF_CZ_TX_FILTER_ALL_VLAN_ETHERTYPES_BIT_WIDTH 1 1823#define FRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_LBN 48 1824#define FRF_CZ_TX_VLAN_MATCH_ETHERTYPE_RANGE_WIDTH 16 1825#define FRF_CZ_TX_FILTER_EN_BIT_LBN 47 1826#define FRF_CZ_TX_FILTER_EN_BIT_WIDTH 1 1827#define FRF_AZ_TX_IP_ID_P0_OFS_LBN 16 1828#define FRF_AZ_TX_IP_ID_P0_OFS_WIDTH 15 1829#define FRF_AZ_TX_NO_EOP_DISC_EN_LBN 5 1830#define FRF_AZ_TX_NO_EOP_DISC_EN_WIDTH 1 1831#define FRF_AZ_TX_P1_PRI_EN_LBN 4 1832#define FRF_AZ_TX_P1_PRI_EN_WIDTH 1 1833#define FRF_AZ_TX_OWNERR_CTL_LBN 2 1834#define FRF_AZ_TX_OWNERR_CTL_WIDTH 1 1835#define FRF_AA_TX_NON_IP_DROP_DIS_LBN 1 1836#define FRF_AA_TX_NON_IP_DROP_DIS_WIDTH 1 1837#define FRF_AZ_TX_IP_ID_REP_EN_LBN 0 1838#define FRF_AZ_TX_IP_ID_REP_EN_WIDTH 1 1839 1840 1841/* 1842 * FR_AZ_TX_PUSH_DROP_REG(128bit): 1843 * Transmit push dropped register 1844 */ 1845#define FR_AZ_TX_PUSH_DROP_REG_OFST 0x00000a60 1846/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1847 1848#define FRF_AZ_TX_PUSH_DROP_CNT_LBN 0 1849#define FRF_AZ_TX_PUSH_DROP_CNT_WIDTH 32 1850 1851 1852/* 1853 * FR_AZ_TX_RESERVED_REG(128bit): 1854 * Transmit configuration register 1855 */ 1856#define FR_AZ_TX_RESERVED_REG_OFST 0x00000a80 1857/* falcona0,falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1858 1859#define FRF_AZ_TX_EVT_CNT_LBN 121 1860#define FRF_AZ_TX_EVT_CNT_WIDTH 7 1861#define FRF_AZ_TX_PREF_AGE_CNT_LBN 119 1862#define FRF_AZ_TX_PREF_AGE_CNT_WIDTH 2 1863#define FRF_AZ_TX_RD_COMP_TMR_LBN 96 1864#define FRF_AZ_TX_RD_COMP_TMR_WIDTH 23 1865#define FRF_AZ_TX_PUSH_EN_LBN 89 1866#define FRF_AZ_TX_PUSH_EN_WIDTH 1 1867#define FRF_AZ_TX_PUSH_CHK_DIS_LBN 88 1868#define FRF_AZ_TX_PUSH_CHK_DIS_WIDTH 1 1869#define FRF_AZ_TX_D_FF_FULL_P0_LBN 85 1870#define FRF_AZ_TX_D_FF_FULL_P0_WIDTH 1 1871#define FRF_AZ_TX_DMAR_ST_P0_LBN 81 1872#define FRF_AZ_TX_DMAR_ST_P0_WIDTH 1 1873#define FRF_AZ_TX_DMAQ_ST_LBN 78 1874#define FRF_AZ_TX_DMAQ_ST_WIDTH 1 1875#define FRF_AZ_TX_RX_SPACER_LBN 64 1876#define FRF_AZ_TX_RX_SPACER_WIDTH 8 1877#define FRF_AZ_TX_DROP_ABORT_EN_LBN 60 1878#define FRF_AZ_TX_DROP_ABORT_EN_WIDTH 1 1879#define FRF_AZ_TX_SOFT_EVT_EN_LBN 59 1880#define FRF_AZ_TX_SOFT_EVT_EN_WIDTH 1 1881#define FRF_AZ_TX_PS_EVT_DIS_LBN 58 1882#define FRF_AZ_TX_PS_EVT_DIS_WIDTH 1 1883#define FRF_AZ_TX_RX_SPACER_EN_LBN 57 1884#define FRF_AZ_TX_RX_SPACER_EN_WIDTH 1 1885#define FRF_AZ_TX_XP_TIMER_LBN 52 1886#define FRF_AZ_TX_XP_TIMER_WIDTH 5 1887#define FRF_AZ_TX_PREF_SPACER_LBN 44 1888#define FRF_AZ_TX_PREF_SPACER_WIDTH 8 1889#define FRF_AZ_TX_PREF_WD_TMR_LBN 22 1890#define FRF_AZ_TX_PREF_WD_TMR_WIDTH 22 1891#define FRF_AZ_TX_ONLY1TAG_LBN 21 1892#define FRF_AZ_TX_ONLY1TAG_WIDTH 1 1893#define FRF_AZ_TX_PREF_THRESHOLD_LBN 19 1894#define FRF_AZ_TX_PREF_THRESHOLD_WIDTH 2 1895#define FRF_AZ_TX_ONE_PKT_PER_Q_LBN 18 1896#define FRF_AZ_TX_ONE_PKT_PER_Q_WIDTH 1 1897#define FRF_AZ_TX_DIS_NON_IP_EV_LBN 17 1898#define FRF_AZ_TX_DIS_NON_IP_EV_WIDTH 1 1899#define FRF_AA_TX_DMA_FF_THR_LBN 16 1900#define FRF_AA_TX_DMA_FF_THR_WIDTH 1 1901#define FRF_AZ_TX_DMA_SPACER_LBN 8 1902#define FRF_AZ_TX_DMA_SPACER_WIDTH 8 1903#define FRF_AA_TX_TCP_DIS_LBN 7 1904#define FRF_AA_TX_TCP_DIS_WIDTH 1 1905#define FRF_BZ_TX_FLUSH_MIN_LEN_EN_LBN 7 1906#define FRF_BZ_TX_FLUSH_MIN_LEN_EN_WIDTH 1 1907#define FRF_AA_TX_IP_DIS_LBN 6 1908#define FRF_AA_TX_IP_DIS_WIDTH 1 1909#define FRF_AZ_TX_MAX_CPL_LBN 2 1910#define FRF_AZ_TX_MAX_CPL_WIDTH 2 1911#define FFE_AZ_TX_MAX_CPL_16 3 1912#define FFE_AZ_TX_MAX_CPL_8 2 1913#define FFE_AZ_TX_MAX_CPL_4 1 1914#define FFE_AZ_TX_MAX_CPL_NOLIMIT 0 1915#define FRF_AZ_TX_MAX_PREF_LBN 0 1916#define FRF_AZ_TX_MAX_PREF_WIDTH 2 1917#define FFE_AZ_TX_MAX_PREF_32 3 1918#define FFE_AZ_TX_MAX_PREF_16 2 1919#define FFE_AZ_TX_MAX_PREF_8 1 1920#define FFE_AZ_TX_MAX_PREF_OFF 0 1921 1922 1923/* 1924 * FR_BZ_TX_PACE_REG(128bit): 1925 * Transmit pace control register 1926 */ 1927#define FR_BZ_TX_PACE_REG_OFST 0x00000a90 1928/* falconb0,sienaa0=net_func_bar2 */ 1929/* 1930 * FR_AA_TX_PACE_REG(128bit): 1931 * Transmit pace control register 1932 */ 1933#define FR_AA_TX_PACE_REG_OFST 0x00f80000 1934/* falcona0=char_func_bar0 */ 1935 1936#define FRF_AZ_TX_PACE_SB_NOT_AF_LBN 19 1937#define FRF_AZ_TX_PACE_SB_NOT_AF_WIDTH 10 1938#define FRF_AZ_TX_PACE_SB_AF_LBN 9 1939#define FRF_AZ_TX_PACE_SB_AF_WIDTH 10 1940#define FRF_AZ_TX_PACE_FB_BASE_LBN 5 1941#define FRF_AZ_TX_PACE_FB_BASE_WIDTH 4 1942#define FRF_AZ_TX_PACE_BIN_TH_LBN 0 1943#define FRF_AZ_TX_PACE_BIN_TH_WIDTH 5 1944 1945 1946/* 1947 * FR_AZ_TX_PACE_DROP_QID_REG(128bit): 1948 * PACE Drop QID Counter 1949 */ 1950#define FR_AZ_TX_PACE_DROP_QID_REG_OFST 0x00000aa0 1951/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 1952 1953#define FRF_AZ_TX_PACE_QID_DRP_CNT_LBN 0 1954#define FRF_AZ_TX_PACE_QID_DRP_CNT_WIDTH 16 1955 1956 1957/* 1958 * FR_AB_TX_VLAN_REG(128bit): 1959 * Transmit VLAN tag register 1960 */ 1961#define FR_AB_TX_VLAN_REG_OFST 0x00000ae0 1962/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 1963 1964#define FRF_AB_TX_VLAN_EN_LBN 127 1965#define FRF_AB_TX_VLAN_EN_WIDTH 1 1966#define FRF_AB_TX_VLAN7_PORT1_EN_LBN 125 1967#define FRF_AB_TX_VLAN7_PORT1_EN_WIDTH 1 1968#define FRF_AB_TX_VLAN7_PORT0_EN_LBN 124 1969#define FRF_AB_TX_VLAN7_PORT0_EN_WIDTH 1 1970#define FRF_AB_TX_VLAN7_LBN 112 1971#define FRF_AB_TX_VLAN7_WIDTH 12 1972#define FRF_AB_TX_VLAN6_PORT1_EN_LBN 109 1973#define FRF_AB_TX_VLAN6_PORT1_EN_WIDTH 1 1974#define FRF_AB_TX_VLAN6_PORT0_EN_LBN 108 1975#define FRF_AB_TX_VLAN6_PORT0_EN_WIDTH 1 1976#define FRF_AB_TX_VLAN6_LBN 96 1977#define FRF_AB_TX_VLAN6_WIDTH 12 1978#define FRF_AB_TX_VLAN5_PORT1_EN_LBN 93 1979#define FRF_AB_TX_VLAN5_PORT1_EN_WIDTH 1 1980#define FRF_AB_TX_VLAN5_PORT0_EN_LBN 92 1981#define FRF_AB_TX_VLAN5_PORT0_EN_WIDTH 1 1982#define FRF_AB_TX_VLAN5_LBN 80 1983#define FRF_AB_TX_VLAN5_WIDTH 12 1984#define FRF_AB_TX_VLAN4_PORT1_EN_LBN 77 1985#define FRF_AB_TX_VLAN4_PORT1_EN_WIDTH 1 1986#define FRF_AB_TX_VLAN4_PORT0_EN_LBN 76 1987#define FRF_AB_TX_VLAN4_PORT0_EN_WIDTH 1 1988#define FRF_AB_TX_VLAN4_LBN 64 1989#define FRF_AB_TX_VLAN4_WIDTH 12 1990#define FRF_AB_TX_VLAN3_PORT1_EN_LBN 61 1991#define FRF_AB_TX_VLAN3_PORT1_EN_WIDTH 1 1992#define FRF_AB_TX_VLAN3_PORT0_EN_LBN 60 1993#define FRF_AB_TX_VLAN3_PORT0_EN_WIDTH 1 1994#define FRF_AB_TX_VLAN3_LBN 48 1995#define FRF_AB_TX_VLAN3_WIDTH 12 1996#define FRF_AB_TX_VLAN2_PORT1_EN_LBN 45 1997#define FRF_AB_TX_VLAN2_PORT1_EN_WIDTH 1 1998#define FRF_AB_TX_VLAN2_PORT0_EN_LBN 44 1999#define FRF_AB_TX_VLAN2_PORT0_EN_WIDTH 1 2000#define FRF_AB_TX_VLAN2_LBN 32 2001#define FRF_AB_TX_VLAN2_WIDTH 12 2002#define FRF_AB_TX_VLAN1_PORT1_EN_LBN 29 2003#define FRF_AB_TX_VLAN1_PORT1_EN_WIDTH 1 2004#define FRF_AB_TX_VLAN1_PORT0_EN_LBN 28 2005#define FRF_AB_TX_VLAN1_PORT0_EN_WIDTH 1 2006#define FRF_AB_TX_VLAN1_LBN 16 2007#define FRF_AB_TX_VLAN1_WIDTH 12 2008#define FRF_AB_TX_VLAN0_PORT1_EN_LBN 13 2009#define FRF_AB_TX_VLAN0_PORT1_EN_WIDTH 1 2010#define FRF_AB_TX_VLAN0_PORT0_EN_LBN 12 2011#define FRF_AB_TX_VLAN0_PORT0_EN_WIDTH 1 2012#define FRF_AB_TX_VLAN0_LBN 0 2013#define FRF_AB_TX_VLAN0_WIDTH 12 2014 2015 2016/* 2017 * FR_AZ_TX_IPFIL_PORTEN_REG(128bit): 2018 * Transmit filter control register 2019 */ 2020#define FR_AZ_TX_IPFIL_PORTEN_REG_OFST 0x00000af0 2021/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 2022 2023#define FRF_AZ_TX_MADR0_FIL_EN_LBN 64 2024#define FRF_AZ_TX_MADR0_FIL_EN_WIDTH 1 2025#define FRF_AB_TX_IPFIL31_PORT_EN_LBN 62 2026#define FRF_AB_TX_IPFIL31_PORT_EN_WIDTH 1 2027#define FRF_AB_TX_IPFIL30_PORT_EN_LBN 60 2028#define FRF_AB_TX_IPFIL30_PORT_EN_WIDTH 1 2029#define FRF_AB_TX_IPFIL29_PORT_EN_LBN 58 2030#define FRF_AB_TX_IPFIL29_PORT_EN_WIDTH 1 2031#define FRF_AB_TX_IPFIL28_PORT_EN_LBN 56 2032#define FRF_AB_TX_IPFIL28_PORT_EN_WIDTH 1 2033#define FRF_AB_TX_IPFIL27_PORT_EN_LBN 54 2034#define FRF_AB_TX_IPFIL27_PORT_EN_WIDTH 1 2035#define FRF_AB_TX_IPFIL26_PORT_EN_LBN 52 2036#define FRF_AB_TX_IPFIL26_PORT_EN_WIDTH 1 2037#define FRF_AB_TX_IPFIL25_PORT_EN_LBN 50 2038#define FRF_AB_TX_IPFIL25_PORT_EN_WIDTH 1 2039#define FRF_AB_TX_IPFIL24_PORT_EN_LBN 48 2040#define FRF_AB_TX_IPFIL24_PORT_EN_WIDTH 1 2041#define FRF_AB_TX_IPFIL23_PORT_EN_LBN 46 2042#define FRF_AB_TX_IPFIL23_PORT_EN_WIDTH 1 2043#define FRF_AB_TX_IPFIL22_PORT_EN_LBN 44 2044#define FRF_AB_TX_IPFIL22_PORT_EN_WIDTH 1 2045#define FRF_AB_TX_IPFIL21_PORT_EN_LBN 42 2046#define FRF_AB_TX_IPFIL21_PORT_EN_WIDTH 1 2047#define FRF_AB_TX_IPFIL20_PORT_EN_LBN 40 2048#define FRF_AB_TX_IPFIL20_PORT_EN_WIDTH 1 2049#define FRF_AB_TX_IPFIL19_PORT_EN_LBN 38 2050#define FRF_AB_TX_IPFIL19_PORT_EN_WIDTH 1 2051#define FRF_AB_TX_IPFIL18_PORT_EN_LBN 36 2052#define FRF_AB_TX_IPFIL18_PORT_EN_WIDTH 1 2053#define FRF_AB_TX_IPFIL17_PORT_EN_LBN 34 2054#define FRF_AB_TX_IPFIL17_PORT_EN_WIDTH 1 2055#define FRF_AB_TX_IPFIL16_PORT_EN_LBN 32 2056#define FRF_AB_TX_IPFIL16_PORT_EN_WIDTH 1 2057#define FRF_AB_TX_IPFIL15_PORT_EN_LBN 30 2058#define FRF_AB_TX_IPFIL15_PORT_EN_WIDTH 1 2059#define FRF_AB_TX_IPFIL14_PORT_EN_LBN 28 2060#define FRF_AB_TX_IPFIL14_PORT_EN_WIDTH 1 2061#define FRF_AB_TX_IPFIL13_PORT_EN_LBN 26 2062#define FRF_AB_TX_IPFIL13_PORT_EN_WIDTH 1 2063#define FRF_AB_TX_IPFIL12_PORT_EN_LBN 24 2064#define FRF_AB_TX_IPFIL12_PORT_EN_WIDTH 1 2065#define FRF_AB_TX_IPFIL11_PORT_EN_LBN 22 2066#define FRF_AB_TX_IPFIL11_PORT_EN_WIDTH 1 2067#define FRF_AB_TX_IPFIL10_PORT_EN_LBN 20 2068#define FRF_AB_TX_IPFIL10_PORT_EN_WIDTH 1 2069#define FRF_AB_TX_IPFIL9_PORT_EN_LBN 18 2070#define FRF_AB_TX_IPFIL9_PORT_EN_WIDTH 1 2071#define FRF_AB_TX_IPFIL8_PORT_EN_LBN 16 2072#define FRF_AB_TX_IPFIL8_PORT_EN_WIDTH 1 2073#define FRF_AB_TX_IPFIL7_PORT_EN_LBN 14 2074#define FRF_AB_TX_IPFIL7_PORT_EN_WIDTH 1 2075#define FRF_AB_TX_IPFIL6_PORT_EN_LBN 12 2076#define FRF_AB_TX_IPFIL6_PORT_EN_WIDTH 1 2077#define FRF_AB_TX_IPFIL5_PORT_EN_LBN 10 2078#define FRF_AB_TX_IPFIL5_PORT_EN_WIDTH 1 2079#define FRF_AB_TX_IPFIL4_PORT_EN_LBN 8 2080#define FRF_AB_TX_IPFIL4_PORT_EN_WIDTH 1 2081#define FRF_AB_TX_IPFIL3_PORT_EN_LBN 6 2082#define FRF_AB_TX_IPFIL3_PORT_EN_WIDTH 1 2083#define FRF_AB_TX_IPFIL2_PORT_EN_LBN 4 2084#define FRF_AB_TX_IPFIL2_PORT_EN_WIDTH 1 2085#define FRF_AB_TX_IPFIL1_PORT_EN_LBN 2 2086#define FRF_AB_TX_IPFIL1_PORT_EN_WIDTH 1 2087#define FRF_AB_TX_IPFIL0_PORT_EN_LBN 0 2088#define FRF_AB_TX_IPFIL0_PORT_EN_WIDTH 1 2089 2090 2091/* 2092 * FR_AB_TX_IPFIL_TBL(128bit): 2093 * Transmit IP source address filter table 2094 */ 2095#define FR_AB_TX_IPFIL_TBL_OFST 0x00000b00 2096/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2097#define FR_AB_TX_IPFIL_TBL_STEP 16 2098#define FR_AB_TX_IPFIL_TBL_ROWS 16 2099 2100#define FRF_AB_TX_IPFIL_MASK_1_LBN 96 2101#define FRF_AB_TX_IPFIL_MASK_1_WIDTH 32 2102#define FRF_AB_TX_IP_SRC_ADR_1_LBN 64 2103#define FRF_AB_TX_IP_SRC_ADR_1_WIDTH 32 2104#define FRF_AB_TX_IPFIL_MASK_0_LBN 32 2105#define FRF_AB_TX_IPFIL_MASK_0_WIDTH 32 2106#define FRF_AB_TX_IP_SRC_ADR_0_LBN 0 2107#define FRF_AB_TX_IP_SRC_ADR_0_WIDTH 32 2108 2109 2110/* 2111 * FR_AB_MD_TXD_REG(128bit): 2112 * PHY management transmit data register 2113 */ 2114#define FR_AB_MD_TXD_REG_OFST 0x00000c00 2115/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2116 2117#define FRF_AB_MD_TXD_LBN 0 2118#define FRF_AB_MD_TXD_WIDTH 16 2119 2120 2121/* 2122 * FR_AB_MD_RXD_REG(128bit): 2123 * PHY management receive data register 2124 */ 2125#define FR_AB_MD_RXD_REG_OFST 0x00000c10 2126/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2127 2128#define FRF_AB_MD_RXD_LBN 0 2129#define FRF_AB_MD_RXD_WIDTH 16 2130 2131 2132/* 2133 * FR_AB_MD_CS_REG(128bit): 2134 * PHY management configuration & status register 2135 */ 2136#define FR_AB_MD_CS_REG_OFST 0x00000c20 2137/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2138 2139#define FRF_AB_MD_RD_EN_LBN 15 2140#define FRF_AB_MD_RD_EN_WIDTH 1 2141#define FRF_AB_MD_WR_EN_LBN 14 2142#define FRF_AB_MD_WR_EN_WIDTH 1 2143#define FRF_AB_MD_ADDR_CMD_LBN 13 2144#define FRF_AB_MD_ADDR_CMD_WIDTH 1 2145#define FRF_AB_MD_PT_LBN 7 2146#define FRF_AB_MD_PT_WIDTH 3 2147#define FRF_AB_MD_PL_LBN 6 2148#define FRF_AB_MD_PL_WIDTH 1 2149#define FRF_AB_MD_INT_CLR_LBN 5 2150#define FRF_AB_MD_INT_CLR_WIDTH 1 2151#define FRF_AB_MD_GC_LBN 4 2152#define FRF_AB_MD_GC_WIDTH 1 2153#define FRF_AB_MD_PRSP_LBN 3 2154#define FRF_AB_MD_PRSP_WIDTH 1 2155#define FRF_AB_MD_RIC_LBN 2 2156#define FRF_AB_MD_RIC_WIDTH 1 2157#define FRF_AB_MD_RDC_LBN 1 2158#define FRF_AB_MD_RDC_WIDTH 1 2159#define FRF_AB_MD_WRC_LBN 0 2160#define FRF_AB_MD_WRC_WIDTH 1 2161 2162 2163/* 2164 * FR_AB_MD_PHY_ADR_REG(128bit): 2165 * PHY management PHY address register 2166 */ 2167#define FR_AB_MD_PHY_ADR_REG_OFST 0x00000c30 2168/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2169 2170#define FRF_AB_MD_PHY_ADR_LBN 0 2171#define FRF_AB_MD_PHY_ADR_WIDTH 16 2172 2173 2174/* 2175 * FR_AB_MD_ID_REG(128bit): 2176 * PHY management ID register 2177 */ 2178#define FR_AB_MD_ID_REG_OFST 0x00000c40 2179/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2180 2181#define FRF_AB_MD_PRT_ADR_LBN 11 2182#define FRF_AB_MD_PRT_ADR_WIDTH 5 2183#define FRF_AB_MD_DEV_ADR_LBN 6 2184#define FRF_AB_MD_DEV_ADR_WIDTH 5 2185 2186 2187/* 2188 * FR_AB_MD_STAT_REG(128bit): 2189 * PHY management status & mask register 2190 */ 2191#define FR_AB_MD_STAT_REG_OFST 0x00000c50 2192/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2193 2194#define FRF_AB_MD_PINT_LBN 4 2195#define FRF_AB_MD_PINT_WIDTH 1 2196#define FRF_AB_MD_DONE_LBN 3 2197#define FRF_AB_MD_DONE_WIDTH 1 2198#define FRF_AB_MD_BSERR_LBN 2 2199#define FRF_AB_MD_BSERR_WIDTH 1 2200#define FRF_AB_MD_LNFL_LBN 1 2201#define FRF_AB_MD_LNFL_WIDTH 1 2202#define FRF_AB_MD_BSY_LBN 0 2203#define FRF_AB_MD_BSY_WIDTH 1 2204 2205 2206/* 2207 * FR_AB_MAC_STAT_DMA_REG(128bit): 2208 * Port MAC statistical counter DMA register 2209 */ 2210#define FR_AB_MAC_STAT_DMA_REG_OFST 0x00000c60 2211/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2212 2213#define FRF_AB_MAC_STAT_DMA_CMD_LBN 48 2214#define FRF_AB_MAC_STAT_DMA_CMD_WIDTH 1 2215#define FRF_AB_MAC_STAT_DMA_ADR_LBN 0 2216#define FRF_AB_MAC_STAT_DMA_ADR_WIDTH 48 2217#define FRF_AB_MAC_STAT_DMA_ADR_DW0_LBN 0 2218#define FRF_AB_MAC_STAT_DMA_ADR_DW0_WIDTH 32 2219#define FRF_AB_MAC_STAT_DMA_ADR_DW1_LBN 32 2220#define FRF_AB_MAC_STAT_DMA_ADR_DW1_WIDTH 16 2221 2222 2223/* 2224 * FR_AB_MAC_CTRL_REG(128bit): 2225 * Port MAC control register 2226 */ 2227#define FR_AB_MAC_CTRL_REG_OFST 0x00000c80 2228/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2229 2230#define FRF_AB_MAC_XOFF_VAL_LBN 16 2231#define FRF_AB_MAC_XOFF_VAL_WIDTH 16 2232#define FRF_BB_TXFIFO_DRAIN_EN_LBN 7 2233#define FRF_BB_TXFIFO_DRAIN_EN_WIDTH 1 2234#define FRF_AB_MAC_XG_DISTXCRC_LBN 5 2235#define FRF_AB_MAC_XG_DISTXCRC_WIDTH 1 2236#define FRF_AB_MAC_BCAD_ACPT_LBN 4 2237#define FRF_AB_MAC_BCAD_ACPT_WIDTH 1 2238#define FRF_AB_MAC_UC_PROM_LBN 3 2239#define FRF_AB_MAC_UC_PROM_WIDTH 1 2240#define FRF_AB_MAC_LINK_STATUS_LBN 2 2241#define FRF_AB_MAC_LINK_STATUS_WIDTH 1 2242#define FRF_AB_MAC_SPEED_LBN 0 2243#define FRF_AB_MAC_SPEED_WIDTH 2 2244#define FRF_AB_MAC_SPEED_10M 0 2245#define FRF_AB_MAC_SPEED_100M 1 2246#define FRF_AB_MAC_SPEED_1G 2 2247#define FRF_AB_MAC_SPEED_10G 3 2248 2249/* 2250 * FR_BB_GEN_MODE_REG(128bit): 2251 * General Purpose mode register (external interrupt mask) 2252 */ 2253#define FR_BB_GEN_MODE_REG_OFST 0x00000c90 2254/* falconb0=net_func_bar2 */ 2255 2256#define FRF_BB_XFP_PHY_INT_POL_SEL_LBN 3 2257#define FRF_BB_XFP_PHY_INT_POL_SEL_WIDTH 1 2258#define FRF_BB_XG_PHY_INT_POL_SEL_LBN 2 2259#define FRF_BB_XG_PHY_INT_POL_SEL_WIDTH 1 2260#define FRF_BB_XFP_PHY_INT_MASK_LBN 1 2261#define FRF_BB_XFP_PHY_INT_MASK_WIDTH 1 2262#define FRF_BB_XG_PHY_INT_MASK_LBN 0 2263#define FRF_BB_XG_PHY_INT_MASK_WIDTH 1 2264 2265 2266/* 2267 * FR_AB_MAC_MC_HASH_REG0(128bit): 2268 * Multicast address hash table 2269 */ 2270#define FR_AB_MAC_MC_HASH0_REG_OFST 0x00000ca0 2271/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2272 2273#define FRF_AB_MAC_MCAST_HASH0_LBN 0 2274#define FRF_AB_MAC_MCAST_HASH0_WIDTH 128 2275#define FRF_AB_MAC_MCAST_HASH0_DW0_LBN 0 2276#define FRF_AB_MAC_MCAST_HASH0_DW0_WIDTH 32 2277#define FRF_AB_MAC_MCAST_HASH0_DW1_LBN 32 2278#define FRF_AB_MAC_MCAST_HASH0_DW1_WIDTH 32 2279#define FRF_AB_MAC_MCAST_HASH0_DW2_LBN 64 2280#define FRF_AB_MAC_MCAST_HASH0_DW2_WIDTH 32 2281#define FRF_AB_MAC_MCAST_HASH0_DW3_LBN 96 2282#define FRF_AB_MAC_MCAST_HASH0_DW3_WIDTH 32 2283 2284 2285/* 2286 * FR_AB_MAC_MC_HASH_REG1(128bit): 2287 * Multicast address hash table 2288 */ 2289#define FR_AB_MAC_MC_HASH1_REG_OFST 0x00000cb0 2290/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2291 2292#define FRF_AB_MAC_MCAST_HASH1_LBN 0 2293#define FRF_AB_MAC_MCAST_HASH1_WIDTH 128 2294#define FRF_AB_MAC_MCAST_HASH1_DW0_LBN 0 2295#define FRF_AB_MAC_MCAST_HASH1_DW0_WIDTH 32 2296#define FRF_AB_MAC_MCAST_HASH1_DW1_LBN 32 2297#define FRF_AB_MAC_MCAST_HASH1_DW1_WIDTH 32 2298#define FRF_AB_MAC_MCAST_HASH1_DW2_LBN 64 2299#define FRF_AB_MAC_MCAST_HASH1_DW2_WIDTH 32 2300#define FRF_AB_MAC_MCAST_HASH1_DW3_LBN 96 2301#define FRF_AB_MAC_MCAST_HASH1_DW3_WIDTH 32 2302 2303 2304/* 2305 * FR_AB_GM_CFG1_REG(32bit): 2306 * GMAC configuration register 1 2307 */ 2308#define FR_AB_GM_CFG1_REG_OFST 0x00000e00 2309/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2310 2311#define FRF_AB_GM_SW_RST_LBN 31 2312#define FRF_AB_GM_SW_RST_WIDTH 1 2313#define FRF_AB_GM_SIM_RST_LBN 30 2314#define FRF_AB_GM_SIM_RST_WIDTH 1 2315#define FRF_AB_GM_RST_RX_MAC_CTL_LBN 19 2316#define FRF_AB_GM_RST_RX_MAC_CTL_WIDTH 1 2317#define FRF_AB_GM_RST_TX_MAC_CTL_LBN 18 2318#define FRF_AB_GM_RST_TX_MAC_CTL_WIDTH 1 2319#define FRF_AB_GM_RST_RX_FUNC_LBN 17 2320#define FRF_AB_GM_RST_RX_FUNC_WIDTH 1 2321#define FRF_AB_GM_RST_TX_FUNC_LBN 16 2322#define FRF_AB_GM_RST_TX_FUNC_WIDTH 1 2323#define FRF_AB_GM_LOOP_LBN 8 2324#define FRF_AB_GM_LOOP_WIDTH 1 2325#define FRF_AB_GM_RX_FC_EN_LBN 5 2326#define FRF_AB_GM_RX_FC_EN_WIDTH 1 2327#define FRF_AB_GM_TX_FC_EN_LBN 4 2328#define FRF_AB_GM_TX_FC_EN_WIDTH 1 2329#define FRF_AB_GM_SYNC_RXEN_LBN 3 2330#define FRF_AB_GM_SYNC_RXEN_WIDTH 1 2331#define FRF_AB_GM_RX_EN_LBN 2 2332#define FRF_AB_GM_RX_EN_WIDTH 1 2333#define FRF_AB_GM_SYNC_TXEN_LBN 1 2334#define FRF_AB_GM_SYNC_TXEN_WIDTH 1 2335#define FRF_AB_GM_TX_EN_LBN 0 2336#define FRF_AB_GM_TX_EN_WIDTH 1 2337 2338 2339/* 2340 * FR_AB_GM_CFG2_REG(32bit): 2341 * GMAC configuration register 2 2342 */ 2343#define FR_AB_GM_CFG2_REG_OFST 0x00000e10 2344/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2345 2346#define FRF_AB_GM_PAMBL_LEN_LBN 12 2347#define FRF_AB_GM_PAMBL_LEN_WIDTH 4 2348#define FRF_AB_GM_IF_MODE_LBN 8 2349#define FRF_AB_GM_IF_MODE_WIDTH 2 2350#define FRF_AB_GM_IF_MODE_BYTE_MODE 2 2351#define FRF_AB_GM_IF_MODE_NIBBLE_MODE 1 2352#define FRF_AB_GM_HUGE_FRM_EN_LBN 5 2353#define FRF_AB_GM_HUGE_FRM_EN_WIDTH 1 2354#define FRF_AB_GM_LEN_CHK_LBN 4 2355#define FRF_AB_GM_LEN_CHK_WIDTH 1 2356#define FRF_AB_GM_PAD_CRC_EN_LBN 2 2357#define FRF_AB_GM_PAD_CRC_EN_WIDTH 1 2358#define FRF_AB_GM_CRC_EN_LBN 1 2359#define FRF_AB_GM_CRC_EN_WIDTH 1 2360#define FRF_AB_GM_FD_LBN 0 2361#define FRF_AB_GM_FD_WIDTH 1 2362 2363 2364/* 2365 * FR_AB_GM_IPG_REG(32bit): 2366 * GMAC IPG register 2367 */ 2368#define FR_AB_GM_IPG_REG_OFST 0x00000e20 2369/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2370 2371#define FRF_AB_GM_NONB2B_IPG1_LBN 24 2372#define FRF_AB_GM_NONB2B_IPG1_WIDTH 7 2373#define FRF_AB_GM_NONB2B_IPG2_LBN 16 2374#define FRF_AB_GM_NONB2B_IPG2_WIDTH 7 2375#define FRF_AB_GM_MIN_IPG_ENF_LBN 8 2376#define FRF_AB_GM_MIN_IPG_ENF_WIDTH 8 2377#define FRF_AB_GM_B2B_IPG_LBN 0 2378#define FRF_AB_GM_B2B_IPG_WIDTH 7 2379 2380 2381/* 2382 * FR_AB_GM_HD_REG(32bit): 2383 * GMAC half duplex register 2384 */ 2385#define FR_AB_GM_HD_REG_OFST 0x00000e30 2386/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2387 2388#define FRF_AB_GM_ALT_BOFF_VAL_LBN 20 2389#define FRF_AB_GM_ALT_BOFF_VAL_WIDTH 4 2390#define FRF_AB_GM_ALT_BOFF_EN_LBN 19 2391#define FRF_AB_GM_ALT_BOFF_EN_WIDTH 1 2392#define FRF_AB_GM_BP_NO_BOFF_LBN 18 2393#define FRF_AB_GM_BP_NO_BOFF_WIDTH 1 2394#define FRF_AB_GM_DIS_BOFF_LBN 17 2395#define FRF_AB_GM_DIS_BOFF_WIDTH 1 2396#define FRF_AB_GM_EXDEF_TX_EN_LBN 16 2397#define FRF_AB_GM_EXDEF_TX_EN_WIDTH 1 2398#define FRF_AB_GM_RTRY_LIMIT_LBN 12 2399#define FRF_AB_GM_RTRY_LIMIT_WIDTH 4 2400#define FRF_AB_GM_COL_WIN_LBN 0 2401#define FRF_AB_GM_COL_WIN_WIDTH 10 2402 2403 2404/* 2405 * FR_AB_GM_MAX_FLEN_REG(32bit): 2406 * GMAC maximum frame length register 2407 */ 2408#define FR_AB_GM_MAX_FLEN_REG_OFST 0x00000e40 2409/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2410 2411#define FRF_AB_GM_MAX_FLEN_LBN 0 2412#define FRF_AB_GM_MAX_FLEN_WIDTH 16 2413 2414 2415/* 2416 * FR_AB_GM_TEST_REG(32bit): 2417 * GMAC test register 2418 */ 2419#define FR_AB_GM_TEST_REG_OFST 0x00000e70 2420/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2421 2422#define FRF_AB_GM_MAX_BOFF_LBN 3 2423#define FRF_AB_GM_MAX_BOFF_WIDTH 1 2424#define FRF_AB_GM_REG_TX_FLOW_EN_LBN 2 2425#define FRF_AB_GM_REG_TX_FLOW_EN_WIDTH 1 2426#define FRF_AB_GM_TEST_PAUSE_LBN 1 2427#define FRF_AB_GM_TEST_PAUSE_WIDTH 1 2428#define FRF_AB_GM_SHORT_SLOT_LBN 0 2429#define FRF_AB_GM_SHORT_SLOT_WIDTH 1 2430 2431 2432/* 2433 * FR_AB_GM_ADR1_REG(32bit): 2434 * GMAC station address register 1 2435 */ 2436#define FR_AB_GM_ADR1_REG_OFST 0x00000f00 2437/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2438 2439#define FRF_AB_GM_ADR_B0_LBN 24 2440#define FRF_AB_GM_ADR_B0_WIDTH 8 2441#define FRF_AB_GM_ADR_B1_LBN 16 2442#define FRF_AB_GM_ADR_B1_WIDTH 8 2443#define FRF_AB_GM_ADR_B2_LBN 8 2444#define FRF_AB_GM_ADR_B2_WIDTH 8 2445#define FRF_AB_GM_ADR_B3_LBN 0 2446#define FRF_AB_GM_ADR_B3_WIDTH 8 2447 2448 2449/* 2450 * FR_AB_GM_ADR2_REG(32bit): 2451 * GMAC station address register 2 2452 */ 2453#define FR_AB_GM_ADR2_REG_OFST 0x00000f10 2454/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2455 2456#define FRF_AB_GM_ADR_B4_LBN 24 2457#define FRF_AB_GM_ADR_B4_WIDTH 8 2458#define FRF_AB_GM_ADR_B5_LBN 16 2459#define FRF_AB_GM_ADR_B5_WIDTH 8 2460 2461 2462/* 2463 * FR_AB_GMF_CFG0_REG(32bit): 2464 * GMAC FIFO configuration register 0 2465 */ 2466#define FR_AB_GMF_CFG0_REG_OFST 0x00000f20 2467/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2468 2469#define FRF_AB_GMF_FTFENRPLY_LBN 20 2470#define FRF_AB_GMF_FTFENRPLY_WIDTH 1 2471#define FRF_AB_GMF_STFENRPLY_LBN 19 2472#define FRF_AB_GMF_STFENRPLY_WIDTH 1 2473#define FRF_AB_GMF_FRFENRPLY_LBN 18 2474#define FRF_AB_GMF_FRFENRPLY_WIDTH 1 2475#define FRF_AB_GMF_SRFENRPLY_LBN 17 2476#define FRF_AB_GMF_SRFENRPLY_WIDTH 1 2477#define FRF_AB_GMF_WTMENRPLY_LBN 16 2478#define FRF_AB_GMF_WTMENRPLY_WIDTH 1 2479#define FRF_AB_GMF_FTFENREQ_LBN 12 2480#define FRF_AB_GMF_FTFENREQ_WIDTH 1 2481#define FRF_AB_GMF_STFENREQ_LBN 11 2482#define FRF_AB_GMF_STFENREQ_WIDTH 1 2483#define FRF_AB_GMF_FRFENREQ_LBN 10 2484#define FRF_AB_GMF_FRFENREQ_WIDTH 1 2485#define FRF_AB_GMF_SRFENREQ_LBN 9 2486#define FRF_AB_GMF_SRFENREQ_WIDTH 1 2487#define FRF_AB_GMF_WTMENREQ_LBN 8 2488#define FRF_AB_GMF_WTMENREQ_WIDTH 1 2489#define FRF_AB_GMF_HSTRSTFT_LBN 4 2490#define FRF_AB_GMF_HSTRSTFT_WIDTH 1 2491#define FRF_AB_GMF_HSTRSTST_LBN 3 2492#define FRF_AB_GMF_HSTRSTST_WIDTH 1 2493#define FRF_AB_GMF_HSTRSTFR_LBN 2 2494#define FRF_AB_GMF_HSTRSTFR_WIDTH 1 2495#define FRF_AB_GMF_HSTRSTSR_LBN 1 2496#define FRF_AB_GMF_HSTRSTSR_WIDTH 1 2497#define FRF_AB_GMF_HSTRSTWT_LBN 0 2498#define FRF_AB_GMF_HSTRSTWT_WIDTH 1 2499 2500 2501/* 2502 * FR_AB_GMF_CFG1_REG(32bit): 2503 * GMAC FIFO configuration register 1 2504 */ 2505#define FR_AB_GMF_CFG1_REG_OFST 0x00000f30 2506/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2507 2508#define FRF_AB_GMF_CFGFRTH_LBN 16 2509#define FRF_AB_GMF_CFGFRTH_WIDTH 5 2510#define FRF_AB_GMF_CFGXOFFRTX_LBN 0 2511#define FRF_AB_GMF_CFGXOFFRTX_WIDTH 16 2512 2513 2514/* 2515 * FR_AB_GMF_CFG2_REG(32bit): 2516 * GMAC FIFO configuration register 2 2517 */ 2518#define FR_AB_GMF_CFG2_REG_OFST 0x00000f40 2519/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2520 2521#define FRF_AB_GMF_CFGHWM_LBN 16 2522#define FRF_AB_GMF_CFGHWM_WIDTH 6 2523#define FRF_AB_GMF_CFGLWM_LBN 0 2524#define FRF_AB_GMF_CFGLWM_WIDTH 6 2525 2526 2527/* 2528 * FR_AB_GMF_CFG3_REG(32bit): 2529 * GMAC FIFO configuration register 3 2530 */ 2531#define FR_AB_GMF_CFG3_REG_OFST 0x00000f50 2532/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2533 2534#define FRF_AB_GMF_CFGHWMFT_LBN 16 2535#define FRF_AB_GMF_CFGHWMFT_WIDTH 6 2536#define FRF_AB_GMF_CFGFTTH_LBN 0 2537#define FRF_AB_GMF_CFGFTTH_WIDTH 6 2538 2539 2540/* 2541 * FR_AB_GMF_CFG4_REG(32bit): 2542 * GMAC FIFO configuration register 4 2543 */ 2544#define FR_AB_GMF_CFG4_REG_OFST 0x00000f60 2545/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2546 2547#define FRF_AB_GMF_HSTFLTRFRM_LBN 0 2548#define FRF_AB_GMF_HSTFLTRFRM_WIDTH 18 2549 2550 2551/* 2552 * FR_AB_GMF_CFG5_REG(32bit): 2553 * GMAC FIFO configuration register 5 2554 */ 2555#define FR_AB_GMF_CFG5_REG_OFST 0x00000f70 2556/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2557 2558#define FRF_AB_GMF_CFGHDPLX_LBN 22 2559#define FRF_AB_GMF_CFGHDPLX_WIDTH 1 2560#define FRF_AB_GMF_SRFULL_LBN 21 2561#define FRF_AB_GMF_SRFULL_WIDTH 1 2562#define FRF_AB_GMF_HSTSRFULLCLR_LBN 20 2563#define FRF_AB_GMF_HSTSRFULLCLR_WIDTH 1 2564#define FRF_AB_GMF_CFGBYTMODE_LBN 19 2565#define FRF_AB_GMF_CFGBYTMODE_WIDTH 1 2566#define FRF_AB_GMF_HSTDRPLT64_LBN 18 2567#define FRF_AB_GMF_HSTDRPLT64_WIDTH 1 2568#define FRF_AB_GMF_HSTFLTRFRMDC_LBN 0 2569#define FRF_AB_GMF_HSTFLTRFRMDC_WIDTH 18 2570 2571 2572/* 2573 * FR_BB_TX_SRC_MAC_TBL(128bit): 2574 * Transmit IP source address filter table 2575 */ 2576#define FR_BB_TX_SRC_MAC_TBL_OFST 0x00001000 2577/* falconb0=net_func_bar2 */ 2578#define FR_BB_TX_SRC_MAC_TBL_STEP 16 2579#define FR_BB_TX_SRC_MAC_TBL_ROWS 16 2580 2581#define FRF_BB_TX_SRC_MAC_ADR_1_LBN 64 2582#define FRF_BB_TX_SRC_MAC_ADR_1_WIDTH 48 2583#define FRF_BB_TX_SRC_MAC_ADR_1_DW0_LBN 64 2584#define FRF_BB_TX_SRC_MAC_ADR_1_DW0_WIDTH 32 2585#define FRF_BB_TX_SRC_MAC_ADR_1_DW1_LBN 96 2586#define FRF_BB_TX_SRC_MAC_ADR_1_DW1_WIDTH 16 2587#define FRF_BB_TX_SRC_MAC_ADR_0_LBN 0 2588#define FRF_BB_TX_SRC_MAC_ADR_0_WIDTH 48 2589#define FRF_BB_TX_SRC_MAC_ADR_0_DW0_LBN 0 2590#define FRF_BB_TX_SRC_MAC_ADR_0_DW0_WIDTH 32 2591#define FRF_BB_TX_SRC_MAC_ADR_0_DW1_LBN 32 2592#define FRF_BB_TX_SRC_MAC_ADR_0_DW1_WIDTH 16 2593 2594 2595/* 2596 * FR_BB_TX_SRC_MAC_CTL_REG(128bit): 2597 * Transmit MAC source address filter control 2598 */ 2599#define FR_BB_TX_SRC_MAC_CTL_REG_OFST 0x00001100 2600/* falconb0=net_func_bar2 */ 2601 2602#define FRF_BB_TX_SRC_DROP_CTR_LBN 16 2603#define FRF_BB_TX_SRC_DROP_CTR_WIDTH 16 2604#define FRF_BB_TX_SRC_FLTR_EN_LBN 15 2605#define FRF_BB_TX_SRC_FLTR_EN_WIDTH 1 2606#define FRF_BB_TX_DROP_CTR_CLR_LBN 12 2607#define FRF_BB_TX_DROP_CTR_CLR_WIDTH 1 2608#define FRF_BB_TX_MAC_QID_SEL_LBN 0 2609#define FRF_BB_TX_MAC_QID_SEL_WIDTH 3 2610 2611 2612/* 2613 * FR_AB_XM_ADR_LO_REG(128bit): 2614 * XGMAC address register low 2615 */ 2616#define FR_AB_XM_ADR_LO_REG_OFST 0x00001200 2617/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2618 2619#define FRF_AB_XM_ADR_LO_LBN 0 2620#define FRF_AB_XM_ADR_LO_WIDTH 32 2621 2622 2623/* 2624 * FR_AB_XM_ADR_HI_REG(128bit): 2625 * XGMAC address register high 2626 */ 2627#define FR_AB_XM_ADR_HI_REG_OFST 0x00001210 2628/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2629 2630#define FRF_AB_XM_ADR_HI_LBN 0 2631#define FRF_AB_XM_ADR_HI_WIDTH 16 2632 2633 2634/* 2635 * FR_AB_XM_GLB_CFG_REG(128bit): 2636 * XGMAC global configuration 2637 */ 2638#define FR_AB_XM_GLB_CFG_REG_OFST 0x00001220 2639/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2640 2641#define FRF_AB_XM_RMTFLT_GEN_LBN 17 2642#define FRF_AB_XM_RMTFLT_GEN_WIDTH 1 2643#define FRF_AB_XM_DEBUG_MODE_LBN 16 2644#define FRF_AB_XM_DEBUG_MODE_WIDTH 1 2645#define FRF_AB_XM_RX_STAT_EN_LBN 11 2646#define FRF_AB_XM_RX_STAT_EN_WIDTH 1 2647#define FRF_AB_XM_TX_STAT_EN_LBN 10 2648#define FRF_AB_XM_TX_STAT_EN_WIDTH 1 2649#define FRF_AB_XM_RX_JUMBO_MODE_LBN 6 2650#define FRF_AB_XM_RX_JUMBO_MODE_WIDTH 1 2651#define FRF_AB_XM_WAN_MODE_LBN 5 2652#define FRF_AB_XM_WAN_MODE_WIDTH 1 2653#define FRF_AB_XM_INTCLR_MODE_LBN 3 2654#define FRF_AB_XM_INTCLR_MODE_WIDTH 1 2655#define FRF_AB_XM_CORE_RST_LBN 0 2656#define FRF_AB_XM_CORE_RST_WIDTH 1 2657 2658 2659/* 2660 * FR_AB_XM_TX_CFG_REG(128bit): 2661 * XGMAC transmit configuration 2662 */ 2663#define FR_AB_XM_TX_CFG_REG_OFST 0x00001230 2664/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2665 2666#define FRF_AB_XM_TX_PROG_LBN 24 2667#define FRF_AB_XM_TX_PROG_WIDTH 1 2668#define FRF_AB_XM_IPG_LBN 16 2669#define FRF_AB_XM_IPG_WIDTH 4 2670#define FRF_AB_XM_FCNTL_LBN 10 2671#define FRF_AB_XM_FCNTL_WIDTH 1 2672#define FRF_AB_XM_TXCRC_LBN 8 2673#define FRF_AB_XM_TXCRC_WIDTH 1 2674#define FRF_AB_XM_EDRC_LBN 6 2675#define FRF_AB_XM_EDRC_WIDTH 1 2676#define FRF_AB_XM_AUTO_PAD_LBN 5 2677#define FRF_AB_XM_AUTO_PAD_WIDTH 1 2678#define FRF_AB_XM_TX_PRMBL_LBN 2 2679#define FRF_AB_XM_TX_PRMBL_WIDTH 1 2680#define FRF_AB_XM_TXEN_LBN 1 2681#define FRF_AB_XM_TXEN_WIDTH 1 2682#define FRF_AB_XM_TX_RST_LBN 0 2683#define FRF_AB_XM_TX_RST_WIDTH 1 2684 2685 2686/* 2687 * FR_AB_XM_RX_CFG_REG(128bit): 2688 * XGMAC receive configuration 2689 */ 2690#define FR_AB_XM_RX_CFG_REG_OFST 0x00001240 2691/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2692 2693#define FRF_AB_XM_PASS_LENERR_LBN 26 2694#define FRF_AB_XM_PASS_LENERR_WIDTH 1 2695#define FRF_AB_XM_PASS_CRC_ERR_LBN 25 2696#define FRF_AB_XM_PASS_CRC_ERR_WIDTH 1 2697#define FRF_AB_XM_PASS_PRMBLE_ERR_LBN 24 2698#define FRF_AB_XM_PASS_PRMBLE_ERR_WIDTH 1 2699#define FRF_AB_XM_REJ_BCAST_LBN 20 2700#define FRF_AB_XM_REJ_BCAST_WIDTH 1 2701#define FRF_AB_XM_ACPT_ALL_MCAST_LBN 11 2702#define FRF_AB_XM_ACPT_ALL_MCAST_WIDTH 1 2703#define FRF_AB_XM_ACPT_ALL_UCAST_LBN 9 2704#define FRF_AB_XM_ACPT_ALL_UCAST_WIDTH 1 2705#define FRF_AB_XM_AUTO_DEPAD_LBN 8 2706#define FRF_AB_XM_AUTO_DEPAD_WIDTH 1 2707#define FRF_AB_XM_RXCRC_LBN 3 2708#define FRF_AB_XM_RXCRC_WIDTH 1 2709#define FRF_AB_XM_RX_PRMBL_LBN 2 2710#define FRF_AB_XM_RX_PRMBL_WIDTH 1 2711#define FRF_AB_XM_RXEN_LBN 1 2712#define FRF_AB_XM_RXEN_WIDTH 1 2713#define FRF_AB_XM_RX_RST_LBN 0 2714#define FRF_AB_XM_RX_RST_WIDTH 1 2715 2716 2717/* 2718 * FR_AB_XM_MGT_INT_MASK(128bit): 2719 * documentation to be written for sum_XM_MGT_INT_MASK 2720 */ 2721#define FR_AB_XM_MGT_INT_MASK_OFST 0x00001250 2722/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2723 2724#define FRF_AB_XM_MSK_STA_INTR_LBN 16 2725#define FRF_AB_XM_MSK_STA_INTR_WIDTH 1 2726#define FRF_AB_XM_MSK_STAT_CNTR_HF_LBN 9 2727#define FRF_AB_XM_MSK_STAT_CNTR_HF_WIDTH 1 2728#define FRF_AB_XM_MSK_STAT_CNTR_OF_LBN 8 2729#define FRF_AB_XM_MSK_STAT_CNTR_OF_WIDTH 1 2730#define FRF_AB_XM_MSK_PRMBLE_ERR_LBN 2 2731#define FRF_AB_XM_MSK_PRMBLE_ERR_WIDTH 1 2732#define FRF_AB_XM_MSK_RMTFLT_LBN 1 2733#define FRF_AB_XM_MSK_RMTFLT_WIDTH 1 2734#define FRF_AB_XM_MSK_LCLFLT_LBN 0 2735#define FRF_AB_XM_MSK_LCLFLT_WIDTH 1 2736 2737 2738/* 2739 * FR_AB_XM_FC_REG(128bit): 2740 * XGMAC flow control register 2741 */ 2742#define FR_AB_XM_FC_REG_OFST 0x00001270 2743/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2744 2745#define FRF_AB_XM_PAUSE_TIME_LBN 16 2746#define FRF_AB_XM_PAUSE_TIME_WIDTH 16 2747#define FRF_AB_XM_RX_MAC_STAT_LBN 11 2748#define FRF_AB_XM_RX_MAC_STAT_WIDTH 1 2749#define FRF_AB_XM_TX_MAC_STAT_LBN 10 2750#define FRF_AB_XM_TX_MAC_STAT_WIDTH 1 2751#define FRF_AB_XM_MCNTL_PASS_LBN 8 2752#define FRF_AB_XM_MCNTL_PASS_WIDTH 2 2753#define FRF_AB_XM_REJ_CNTL_UCAST_LBN 6 2754#define FRF_AB_XM_REJ_CNTL_UCAST_WIDTH 1 2755#define FRF_AB_XM_REJ_CNTL_MCAST_LBN 5 2756#define FRF_AB_XM_REJ_CNTL_MCAST_WIDTH 1 2757#define FRF_AB_XM_ZPAUSE_LBN 2 2758#define FRF_AB_XM_ZPAUSE_WIDTH 1 2759#define FRF_AB_XM_XMIT_PAUSE_LBN 1 2760#define FRF_AB_XM_XMIT_PAUSE_WIDTH 1 2761#define FRF_AB_XM_DIS_FCNTL_LBN 0 2762#define FRF_AB_XM_DIS_FCNTL_WIDTH 1 2763 2764 2765/* 2766 * FR_AB_XM_PAUSE_TIME_REG(128bit): 2767 * XGMAC pause time register 2768 */ 2769#define FR_AB_XM_PAUSE_TIME_REG_OFST 0x00001290 2770/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2771 2772#define FRF_AB_XM_TX_PAUSE_CNT_LBN 16 2773#define FRF_AB_XM_TX_PAUSE_CNT_WIDTH 16 2774#define FRF_AB_XM_RX_PAUSE_CNT_LBN 0 2775#define FRF_AB_XM_RX_PAUSE_CNT_WIDTH 16 2776 2777 2778/* 2779 * FR_AB_XM_TX_PARAM_REG(128bit): 2780 * XGMAC transmit parameter register 2781 */ 2782#define FR_AB_XM_TX_PARAM_REG_OFST 0x000012d0 2783/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2784 2785#define FRF_AB_XM_TX_JUMBO_MODE_LBN 31 2786#define FRF_AB_XM_TX_JUMBO_MODE_WIDTH 1 2787#define FRF_AB_XM_MAX_TX_FRM_SIZE_HI_LBN 19 2788#define FRF_AB_XM_MAX_TX_FRM_SIZE_HI_WIDTH 11 2789#define FRF_AB_XM_MAX_TX_FRM_SIZE_LO_LBN 16 2790#define FRF_AB_XM_MAX_TX_FRM_SIZE_LO_WIDTH 3 2791#define FRF_AB_XM_PAD_CHAR_LBN 0 2792#define FRF_AB_XM_PAD_CHAR_WIDTH 8 2793 2794 2795/* 2796 * FR_AB_XM_RX_PARAM_REG(128bit): 2797 * XGMAC receive parameter register 2798 */ 2799#define FR_AB_XM_RX_PARAM_REG_OFST 0x000012e0 2800/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2801 2802#define FRF_AB_XM_MAX_RX_FRM_SIZE_HI_LBN 3 2803#define FRF_AB_XM_MAX_RX_FRM_SIZE_HI_WIDTH 11 2804#define FRF_AB_XM_MAX_RX_FRM_SIZE_LO_LBN 0 2805#define FRF_AB_XM_MAX_RX_FRM_SIZE_LO_WIDTH 3 2806 2807 2808/* 2809 * FR_AB_XM_MGT_INT_MSK_REG(128bit): 2810 * XGMAC management interrupt mask register 2811 */ 2812#define FR_AB_XM_MGT_INT_REG_OFST 0x000012f0 2813/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2814 2815#define FRF_AB_XM_STAT_CNTR_OF_LBN 9 2816#define FRF_AB_XM_STAT_CNTR_OF_WIDTH 1 2817#define FRF_AB_XM_STAT_CNTR_HF_LBN 8 2818#define FRF_AB_XM_STAT_CNTR_HF_WIDTH 1 2819#define FRF_AB_XM_PRMBLE_ERR_LBN 2 2820#define FRF_AB_XM_PRMBLE_ERR_WIDTH 1 2821#define FRF_AB_XM_RMTFLT_LBN 1 2822#define FRF_AB_XM_RMTFLT_WIDTH 1 2823#define FRF_AB_XM_LCLFLT_LBN 0 2824#define FRF_AB_XM_LCLFLT_WIDTH 1 2825 2826 2827/* 2828 * FR_AB_XX_PWR_RST_REG(128bit): 2829 * XGXS/XAUI powerdown/reset register 2830 */ 2831#define FR_AB_XX_PWR_RST_REG_OFST 0x00001300 2832/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2833 2834#define FRF_AB_XX_PWRDND_SIG_LBN 31 2835#define FRF_AB_XX_PWRDND_SIG_WIDTH 1 2836#define FRF_AB_XX_PWRDNC_SIG_LBN 30 2837#define FRF_AB_XX_PWRDNC_SIG_WIDTH 1 2838#define FRF_AB_XX_PWRDNB_SIG_LBN 29 2839#define FRF_AB_XX_PWRDNB_SIG_WIDTH 1 2840#define FRF_AB_XX_PWRDNA_SIG_LBN 28 2841#define FRF_AB_XX_PWRDNA_SIG_WIDTH 1 2842#define FRF_AB_XX_SIM_MODE_LBN 27 2843#define FRF_AB_XX_SIM_MODE_WIDTH 1 2844#define FRF_AB_XX_RSTPLLCD_SIG_LBN 25 2845#define FRF_AB_XX_RSTPLLCD_SIG_WIDTH 1 2846#define FRF_AB_XX_RSTPLLAB_SIG_LBN 24 2847#define FRF_AB_XX_RSTPLLAB_SIG_WIDTH 1 2848#define FRF_AB_XX_RESETD_SIG_LBN 23 2849#define FRF_AB_XX_RESETD_SIG_WIDTH 1 2850#define FRF_AB_XX_RESETC_SIG_LBN 22 2851#define FRF_AB_XX_RESETC_SIG_WIDTH 1 2852#define FRF_AB_XX_RESETB_SIG_LBN 21 2853#define FRF_AB_XX_RESETB_SIG_WIDTH 1 2854#define FRF_AB_XX_RESETA_SIG_LBN 20 2855#define FRF_AB_XX_RESETA_SIG_WIDTH 1 2856#define FRF_AB_XX_RSTXGXSRX_SIG_LBN 18 2857#define FRF_AB_XX_RSTXGXSRX_SIG_WIDTH 1 2858#define FRF_AB_XX_RSTXGXSTX_SIG_LBN 17 2859#define FRF_AB_XX_RSTXGXSTX_SIG_WIDTH 1 2860#define FRF_AB_XX_SD_RST_ACT_LBN 16 2861#define FRF_AB_XX_SD_RST_ACT_WIDTH 1 2862#define FRF_AB_XX_PWRDND_EN_LBN 15 2863#define FRF_AB_XX_PWRDND_EN_WIDTH 1 2864#define FRF_AB_XX_PWRDNC_EN_LBN 14 2865#define FRF_AB_XX_PWRDNC_EN_WIDTH 1 2866#define FRF_AB_XX_PWRDNB_EN_LBN 13 2867#define FRF_AB_XX_PWRDNB_EN_WIDTH 1 2868#define FRF_AB_XX_PWRDNA_EN_LBN 12 2869#define FRF_AB_XX_PWRDNA_EN_WIDTH 1 2870#define FRF_AB_XX_RSTPLLCD_EN_LBN 9 2871#define FRF_AB_XX_RSTPLLCD_EN_WIDTH 1 2872#define FRF_AB_XX_RSTPLLAB_EN_LBN 8 2873#define FRF_AB_XX_RSTPLLAB_EN_WIDTH 1 2874#define FRF_AB_XX_RESETD_EN_LBN 7 2875#define FRF_AB_XX_RESETD_EN_WIDTH 1 2876#define FRF_AB_XX_RESETC_EN_LBN 6 2877#define FRF_AB_XX_RESETC_EN_WIDTH 1 2878#define FRF_AB_XX_RESETB_EN_LBN 5 2879#define FRF_AB_XX_RESETB_EN_WIDTH 1 2880#define FRF_AB_XX_RESETA_EN_LBN 4 2881#define FRF_AB_XX_RESETA_EN_WIDTH 1 2882#define FRF_AB_XX_RSTXGXSRX_EN_LBN 2 2883#define FRF_AB_XX_RSTXGXSRX_EN_WIDTH 1 2884#define FRF_AB_XX_RSTXGXSTX_EN_LBN 1 2885#define FRF_AB_XX_RSTXGXSTX_EN_WIDTH 1 2886#define FRF_AB_XX_RST_XX_EN_LBN 0 2887#define FRF_AB_XX_RST_XX_EN_WIDTH 1 2888 2889 2890/* 2891 * FR_AB_XX_SD_CTL_REG(128bit): 2892 * XGXS/XAUI powerdown/reset control register 2893 */ 2894#define FR_AB_XX_SD_CTL_REG_OFST 0x00001310 2895/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2896 2897#define FRF_AB_XX_TERMADJ1_LBN 17 2898#define FRF_AB_XX_TERMADJ1_WIDTH 1 2899#define FRF_AB_XX_TERMADJ0_LBN 16 2900#define FRF_AB_XX_TERMADJ0_WIDTH 1 2901#define FRF_AB_XX_HIDRVD_LBN 15 2902#define FRF_AB_XX_HIDRVD_WIDTH 1 2903#define FRF_AB_XX_LODRVD_LBN 14 2904#define FRF_AB_XX_LODRVD_WIDTH 1 2905#define FRF_AB_XX_HIDRVC_LBN 13 2906#define FRF_AB_XX_HIDRVC_WIDTH 1 2907#define FRF_AB_XX_LODRVC_LBN 12 2908#define FRF_AB_XX_LODRVC_WIDTH 1 2909#define FRF_AB_XX_HIDRVB_LBN 11 2910#define FRF_AB_XX_HIDRVB_WIDTH 1 2911#define FRF_AB_XX_LODRVB_LBN 10 2912#define FRF_AB_XX_LODRVB_WIDTH 1 2913#define FRF_AB_XX_HIDRVA_LBN 9 2914#define FRF_AB_XX_HIDRVA_WIDTH 1 2915#define FRF_AB_XX_LODRVA_LBN 8 2916#define FRF_AB_XX_LODRVA_WIDTH 1 2917#define FRF_AB_XX_LPBKD_LBN 3 2918#define FRF_AB_XX_LPBKD_WIDTH 1 2919#define FRF_AB_XX_LPBKC_LBN 2 2920#define FRF_AB_XX_LPBKC_WIDTH 1 2921#define FRF_AB_XX_LPBKB_LBN 1 2922#define FRF_AB_XX_LPBKB_WIDTH 1 2923#define FRF_AB_XX_LPBKA_LBN 0 2924#define FRF_AB_XX_LPBKA_WIDTH 1 2925 2926 2927/* 2928 * FR_AB_XX_TXDRV_CTL_REG(128bit): 2929 * XAUI SerDes transmit drive control register 2930 */ 2931#define FR_AB_XX_TXDRV_CTL_REG_OFST 0x00001320 2932/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2933 2934#define FRF_AB_XX_DEQD_LBN 28 2935#define FRF_AB_XX_DEQD_WIDTH 4 2936#define FRF_AB_XX_DEQC_LBN 24 2937#define FRF_AB_XX_DEQC_WIDTH 4 2938#define FRF_AB_XX_DEQB_LBN 20 2939#define FRF_AB_XX_DEQB_WIDTH 4 2940#define FRF_AB_XX_DEQA_LBN 16 2941#define FRF_AB_XX_DEQA_WIDTH 4 2942#define FRF_AB_XX_DTXD_LBN 12 2943#define FRF_AB_XX_DTXD_WIDTH 4 2944#define FRF_AB_XX_DTXC_LBN 8 2945#define FRF_AB_XX_DTXC_WIDTH 4 2946#define FRF_AB_XX_DTXB_LBN 4 2947#define FRF_AB_XX_DTXB_WIDTH 4 2948#define FRF_AB_XX_DTXA_LBN 0 2949#define FRF_AB_XX_DTXA_WIDTH 4 2950 2951 2952/* 2953 * FR_AB_XX_PRBS_CTL_REG(128bit): 2954 * documentation to be written for sum_XX_PRBS_CTL_REG 2955 */ 2956#define FR_AB_XX_PRBS_CTL_REG_OFST 0x00001330 2957/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 2958 2959#define FRF_AB_XX_CH3_RX_PRBS_SEL_LBN 30 2960#define FRF_AB_XX_CH3_RX_PRBS_SEL_WIDTH 2 2961#define FRF_AB_XX_CH3_RX_PRBS_INV_LBN 29 2962#define FRF_AB_XX_CH3_RX_PRBS_INV_WIDTH 1 2963#define FRF_AB_XX_CH3_RX_PRBS_CHKEN_LBN 28 2964#define FRF_AB_XX_CH3_RX_PRBS_CHKEN_WIDTH 1 2965#define FRF_AB_XX_CH2_RX_PRBS_SEL_LBN 26 2966#define FRF_AB_XX_CH2_RX_PRBS_SEL_WIDTH 2 2967#define FRF_AB_XX_CH2_RX_PRBS_INV_LBN 25 2968#define FRF_AB_XX_CH2_RX_PRBS_INV_WIDTH 1 2969#define FRF_AB_XX_CH2_RX_PRBS_CHKEN_LBN 24 2970#define FRF_AB_XX_CH2_RX_PRBS_CHKEN_WIDTH 1 2971#define FRF_AB_XX_CH1_RX_PRBS_SEL_LBN 22 2972#define FRF_AB_XX_CH1_RX_PRBS_SEL_WIDTH 2 2973#define FRF_AB_XX_CH1_RX_PRBS_INV_LBN 21 2974#define FRF_AB_XX_CH1_RX_PRBS_INV_WIDTH 1 2975#define FRF_AB_XX_CH1_RX_PRBS_CHKEN_LBN 20 2976#define FRF_AB_XX_CH1_RX_PRBS_CHKEN_WIDTH 1 2977#define FRF_AB_XX_CH0_RX_PRBS_SEL_LBN 18 2978#define FRF_AB_XX_CH0_RX_PRBS_SEL_WIDTH 2 2979#define FRF_AB_XX_CH0_RX_PRBS_INV_LBN 17 2980#define FRF_AB_XX_CH0_RX_PRBS_INV_WIDTH 1 2981#define FRF_AB_XX_CH0_RX_PRBS_CHKEN_LBN 16 2982#define FRF_AB_XX_CH0_RX_PRBS_CHKEN_WIDTH 1 2983#define FRF_AB_XX_CH3_TX_PRBS_SEL_LBN 14 2984#define FRF_AB_XX_CH3_TX_PRBS_SEL_WIDTH 2 2985#define FRF_AB_XX_CH3_TX_PRBS_INV_LBN 13 2986#define FRF_AB_XX_CH3_TX_PRBS_INV_WIDTH 1 2987#define FRF_AB_XX_CH3_TX_PRBS_CHKEN_LBN 12 2988#define FRF_AB_XX_CH3_TX_PRBS_CHKEN_WIDTH 1 2989#define FRF_AB_XX_CH2_TX_PRBS_SEL_LBN 10 2990#define FRF_AB_XX_CH2_TX_PRBS_SEL_WIDTH 2 2991#define FRF_AB_XX_CH2_TX_PRBS_INV_LBN 9 2992#define FRF_AB_XX_CH2_TX_PRBS_INV_WIDTH 1 2993#define FRF_AB_XX_CH2_TX_PRBS_CHKEN_LBN 8 2994#define FRF_AB_XX_CH2_TX_PRBS_CHKEN_WIDTH 1 2995#define FRF_AB_XX_CH1_TX_PRBS_SEL_LBN 6 2996#define FRF_AB_XX_CH1_TX_PRBS_SEL_WIDTH 2 2997#define FRF_AB_XX_CH1_TX_PRBS_INV_LBN 5 2998#define FRF_AB_XX_CH1_TX_PRBS_INV_WIDTH 1 2999#define FRF_AB_XX_CH1_TX_PRBS_CHKEN_LBN 4 3000#define FRF_AB_XX_CH1_TX_PRBS_CHKEN_WIDTH 1 3001#define FRF_AB_XX_CH0_TX_PRBS_SEL_LBN 2 3002#define FRF_AB_XX_CH0_TX_PRBS_SEL_WIDTH 2 3003#define FRF_AB_XX_CH0_TX_PRBS_INV_LBN 1 3004#define FRF_AB_XX_CH0_TX_PRBS_INV_WIDTH 1 3005#define FRF_AB_XX_CH0_TX_PRBS_CHKEN_LBN 0 3006#define FRF_AB_XX_CH0_TX_PRBS_CHKEN_WIDTH 1 3007 3008 3009/* 3010 * FR_AB_XX_PRBS_CHK_REG(128bit): 3011 * documentation to be written for sum_XX_PRBS_CHK_REG 3012 */ 3013#define FR_AB_XX_PRBS_CHK_REG_OFST 0x00001340 3014/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3015 3016#define FRF_AB_XX_REV_LB_EN_LBN 16 3017#define FRF_AB_XX_REV_LB_EN_WIDTH 1 3018#define FRF_AB_XX_CH3_DEG_DET_LBN 15 3019#define FRF_AB_XX_CH3_DEG_DET_WIDTH 1 3020#define FRF_AB_XX_CH3_LFSR_LOCK_IND_LBN 14 3021#define FRF_AB_XX_CH3_LFSR_LOCK_IND_WIDTH 1 3022#define FRF_AB_XX_CH3_PRBS_FRUN_LBN 13 3023#define FRF_AB_XX_CH3_PRBS_FRUN_WIDTH 1 3024#define FRF_AB_XX_CH3_ERR_CHK_LBN 12 3025#define FRF_AB_XX_CH3_ERR_CHK_WIDTH 1 3026#define FRF_AB_XX_CH2_DEG_DET_LBN 11 3027#define FRF_AB_XX_CH2_DEG_DET_WIDTH 1 3028#define FRF_AB_XX_CH2_LFSR_LOCK_IND_LBN 10 3029#define FRF_AB_XX_CH2_LFSR_LOCK_IND_WIDTH 1 3030#define FRF_AB_XX_CH2_PRBS_FRUN_LBN 9 3031#define FRF_AB_XX_CH2_PRBS_FRUN_WIDTH 1 3032#define FRF_AB_XX_CH2_ERR_CHK_LBN 8 3033#define FRF_AB_XX_CH2_ERR_CHK_WIDTH 1 3034#define FRF_AB_XX_CH1_DEG_DET_LBN 7 3035#define FRF_AB_XX_CH1_DEG_DET_WIDTH 1 3036#define FRF_AB_XX_CH1_LFSR_LOCK_IND_LBN 6 3037#define FRF_AB_XX_CH1_LFSR_LOCK_IND_WIDTH 1 3038#define FRF_AB_XX_CH1_PRBS_FRUN_LBN 5 3039#define FRF_AB_XX_CH1_PRBS_FRUN_WIDTH 1 3040#define FRF_AB_XX_CH1_ERR_CHK_LBN 4 3041#define FRF_AB_XX_CH1_ERR_CHK_WIDTH 1 3042#define FRF_AB_XX_CH0_DEG_DET_LBN 3 3043#define FRF_AB_XX_CH0_DEG_DET_WIDTH 1 3044#define FRF_AB_XX_CH0_LFSR_LOCK_IND_LBN 2 3045#define FRF_AB_XX_CH0_LFSR_LOCK_IND_WIDTH 1 3046#define FRF_AB_XX_CH0_PRBS_FRUN_LBN 1 3047#define FRF_AB_XX_CH0_PRBS_FRUN_WIDTH 1 3048#define FRF_AB_XX_CH0_ERR_CHK_LBN 0 3049#define FRF_AB_XX_CH0_ERR_CHK_WIDTH 1 3050 3051 3052/* 3053 * FR_AB_XX_PRBS_ERR_REG(128bit): 3054 * documentation to be written for sum_XX_PRBS_ERR_REG 3055 */ 3056#define FR_AB_XX_PRBS_ERR_REG_OFST 0x00001350 3057/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3058 3059#define FRF_AB_XX_CH3_PRBS_ERR_CNT_LBN 24 3060#define FRF_AB_XX_CH3_PRBS_ERR_CNT_WIDTH 8 3061#define FRF_AB_XX_CH2_PRBS_ERR_CNT_LBN 16 3062#define FRF_AB_XX_CH2_PRBS_ERR_CNT_WIDTH 8 3063#define FRF_AB_XX_CH1_PRBS_ERR_CNT_LBN 8 3064#define FRF_AB_XX_CH1_PRBS_ERR_CNT_WIDTH 8 3065#define FRF_AB_XX_CH0_PRBS_ERR_CNT_LBN 0 3066#define FRF_AB_XX_CH0_PRBS_ERR_CNT_WIDTH 8 3067 3068 3069/* 3070 * FR_AB_XX_CORE_STAT_REG(128bit): 3071 * XAUI XGXS core status register 3072 */ 3073#define FR_AB_XX_CORE_STAT_REG_OFST 0x00001360 3074/* falcona0,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3075 3076#define FRF_AB_XX_FORCE_SIG3_LBN 31 3077#define FRF_AB_XX_FORCE_SIG3_WIDTH 1 3078#define FRF_AB_XX_FORCE_SIG3_VAL_LBN 30 3079#define FRF_AB_XX_FORCE_SIG3_VAL_WIDTH 1 3080#define FRF_AB_XX_FORCE_SIG2_LBN 29 3081#define FRF_AB_XX_FORCE_SIG2_WIDTH 1 3082#define FRF_AB_XX_FORCE_SIG2_VAL_LBN 28 3083#define FRF_AB_XX_FORCE_SIG2_VAL_WIDTH 1 3084#define FRF_AB_XX_FORCE_SIG1_LBN 27 3085#define FRF_AB_XX_FORCE_SIG1_WIDTH 1 3086#define FRF_AB_XX_FORCE_SIG1_VAL_LBN 26 3087#define FRF_AB_XX_FORCE_SIG1_VAL_WIDTH 1 3088#define FRF_AB_XX_FORCE_SIG0_LBN 25 3089#define FRF_AB_XX_FORCE_SIG0_WIDTH 1 3090#define FRF_AB_XX_FORCE_SIG0_VAL_LBN 24 3091#define FRF_AB_XX_FORCE_SIG0_VAL_WIDTH 1 3092#define FRF_AB_XX_XGXS_LB_EN_LBN 23 3093#define FRF_AB_XX_XGXS_LB_EN_WIDTH 1 3094#define FRF_AB_XX_XGMII_LB_EN_LBN 22 3095#define FRF_AB_XX_XGMII_LB_EN_WIDTH 1 3096#define FRF_AB_XX_MATCH_FAULT_LBN 21 3097#define FRF_AB_XX_MATCH_FAULT_WIDTH 1 3098#define FRF_AB_XX_ALIGN_DONE_LBN 20 3099#define FRF_AB_XX_ALIGN_DONE_WIDTH 1 3100#define FRF_AB_XX_SYNC_STAT3_LBN 19 3101#define FRF_AB_XX_SYNC_STAT3_WIDTH 1 3102#define FRF_AB_XX_SYNC_STAT2_LBN 18 3103#define FRF_AB_XX_SYNC_STAT2_WIDTH 1 3104#define FRF_AB_XX_SYNC_STAT1_LBN 17 3105#define FRF_AB_XX_SYNC_STAT1_WIDTH 1 3106#define FRF_AB_XX_SYNC_STAT0_LBN 16 3107#define FRF_AB_XX_SYNC_STAT0_WIDTH 1 3108#define FRF_AB_XX_COMMA_DET_CH3_LBN 15 3109#define FRF_AB_XX_COMMA_DET_CH3_WIDTH 1 3110#define FRF_AB_XX_COMMA_DET_CH2_LBN 14 3111#define FRF_AB_XX_COMMA_DET_CH2_WIDTH 1 3112#define FRF_AB_XX_COMMA_DET_CH1_LBN 13 3113#define FRF_AB_XX_COMMA_DET_CH1_WIDTH 1 3114#define FRF_AB_XX_COMMA_DET_CH0_LBN 12 3115#define FRF_AB_XX_COMMA_DET_CH0_WIDTH 1 3116#define FRF_AB_XX_CGRP_ALIGN_CH3_LBN 11 3117#define FRF_AB_XX_CGRP_ALIGN_CH3_WIDTH 1 3118#define FRF_AB_XX_CGRP_ALIGN_CH2_LBN 10 3119#define FRF_AB_XX_CGRP_ALIGN_CH2_WIDTH 1 3120#define FRF_AB_XX_CGRP_ALIGN_CH1_LBN 9 3121#define FRF_AB_XX_CGRP_ALIGN_CH1_WIDTH 1 3122#define FRF_AB_XX_CGRP_ALIGN_CH0_LBN 8 3123#define FRF_AB_XX_CGRP_ALIGN_CH0_WIDTH 1 3124#define FRF_AB_XX_CHAR_ERR_CH3_LBN 7 3125#define FRF_AB_XX_CHAR_ERR_CH3_WIDTH 1 3126#define FRF_AB_XX_CHAR_ERR_CH2_LBN 6 3127#define FRF_AB_XX_CHAR_ERR_CH2_WIDTH 1 3128#define FRF_AB_XX_CHAR_ERR_CH1_LBN 5 3129#define FRF_AB_XX_CHAR_ERR_CH1_WIDTH 1 3130#define FRF_AB_XX_CHAR_ERR_CH0_LBN 4 3131#define FRF_AB_XX_CHAR_ERR_CH0_WIDTH 1 3132#define FRF_AB_XX_DISPERR_CH3_LBN 3 3133#define FRF_AB_XX_DISPERR_CH3_WIDTH 1 3134#define FRF_AB_XX_DISPERR_CH2_LBN 2 3135#define FRF_AB_XX_DISPERR_CH2_WIDTH 1 3136#define FRF_AB_XX_DISPERR_CH1_LBN 1 3137#define FRF_AB_XX_DISPERR_CH1_WIDTH 1 3138#define FRF_AB_XX_DISPERR_CH0_LBN 0 3139#define FRF_AB_XX_DISPERR_CH0_WIDTH 1 3140 3141 3142/* 3143 * FR_AA_RX_DESC_PTR_TBL_KER(128bit): 3144 * Receive descriptor pointer table 3145 */ 3146#define FR_AA_RX_DESC_PTR_TBL_KER_OFST 0x00011800 3147/* falcona0=net_func_bar2 */ 3148#define FR_AA_RX_DESC_PTR_TBL_KER_STEP 16 3149#define FR_AA_RX_DESC_PTR_TBL_KER_ROWS 4 3150/* 3151 * FR_AZ_RX_DESC_PTR_TBL(128bit): 3152 * Receive descriptor pointer table 3153 */ 3154#define FR_AZ_RX_DESC_PTR_TBL_OFST 0x00f40000 3155/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3156#define FR_AZ_RX_DESC_PTR_TBL_STEP 16 3157#define FR_CZ_RX_DESC_PTR_TBL_ROWS 1024 3158#define FR_AB_RX_DESC_PTR_TBL_ROWS 4096 3159 3160#define FRF_CZ_RX_HDR_SPLIT_LBN 90 3161#define FRF_CZ_RX_HDR_SPLIT_WIDTH 1 3162#define FRF_AZ_RX_RESET_LBN 89 3163#define FRF_AZ_RX_RESET_WIDTH 1 3164#define FRF_AZ_RX_ISCSI_DDIG_EN_LBN 88 3165#define FRF_AZ_RX_ISCSI_DDIG_EN_WIDTH 1 3166#define FRF_AZ_RX_ISCSI_HDIG_EN_LBN 87 3167#define FRF_AZ_RX_ISCSI_HDIG_EN_WIDTH 1 3168#define FRF_AZ_RX_DESC_PREF_ACT_LBN 86 3169#define FRF_AZ_RX_DESC_PREF_ACT_WIDTH 1 3170#define FRF_AZ_RX_DC_HW_RPTR_LBN 80 3171#define FRF_AZ_RX_DC_HW_RPTR_WIDTH 6 3172#define FRF_AZ_RX_DESCQ_HW_RPTR_LBN 68 3173#define FRF_AZ_RX_DESCQ_HW_RPTR_WIDTH 12 3174#define FRF_AZ_RX_DESCQ_SW_WPTR_LBN 56 3175#define FRF_AZ_RX_DESCQ_SW_WPTR_WIDTH 12 3176#define FRF_AZ_RX_DESCQ_BUF_BASE_ID_LBN 36 3177#define FRF_AZ_RX_DESCQ_BUF_BASE_ID_WIDTH 20 3178#define FRF_AZ_RX_DESCQ_EVQ_ID_LBN 24 3179#define FRF_AZ_RX_DESCQ_EVQ_ID_WIDTH 12 3180#define FRF_AZ_RX_DESCQ_OWNER_ID_LBN 10 3181#define FRF_AZ_RX_DESCQ_OWNER_ID_WIDTH 14 3182#define FRF_AZ_RX_DESCQ_LABEL_LBN 5 3183#define FRF_AZ_RX_DESCQ_LABEL_WIDTH 5 3184#define FRF_AZ_RX_DESCQ_SIZE_LBN 3 3185#define FRF_AZ_RX_DESCQ_SIZE_WIDTH 2 3186#define FFE_AZ_RX_DESCQ_SIZE_4K 3 3187#define FFE_AZ_RX_DESCQ_SIZE_2K 2 3188#define FFE_AZ_RX_DESCQ_SIZE_1K 1 3189#define FFE_AZ_RX_DESCQ_SIZE_512 0 3190#define FRF_AZ_RX_DESCQ_TYPE_LBN 2 3191#define FRF_AZ_RX_DESCQ_TYPE_WIDTH 1 3192#define FRF_AZ_RX_DESCQ_JUMBO_LBN 1 3193#define FRF_AZ_RX_DESCQ_JUMBO_WIDTH 1 3194#define FRF_AZ_RX_DESCQ_EN_LBN 0 3195#define FRF_AZ_RX_DESCQ_EN_WIDTH 1 3196 3197 3198/* 3199 * FR_AA_TX_DESC_PTR_TBL_KER(128bit): 3200 * Transmit descriptor pointer 3201 */ 3202#define FR_AA_TX_DESC_PTR_TBL_KER_OFST 0x00011900 3203/* falcona0=net_func_bar2 */ 3204#define FR_AA_TX_DESC_PTR_TBL_KER_STEP 16 3205#define FR_AA_TX_DESC_PTR_TBL_KER_ROWS 8 3206/* 3207 * FR_AZ_TX_DESC_PTR_TBL(128bit): 3208 * Transmit descriptor pointer 3209 */ 3210#define FR_AZ_TX_DESC_PTR_TBL_OFST 0x00f50000 3211/* falconb0=net_func_bar2,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 3212#define FR_AZ_TX_DESC_PTR_TBL_STEP 16 3213#define FR_AB_TX_DESC_PTR_TBL_ROWS 4096 3214#define FR_CZ_TX_DESC_PTR_TBL_ROWS 1024 3215 3216#define FRF_CZ_TX_DPT_Q_MASK_WIDTH_LBN 94 3217#define FRF_CZ_TX_DPT_Q_MASK_WIDTH_WIDTH 2 3218#define FRF_CZ_TX_DPT_ETH_FILT_EN_LBN 93 3219#define FRF_CZ_TX_DPT_ETH_FILT_EN_WIDTH 1 3220#define FRF_CZ_TX_DPT_IP_FILT_EN_LBN 92 3221#define FRF_CZ_TX_DPT_IP_FILT_EN_WIDTH 1 3222#define FRF_BZ_TX_NON_IP_DROP_DIS_LBN 91 3223#define FRF_BZ_TX_NON_IP_DROP_DIS_WIDTH 1 3224#define FRF_BZ_TX_IP_CHKSM_DIS_LBN 90 3225#define FRF_BZ_TX_IP_CHKSM_DIS_WIDTH 1 3226#define FRF_BZ_TX_TCP_CHKSM_DIS_LBN 89 3227#define FRF_BZ_TX_TCP_CHKSM_DIS_WIDTH 1 3228#define FRF_AZ_TX_DESCQ_EN_LBN 88 3229#define FRF_AZ_TX_DESCQ_EN_WIDTH 1 3230#define FRF_AZ_TX_ISCSI_DDIG_EN_LBN 87 3231#define FRF_AZ_TX_ISCSI_DDIG_EN_WIDTH 1 3232#define FRF_AZ_TX_ISCSI_HDIG_EN_LBN 86 3233#define FRF_AZ_TX_ISCSI_HDIG_EN_WIDTH 1 3234#define FRF_AZ_TX_DC_HW_RPTR_LBN 80 3235#define FRF_AZ_TX_DC_HW_RPTR_WIDTH 6 3236#define FRF_AZ_TX_DESCQ_HW_RPTR_LBN 68 3237#define FRF_AZ_TX_DESCQ_HW_RPTR_WIDTH 12 3238#define FRF_AZ_TX_DESCQ_SW_WPTR_LBN 56 3239#define FRF_AZ_TX_DESCQ_SW_WPTR_WIDTH 12 3240#define FRF_AZ_TX_DESCQ_BUF_BASE_ID_LBN 36 3241#define FRF_AZ_TX_DESCQ_BUF_BASE_ID_WIDTH 20 3242#define FRF_AZ_TX_DESCQ_EVQ_ID_LBN 24 3243#define FRF_AZ_TX_DESCQ_EVQ_ID_WIDTH 12 3244#define FRF_AZ_TX_DESCQ_OWNER_ID_LBN 10 3245#define FRF_AZ_TX_DESCQ_OWNER_ID_WIDTH 14 3246#define FRF_AZ_TX_DESCQ_LABEL_LBN 5 3247#define FRF_AZ_TX_DESCQ_LABEL_WIDTH 5 3248#define FRF_AZ_TX_DESCQ_SIZE_LBN 3 3249#define FRF_AZ_TX_DESCQ_SIZE_WIDTH 2 3250#define FFE_AZ_TX_DESCQ_SIZE_4K 3 3251#define FFE_AZ_TX_DESCQ_SIZE_2K 2 3252#define FFE_AZ_TX_DESCQ_SIZE_1K 1 3253#define FFE_AZ_TX_DESCQ_SIZE_512 0 3254#define FRF_AZ_TX_DESCQ_TYPE_LBN 1 3255#define FRF_AZ_TX_DESCQ_TYPE_WIDTH 2 3256#define FRF_AZ_TX_DESCQ_FLUSH_LBN 0 3257#define FRF_AZ_TX_DESCQ_FLUSH_WIDTH 1 3258 3259 3260/* 3261 * FR_AA_EVQ_PTR_TBL_KER(128bit): 3262 * Event queue pointer table 3263 */ 3264#define FR_AA_EVQ_PTR_TBL_KER_OFST 0x00011a00 3265/* falcona0=net_func_bar2 */ 3266#define FR_AA_EVQ_PTR_TBL_KER_STEP 16 3267#define FR_AA_EVQ_PTR_TBL_KER_ROWS 4 3268/* 3269 * FR_AZ_EVQ_PTR_TBL(128bit): 3270 * Event queue pointer table 3271 */ 3272#define FR_AZ_EVQ_PTR_TBL_OFST 0x00f60000 3273/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3274#define FR_AZ_EVQ_PTR_TBL_STEP 16 3275#define FR_CZ_EVQ_PTR_TBL_ROWS 1024 3276#define FR_AB_EVQ_PTR_TBL_ROWS 4096 3277 3278#define FRF_BZ_EVQ_RPTR_IGN_LBN 40 3279#define FRF_BZ_EVQ_RPTR_IGN_WIDTH 1 3280#define FRF_AZ_EVQ_WKUP_OR_INT_EN_LBN 39 3281#define FRF_AZ_EVQ_WKUP_OR_INT_EN_WIDTH 1 3282#define FRF_AZ_EVQ_NXT_WPTR_LBN 24 3283#define FRF_AZ_EVQ_NXT_WPTR_WIDTH 15 3284#define FRF_AZ_EVQ_EN_LBN 23 3285#define FRF_AZ_EVQ_EN_WIDTH 1 3286#define FRF_AZ_EVQ_SIZE_LBN 20 3287#define FRF_AZ_EVQ_SIZE_WIDTH 3 3288#define FFE_AZ_EVQ_SIZE_32K 6 3289#define FFE_AZ_EVQ_SIZE_16K 5 3290#define FFE_AZ_EVQ_SIZE_8K 4 3291#define FFE_AZ_EVQ_SIZE_4K 3 3292#define FFE_AZ_EVQ_SIZE_2K 2 3293#define FFE_AZ_EVQ_SIZE_1K 1 3294#define FFE_AZ_EVQ_SIZE_512 0 3295#define FRF_AZ_EVQ_BUF_BASE_ID_LBN 0 3296#define FRF_AZ_EVQ_BUF_BASE_ID_WIDTH 20 3297 3298 3299/* 3300 * FR_AA_BUF_HALF_TBL_KER(64bit): 3301 * Buffer table in half buffer table mode direct access by driver 3302 */ 3303#define FR_AA_BUF_HALF_TBL_KER_OFST 0x00018000 3304/* falcona0=net_func_bar2 */ 3305#define FR_AA_BUF_HALF_TBL_KER_STEP 8 3306#define FR_AA_BUF_HALF_TBL_KER_ROWS 4096 3307/* 3308 * FR_AZ_BUF_HALF_TBL(64bit): 3309 * Buffer table in half buffer table mode direct access by driver 3310 */ 3311#define FR_AZ_BUF_HALF_TBL_OFST 0x00800000 3312/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3313#define FR_AZ_BUF_HALF_TBL_STEP 8 3314#define FR_CZ_BUF_HALF_TBL_ROWS 147456 3315#define FR_AB_BUF_HALF_TBL_ROWS 524288 3316 3317#define FRF_AZ_BUF_ADR_HBUF_ODD_LBN 44 3318#define FRF_AZ_BUF_ADR_HBUF_ODD_WIDTH 20 3319#define FRF_AZ_BUF_OWNER_ID_HBUF_ODD_LBN 32 3320#define FRF_AZ_BUF_OWNER_ID_HBUF_ODD_WIDTH 12 3321#define FRF_AZ_BUF_ADR_HBUF_EVEN_LBN 12 3322#define FRF_AZ_BUF_ADR_HBUF_EVEN_WIDTH 20 3323#define FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_LBN 0 3324#define FRF_AZ_BUF_OWNER_ID_HBUF_EVEN_WIDTH 12 3325 3326 3327/* 3328 * FR_AA_BUF_FULL_TBL_KER(64bit): 3329 * Buffer table in full buffer table mode direct access by driver 3330 */ 3331#define FR_AA_BUF_FULL_TBL_KER_OFST 0x00018000 3332/* falcona0=net_func_bar2 */ 3333#define FR_AA_BUF_FULL_TBL_KER_STEP 8 3334#define FR_AA_BUF_FULL_TBL_KER_ROWS 4096 3335/* 3336 * FR_AZ_BUF_FULL_TBL(64bit): 3337 * Buffer table in full buffer table mode direct access by driver 3338 */ 3339#define FR_AZ_BUF_FULL_TBL_OFST 0x00800000 3340/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3341#define FR_AZ_BUF_FULL_TBL_STEP 8 3342 3343#define FR_CZ_BUF_FULL_TBL_ROWS 147456 3344#define FR_AB_BUF_FULL_TBL_ROWS 917504 3345 3346#define FRF_AZ_BUF_FULL_UNUSED_LBN 51 3347#define FRF_AZ_BUF_FULL_UNUSED_WIDTH 13 3348#define FRF_AZ_IP_DAT_BUF_SIZE_LBN 50 3349#define FRF_AZ_IP_DAT_BUF_SIZE_WIDTH 1 3350#define FRF_AZ_BUF_ADR_REGION_LBN 48 3351#define FRF_AZ_BUF_ADR_REGION_WIDTH 2 3352#define FFE_AZ_BUF_ADR_REGN3 3 3353#define FFE_AZ_BUF_ADR_REGN2 2 3354#define FFE_AZ_BUF_ADR_REGN1 1 3355#define FFE_AZ_BUF_ADR_REGN0 0 3356#define FRF_AZ_BUF_ADR_FBUF_LBN 14 3357#define FRF_AZ_BUF_ADR_FBUF_WIDTH 34 3358#define FRF_AZ_BUF_ADR_FBUF_DW0_LBN 14 3359#define FRF_AZ_BUF_ADR_FBUF_DW0_WIDTH 32 3360#define FRF_AZ_BUF_ADR_FBUF_DW1_LBN 46 3361#define FRF_AZ_BUF_ADR_FBUF_DW1_WIDTH 2 3362#define FRF_AZ_BUF_OWNER_ID_FBUF_LBN 0 3363#define FRF_AZ_BUF_OWNER_ID_FBUF_WIDTH 14 3364 3365 3366/* 3367 * FR_AZ_RX_FILTER_TBL0(128bit): 3368 * TCP/IPv4 Receive filter table 3369 */ 3370#define FR_AZ_RX_FILTER_TBL0_OFST 0x00f00000 3371/* falconb0,sienaa0=net_func_bar2,falcona0=char_func_bar0 */ 3372#define FR_AZ_RX_FILTER_TBL0_STEP 32 3373#define FR_AZ_RX_FILTER_TBL0_ROWS 8192 3374/* 3375 * FR_AB_RX_FILTER_TBL1(128bit): 3376 * TCP/IPv4 Receive filter table 3377 */ 3378#define FR_AB_RX_FILTER_TBL1_OFST 0x00f00010 3379/* falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3380#define FR_AB_RX_FILTER_TBL1_STEP 32 3381#define FR_AB_RX_FILTER_TBL1_ROWS 8192 3382 3383#define FRF_BZ_RSS_EN_LBN 110 3384#define FRF_BZ_RSS_EN_WIDTH 1 3385#define FRF_BZ_SCATTER_EN_LBN 109 3386#define FRF_BZ_SCATTER_EN_WIDTH 1 3387#define FRF_AZ_TCP_UDP_LBN 108 3388#define FRF_AZ_TCP_UDP_WIDTH 1 3389#define FRF_AZ_RXQ_ID_LBN 96 3390#define FRF_AZ_RXQ_ID_WIDTH 12 3391#define FRF_AZ_DEST_IP_LBN 64 3392#define FRF_AZ_DEST_IP_WIDTH 32 3393#define FRF_AZ_DEST_PORT_TCP_LBN 48 3394#define FRF_AZ_DEST_PORT_TCP_WIDTH 16 3395#define FRF_AZ_SRC_IP_LBN 16 3396#define FRF_AZ_SRC_IP_WIDTH 32 3397#define FRF_AZ_SRC_TCP_DEST_UDP_LBN 0 3398#define FRF_AZ_SRC_TCP_DEST_UDP_WIDTH 16 3399 3400 3401/* 3402 * FR_CZ_RX_MAC_FILTER_TBL0(128bit): 3403 * Receive Ethernet filter table 3404 */ 3405#define FR_CZ_RX_MAC_FILTER_TBL0_OFST 0x00f00010 3406/* sienaa0=net_func_bar2 */ 3407#define FR_CZ_RX_MAC_FILTER_TBL0_STEP 32 3408#define FR_CZ_RX_MAC_FILTER_TBL0_ROWS 512 3409 3410#define FRF_CZ_RMFT_RSS_EN_LBN 75 3411#define FRF_CZ_RMFT_RSS_EN_WIDTH 1 3412#define FRF_CZ_RMFT_SCATTER_EN_LBN 74 3413#define FRF_CZ_RMFT_SCATTER_EN_WIDTH 1 3414#define FRF_CZ_RMFT_IP_OVERRIDE_LBN 73 3415#define FRF_CZ_RMFT_IP_OVERRIDE_WIDTH 1 3416#define FRF_CZ_RMFT_RXQ_ID_LBN 61 3417#define FRF_CZ_RMFT_RXQ_ID_WIDTH 12 3418#define FRF_CZ_RMFT_WILDCARD_MATCH_LBN 60 3419#define FRF_CZ_RMFT_WILDCARD_MATCH_WIDTH 1 3420#define FRF_CZ_RMFT_DEST_MAC_LBN 12 3421#define FRF_CZ_RMFT_DEST_MAC_WIDTH 48 3422#define FRF_CZ_RMFT_DEST_MAC_DW0_LBN 12 3423#define FRF_CZ_RMFT_DEST_MAC_DW0_WIDTH 32 3424#define FRF_CZ_RMFT_DEST_MAC_DW1_LBN 44 3425#define FRF_CZ_RMFT_DEST_MAC_DW1_WIDTH 16 3426#define FRF_CZ_RMFT_VLAN_ID_LBN 0 3427#define FRF_CZ_RMFT_VLAN_ID_WIDTH 12 3428 3429 3430/* 3431 * FR_AZ_TIMER_TBL(128bit): 3432 * Timer table 3433 */ 3434#define FR_AZ_TIMER_TBL_OFST 0x00f70000 3435/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3436#define FR_AZ_TIMER_TBL_STEP 16 3437#define FR_CZ_TIMER_TBL_ROWS 1024 3438#define FR_AB_TIMER_TBL_ROWS 4096 3439 3440#define FRF_CZ_TIMER_Q_EN_LBN 33 3441#define FRF_CZ_TIMER_Q_EN_WIDTH 1 3442#define FRF_CZ_INT_ARMD_LBN 32 3443#define FRF_CZ_INT_ARMD_WIDTH 1 3444#define FRF_CZ_INT_PEND_LBN 31 3445#define FRF_CZ_INT_PEND_WIDTH 1 3446#define FRF_CZ_HOST_NOTIFY_MODE_LBN 30 3447#define FRF_CZ_HOST_NOTIFY_MODE_WIDTH 1 3448#define FRF_CZ_RELOAD_TIMER_VAL_LBN 16 3449#define FRF_CZ_RELOAD_TIMER_VAL_WIDTH 14 3450#define FRF_CZ_TIMER_MODE_LBN 14 3451#define FRF_CZ_TIMER_MODE_WIDTH 2 3452#define FFE_CZ_TIMER_MODE_INT_HLDOFF 3 3453#define FFE_CZ_TIMER_MODE_TRIG_START 2 3454#define FFE_CZ_TIMER_MODE_IMMED_START 1 3455#define FFE_CZ_TIMER_MODE_DIS 0 3456#define FRF_AB_TIMER_MODE_LBN 12 3457#define FRF_AB_TIMER_MODE_WIDTH 2 3458#define FFE_AB_TIMER_MODE_INT_HLDOFF 2 3459#define FFE_AB_TIMER_MODE_TRIG_START 2 3460#define FFE_AB_TIMER_MODE_IMMED_START 1 3461#define FFE_AB_TIMER_MODE_DIS 0 3462#define FRF_CZ_TIMER_VAL_LBN 0 3463#define FRF_CZ_TIMER_VAL_WIDTH 14 3464#define FRF_AB_TIMER_VAL_LBN 0 3465#define FRF_AB_TIMER_VAL_WIDTH 12 3466 3467 3468/* 3469 * FR_BZ_TX_PACE_TBL(128bit): 3470 * Transmit pacing table 3471 */ 3472#define FR_BZ_TX_PACE_TBL_OFST 0x00f80000 3473/* sienaa0=net_func_bar2,falconb0=net_func_bar2 */ 3474#define FR_AZ_TX_PACE_TBL_STEP 16 3475#define FR_CZ_TX_PACE_TBL_ROWS 1024 3476#define FR_BB_TX_PACE_TBL_ROWS 4096 3477/* 3478 * FR_AA_TX_PACE_TBL(128bit): 3479 * Transmit pacing table 3480 */ 3481#define FR_AA_TX_PACE_TBL_OFST 0x00f80040 3482/* falcona0=char_func_bar0 */ 3483/* FR_AZ_TX_PACE_TBL_STEP 16 */ 3484#define FR_AA_TX_PACE_TBL_ROWS 4092 3485 3486#define FRF_AZ_TX_PACE_LBN 0 3487#define FRF_AZ_TX_PACE_WIDTH 5 3488 3489 3490/* 3491 * FR_BZ_RX_INDIRECTION_TBL(7bit): 3492 * RX Indirection Table 3493 */ 3494#define FR_BZ_RX_INDIRECTION_TBL_OFST 0x00fb0000 3495/* falconb0,sienaa0=net_func_bar2 */ 3496#define FR_BZ_RX_INDIRECTION_TBL_STEP 16 3497#define FR_BZ_RX_INDIRECTION_TBL_ROWS 128 3498 3499#define FRF_BZ_IT_QUEUE_LBN 0 3500#define FRF_BZ_IT_QUEUE_WIDTH 6 3501 3502 3503/* 3504 * FR_CZ_TX_FILTER_TBL0(128bit): 3505 * TCP/IPv4 Transmit filter table 3506 */ 3507#define FR_CZ_TX_FILTER_TBL0_OFST 0x00fc0000 3508/* sienaa0=net_func_bar2 */ 3509#define FR_CZ_TX_FILTER_TBL0_STEP 16 3510#define FR_CZ_TX_FILTER_TBL0_ROWS 8192 3511 3512#define FRF_CZ_TIFT_TCP_UDP_LBN 108 3513#define FRF_CZ_TIFT_TCP_UDP_WIDTH 1 3514#define FRF_CZ_TIFT_TXQ_ID_LBN 96 3515#define FRF_CZ_TIFT_TXQ_ID_WIDTH 12 3516#define FRF_CZ_TIFT_DEST_IP_LBN 64 3517#define FRF_CZ_TIFT_DEST_IP_WIDTH 32 3518#define FRF_CZ_TIFT_DEST_PORT_TCP_LBN 48 3519#define FRF_CZ_TIFT_DEST_PORT_TCP_WIDTH 16 3520#define FRF_CZ_TIFT_SRC_IP_LBN 16 3521#define FRF_CZ_TIFT_SRC_IP_WIDTH 32 3522#define FRF_CZ_TIFT_SRC_TCP_DEST_UDP_LBN 0 3523#define FRF_CZ_TIFT_SRC_TCP_DEST_UDP_WIDTH 16 3524 3525 3526/* 3527 * FR_CZ_TX_MAC_FILTER_TBL0(128bit): 3528 * Transmit Ethernet filter table 3529 */ 3530#define FR_CZ_TX_MAC_FILTER_TBL0_OFST 0x00fe0000 3531/* sienaa0=net_func_bar2 */ 3532#define FR_CZ_TX_MAC_FILTER_TBL0_STEP 16 3533#define FR_CZ_TX_MAC_FILTER_TBL0_ROWS 512 3534 3535#define FRF_CZ_TMFT_TXQ_ID_LBN 61 3536#define FRF_CZ_TMFT_TXQ_ID_WIDTH 12 3537#define FRF_CZ_TMFT_WILDCARD_MATCH_LBN 60 3538#define FRF_CZ_TMFT_WILDCARD_MATCH_WIDTH 1 3539#define FRF_CZ_TMFT_SRC_MAC_LBN 12 3540#define FRF_CZ_TMFT_SRC_MAC_WIDTH 48 3541#define FRF_CZ_TMFT_SRC_MAC_DW0_LBN 12 3542#define FRF_CZ_TMFT_SRC_MAC_DW0_WIDTH 32 3543#define FRF_CZ_TMFT_SRC_MAC_DW1_LBN 44 3544#define FRF_CZ_TMFT_SRC_MAC_DW1_WIDTH 16 3545#define FRF_CZ_TMFT_VLAN_ID_LBN 0 3546#define FRF_CZ_TMFT_VLAN_ID_WIDTH 12 3547 3548 3549/* 3550 * FR_CZ_MC_TREG_SMEM(32bit): 3551 * MC Shared Memory 3552 */ 3553#define FR_CZ_MC_TREG_SMEM_OFST 0x00ff0000 3554/* sienaa0=net_func_bar2 */ 3555#define FR_CZ_MC_TREG_SMEM_STEP 4 3556#define FR_CZ_MC_TREG_SMEM_ROWS 512 3557 3558#define FRF_CZ_MC_TREG_SMEM_ROW_LBN 0 3559#define FRF_CZ_MC_TREG_SMEM_ROW_WIDTH 32 3560 3561 3562/* 3563 * FR_BB_MSIX_VECTOR_TABLE(128bit): 3564 * MSIX Vector Table 3565 */ 3566#define FR_BB_MSIX_VECTOR_TABLE_OFST 0x00ff0000 3567/* falconb0=net_func_bar2 */ 3568#define FR_BZ_MSIX_VECTOR_TABLE_STEP 16 3569#define FR_BB_MSIX_VECTOR_TABLE_ROWS 64 3570/* 3571 * FR_CZ_MSIX_VECTOR_TABLE(128bit): 3572 * MSIX Vector Table 3573 */ 3574#define FR_CZ_MSIX_VECTOR_TABLE_OFST 0x00000000 3575/* sienaa0=pci_f0_bar4 */ 3576/* FR_BZ_MSIX_VECTOR_TABLE_STEP 16 */ 3577#define FR_CZ_MSIX_VECTOR_TABLE_ROWS 1024 3578 3579#define FRF_BZ_MSIX_VECTOR_RESERVED_LBN 97 3580#define FRF_BZ_MSIX_VECTOR_RESERVED_WIDTH 31 3581#define FRF_BZ_MSIX_VECTOR_MASK_LBN 96 3582#define FRF_BZ_MSIX_VECTOR_MASK_WIDTH 1 3583#define FRF_BZ_MSIX_MESSAGE_DATA_LBN 64 3584#define FRF_BZ_MSIX_MESSAGE_DATA_WIDTH 32 3585#define FRF_BZ_MSIX_MESSAGE_ADDRESS_HI_LBN 32 3586#define FRF_BZ_MSIX_MESSAGE_ADDRESS_HI_WIDTH 32 3587#define FRF_BZ_MSIX_MESSAGE_ADDRESS_LO_LBN 0 3588#define FRF_BZ_MSIX_MESSAGE_ADDRESS_LO_WIDTH 32 3589 3590 3591/* 3592 * FR_BB_MSIX_PBA_TABLE(32bit): 3593 * MSIX Pending Bit Array 3594 */ 3595#define FR_BB_MSIX_PBA_TABLE_OFST 0x00ff2000 3596/* falconb0=net_func_bar2 */ 3597#define FR_BZ_MSIX_PBA_TABLE_STEP 4 3598#define FR_BB_MSIX_PBA_TABLE_ROWS 2 3599/* 3600 * FR_CZ_MSIX_PBA_TABLE(32bit): 3601 * MSIX Pending Bit Array 3602 */ 3603#define FR_CZ_MSIX_PBA_TABLE_OFST 0x00008000 3604/* sienaa0=pci_f0_bar4 */ 3605/* FR_BZ_MSIX_PBA_TABLE_STEP 4 */ 3606#define FR_CZ_MSIX_PBA_TABLE_ROWS 32 3607 3608#define FRF_BZ_MSIX_PBA_PEND_DWORD_LBN 0 3609#define FRF_BZ_MSIX_PBA_PEND_DWORD_WIDTH 32 3610 3611 3612/* 3613 * FR_AZ_SRM_DBG_REG(64bit): 3614 * SRAM debug access 3615 */ 3616#define FR_AZ_SRM_DBG_REG_OFST 0x03000000 3617/* sienaa0=net_func_bar2,falconb0=net_func_bar2,falcona0=char_func_bar0 */ 3618#define FR_AZ_SRM_DBG_REG_STEP 8 3619 3620#define FR_CZ_SRM_DBG_REG_ROWS 262144 3621#define FR_AB_SRM_DBG_REG_ROWS 2097152 3622 3623#define FRF_AZ_SRM_DBG_LBN 0 3624#define FRF_AZ_SRM_DBG_WIDTH 64 3625#define FRF_AZ_SRM_DBG_DW0_LBN 0 3626#define FRF_AZ_SRM_DBG_DW0_WIDTH 32 3627#define FRF_AZ_SRM_DBG_DW1_LBN 32 3628#define FRF_AZ_SRM_DBG_DW1_WIDTH 32 3629 3630 3631/* 3632 * FR_AA_INT_ACK_CHAR(32bit): 3633 * CHAR interrupt acknowledge register 3634 */ 3635#define FR_AA_INT_ACK_CHAR_OFST 0x00000060 3636/* falcona0=char_func_bar0 */ 3637 3638#define FRF_AA_INT_ACK_CHAR_FIELD_LBN 0 3639#define FRF_AA_INT_ACK_CHAR_FIELD_WIDTH 32 3640 3641 3642/* FS_DRIVER_EV */ 3643#define FSF_AZ_DRIVER_EV_SUBCODE_LBN 56 3644#define FSF_AZ_DRIVER_EV_SUBCODE_WIDTH 4 3645#define FSE_AZ_TX_DSC_ERROR_EV 15 3646#define FSE_AZ_RX_DSC_ERROR_EV 14 3647#define FSE_AZ_RX_RECOVER_EV 11 3648#define FSE_AZ_TIMER_EV 10 3649#define FSE_AZ_TX_PKT_NON_TCP_UDP 9 3650#define FSE_AZ_WAKE_UP_EV 6 3651#define FSE_AZ_SRM_UPD_DONE_EV 5 3652#define FSE_AZ_EVQ_NOT_EN_EV 3 3653#define FSE_AZ_EVQ_INIT_DONE_EV 2 3654#define FSE_AZ_RX_DESCQ_FLS_DONE_EV 1 3655#define FSE_AZ_TX_DESCQ_FLS_DONE_EV 0 3656#define FSF_AZ_DRIVER_EV_SUBDATA_LBN 0 3657#define FSF_AZ_DRIVER_EV_SUBDATA_WIDTH 14 3658 3659 3660/* FS_EVENT_ENTRY */ 3661#define FSF_AZ_EV_CODE_LBN 60 3662#define FSF_AZ_EV_CODE_WIDTH 4 3663#define FSE_AZ_EV_CODE_USER_EV 8 3664#define FSE_AZ_EV_CODE_DRV_GEN_EV 7 3665#define FSE_AZ_EV_CODE_GLOBAL_EV 6 3666#define FSE_AZ_EV_CODE_DRIVER_EV 5 3667#define FSE_AZ_EV_CODE_TX_EV 2 3668#define FSE_AZ_EV_CODE_RX_EV 0 3669#define FSF_AZ_EV_DATA_LBN 0 3670#define FSF_AZ_EV_DATA_WIDTH 60 3671#define FSF_AZ_EV_DATA_DW0_LBN 0 3672#define FSF_AZ_EV_DATA_DW0_WIDTH 32 3673#define FSF_AZ_EV_DATA_DW1_LBN 32 3674#define FSF_AZ_EV_DATA_DW1_WIDTH 28 3675 3676 3677/* FS_GLOBAL_EV */ 3678#define FSF_AA_GLB_EV_RX_RECOVERY_LBN 12 3679#define FSF_AA_GLB_EV_RX_RECOVERY_WIDTH 1 3680#define FSF_BZ_GLB_EV_XG_MNT_INTR_LBN 11 3681#define FSF_BZ_GLB_EV_XG_MNT_INTR_WIDTH 1 3682#define FSF_AZ_GLB_EV_XFP_PHY0_INTR_LBN 10 3683#define FSF_AZ_GLB_EV_XFP_PHY0_INTR_WIDTH 1 3684#define FSF_AZ_GLB_EV_XG_PHY0_INTR_LBN 9 3685#define FSF_AZ_GLB_EV_XG_PHY0_INTR_WIDTH 1 3686#define FSF_AZ_GLB_EV_G_PHY0_INTR_LBN 7 3687#define FSF_AZ_GLB_EV_G_PHY0_INTR_WIDTH 1 3688 3689 3690/* FS_RX_EV */ 3691#define FSF_CZ_RX_EV_PKT_NOT_PARSED_LBN 58 3692#define FSF_CZ_RX_EV_PKT_NOT_PARSED_WIDTH 1 3693#define FSF_CZ_RX_EV_IPV6_PKT_LBN 57 3694#define FSF_CZ_RX_EV_IPV6_PKT_WIDTH 1 3695#define FSF_AZ_RX_EV_PKT_OK_LBN 56 3696#define FSF_AZ_RX_EV_PKT_OK_WIDTH 1 3697#define FSF_AZ_RX_EV_PAUSE_FRM_ERR_LBN 55 3698#define FSF_AZ_RX_EV_PAUSE_FRM_ERR_WIDTH 1 3699#define FSF_AZ_RX_EV_BUF_OWNER_ID_ERR_LBN 54 3700#define FSF_AZ_RX_EV_BUF_OWNER_ID_ERR_WIDTH 1 3701#define FSF_AZ_RX_EV_IP_FRAG_ERR_LBN 53 3702#define FSF_AZ_RX_EV_IP_FRAG_ERR_WIDTH 1 3703#define FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR_LBN 52 3704#define FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR_WIDTH 1 3705#define FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR_LBN 51 3706#define FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR_WIDTH 1 3707#define FSF_AZ_RX_EV_ETH_CRC_ERR_LBN 50 3708#define FSF_AZ_RX_EV_ETH_CRC_ERR_WIDTH 1 3709#define FSF_AZ_RX_EV_FRM_TRUNC_LBN 49 3710#define FSF_AZ_RX_EV_FRM_TRUNC_WIDTH 1 3711#define FSF_AZ_RX_EV_TOBE_DISC_LBN 47 3712#define FSF_AZ_RX_EV_TOBE_DISC_WIDTH 1 3713#define FSF_AZ_RX_EV_PKT_TYPE_LBN 44 3714#define FSF_AZ_RX_EV_PKT_TYPE_WIDTH 3 3715#define FSE_AZ_RX_EV_PKT_TYPE_VLAN_JUMBO 5 3716#define FSE_AZ_RX_EV_PKT_TYPE_VLAN_LLC 4 3717#define FSE_AZ_RX_EV_PKT_TYPE_VLAN 3 3718#define FSE_AZ_RX_EV_PKT_TYPE_JUMBO 2 3719#define FSE_AZ_RX_EV_PKT_TYPE_LLC 1 3720#define FSE_AZ_RX_EV_PKT_TYPE_ETH 0 3721#define FSF_AZ_RX_EV_HDR_TYPE_LBN 42 3722#define FSF_AZ_RX_EV_HDR_TYPE_WIDTH 2 3723#define FSE_AZ_RX_EV_HDR_TYPE_OTHER 3 3724#define FSE_AZ_RX_EV_HDR_TYPE_IPV4_OTHER 2 3725#define FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER 2 3726#define FSE_AZ_RX_EV_HDR_TYPE_IPV4_UDP 1 3727#define FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP 1 3728#define FSE_AZ_RX_EV_HDR_TYPE_IPV4_TCP 0 3729#define FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP 0 3730#define FSF_AZ_RX_EV_DESC_Q_EMPTY_LBN 41 3731#define FSF_AZ_RX_EV_DESC_Q_EMPTY_WIDTH 1 3732#define FSF_AZ_RX_EV_MCAST_HASH_MATCH_LBN 40 3733#define FSF_AZ_RX_EV_MCAST_HASH_MATCH_WIDTH 1 3734#define FSF_AZ_RX_EV_MCAST_PKT_LBN 39 3735#define FSF_AZ_RX_EV_MCAST_PKT_WIDTH 1 3736#define FSF_AA_RX_EV_RECOVERY_FLAG_LBN 37 3737#define FSF_AA_RX_EV_RECOVERY_FLAG_WIDTH 1 3738#define FSF_AZ_RX_EV_Q_LABEL_LBN 32 3739#define FSF_AZ_RX_EV_Q_LABEL_WIDTH 5 3740#define FSF_AZ_RX_EV_JUMBO_CONT_LBN 31 3741#define FSF_AZ_RX_EV_JUMBO_CONT_WIDTH 1 3742#define FSF_AZ_RX_EV_PORT_LBN 30 3743#define FSF_AZ_RX_EV_PORT_WIDTH 1 3744#define FSF_AZ_RX_EV_BYTE_CNT_LBN 16 3745#define FSF_AZ_RX_EV_BYTE_CNT_WIDTH 14 3746#define FSF_AZ_RX_EV_SOP_LBN 15 3747#define FSF_AZ_RX_EV_SOP_WIDTH 1 3748#define FSF_AZ_RX_EV_ISCSI_PKT_OK_LBN 14 3749#define FSF_AZ_RX_EV_ISCSI_PKT_OK_WIDTH 1 3750#define FSF_AZ_RX_EV_ISCSI_DDIG_ERR_LBN 13 3751#define FSF_AZ_RX_EV_ISCSI_DDIG_ERR_WIDTH 1 3752#define FSF_AZ_RX_EV_ISCSI_HDIG_ERR_LBN 12 3753#define FSF_AZ_RX_EV_ISCSI_HDIG_ERR_WIDTH 1 3754#define FSF_AZ_RX_EV_DESC_PTR_LBN 0 3755#define FSF_AZ_RX_EV_DESC_PTR_WIDTH 12 3756 3757 3758/* FS_RX_KER_DESC */ 3759#define FSF_AZ_RX_KER_BUF_SIZE_LBN 48 3760#define FSF_AZ_RX_KER_BUF_SIZE_WIDTH 14 3761#define FSF_AZ_RX_KER_BUF_REGION_LBN 46 3762#define FSF_AZ_RX_KER_BUF_REGION_WIDTH 2 3763#define FSF_AZ_RX_KER_BUF_ADDR_LBN 0 3764#define FSF_AZ_RX_KER_BUF_ADDR_WIDTH 46 3765#define FSF_AZ_RX_KER_BUF_ADDR_DW0_LBN 0 3766#define FSF_AZ_RX_KER_BUF_ADDR_DW0_WIDTH 32 3767#define FSF_AZ_RX_KER_BUF_ADDR_DW1_LBN 32 3768#define FSF_AZ_RX_KER_BUF_ADDR_DW1_WIDTH 14 3769 3770 3771/* FS_RX_USER_DESC */ 3772#define FSF_AZ_RX_USER_2BYTE_OFFSET_LBN 20 3773#define FSF_AZ_RX_USER_2BYTE_OFFSET_WIDTH 12 3774#define FSF_AZ_RX_USER_BUF_ID_LBN 0 3775#define FSF_AZ_RX_USER_BUF_ID_WIDTH 20 3776 3777 3778/* FS_TX_EV */ 3779#define FSF_AZ_TX_EV_PKT_ERR_LBN 38 3780#define FSF_AZ_TX_EV_PKT_ERR_WIDTH 1 3781#define FSF_AZ_TX_EV_PKT_TOO_BIG_LBN 37 3782#define FSF_AZ_TX_EV_PKT_TOO_BIG_WIDTH 1 3783#define FSF_AZ_TX_EV_Q_LABEL_LBN 32 3784#define FSF_AZ_TX_EV_Q_LABEL_WIDTH 5 3785#define FSF_AZ_TX_EV_PORT_LBN 16 3786#define FSF_AZ_TX_EV_PORT_WIDTH 1 3787#define FSF_AZ_TX_EV_WQ_FF_FULL_LBN 15 3788#define FSF_AZ_TX_EV_WQ_FF_FULL_WIDTH 1 3789#define FSF_AZ_TX_EV_BUF_OWNER_ID_ERR_LBN 14 3790#define FSF_AZ_TX_EV_BUF_OWNER_ID_ERR_WIDTH 1 3791#define FSF_AZ_TX_EV_COMP_LBN 12 3792#define FSF_AZ_TX_EV_COMP_WIDTH 1 3793#define FSF_AZ_TX_EV_DESC_PTR_LBN 0 3794#define FSF_AZ_TX_EV_DESC_PTR_WIDTH 12 3795 3796 3797/* FS_TX_KER_DESC */ 3798#define FSF_AZ_TX_KER_CONT_LBN 62 3799#define FSF_AZ_TX_KER_CONT_WIDTH 1 3800#define FSF_AZ_TX_KER_BYTE_COUNT_LBN 48 3801#define FSF_AZ_TX_KER_BYTE_COUNT_WIDTH 14 3802#define FSF_AZ_TX_KER_BUF_REGION_LBN 46 3803#define FSF_AZ_TX_KER_BUF_REGION_WIDTH 2 3804#define FSF_AZ_TX_KER_BUF_ADDR_LBN 0 3805#define FSF_AZ_TX_KER_BUF_ADDR_WIDTH 46 3806#define FSF_AZ_TX_KER_BUF_ADDR_DW0_LBN 0 3807#define FSF_AZ_TX_KER_BUF_ADDR_DW0_WIDTH 32 3808#define FSF_AZ_TX_KER_BUF_ADDR_DW1_LBN 32 3809#define FSF_AZ_TX_KER_BUF_ADDR_DW1_WIDTH 14 3810 3811 3812/* FS_TX_USER_DESC */ 3813#define FSF_AZ_TX_USER_SW_EV_EN_LBN 48 3814#define FSF_AZ_TX_USER_SW_EV_EN_WIDTH 1 3815#define FSF_AZ_TX_USER_CONT_LBN 46 3816#define FSF_AZ_TX_USER_CONT_WIDTH 1 3817#define FSF_AZ_TX_USER_BYTE_CNT_LBN 33 3818#define FSF_AZ_TX_USER_BYTE_CNT_WIDTH 13 3819#define FSF_AZ_TX_USER_BUF_ID_LBN 13 3820#define FSF_AZ_TX_USER_BUF_ID_WIDTH 20 3821#define FSF_AZ_TX_USER_BYTE_OFS_LBN 0 3822#define FSF_AZ_TX_USER_BYTE_OFS_WIDTH 13 3823 3824 3825/* FS_USER_EV */ 3826#define FSF_CZ_USER_QID_LBN 32 3827#define FSF_CZ_USER_QID_WIDTH 10 3828#define FSF_CZ_USER_EV_REG_VALUE_LBN 0 3829#define FSF_CZ_USER_EV_REG_VALUE_WIDTH 32 3830 3831 3832/* FS_NET_IVEC */ 3833#define FSF_AZ_NET_IVEC_FATAL_INT_LBN 64 3834#define FSF_AZ_NET_IVEC_FATAL_INT_WIDTH 1 3835#define FSF_AZ_NET_IVEC_INT_Q_LBN 40 3836#define FSF_AZ_NET_IVEC_INT_Q_WIDTH 4 3837#define FSF_AZ_NET_IVEC_INT_FLAG_LBN 32 3838#define FSF_AZ_NET_IVEC_INT_FLAG_WIDTH 1 3839#define FSF_AZ_NET_IVEC_EVQ_FIFO_HF_LBN 1 3840#define FSF_AZ_NET_IVEC_EVQ_FIFO_HF_WIDTH 1 3841#define FSF_AZ_NET_IVEC_EVQ_FIFO_AF_LBN 0 3842#define FSF_AZ_NET_IVEC_EVQ_FIFO_AF_WIDTH 1 3843 3844 3845/* DRIVER_EV */ 3846/* Sub-fields of an RX flush completion event */ 3847#define FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL_LBN 12 3848#define FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL_WIDTH 1 3849#define FSF_AZ_DRIVER_EV_RX_DESCQ_ID_LBN 0 3850#define FSF_AZ_DRIVER_EV_RX_DESCQ_ID_WIDTH 12 3851 3852 3853 3854/************************************************************************** 3855 * 3856 * Falcon non-volatile configuration 3857 * 3858 ************************************************************************** 3859 */ 3860 3861 3862#define FR_AZ_TX_PACE_TBL_OFST FR_BZ_TX_PACE_TBL_OFST 3863 3864 3865#ifdef __cplusplus 3866} 3867#endif 3868 3869 3870 3871 3872#endif /* _SYS_EFX_REGS_H */ 3873