efx_impl.h revision 311500 
1/*-
2 * Copyright (c) 2007-2016 Solarflare Communications Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 *    this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 *    this list of conditions and the following disclaimer in the documentation
12 *    and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
29 *
30 * $FreeBSD: stable/10/sys/dev/sfxge/common/efx_impl.h 311500 2017-01-06 07:38:12Z arybchik $
31 */
32
33#ifndef	_SYS_EFX_IMPL_H
34#define	_SYS_EFX_IMPL_H
35
36#include "efx.h"
37#include "efx_regs.h"
38#include "efx_regs_ef10.h"
39
40/* FIXME: Add definition for driver generated software events */
41#ifndef	ESE_DZ_EV_CODE_DRV_GEN_EV
42#define	ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
43#endif
44
45
46#if EFSYS_OPT_SIENA
47#include "siena_impl.h"
48#endif	/* EFSYS_OPT_SIENA */
49
50#if EFSYS_OPT_HUNTINGTON
51#include "hunt_impl.h"
52#endif	/* EFSYS_OPT_HUNTINGTON */
53
54#if EFSYS_OPT_MEDFORD
55#include "medford_impl.h"
56#endif	/* EFSYS_OPT_MEDFORD */
57
58#if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
59#include "ef10_impl.h"
60#endif	/* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
61
62#ifdef	__cplusplus
63extern "C" {
64#endif
65
66#define	EFX_MOD_MCDI		0x00000001
67#define	EFX_MOD_PROBE		0x00000002
68#define	EFX_MOD_NVRAM		0x00000004
69#define	EFX_MOD_VPD		0x00000008
70#define	EFX_MOD_NIC		0x00000010
71#define	EFX_MOD_INTR		0x00000020
72#define	EFX_MOD_EV		0x00000040
73#define	EFX_MOD_RX		0x00000080
74#define	EFX_MOD_TX		0x00000100
75#define	EFX_MOD_PORT		0x00000200
76#define	EFX_MOD_MON		0x00000400
77#define	EFX_MOD_FILTER		0x00001000
78#define	EFX_MOD_LIC		0x00002000
79
80#define	EFX_RESET_PHY		0x00000001
81#define	EFX_RESET_RXQ_ERR	0x00000002
82#define	EFX_RESET_TXQ_ERR	0x00000004
83
84typedef enum efx_mac_type_e {
85	EFX_MAC_INVALID = 0,
86	EFX_MAC_SIENA,
87	EFX_MAC_HUNTINGTON,
88	EFX_MAC_MEDFORD,
89	EFX_MAC_NTYPES
90} efx_mac_type_t;
91
92typedef struct efx_ev_ops_s {
93	efx_rc_t	(*eevo_init)(efx_nic_t *);
94	void		(*eevo_fini)(efx_nic_t *);
95	efx_rc_t	(*eevo_qcreate)(efx_nic_t *, unsigned int,
96					  efsys_mem_t *, size_t, uint32_t,
97					  uint32_t, uint32_t, efx_evq_t *);
98	void		(*eevo_qdestroy)(efx_evq_t *);
99	efx_rc_t	(*eevo_qprime)(efx_evq_t *, unsigned int);
100	void		(*eevo_qpost)(efx_evq_t *, uint16_t);
101	efx_rc_t	(*eevo_qmoderate)(efx_evq_t *, unsigned int);
102#if EFSYS_OPT_QSTATS
103	void		(*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
104#endif
105} efx_ev_ops_t;
106
107typedef struct efx_tx_ops_s {
108	efx_rc_t	(*etxo_init)(efx_nic_t *);
109	void		(*etxo_fini)(efx_nic_t *);
110	efx_rc_t	(*etxo_qcreate)(efx_nic_t *,
111					unsigned int, unsigned int,
112					efsys_mem_t *, size_t,
113					uint32_t, uint16_t,
114					efx_evq_t *, efx_txq_t *,
115					unsigned int *);
116	void		(*etxo_qdestroy)(efx_txq_t *);
117	efx_rc_t	(*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
118				      unsigned int, unsigned int,
119				      unsigned int *);
120	void		(*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
121	efx_rc_t	(*etxo_qpace)(efx_txq_t *, unsigned int);
122	efx_rc_t	(*etxo_qflush)(efx_txq_t *);
123	void		(*etxo_qenable)(efx_txq_t *);
124	efx_rc_t	(*etxo_qpio_enable)(efx_txq_t *);
125	void		(*etxo_qpio_disable)(efx_txq_t *);
126	efx_rc_t	(*etxo_qpio_write)(efx_txq_t *, uint8_t *, size_t,
127					   size_t);
128	efx_rc_t	(*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
129					   unsigned int *);
130	efx_rc_t	(*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
131				      unsigned int, unsigned int,
132				      unsigned int *);
133	void		(*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
134						size_t, boolean_t,
135						efx_desc_t *);
136	void		(*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
137						uint32_t, uint8_t,
138						efx_desc_t *);
139	void		(*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
140						uint32_t, uint16_t,
141						efx_desc_t *, int);
142	void		(*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
143						efx_desc_t *);
144#if EFSYS_OPT_QSTATS
145	void		(*etxo_qstats_update)(efx_txq_t *,
146					      efsys_stat_t *);
147#endif
148} efx_tx_ops_t;
149
150typedef struct efx_rx_ops_s {
151	efx_rc_t	(*erxo_init)(efx_nic_t *);
152	void		(*erxo_fini)(efx_nic_t *);
153#if EFSYS_OPT_RX_SCATTER
154	efx_rc_t	(*erxo_scatter_enable)(efx_nic_t *, unsigned int);
155#endif
156#if EFSYS_OPT_RX_SCALE
157	efx_rc_t	(*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t,
158					       efx_rx_hash_type_t, boolean_t);
159	efx_rc_t	(*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t);
160	efx_rc_t	(*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *,
161					      size_t);
162	uint32_t	(*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
163					    uint8_t *);
164#endif /* EFSYS_OPT_RX_SCALE */
165	efx_rc_t	(*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
166					      uint16_t *);
167	void		(*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
168				      unsigned int, unsigned int,
169				      unsigned int);
170	void		(*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
171	efx_rc_t	(*erxo_qflush)(efx_rxq_t *);
172	void		(*erxo_qenable)(efx_rxq_t *);
173	efx_rc_t	(*erxo_qcreate)(efx_nic_t *enp, unsigned int,
174					unsigned int, efx_rxq_type_t,
175					efsys_mem_t *, size_t, uint32_t,
176					efx_evq_t *, efx_rxq_t *);
177	void		(*erxo_qdestroy)(efx_rxq_t *);
178} efx_rx_ops_t;
179
180typedef struct efx_mac_ops_s {
181	efx_rc_t	(*emo_poll)(efx_nic_t *, efx_link_mode_t *);
182	efx_rc_t	(*emo_up)(efx_nic_t *, boolean_t *);
183	efx_rc_t	(*emo_addr_set)(efx_nic_t *);
184	efx_rc_t	(*emo_pdu_set)(efx_nic_t *);
185	efx_rc_t	(*emo_pdu_get)(efx_nic_t *, size_t *);
186	efx_rc_t	(*emo_reconfigure)(efx_nic_t *);
187	efx_rc_t	(*emo_multicast_list_set)(efx_nic_t *);
188	efx_rc_t	(*emo_filter_default_rxq_set)(efx_nic_t *,
189						      efx_rxq_t *, boolean_t);
190	void		(*emo_filter_default_rxq_clear)(efx_nic_t *);
191#if EFSYS_OPT_LOOPBACK
192	efx_rc_t	(*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
193					    efx_loopback_type_t);
194#endif	/* EFSYS_OPT_LOOPBACK */
195#if EFSYS_OPT_MAC_STATS
196	efx_rc_t	(*emo_stats_get_mask)(efx_nic_t *, uint32_t *, size_t);
197	efx_rc_t	(*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
198	efx_rc_t	(*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
199					      uint16_t, boolean_t);
200	efx_rc_t	(*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
201					    efsys_stat_t *, uint32_t *);
202#endif	/* EFSYS_OPT_MAC_STATS */
203} efx_mac_ops_t;
204
205typedef struct efx_phy_ops_s {
206	efx_rc_t	(*epo_power)(efx_nic_t *, boolean_t); /* optional */
207	efx_rc_t	(*epo_reset)(efx_nic_t *);
208	efx_rc_t	(*epo_reconfigure)(efx_nic_t *);
209	efx_rc_t	(*epo_verify)(efx_nic_t *);
210	efx_rc_t	(*epo_oui_get)(efx_nic_t *, uint32_t *);
211#if EFSYS_OPT_PHY_STATS
212	efx_rc_t	(*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
213					    uint32_t *);
214#endif	/* EFSYS_OPT_PHY_STATS */
215#if EFSYS_OPT_BIST
216	efx_rc_t	(*epo_bist_enable_offline)(efx_nic_t *);
217	efx_rc_t	(*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
218	efx_rc_t	(*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
219					 efx_bist_result_t *, uint32_t *,
220					 unsigned long *, size_t);
221	void		(*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
222#endif	/* EFSYS_OPT_BIST */
223} efx_phy_ops_t;
224
225#if EFSYS_OPT_FILTER
226typedef struct efx_filter_ops_s {
227	efx_rc_t	(*efo_init)(efx_nic_t *);
228	void		(*efo_fini)(efx_nic_t *);
229	efx_rc_t	(*efo_restore)(efx_nic_t *);
230	efx_rc_t	(*efo_add)(efx_nic_t *, efx_filter_spec_t *,
231				   boolean_t may_replace);
232	efx_rc_t	(*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
233	efx_rc_t	(*efo_supported_filters)(efx_nic_t *, uint32_t *,
234				   size_t, size_t *);
235	efx_rc_t	(*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
236				   boolean_t, boolean_t, boolean_t,
237				   uint8_t const *, uint32_t);
238} efx_filter_ops_t;
239
240extern	__checkReturn	efx_rc_t
241efx_filter_reconfigure(
242	__in				efx_nic_t *enp,
243	__in_ecount(6)			uint8_t const *mac_addr,
244	__in				boolean_t all_unicst,
245	__in				boolean_t mulcst,
246	__in				boolean_t all_mulcst,
247	__in				boolean_t brdcst,
248	__in_ecount(6*count)		uint8_t const *addrs,
249	__in				uint32_t count);
250
251#endif /* EFSYS_OPT_FILTER */
252
253
254typedef struct efx_port_s {
255	efx_mac_type_t		ep_mac_type;
256	uint32_t		ep_phy_type;
257	uint8_t			ep_port;
258	uint32_t		ep_mac_pdu;
259	uint8_t			ep_mac_addr[6];
260	efx_link_mode_t		ep_link_mode;
261	boolean_t		ep_all_unicst;
262	boolean_t		ep_mulcst;
263	boolean_t		ep_all_mulcst;
264	boolean_t		ep_brdcst;
265	unsigned int		ep_fcntl;
266	boolean_t		ep_fcntl_autoneg;
267	efx_oword_t		ep_multicst_hash[2];
268	uint8_t			ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
269						    EFX_MAC_MULTICAST_LIST_MAX];
270	uint32_t		ep_mulcst_addr_count;
271#if EFSYS_OPT_LOOPBACK
272	efx_loopback_type_t	ep_loopback_type;
273	efx_link_mode_t		ep_loopback_link_mode;
274#endif	/* EFSYS_OPT_LOOPBACK */
275#if EFSYS_OPT_PHY_FLAGS
276	uint32_t		ep_phy_flags;
277#endif	/* EFSYS_OPT_PHY_FLAGS */
278#if EFSYS_OPT_PHY_LED_CONTROL
279	efx_phy_led_mode_t	ep_phy_led_mode;
280#endif	/* EFSYS_OPT_PHY_LED_CONTROL */
281	efx_phy_media_type_t	ep_fixed_port_type;
282	efx_phy_media_type_t	ep_module_type;
283	uint32_t		ep_adv_cap_mask;
284	uint32_t		ep_lp_cap_mask;
285	uint32_t		ep_default_adv_cap_mask;
286	uint32_t		ep_phy_cap_mask;
287	boolean_t		ep_mac_drain;
288	boolean_t		ep_mac_stats_pending;
289#if EFSYS_OPT_BIST
290	efx_bist_type_t		ep_current_bist;
291#endif
292	const efx_mac_ops_t	*ep_emop;
293	const efx_phy_ops_t	*ep_epop;
294} efx_port_t;
295
296typedef struct efx_mon_ops_s {
297#if EFSYS_OPT_MON_STATS
298	efx_rc_t	(*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
299					    efx_mon_stat_value_t *);
300#endif	/* EFSYS_OPT_MON_STATS */
301} efx_mon_ops_t;
302
303typedef struct efx_mon_s {
304	efx_mon_type_t		em_type;
305	const efx_mon_ops_t	*em_emop;
306} efx_mon_t;
307
308typedef struct efx_intr_ops_s {
309	efx_rc_t	(*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
310	void		(*eio_enable)(efx_nic_t *);
311	void		(*eio_disable)(efx_nic_t *);
312	void		(*eio_disable_unlocked)(efx_nic_t *);
313	efx_rc_t	(*eio_trigger)(efx_nic_t *, unsigned int);
314	void		(*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
315	void		(*eio_status_message)(efx_nic_t *, unsigned int,
316				 boolean_t *);
317	void		(*eio_fatal)(efx_nic_t *);
318	void		(*eio_fini)(efx_nic_t *);
319} efx_intr_ops_t;
320
321typedef struct efx_intr_s {
322	const efx_intr_ops_t	*ei_eiop;
323	efsys_mem_t		*ei_esmp;
324	efx_intr_type_t		ei_type;
325	unsigned int		ei_level;
326} efx_intr_t;
327
328typedef struct efx_nic_ops_s {
329	efx_rc_t	(*eno_probe)(efx_nic_t *);
330	efx_rc_t	(*eno_board_cfg)(efx_nic_t *);
331	efx_rc_t	(*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
332	efx_rc_t	(*eno_reset)(efx_nic_t *);
333	efx_rc_t	(*eno_init)(efx_nic_t *);
334	efx_rc_t	(*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
335	efx_rc_t	(*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
336					uint32_t *, size_t *);
337#if EFSYS_OPT_DIAG
338	efx_rc_t	(*eno_register_test)(efx_nic_t *);
339#endif	/* EFSYS_OPT_DIAG */
340	void		(*eno_fini)(efx_nic_t *);
341	void		(*eno_unprobe)(efx_nic_t *);
342} efx_nic_ops_t;
343
344#ifndef EFX_TXQ_LIMIT_TARGET
345#define	EFX_TXQ_LIMIT_TARGET 259
346#endif
347#ifndef EFX_RXQ_LIMIT_TARGET
348#define	EFX_RXQ_LIMIT_TARGET 512
349#endif
350#ifndef EFX_TXQ_DC_SIZE
351#define	EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
352#endif
353#ifndef EFX_RXQ_DC_SIZE
354#define	EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
355#endif
356
357#if EFSYS_OPT_FILTER
358
359typedef struct siena_filter_spec_s {
360	uint8_t		sfs_type;
361	uint32_t	sfs_flags;
362	uint32_t	sfs_dmaq_id;
363	uint32_t	sfs_dword[3];
364} siena_filter_spec_t;
365
366typedef enum siena_filter_type_e {
367	EFX_SIENA_FILTER_RX_TCP_FULL,	/* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
368	EFX_SIENA_FILTER_RX_TCP_WILD,	/* TCP/IPv4 {dIP,dTCP,  -,   -} */
369	EFX_SIENA_FILTER_RX_UDP_FULL,	/* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
370	EFX_SIENA_FILTER_RX_UDP_WILD,	/* UDP/IPv4 {dIP,dUDP,  -,   -} */
371	EFX_SIENA_FILTER_RX_MAC_FULL,	/* Ethernet {dMAC,VLAN} */
372	EFX_SIENA_FILTER_RX_MAC_WILD,	/* Ethernet {dMAC,   -} */
373
374	EFX_SIENA_FILTER_TX_TCP_FULL,	/* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
375	EFX_SIENA_FILTER_TX_TCP_WILD,	/* TCP/IPv4 {  -,   -,sIP,sTCP} */
376	EFX_SIENA_FILTER_TX_UDP_FULL,	/* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
377	EFX_SIENA_FILTER_TX_UDP_WILD,	/* UDP/IPv4 {  -,   -,sIP,sUDP} */
378	EFX_SIENA_FILTER_TX_MAC_FULL,	/* Ethernet {sMAC,VLAN} */
379	EFX_SIENA_FILTER_TX_MAC_WILD,	/* Ethernet {sMAC,   -} */
380
381	EFX_SIENA_FILTER_NTYPES
382} siena_filter_type_t;
383
384typedef enum siena_filter_tbl_id_e {
385	EFX_SIENA_FILTER_TBL_RX_IP = 0,
386	EFX_SIENA_FILTER_TBL_RX_MAC,
387	EFX_SIENA_FILTER_TBL_TX_IP,
388	EFX_SIENA_FILTER_TBL_TX_MAC,
389	EFX_SIENA_FILTER_NTBLS
390} siena_filter_tbl_id_t;
391
392typedef struct siena_filter_tbl_s {
393	int			sft_size;	/* number of entries */
394	int			sft_used;	/* active count */
395	uint32_t		*sft_bitmap;	/* active bitmap */
396	siena_filter_spec_t	*sft_spec;	/* array of saved specs */
397} siena_filter_tbl_t;
398
399typedef struct siena_filter_s {
400	siena_filter_tbl_t	sf_tbl[EFX_SIENA_FILTER_NTBLS];
401	unsigned int		sf_depth[EFX_SIENA_FILTER_NTYPES];
402} siena_filter_t;
403
404typedef struct efx_filter_s {
405#if EFSYS_OPT_SIENA
406	siena_filter_t		*ef_siena_filter;
407#endif /* EFSYS_OPT_SIENA */
408#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
409	ef10_filter_table_t	*ef_ef10_filter_table;
410#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
411} efx_filter_t;
412
413extern			void
414siena_filter_tbl_clear(
415	__in		efx_nic_t *enp,
416	__in		siena_filter_tbl_id_t tbl);
417
418#endif	/* EFSYS_OPT_FILTER */
419
420#if EFSYS_OPT_MCDI
421
422typedef struct efx_mcdi_ops_s {
423	efx_rc_t	(*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
424	void		(*emco_send_request)(efx_nic_t *, void *, size_t,
425					void *, size_t);
426	efx_rc_t	(*emco_poll_reboot)(efx_nic_t *);
427	boolean_t	(*emco_poll_response)(efx_nic_t *);
428	void		(*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
429	void		(*emco_fini)(efx_nic_t *);
430	efx_rc_t	(*emco_feature_supported)(efx_nic_t *,
431					    efx_mcdi_feature_id_t, boolean_t *);
432	void		(*emco_get_timeout)(efx_nic_t *, efx_mcdi_req_t *,
433					    uint32_t *);
434} efx_mcdi_ops_t;
435
436typedef struct efx_mcdi_s {
437	const efx_mcdi_ops_t		*em_emcop;
438	const efx_mcdi_transport_t	*em_emtp;
439	efx_mcdi_iface_t		em_emip;
440} efx_mcdi_t;
441
442#endif /* EFSYS_OPT_MCDI */
443
444#if EFSYS_OPT_NVRAM
445typedef struct efx_nvram_ops_s {
446#if EFSYS_OPT_DIAG
447	efx_rc_t	(*envo_test)(efx_nic_t *);
448#endif	/* EFSYS_OPT_DIAG */
449	efx_rc_t	(*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
450					    uint32_t *);
451	efx_rc_t	(*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
452	efx_rc_t	(*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
453	efx_rc_t	(*envo_partn_read)(efx_nic_t *, uint32_t,
454					    unsigned int, caddr_t, size_t);
455	efx_rc_t	(*envo_partn_erase)(efx_nic_t *, uint32_t,
456					    unsigned int, size_t);
457	efx_rc_t	(*envo_partn_write)(efx_nic_t *, uint32_t,
458					    unsigned int, caddr_t, size_t);
459	efx_rc_t	(*envo_partn_rw_finish)(efx_nic_t *, uint32_t);
460	efx_rc_t	(*envo_partn_get_version)(efx_nic_t *, uint32_t,
461					    uint32_t *, uint16_t *);
462	efx_rc_t	(*envo_partn_set_version)(efx_nic_t *, uint32_t,
463					    uint16_t *);
464	efx_rc_t	(*envo_buffer_validate)(efx_nic_t *, uint32_t,
465					    caddr_t, size_t);
466} efx_nvram_ops_t;
467#endif /* EFSYS_OPT_NVRAM */
468
469#if EFSYS_OPT_VPD
470typedef struct efx_vpd_ops_s {
471	efx_rc_t	(*evpdo_init)(efx_nic_t *);
472	efx_rc_t	(*evpdo_size)(efx_nic_t *, size_t *);
473	efx_rc_t	(*evpdo_read)(efx_nic_t *, caddr_t, size_t);
474	efx_rc_t	(*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
475	efx_rc_t	(*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
476	efx_rc_t	(*evpdo_get)(efx_nic_t *, caddr_t, size_t,
477					efx_vpd_value_t *);
478	efx_rc_t	(*evpdo_set)(efx_nic_t *, caddr_t, size_t,
479					efx_vpd_value_t *);
480	efx_rc_t	(*evpdo_next)(efx_nic_t *, caddr_t, size_t,
481					efx_vpd_value_t *, unsigned int *);
482	efx_rc_t	(*evpdo_write)(efx_nic_t *, caddr_t, size_t);
483	void		(*evpdo_fini)(efx_nic_t *);
484} efx_vpd_ops_t;
485#endif	/* EFSYS_OPT_VPD */
486
487#if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
488
489	__checkReturn		efx_rc_t
490efx_mcdi_nvram_partitions(
491	__in			efx_nic_t *enp,
492	__out_bcount(size)	caddr_t data,
493	__in			size_t size,
494	__out			unsigned int *npartnp);
495
496	__checkReturn		efx_rc_t
497efx_mcdi_nvram_metadata(
498	__in			efx_nic_t *enp,
499	__in			uint32_t partn,
500	__out			uint32_t *subtypep,
501	__out_ecount(4)		uint16_t version[4],
502	__out_bcount_opt(size)	char *descp,
503	__in			size_t size);
504
505	__checkReturn		efx_rc_t
506efx_mcdi_nvram_info(
507	__in			efx_nic_t *enp,
508	__in			uint32_t partn,
509	__out_opt		size_t *sizep,
510	__out_opt		uint32_t *addressp,
511	__out_opt		uint32_t *erase_sizep,
512	__out_opt		uint32_t *write_sizep);
513
514	__checkReturn		efx_rc_t
515efx_mcdi_nvram_update_start(
516	__in			efx_nic_t *enp,
517	__in			uint32_t partn);
518
519	__checkReturn		efx_rc_t
520efx_mcdi_nvram_read(
521	__in			efx_nic_t *enp,
522	__in			uint32_t partn,
523	__in			uint32_t offset,
524	__out_bcount(size)	caddr_t data,
525	__in			size_t size,
526	__in			uint32_t mode);
527
528	__checkReturn		efx_rc_t
529efx_mcdi_nvram_erase(
530	__in			efx_nic_t *enp,
531	__in			uint32_t partn,
532	__in			uint32_t offset,
533	__in			size_t size);
534
535	__checkReturn		efx_rc_t
536efx_mcdi_nvram_write(
537	__in			efx_nic_t *enp,
538	__in			uint32_t partn,
539	__in			uint32_t offset,
540	__out_bcount(size)	caddr_t data,
541	__in			size_t size);
542
543	__checkReturn		efx_rc_t
544efx_mcdi_nvram_update_finish(
545	__in			efx_nic_t *enp,
546	__in			uint32_t partn,
547	__in			boolean_t reboot,
548	__out_opt		uint32_t *resultp);
549
550#if EFSYS_OPT_DIAG
551
552	__checkReturn		efx_rc_t
553efx_mcdi_nvram_test(
554	__in			efx_nic_t *enp,
555	__in			uint32_t partn);
556
557#endif	/* EFSYS_OPT_DIAG */
558
559#endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
560
561#if EFSYS_OPT_LICENSING
562
563typedef struct efx_lic_ops_s {
564	efx_rc_t	(*elo_update_licenses)(efx_nic_t *);
565	efx_rc_t	(*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
566	efx_rc_t	(*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
567	efx_rc_t	(*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
568				      size_t *, uint8_t *);
569	efx_rc_t	(*elo_find_start)
570				(efx_nic_t *, caddr_t, size_t, uint32_t *);
571	efx_rc_t	(*elo_find_end)(efx_nic_t *, caddr_t, size_t,
572				uint32_t, uint32_t *);
573	boolean_t	(*elo_find_key)(efx_nic_t *, caddr_t, size_t,
574				uint32_t, uint32_t *, uint32_t *);
575	boolean_t	(*elo_validate_key)(efx_nic_t *,
576				caddr_t, uint32_t);
577	efx_rc_t	(*elo_read_key)(efx_nic_t *,
578				caddr_t, size_t, uint32_t, uint32_t,
579				caddr_t, size_t, uint32_t *);
580	efx_rc_t	(*elo_write_key)(efx_nic_t *,
581				caddr_t, size_t, uint32_t,
582				caddr_t, uint32_t, uint32_t *);
583	efx_rc_t	(*elo_delete_key)(efx_nic_t *,
584				caddr_t, size_t, uint32_t,
585				uint32_t, uint32_t, uint32_t *);
586	efx_rc_t	(*elo_create_partition)(efx_nic_t *,
587				caddr_t, size_t);
588	efx_rc_t	(*elo_finish_partition)(efx_nic_t *,
589				caddr_t, size_t);
590} efx_lic_ops_t;
591
592#endif
593
594typedef struct efx_drv_cfg_s {
595	uint32_t		edc_min_vi_count;
596	uint32_t		edc_max_vi_count;
597
598	uint32_t		edc_max_piobuf_count;
599	uint32_t		edc_pio_alloc_size;
600} efx_drv_cfg_t;
601
602struct efx_nic_s {
603	uint32_t		en_magic;
604	efx_family_t		en_family;
605	uint32_t		en_features;
606	efsys_identifier_t	*en_esip;
607	efsys_lock_t		*en_eslp;
608	efsys_bar_t		*en_esbp;
609	unsigned int		en_mod_flags;
610	unsigned int		en_reset_flags;
611	efx_nic_cfg_t		en_nic_cfg;
612	efx_drv_cfg_t		en_drv_cfg;
613	efx_port_t		en_port;
614	efx_mon_t		en_mon;
615	efx_intr_t		en_intr;
616	uint32_t		en_ev_qcount;
617	uint32_t		en_rx_qcount;
618	uint32_t		en_tx_qcount;
619	const efx_nic_ops_t	*en_enop;
620	const efx_ev_ops_t	*en_eevop;
621	const efx_tx_ops_t	*en_etxop;
622	const efx_rx_ops_t	*en_erxop;
623#if EFSYS_OPT_FILTER
624	efx_filter_t		en_filter;
625	const efx_filter_ops_t	*en_efop;
626#endif	/* EFSYS_OPT_FILTER */
627#if EFSYS_OPT_MCDI
628	efx_mcdi_t		en_mcdi;
629#endif	/* EFSYS_OPT_MCDI */
630#if EFSYS_OPT_NVRAM
631	efx_nvram_type_t	en_nvram_locked;
632	const efx_nvram_ops_t	*en_envop;
633#endif	/* EFSYS_OPT_NVRAM */
634#if EFSYS_OPT_VPD
635	const efx_vpd_ops_t	*en_evpdop;
636#endif	/* EFSYS_OPT_VPD */
637#if EFSYS_OPT_RX_SCALE
638	efx_rx_hash_support_t	en_hash_support;
639	efx_rx_scale_support_t	en_rss_support;
640	uint32_t		en_rss_context;
641#endif	/* EFSYS_OPT_RX_SCALE */
642	uint32_t		en_vport_id;
643#if EFSYS_OPT_LICENSING
644	const efx_lic_ops_t	*en_elop;
645	boolean_t		en_licensing_supported;
646#endif
647	union {
648#if EFSYS_OPT_SIENA
649		struct {
650#if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
651			unsigned int		enu_partn_mask;
652#endif	/* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
653#if EFSYS_OPT_VPD
654			caddr_t			enu_svpd;
655			size_t			enu_svpd_length;
656#endif	/* EFSYS_OPT_VPD */
657			int			enu_unused;
658		} siena;
659#endif	/* EFSYS_OPT_SIENA */
660		int	enu_unused;
661	} en_u;
662#if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
663	union en_arch {
664		struct {
665			int			ena_vi_base;
666			int			ena_vi_count;
667			int			ena_vi_shift;
668#if EFSYS_OPT_VPD
669			caddr_t			ena_svpd;
670			size_t			ena_svpd_length;
671#endif	/* EFSYS_OPT_VPD */
672			efx_piobuf_handle_t	ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
673			uint32_t		ena_piobuf_count;
674			uint32_t		ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
675			uint32_t		ena_pio_write_vi_base;
676			/* Memory BAR mapping regions */
677			uint32_t		ena_uc_mem_map_offset;
678			size_t			ena_uc_mem_map_size;
679			uint32_t		ena_wc_mem_map_offset;
680			size_t			ena_wc_mem_map_size;
681		} ef10;
682	} en_arch;
683#endif	/* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
684};
685
686
687#define	EFX_NIC_MAGIC	0x02121996
688
689typedef	boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
690    const efx_ev_callbacks_t *, void *);
691
692typedef struct efx_evq_rxq_state_s {
693	unsigned int			eers_rx_read_ptr;
694	unsigned int			eers_rx_mask;
695} efx_evq_rxq_state_t;
696
697struct efx_evq_s {
698	uint32_t			ee_magic;
699	efx_nic_t			*ee_enp;
700	unsigned int			ee_index;
701	unsigned int			ee_mask;
702	efsys_mem_t			*ee_esmp;
703#if EFSYS_OPT_QSTATS
704	uint32_t			ee_stat[EV_NQSTATS];
705#endif	/* EFSYS_OPT_QSTATS */
706
707	efx_ev_handler_t		ee_rx;
708	efx_ev_handler_t		ee_tx;
709	efx_ev_handler_t		ee_driver;
710	efx_ev_handler_t		ee_global;
711	efx_ev_handler_t		ee_drv_gen;
712#if EFSYS_OPT_MCDI
713	efx_ev_handler_t		ee_mcdi;
714#endif	/* EFSYS_OPT_MCDI */
715
716	efx_evq_rxq_state_t		ee_rxq_state[EFX_EV_RX_NLABELS];
717
718	uint32_t			ee_flags;
719};
720
721#define	EFX_EVQ_MAGIC	0x08081997
722
723#define	EFX_EVQ_SIENA_TIMER_QUANTUM_NS	6144 /* 768 cycles */
724
725struct efx_rxq_s {
726	uint32_t			er_magic;
727	efx_nic_t			*er_enp;
728	efx_evq_t			*er_eep;
729	unsigned int			er_index;
730	unsigned int			er_label;
731	unsigned int			er_mask;
732	efsys_mem_t			*er_esmp;
733};
734
735#define	EFX_RXQ_MAGIC	0x15022005
736
737struct efx_txq_s {
738	uint32_t			et_magic;
739	efx_nic_t			*et_enp;
740	unsigned int			et_index;
741	unsigned int			et_mask;
742	efsys_mem_t			*et_esmp;
743#if EFSYS_OPT_HUNTINGTON
744	uint32_t			et_pio_bufnum;
745	uint32_t			et_pio_blknum;
746	uint32_t			et_pio_write_offset;
747	uint32_t			et_pio_offset;
748	size_t				et_pio_size;
749#endif
750#if EFSYS_OPT_QSTATS
751	uint32_t			et_stat[TX_NQSTATS];
752#endif	/* EFSYS_OPT_QSTATS */
753};
754
755#define	EFX_TXQ_MAGIC	0x05092005
756
757#define	EFX_MAC_ADDR_COPY(_dst, _src)					\
758	do {								\
759		(_dst)[0] = (_src)[0];					\
760		(_dst)[1] = (_src)[1];					\
761		(_dst)[2] = (_src)[2];					\
762		(_dst)[3] = (_src)[3];					\
763		(_dst)[4] = (_src)[4];					\
764		(_dst)[5] = (_src)[5];					\
765	_NOTE(CONSTANTCONDITION)					\
766	} while (B_FALSE)
767
768#define	EFX_MAC_BROADCAST_ADDR_SET(_dst)				\
769	do {								\
770		uint16_t *_d = (uint16_t *)(_dst);			\
771		_d[0] = 0xffff;						\
772		_d[1] = 0xffff;						\
773		_d[2] = 0xffff;						\
774	_NOTE(CONSTANTCONDITION)					\
775	} while (B_FALSE)
776
777#if EFSYS_OPT_CHECK_REG
778#define	EFX_CHECK_REG(_enp, _reg)					\
779	do {								\
780		const char *name = #_reg;				\
781		char min = name[4];					\
782		char max = name[5];					\
783		char rev;						\
784									\
785		switch ((_enp)->en_family) {				\
786		case EFX_FAMILY_SIENA:					\
787			rev = 'C';					\
788			break;						\
789									\
790		case EFX_FAMILY_HUNTINGTON:				\
791			rev = 'D';					\
792			break;						\
793									\
794		case EFX_FAMILY_MEDFORD:				\
795			rev = 'E';					\
796			break;						\
797									\
798		default:						\
799			rev = '?';					\
800			break;						\
801		}							\
802									\
803		EFSYS_ASSERT3S(rev, >=, min);				\
804		EFSYS_ASSERT3S(rev, <=, max);				\
805									\
806	_NOTE(CONSTANTCONDITION)					\
807	} while (B_FALSE)
808#else
809#define	EFX_CHECK_REG(_enp, _reg) do {					\
810	_NOTE(CONSTANTCONDITION)					\
811	} while (B_FALSE)
812#endif
813
814#define	EFX_BAR_READD(_enp, _reg, _edp, _lock)				\
815	do {								\
816		EFX_CHECK_REG((_enp), (_reg));				\
817		EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,		\
818		    (_edp), (_lock));					\
819		EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,	\
820		    uint32_t, _reg ## _OFST,				\
821		    uint32_t, (_edp)->ed_u32[0]);			\
822	_NOTE(CONSTANTCONDITION)					\
823	} while (B_FALSE)
824
825#define	EFX_BAR_WRITED(_enp, _reg, _edp, _lock)				\
826	do {								\
827		EFX_CHECK_REG((_enp), (_reg));				\
828		EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,	\
829		    uint32_t, _reg ## _OFST,				\
830		    uint32_t, (_edp)->ed_u32[0]);			\
831		EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,	\
832		    (_edp), (_lock));					\
833	_NOTE(CONSTANTCONDITION)					\
834	} while (B_FALSE)
835
836#define	EFX_BAR_READQ(_enp, _reg, _eqp)					\
837	do {								\
838		EFX_CHECK_REG((_enp), (_reg));				\
839		EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,		\
840		    (_eqp));						\
841		EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,	\
842		    uint32_t, _reg ## _OFST,				\
843		    uint32_t, (_eqp)->eq_u32[1],			\
844		    uint32_t, (_eqp)->eq_u32[0]);			\
845	_NOTE(CONSTANTCONDITION)					\
846	} while (B_FALSE)
847
848#define	EFX_BAR_WRITEQ(_enp, _reg, _eqp)				\
849	do {								\
850		EFX_CHECK_REG((_enp), (_reg));				\
851		EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,	\
852		    uint32_t, _reg ## _OFST,				\
853		    uint32_t, (_eqp)->eq_u32[1],			\
854		    uint32_t, (_eqp)->eq_u32[0]);			\
855		EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,	\
856		    (_eqp));						\
857	_NOTE(CONSTANTCONDITION)					\
858	} while (B_FALSE)
859
860#define	EFX_BAR_READO(_enp, _reg, _eop)					\
861	do {								\
862		EFX_CHECK_REG((_enp), (_reg));				\
863		EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,		\
864		    (_eop), B_TRUE);					\
865		EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,	\
866		    uint32_t, _reg ## _OFST,				\
867		    uint32_t, (_eop)->eo_u32[3],			\
868		    uint32_t, (_eop)->eo_u32[2],			\
869		    uint32_t, (_eop)->eo_u32[1],			\
870		    uint32_t, (_eop)->eo_u32[0]);			\
871	_NOTE(CONSTANTCONDITION)					\
872	} while (B_FALSE)
873
874#define	EFX_BAR_WRITEO(_enp, _reg, _eop)				\
875	do {								\
876		EFX_CHECK_REG((_enp), (_reg));				\
877		EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,	\
878		    uint32_t, _reg ## _OFST,				\
879		    uint32_t, (_eop)->eo_u32[3],			\
880		    uint32_t, (_eop)->eo_u32[2],			\
881		    uint32_t, (_eop)->eo_u32[1],			\
882		    uint32_t, (_eop)->eo_u32[0]);			\
883		EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,	\
884		    (_eop), B_TRUE);					\
885	_NOTE(CONSTANTCONDITION)					\
886	} while (B_FALSE)
887
888#define	EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)		\
889	do {								\
890		EFX_CHECK_REG((_enp), (_reg));				\
891		EFSYS_BAR_READD((_enp)->en_esbp,			\
892		    (_reg ## _OFST + ((_index) * _reg ## _STEP)),	\
893		    (_edp), (_lock));					\
894		EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,	\
895		    uint32_t, (_index),					\
896		    uint32_t, _reg ## _OFST,				\
897		    uint32_t, (_edp)->ed_u32[0]);			\
898	_NOTE(CONSTANTCONDITION)					\
899	} while (B_FALSE)
900
901#define	EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)		\
902	do {								\
903		EFX_CHECK_REG((_enp), (_reg));				\
904		EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,	\
905		    uint32_t, (_index),					\
906		    uint32_t, _reg ## _OFST,				\
907		    uint32_t, (_edp)->ed_u32[0]);			\
908		EFSYS_BAR_WRITED((_enp)->en_esbp,			\
909		    (_reg ## _OFST + ((_index) * _reg ## _STEP)),	\
910		    (_edp), (_lock));					\
911	_NOTE(CONSTANTCONDITION)					\
912	} while (B_FALSE)
913
914#define	EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock)		\
915	do {								\
916		EFX_CHECK_REG((_enp), (_reg));				\
917		EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,	\
918		    uint32_t, (_index),					\
919		    uint32_t, _reg ## _OFST,				\
920		    uint32_t, (_edp)->ed_u32[0]);			\
921		EFSYS_BAR_WRITED((_enp)->en_esbp,			\
922		    (_reg ## _OFST +					\
923		    (2 * sizeof (efx_dword_t)) +			\
924		    ((_index) * _reg ## _STEP)),			\
925		    (_edp), (_lock));					\
926	_NOTE(CONSTANTCONDITION)					\
927	} while (B_FALSE)
928
929#define	EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)		\
930	do {								\
931		EFX_CHECK_REG((_enp), (_reg));				\
932		EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,	\
933		    uint32_t, (_index),					\
934		    uint32_t, _reg ## _OFST,				\
935		    uint32_t, (_edp)->ed_u32[0]);			\
936		EFSYS_BAR_WRITED((_enp)->en_esbp,			\
937		    (_reg ## _OFST +					\
938		    (3 * sizeof (efx_dword_t)) +			\
939		    ((_index) * _reg ## _STEP)),			\
940		    (_edp), (_lock));					\
941	_NOTE(CONSTANTCONDITION)					\
942	} while (B_FALSE)
943
944#define	EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)			\
945	do {								\
946		EFX_CHECK_REG((_enp), (_reg));				\
947		EFSYS_BAR_READQ((_enp)->en_esbp,			\
948		    (_reg ## _OFST + ((_index) * _reg ## _STEP)),	\
949		    (_eqp));						\
950		EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,	\
951		    uint32_t, (_index),					\
952		    uint32_t, _reg ## _OFST,				\
953		    uint32_t, (_eqp)->eq_u32[1],			\
954		    uint32_t, (_eqp)->eq_u32[0]);			\
955	_NOTE(CONSTANTCONDITION)					\
956	} while (B_FALSE)
957
958#define	EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)			\
959	do {								\
960		EFX_CHECK_REG((_enp), (_reg));				\
961		EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,	\
962		    uint32_t, (_index),					\
963		    uint32_t, _reg ## _OFST,				\
964		    uint32_t, (_eqp)->eq_u32[1],			\
965		    uint32_t, (_eqp)->eq_u32[0]);			\
966		EFSYS_BAR_WRITEQ((_enp)->en_esbp,			\
967		    (_reg ## _OFST + ((_index) * _reg ## _STEP)),	\
968		    (_eqp));						\
969	_NOTE(CONSTANTCONDITION)					\
970	} while (B_FALSE)
971
972#define	EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)		\
973	do {								\
974		EFX_CHECK_REG((_enp), (_reg));				\
975		EFSYS_BAR_READO((_enp)->en_esbp,			\
976		    (_reg ## _OFST + ((_index) * _reg ## _STEP)),	\
977		    (_eop), (_lock));					\
978		EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,	\
979		    uint32_t, (_index),					\
980		    uint32_t, _reg ## _OFST,				\
981		    uint32_t, (_eop)->eo_u32[3],			\
982		    uint32_t, (_eop)->eo_u32[2],			\
983		    uint32_t, (_eop)->eo_u32[1],			\
984		    uint32_t, (_eop)->eo_u32[0]);			\
985	_NOTE(CONSTANTCONDITION)					\
986	} while (B_FALSE)
987
988#define	EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)		\
989	do {								\
990		EFX_CHECK_REG((_enp), (_reg));				\
991		EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,	\
992		    uint32_t, (_index),					\
993		    uint32_t, _reg ## _OFST,				\
994		    uint32_t, (_eop)->eo_u32[3],			\
995		    uint32_t, (_eop)->eo_u32[2],			\
996		    uint32_t, (_eop)->eo_u32[1],			\
997		    uint32_t, (_eop)->eo_u32[0]);			\
998		EFSYS_BAR_WRITEO((_enp)->en_esbp,			\
999		    (_reg ## _OFST + ((_index) * _reg ## _STEP)),	\
1000		    (_eop), (_lock));					\
1001	_NOTE(CONSTANTCONDITION)					\
1002	} while (B_FALSE)
1003
1004/*
1005 * Allow drivers to perform optimised 128-bit doorbell writes.
1006 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1007 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1008 * the need for locking in the host, and are the only ones known to be safe to
1009 * use 128-bites write with.
1010 */
1011#define	EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop)		\
1012	do {								\
1013		EFX_CHECK_REG((_enp), (_reg));				\
1014		EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo,		\
1015		    const char *,					\
1016		    #_reg,						\
1017		    uint32_t, (_index),					\
1018		    uint32_t, _reg ## _OFST,				\
1019		    uint32_t, (_eop)->eo_u32[3],			\
1020		    uint32_t, (_eop)->eo_u32[2],			\
1021		    uint32_t, (_eop)->eo_u32[1],			\
1022		    uint32_t, (_eop)->eo_u32[0]);			\
1023		EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,		\
1024		    (_reg ## _OFST + ((_index) * _reg ## _STEP)),	\
1025		    (_eop));						\
1026	_NOTE(CONSTANTCONDITION)					\
1027	} while (B_FALSE)
1028
1029#define	EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)	\
1030	do {								\
1031		unsigned int _new = (_wptr);				\
1032		unsigned int _old = (_owptr);				\
1033									\
1034		if ((_new) >= (_old))					\
1035			EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),		\
1036			    (_old) * sizeof (efx_desc_t),		\
1037			    ((_new) - (_old)) * sizeof (efx_desc_t));	\
1038		else							\
1039			/*						\
1040			 * It is cheaper to sync entire map than sync	\
1041			 * two parts especially when offset/size are	\
1042			 * ignored and entire map is synced in any case.\
1043			 */						\
1044			EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),		\
1045			    0,						\
1046			    (_entries) * sizeof (efx_desc_t));		\
1047	_NOTE(CONSTANTCONDITION)					\
1048	} while (B_FALSE)
1049
1050extern	__checkReturn	efx_rc_t
1051efx_nic_biu_test(
1052	__in		efx_nic_t *enp);
1053
1054extern	__checkReturn	efx_rc_t
1055efx_mac_select(
1056	__in		efx_nic_t *enp);
1057
1058extern	void
1059efx_mac_multicast_hash_compute(
1060	__in_ecount(6*count)		uint8_t const *addrs,
1061	__in				int count,
1062	__out				efx_oword_t *hash_low,
1063	__out				efx_oword_t *hash_high);
1064
1065extern	__checkReturn	efx_rc_t
1066efx_phy_probe(
1067	__in		efx_nic_t *enp);
1068
1069extern			void
1070efx_phy_unprobe(
1071	__in		efx_nic_t *enp);
1072
1073#if EFSYS_OPT_VPD
1074
1075/* VPD utility functions */
1076
1077extern	__checkReturn		efx_rc_t
1078efx_vpd_hunk_length(
1079	__in_bcount(size)	caddr_t data,
1080	__in			size_t size,
1081	__out			size_t *lengthp);
1082
1083extern	__checkReturn		efx_rc_t
1084efx_vpd_hunk_verify(
1085	__in_bcount(size)	caddr_t data,
1086	__in			size_t size,
1087	__out_opt		boolean_t *cksummedp);
1088
1089extern	__checkReturn		efx_rc_t
1090efx_vpd_hunk_reinit(
1091	__in_bcount(size)	caddr_t data,
1092	__in			size_t size,
1093	__in			boolean_t wantpid);
1094
1095extern	__checkReturn		efx_rc_t
1096efx_vpd_hunk_get(
1097	__in_bcount(size)	caddr_t data,
1098	__in			size_t size,
1099	__in			efx_vpd_tag_t tag,
1100	__in			efx_vpd_keyword_t keyword,
1101	__out			unsigned int *payloadp,
1102	__out			uint8_t *paylenp);
1103
1104extern	__checkReturn			efx_rc_t
1105efx_vpd_hunk_next(
1106	__in_bcount(size)		caddr_t data,
1107	__in				size_t size,
1108	__out				efx_vpd_tag_t *tagp,
1109	__out				efx_vpd_keyword_t *keyword,
1110	__out_opt			unsigned int *payloadp,
1111	__out_opt			uint8_t *paylenp,
1112	__inout				unsigned int *contp);
1113
1114extern	__checkReturn		efx_rc_t
1115efx_vpd_hunk_set(
1116	__in_bcount(size)	caddr_t data,
1117	__in			size_t size,
1118	__in			efx_vpd_value_t *evvp);
1119
1120#endif	/* EFSYS_OPT_VPD */
1121
1122#if EFSYS_OPT_DIAG
1123
1124extern	efx_sram_pattern_fn_t	__efx_sram_pattern_fns[];
1125
1126typedef struct efx_register_set_s {
1127	unsigned int		address;
1128	unsigned int		step;
1129	unsigned int		rows;
1130	efx_oword_t		mask;
1131} efx_register_set_t;
1132
1133extern	__checkReturn	efx_rc_t
1134efx_nic_test_registers(
1135	__in		efx_nic_t *enp,
1136	__in		efx_register_set_t *rsp,
1137	__in		size_t count);
1138
1139extern	__checkReturn	efx_rc_t
1140efx_nic_test_tables(
1141	__in		efx_nic_t *enp,
1142	__in		efx_register_set_t *rsp,
1143	__in		efx_pattern_type_t pattern,
1144	__in		size_t count);
1145
1146#endif	/* EFSYS_OPT_DIAG */
1147
1148#if EFSYS_OPT_MCDI
1149
1150extern	__checkReturn		efx_rc_t
1151efx_mcdi_set_workaround(
1152	__in			efx_nic_t *enp,
1153	__in			uint32_t type,
1154	__in			boolean_t enabled,
1155	__out_opt		uint32_t *flagsp);
1156
1157extern	__checkReturn		efx_rc_t
1158efx_mcdi_get_workarounds(
1159	__in			efx_nic_t *enp,
1160	__out_opt		uint32_t *implementedp,
1161	__out_opt		uint32_t *enabledp);
1162
1163#endif /* EFSYS_OPT_MCDI */
1164
1165#if EFSYS_OPT_MAC_STATS
1166
1167/*
1168 * Closed range of stats (i.e. the first and the last are included).
1169 * The last must be greater or equal (if the range is one item only) to
1170 * the first.
1171 */
1172struct efx_mac_stats_range {
1173	efx_mac_stat_t		first;
1174	efx_mac_stat_t		last;
1175};
1176
1177extern					efx_rc_t
1178efx_mac_stats_mask_add_ranges(
1179	__inout_bcount(mask_size)	uint32_t *maskp,
1180	__in				size_t mask_size,
1181	__in_ecount(rng_count)		const struct efx_mac_stats_range *rngp,
1182	__in				unsigned int rng_count);
1183
1184#endif	/* EFSYS_OPT_MAC_STATS */
1185
1186#ifdef	__cplusplus
1187}
1188#endif
1189
1190#endif	/* _SYS_EFX_IMPL_H */
1191