efx_impl.h revision 294386 
1/*-
2 * Copyright (c) 2007-2015 Solarflare Communications Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 *    this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 *    this list of conditions and the following disclaimer in the documentation
12 *    and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
29 *
30 * $FreeBSD: stable/10/sys/dev/sfxge/common/efx_impl.h 294386 2016-01-20 08:01:21Z arybchik $
31 */
32
33#ifndef	_SYS_EFX_IMPL_H
34#define	_SYS_EFX_IMPL_H
35
36#include "efsys.h"
37#include "efx.h"
38#include "efx_regs.h"
39#include "efx_regs_ef10.h"
40
41/* FIXME: Add definition for driver generated software events */
42#ifndef	ESE_DZ_EV_CODE_DRV_GEN_EV
43#define	ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
44#endif
45
46#include "efx_check.h"
47
48
49#if EFSYS_OPT_FALCON
50#include "falcon_impl.h"
51#endif	/* EFSYS_OPT_FALCON */
52
53#if EFSYS_OPT_SIENA
54#include "siena_impl.h"
55#endif	/* EFSYS_OPT_SIENA */
56
57#if EFSYS_OPT_HUNTINGTON
58#include "hunt_impl.h"
59#endif	/* EFSYS_OPT_HUNTINGTON */
60
61#if EFSYS_OPT_MEDFORD
62#include "medford_impl.h"
63#endif	/* EFSYS_OPT_MEDFORD */
64
65#if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
66#include "ef10_impl.h"
67#endif	/* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
68
69#ifdef	__cplusplus
70extern "C" {
71#endif
72
73#define	EFX_MOD_MCDI		0x00000001
74#define	EFX_MOD_PROBE		0x00000002
75#define	EFX_MOD_NVRAM		0x00000004
76#define	EFX_MOD_VPD		0x00000008
77#define	EFX_MOD_NIC		0x00000010
78#define	EFX_MOD_INTR		0x00000020
79#define	EFX_MOD_EV		0x00000040
80#define	EFX_MOD_RX		0x00000080
81#define	EFX_MOD_TX		0x00000100
82#define	EFX_MOD_PORT		0x00000200
83#define	EFX_MOD_MON		0x00000400
84#define	EFX_MOD_WOL		0x00000800
85#define	EFX_MOD_FILTER		0x00001000
86#define	EFX_MOD_PKTFILTER	0x00002000
87#define	EFX_MOD_LIC		0x00004000
88
89#define	EFX_RESET_MAC		0x00000001
90#define	EFX_RESET_PHY		0x00000002
91#define	EFX_RESET_RXQ_ERR	0x00000004
92#define	EFX_RESET_TXQ_ERR	0x00000008
93
94typedef enum efx_mac_type_e {
95	EFX_MAC_INVALID = 0,
96	EFX_MAC_FALCON_GMAC,
97	EFX_MAC_FALCON_XMAC,
98	EFX_MAC_SIENA,
99	EFX_MAC_HUNTINGTON,
100	EFX_MAC_NTYPES
101} efx_mac_type_t;
102
103typedef struct efx_ev_ops_s {
104	efx_rc_t	(*eevo_init)(efx_nic_t *);
105	void		(*eevo_fini)(efx_nic_t *);
106	efx_rc_t	(*eevo_qcreate)(efx_nic_t *, unsigned int,
107					  efsys_mem_t *, size_t, uint32_t,
108					  efx_evq_t *);
109	void		(*eevo_qdestroy)(efx_evq_t *);
110	efx_rc_t	(*eevo_qprime)(efx_evq_t *, unsigned int);
111	void		(*eevo_qpost)(efx_evq_t *, uint16_t);
112	efx_rc_t	(*eevo_qmoderate)(efx_evq_t *, unsigned int);
113#if EFSYS_OPT_QSTATS
114	void		(*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
115#endif
116} efx_ev_ops_t;
117
118typedef struct efx_tx_ops_s {
119	efx_rc_t	(*etxo_init)(efx_nic_t *);
120	void		(*etxo_fini)(efx_nic_t *);
121	efx_rc_t	(*etxo_qcreate)(efx_nic_t *,
122					unsigned int, unsigned int,
123					efsys_mem_t *, size_t,
124					uint32_t, uint16_t,
125					efx_evq_t *, efx_txq_t *,
126					unsigned int *);
127	void		(*etxo_qdestroy)(efx_txq_t *);
128	efx_rc_t	(*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
129				      unsigned int, unsigned int,
130				      unsigned int *);
131	void		(*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
132	efx_rc_t	(*etxo_qpace)(efx_txq_t *, unsigned int);
133	efx_rc_t	(*etxo_qflush)(efx_txq_t *);
134	void		(*etxo_qenable)(efx_txq_t *);
135	efx_rc_t	(*etxo_qpio_enable)(efx_txq_t *);
136	void		(*etxo_qpio_disable)(efx_txq_t *);
137	efx_rc_t	(*etxo_qpio_write)(efx_txq_t *,uint8_t *, size_t,
138					   size_t);
139	efx_rc_t	(*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
140					   unsigned int *);
141	efx_rc_t	(*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
142				      unsigned int, unsigned int,
143				      unsigned int *);
144	void		(*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
145						size_t, boolean_t,
146						efx_desc_t *);
147	void		(*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
148						uint32_t, uint8_t,
149						efx_desc_t *);
150	void		(*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
151						uint32_t, uint16_t,
152						efx_desc_t *, int);
153	void		(*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
154						efx_desc_t *);
155#if EFSYS_OPT_QSTATS
156	void		(*etxo_qstats_update)(efx_txq_t *,
157					      efsys_stat_t *);
158#endif
159} efx_tx_ops_t;
160
161typedef struct efx_rx_ops_s {
162	efx_rc_t	(*erxo_init)(efx_nic_t *);
163	void		(*erxo_fini)(efx_nic_t *);
164#if EFSYS_OPT_RX_SCATTER
165	efx_rc_t	(*erxo_scatter_enable)(efx_nic_t *, unsigned int);
166#endif
167#if EFSYS_OPT_RX_SCALE
168	efx_rc_t	(*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t,
169					       efx_rx_hash_type_t, boolean_t);
170	efx_rc_t	(*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t);
171	efx_rc_t	(*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *,
172					      size_t);
173	uint32_t	(*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
174					    uint8_t *);
175#endif /* EFSYS_OPT_RX_SCALE */
176	efx_rc_t	(*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
177					      uint16_t *);
178	void		(*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
179				      unsigned int, unsigned int,
180				      unsigned int);
181	void		(*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
182	efx_rc_t	(*erxo_qflush)(efx_rxq_t *);
183	void		(*erxo_qenable)(efx_rxq_t *);
184	efx_rc_t	(*erxo_qcreate)(efx_nic_t *enp, unsigned int,
185					unsigned int, efx_rxq_type_t,
186					efsys_mem_t *, size_t, uint32_t,
187					efx_evq_t *, efx_rxq_t *);
188	void		(*erxo_qdestroy)(efx_rxq_t *);
189} efx_rx_ops_t;
190
191typedef struct efx_mac_ops_s {
192	efx_rc_t	(*emo_reset)(efx_nic_t *); /* optional */
193	efx_rc_t	(*emo_poll)(efx_nic_t *, efx_link_mode_t *);
194	efx_rc_t	(*emo_up)(efx_nic_t *, boolean_t *);
195	efx_rc_t	(*emo_addr_set)(efx_nic_t *);
196	efx_rc_t	(*emo_reconfigure)(efx_nic_t *);
197	efx_rc_t	(*emo_multicast_list_set)(efx_nic_t *);
198	efx_rc_t	(*emo_filter_default_rxq_set)(efx_nic_t *,
199						      efx_rxq_t *, boolean_t);
200	void		(*emo_filter_default_rxq_clear)(efx_nic_t *);
201#if EFSYS_OPT_LOOPBACK
202	efx_rc_t	(*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
203					    efx_loopback_type_t);
204#endif	/* EFSYS_OPT_LOOPBACK */
205#if EFSYS_OPT_MAC_STATS
206	efx_rc_t	(*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
207	efx_rc_t	(*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
208					      uint16_t, boolean_t);
209	efx_rc_t	(*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
210					    efsys_stat_t *, uint32_t *);
211#endif	/* EFSYS_OPT_MAC_STATS */
212} efx_mac_ops_t;
213
214typedef struct efx_phy_ops_s {
215	efx_rc_t	(*epo_power)(efx_nic_t *, boolean_t); /* optional */
216	efx_rc_t	(*epo_reset)(efx_nic_t *);
217	efx_rc_t	(*epo_reconfigure)(efx_nic_t *);
218	efx_rc_t	(*epo_verify)(efx_nic_t *);
219	efx_rc_t	(*epo_uplink_check)(efx_nic_t *,
220					    boolean_t *); /* optional */
221	efx_rc_t	(*epo_downlink_check)(efx_nic_t *, efx_link_mode_t *,
222					      unsigned int *, uint32_t *);
223	efx_rc_t	(*epo_oui_get)(efx_nic_t *, uint32_t *);
224#if EFSYS_OPT_PHY_STATS
225	efx_rc_t	(*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
226					    uint32_t *);
227#endif	/* EFSYS_OPT_PHY_STATS */
228#if EFSYS_OPT_PHY_PROPS
229#if EFSYS_OPT_NAMES
230	const char	*(*epo_prop_name)(efx_nic_t *, unsigned int);
231#endif	/* EFSYS_OPT_PHY_PROPS */
232	efx_rc_t	(*epo_prop_get)(efx_nic_t *, unsigned int, uint32_t,
233					uint32_t *);
234	efx_rc_t	(*epo_prop_set)(efx_nic_t *, unsigned int, uint32_t);
235#endif	/* EFSYS_OPT_PHY_PROPS */
236#if EFSYS_OPT_BIST
237	efx_rc_t	(*epo_bist_enable_offline)(efx_nic_t *);
238	efx_rc_t	(*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
239	efx_rc_t	(*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
240					 efx_bist_result_t *, uint32_t *,
241					 unsigned long *, size_t);
242	void		(*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
243#endif	/* EFSYS_OPT_BIST */
244} efx_phy_ops_t;
245
246#if EFSYS_OPT_FILTER
247typedef struct efx_filter_ops_s {
248	efx_rc_t	(*efo_init)(efx_nic_t *);
249	void		(*efo_fini)(efx_nic_t *);
250	efx_rc_t	(*efo_restore)(efx_nic_t *);
251	efx_rc_t	(*efo_add)(efx_nic_t *, efx_filter_spec_t *,
252				   boolean_t may_replace);
253	efx_rc_t	(*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
254	efx_rc_t	(*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
255	efx_rc_t	(*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
256				   boolean_t, boolean_t, boolean_t,
257				   uint8_t const *, int);
258} efx_filter_ops_t;
259
260extern	__checkReturn	efx_rc_t
261efx_filter_reconfigure(
262	__in				efx_nic_t *enp,
263	__in_ecount(6)			uint8_t const *mac_addr,
264	__in				boolean_t all_unicst,
265	__in				boolean_t mulcst,
266	__in				boolean_t all_mulcst,
267	__in				boolean_t brdcst,
268	__in_ecount(6*count)		uint8_t const *addrs,
269	__in				int count);
270
271#endif /* EFSYS_OPT_FILTER */
272
273
274typedef struct efx_port_s {
275	efx_mac_type_t		ep_mac_type;
276	uint32_t  		ep_phy_type;
277	uint8_t			ep_port;
278	uint32_t		ep_mac_pdu;
279	uint8_t			ep_mac_addr[6];
280	efx_link_mode_t		ep_link_mode;
281	boolean_t		ep_all_unicst;
282	boolean_t		ep_mulcst;
283	boolean_t		ep_all_mulcst;
284	boolean_t		ep_brdcst;
285	unsigned int		ep_fcntl;
286	boolean_t		ep_fcntl_autoneg;
287	efx_oword_t		ep_multicst_hash[2];
288	uint8_t			ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
289						    EFX_MAC_MULTICAST_LIST_MAX];
290	uint32_t		ep_mulcst_addr_count;
291#if EFSYS_OPT_LOOPBACK
292	efx_loopback_type_t	ep_loopback_type;
293	efx_link_mode_t		ep_loopback_link_mode;
294#endif	/* EFSYS_OPT_LOOPBACK */
295#if EFSYS_OPT_PHY_FLAGS
296	uint32_t		ep_phy_flags;
297#endif	/* EFSYS_OPT_PHY_FLAGS */
298#if EFSYS_OPT_PHY_LED_CONTROL
299	efx_phy_led_mode_t	ep_phy_led_mode;
300#endif	/* EFSYS_OPT_PHY_LED_CONTROL */
301	efx_phy_media_type_t	ep_fixed_port_type;
302	efx_phy_media_type_t	ep_module_type;
303	uint32_t		ep_adv_cap_mask;
304	uint32_t		ep_lp_cap_mask;
305	uint32_t		ep_default_adv_cap_mask;
306	uint32_t		ep_phy_cap_mask;
307#if EFSYS_OPT_PHY_TXC43128 || EFSYS_OPT_PHY_QT2025C
308	union {
309		struct {
310			unsigned int	bug10934_count;
311		} ep_txc43128;
312		struct {
313			unsigned int	bug17190_count;
314		} ep_qt2025c;
315	};
316#endif
317	boolean_t		ep_mac_poll_needed; /* falcon only */
318	boolean_t		ep_mac_up; /* falcon only */
319	uint32_t		ep_fwver; /* falcon only */
320	boolean_t		ep_mac_drain;
321	boolean_t		ep_mac_stats_pending;
322#if EFSYS_OPT_BIST
323	efx_bist_type_t		ep_current_bist;
324#endif
325	efx_mac_ops_t		*ep_emop;
326	efx_phy_ops_t		*ep_epop;
327} efx_port_t;
328
329typedef struct efx_mon_ops_s {
330	efx_rc_t	(*emo_reset)(efx_nic_t *);
331	efx_rc_t	(*emo_reconfigure)(efx_nic_t *);
332#if EFSYS_OPT_MON_STATS
333	efx_rc_t	(*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
334					    efx_mon_stat_value_t *);
335#endif	/* EFSYS_OPT_MON_STATS */
336} efx_mon_ops_t;
337
338typedef struct efx_mon_s {
339	efx_mon_type_t	em_type;
340	efx_mon_ops_t	*em_emop;
341} efx_mon_t;
342
343typedef struct efx_intr_ops_s {
344	efx_rc_t	(*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
345	void		(*eio_enable)(efx_nic_t *);
346	void		(*eio_disable)(efx_nic_t *);
347	void		(*eio_disable_unlocked)(efx_nic_t *);
348	efx_rc_t	(*eio_trigger)(efx_nic_t *, unsigned int);
349	void		(*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
350	void		(*eio_status_message)(efx_nic_t *, unsigned int,
351				 boolean_t *);
352	void		(*eio_fatal)(efx_nic_t *);
353	void		(*eio_fini)(efx_nic_t *);
354} efx_intr_ops_t;
355
356typedef struct efx_intr_s {
357	efx_intr_ops_t	*ei_eiop;
358	efsys_mem_t	*ei_esmp;
359	efx_intr_type_t	ei_type;
360	unsigned int	ei_level;
361} efx_intr_t;
362
363typedef struct efx_nic_ops_s {
364	efx_rc_t	(*eno_probe)(efx_nic_t *);
365	efx_rc_t	(*eno_board_cfg)(efx_nic_t *);
366	efx_rc_t	(*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
367	efx_rc_t	(*eno_reset)(efx_nic_t *);
368	efx_rc_t	(*eno_init)(efx_nic_t *);
369	efx_rc_t	(*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
370	efx_rc_t	(*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
371					uint32_t *, size_t *);
372#if EFSYS_OPT_DIAG
373	efx_rc_t	(*eno_sram_test)(efx_nic_t *, efx_sram_pattern_fn_t);
374	efx_rc_t	(*eno_register_test)(efx_nic_t *);
375#endif	/* EFSYS_OPT_DIAG */
376	void		(*eno_fini)(efx_nic_t *);
377	void		(*eno_unprobe)(efx_nic_t *);
378} efx_nic_ops_t;
379
380#ifndef EFX_TXQ_LIMIT_TARGET
381#define	EFX_TXQ_LIMIT_TARGET 259
382#endif
383#ifndef EFX_RXQ_LIMIT_TARGET
384#define	EFX_RXQ_LIMIT_TARGET 512
385#endif
386#ifndef EFX_TXQ_DC_SIZE
387#define	EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
388#endif
389#ifndef EFX_RXQ_DC_SIZE
390#define	EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
391#endif
392
393#if EFSYS_OPT_FILTER
394
395typedef struct falconsiena_filter_spec_s {
396	uint8_t		fsfs_type;
397	uint32_t	fsfs_flags;
398	uint32_t	fsfs_dmaq_id;
399	uint32_t	fsfs_dword[3];
400} falconsiena_filter_spec_t;
401
402typedef enum falconsiena_filter_type_e {
403	EFX_FS_FILTER_RX_TCP_FULL,	/* TCP/IPv4 4-tuple {dIP,dTCP,sIP,sTCP} */
404	EFX_FS_FILTER_RX_TCP_WILD,	/* TCP/IPv4 dest    {dIP,dTCP,  -,   -} */
405	EFX_FS_FILTER_RX_UDP_FULL,	/* UDP/IPv4 4-tuple {dIP,dUDP,sIP,sUDP} */
406	EFX_FS_FILTER_RX_UDP_WILD,	/* UDP/IPv4 dest    {dIP,dUDP,  -,   -} */
407
408#if EFSYS_OPT_SIENA
409	EFX_FS_FILTER_RX_MAC_FULL,	/* Ethernet {dMAC,VLAN} */
410	EFX_FS_FILTER_RX_MAC_WILD,	/* Ethernet {dMAC,   -} */
411
412	EFX_FS_FILTER_TX_TCP_FULL,		/* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
413	EFX_FS_FILTER_TX_TCP_WILD,		/* TCP/IPv4 {  -,   -,sIP,sTCP} */
414	EFX_FS_FILTER_TX_UDP_FULL,		/* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
415	EFX_FS_FILTER_TX_UDP_WILD,		/* UDP/IPv4 source (host, port) */
416
417	EFX_FS_FILTER_TX_MAC_FULL,		/* Ethernet source (MAC address, VLAN ID) */
418	EFX_FS_FILTER_TX_MAC_WILD,		/* Ethernet source (MAC address) */
419#endif /* EFSYS_OPT_SIENA */
420
421	EFX_FS_FILTER_NTYPES
422} falconsiena_filter_type_t;
423
424typedef enum falconsiena_filter_tbl_id_e {
425	EFX_FS_FILTER_TBL_RX_IP = 0,
426	EFX_FS_FILTER_TBL_RX_MAC,
427	EFX_FS_FILTER_TBL_TX_IP,
428	EFX_FS_FILTER_TBL_TX_MAC,
429	EFX_FS_FILTER_NTBLS
430} falconsiena_filter_tbl_id_t;
431
432typedef struct falconsiena_filter_tbl_s {
433	int				fsft_size;	/* number of entries */
434	int				fsft_used;	/* active count */
435	uint32_t			*fsft_bitmap;	/* active bitmap */
436	falconsiena_filter_spec_t	*fsft_spec;	/* array of saved specs */
437} falconsiena_filter_tbl_t;
438
439typedef struct falconsiena_filter_s {
440	falconsiena_filter_tbl_t	fsf_tbl[EFX_FS_FILTER_NTBLS];
441	unsigned int			fsf_depth[EFX_FS_FILTER_NTYPES];
442} falconsiena_filter_t;
443
444typedef struct efx_filter_s {
445#if EFSYS_OPT_FALCON || EFSYS_OPT_SIENA
446	falconsiena_filter_t	*ef_falconsiena_filter;
447#endif /* EFSYS_OPT_FALCON || EFSYS_OPT_SIENA */
448#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
449	ef10_filter_table_t	*ef_ef10_filter_table;
450#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
451} efx_filter_t;
452
453extern			void
454falconsiena_filter_tbl_clear(
455	__in		efx_nic_t *enp,
456	__in		falconsiena_filter_tbl_id_t tbl);
457
458#endif	/* EFSYS_OPT_FILTER */
459
460#if EFSYS_OPT_MCDI
461
462typedef struct efx_mcdi_ops_s {
463	efx_rc_t	(*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
464	void		(*emco_send_request)(efx_nic_t *, void *, size_t,
465					void *, size_t);
466	void		(*emco_request_copyout)(efx_nic_t *, efx_mcdi_req_t *);
467	efx_rc_t	(*emco_poll_reboot)(efx_nic_t *);
468	boolean_t	(*emco_poll_response)(efx_nic_t *);
469	void		(*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
470	void		(*emco_fini)(efx_nic_t *);
471	efx_rc_t	(*emco_feature_supported)(efx_nic_t *, efx_mcdi_feature_id_t, boolean_t *);
472} efx_mcdi_ops_t;
473
474typedef struct efx_mcdi_s {
475	efx_mcdi_ops_t			*em_emcop;
476	const efx_mcdi_transport_t	*em_emtp;
477	efx_mcdi_iface_t		em_emip;
478} efx_mcdi_t;
479
480#endif /* EFSYS_OPT_MCDI */
481
482#if EFSYS_OPT_NVRAM
483typedef struct efx_nvram_ops_s {
484#if EFSYS_OPT_DIAG
485	efx_rc_t	(*envo_test)(efx_nic_t *);
486#endif	/* EFSYS_OPT_DIAG */
487	efx_rc_t	(*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
488					    uint32_t *);
489	efx_rc_t	(*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
490	efx_rc_t	(*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
491	efx_rc_t	(*envo_partn_read)(efx_nic_t *, uint32_t,
492					    unsigned int, caddr_t, size_t);
493	efx_rc_t	(*envo_partn_erase)(efx_nic_t *, uint32_t,
494					    unsigned int, size_t);
495	efx_rc_t	(*envo_partn_write)(efx_nic_t *, uint32_t,
496					    unsigned int, caddr_t, size_t);
497	void		(*envo_partn_rw_finish)(efx_nic_t *, uint32_t);
498	efx_rc_t	(*envo_partn_get_version)(efx_nic_t *, uint32_t,
499					    uint32_t *, uint16_t *);
500	efx_rc_t	(*envo_partn_set_version)(efx_nic_t *, uint32_t,
501					    uint16_t *);
502} efx_nvram_ops_t;
503#endif /* EFSYS_OPT_NVRAM */
504
505#if EFSYS_OPT_VPD
506typedef struct efx_vpd_ops_s {
507	efx_rc_t	(*evpdo_init)(efx_nic_t *);
508	efx_rc_t	(*evpdo_size)(efx_nic_t *, size_t *);
509	efx_rc_t	(*evpdo_read)(efx_nic_t *, caddr_t, size_t);
510	efx_rc_t	(*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
511	efx_rc_t	(*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
512	efx_rc_t	(*evpdo_get)(efx_nic_t *, caddr_t, size_t,
513					efx_vpd_value_t *);
514	efx_rc_t	(*evpdo_set)(efx_nic_t *, caddr_t, size_t,
515					efx_vpd_value_t *);
516	efx_rc_t	(*evpdo_next)(efx_nic_t *, caddr_t, size_t,
517					efx_vpd_value_t *, unsigned int *);
518	efx_rc_t	(*evpdo_write)(efx_nic_t *, caddr_t, size_t);
519	void		(*evpdo_fini)(efx_nic_t *);
520} efx_vpd_ops_t;
521#endif	/* EFSYS_OPT_VPD */
522
523#if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
524
525	__checkReturn		efx_rc_t
526efx_mcdi_nvram_partitions(
527	__in			efx_nic_t *enp,
528	__out_bcount(size)	caddr_t data,
529	__in			size_t size,
530	__out			unsigned int *npartnp);
531
532	__checkReturn		efx_rc_t
533efx_mcdi_nvram_metadata(
534	__in			efx_nic_t *enp,
535	__in			uint32_t partn,
536	__out			uint32_t *subtypep,
537	__out_ecount(4)		uint16_t version[4],
538	__out_bcount_opt(size)	char *descp,
539	__in			size_t size);
540
541	__checkReturn		efx_rc_t
542efx_mcdi_nvram_info(
543	__in			efx_nic_t *enp,
544	__in			uint32_t partn,
545	__out_opt		size_t *sizep,
546	__out_opt		uint32_t *addressp,
547	__out_opt		uint32_t *erase_sizep,
548	__out_opt		uint32_t *write_sizep);
549
550	__checkReturn		efx_rc_t
551efx_mcdi_nvram_update_start(
552	__in			efx_nic_t *enp,
553	__in			uint32_t partn);
554
555	__checkReturn		efx_rc_t
556efx_mcdi_nvram_read(
557	__in			efx_nic_t *enp,
558	__in			uint32_t partn,
559	__in			uint32_t offset,
560	__out_bcount(size)	caddr_t data,
561	__in			size_t size);
562
563	__checkReturn		efx_rc_t
564efx_mcdi_nvram_erase(
565	__in			efx_nic_t *enp,
566	__in			uint32_t partn,
567	__in			uint32_t offset,
568	__in			size_t size);
569
570	__checkReturn		efx_rc_t
571efx_mcdi_nvram_write(
572	__in			efx_nic_t *enp,
573	__in			uint32_t partn,
574	__in			uint32_t offset,
575	__out_bcount(size)	caddr_t data,
576	__in			size_t size);
577
578	__checkReturn		efx_rc_t
579efx_mcdi_nvram_update_finish(
580	__in			efx_nic_t *enp,
581	__in			uint32_t partn,
582	__in			boolean_t reboot);
583
584#if EFSYS_OPT_DIAG
585
586	__checkReturn		efx_rc_t
587efx_mcdi_nvram_test(
588	__in			efx_nic_t *enp,
589	__in			uint32_t partn);
590
591#endif	/* EFSYS_OPT_DIAG */
592
593#endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
594
595#if EFSYS_OPT_LICENSING
596
597typedef struct efx_lic_ops_s {
598	efx_rc_t	(*elo_update_licenses)(efx_nic_t *);
599	efx_rc_t	(*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
600	efx_rc_t	(*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
601	efx_rc_t	(*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
602				      size_t *, uint8_t *);
603} efx_lic_ops_t;
604
605#endif
606
607typedef struct efx_drv_cfg_s {
608	uint32_t		edc_min_vi_count;
609	uint32_t		edc_max_vi_count;
610
611	uint32_t		edc_max_piobuf_count;
612	uint32_t		edc_pio_alloc_size;
613} efx_drv_cfg_t;
614
615struct efx_nic_s {
616	uint32_t		en_magic;
617	efx_family_t		en_family;
618	uint32_t		en_features;
619	efsys_identifier_t	*en_esip;
620	efsys_lock_t		*en_eslp;
621	efsys_bar_t 		*en_esbp;
622	unsigned int		en_mod_flags;
623	unsigned int		en_reset_flags;
624	efx_nic_cfg_t		en_nic_cfg;
625	efx_drv_cfg_t		en_drv_cfg;
626	efx_port_t		en_port;
627	efx_mon_t		en_mon;
628	efx_intr_t		en_intr;
629	uint32_t		en_ev_qcount;
630	uint32_t		en_rx_qcount;
631	uint32_t		en_tx_qcount;
632	efx_nic_ops_t		*en_enop;
633	efx_ev_ops_t		*en_eevop;
634	efx_tx_ops_t		*en_etxop;
635	efx_rx_ops_t		*en_erxop;
636#if EFSYS_OPT_FILTER
637	efx_filter_t		en_filter;
638	efx_filter_ops_t	*en_efop;
639#endif	/* EFSYS_OPT_FILTER */
640#if EFSYS_OPT_MCDI
641	efx_mcdi_t		en_mcdi;
642#endif	/* EFSYS_OPT_MCDI */
643#if EFSYS_OPT_NVRAM
644	efx_nvram_type_t	en_nvram_locked;
645	efx_nvram_ops_t		*en_envop;
646#endif	/* EFSYS_OPT_NVRAM */
647#if EFSYS_OPT_VPD
648	efx_vpd_ops_t		*en_evpdop;
649#endif	/* EFSYS_OPT_VPD */
650#if EFSYS_OPT_RX_SCALE
651	efx_rx_hash_support_t	en_hash_support;
652	efx_rx_scale_support_t	en_rss_support;
653	uint32_t		en_rss_context;
654#endif	/* EFSYS_OPT_RX_SCALE */
655	uint32_t		en_vport_id;
656#if EFSYS_OPT_LICENSING
657	efx_lic_ops_t		*en_elop;
658#endif
659	union {
660#if EFSYS_OPT_FALCON
661		struct {
662			falcon_spi_dev_t	enu_fsd[FALCON_SPI_NTYPES];
663			falcon_i2c_t		enu_fip;
664			boolean_t		enu_i2c_locked;
665#if EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE
666			const uint8_t		*enu_forced_cfg;
667#endif	/* EFSYS_OPT_FALCON_NIC_CFG_OVERRIDE */
668			uint8_t			enu_mon_devid;
669#if EFSYS_OPT_PCIE_TUNE
670			unsigned int 		enu_nlanes;
671#endif	/* EFSYS_OPT_PCIE_TUNE */
672			uint16_t		enu_board_rev;
673			boolean_t		enu_internal_sram;
674			uint8_t			enu_sram_num_bank;
675			uint8_t			enu_sram_bank_size;
676		} falcon;
677#endif	/* EFSYS_OPT_FALCON */
678#if EFSYS_OPT_SIENA
679		struct {
680#if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
681			unsigned int		enu_partn_mask;
682#endif	/* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
683#if EFSYS_OPT_VPD
684			caddr_t			enu_svpd;
685			size_t			enu_svpd_length;
686#endif	/* EFSYS_OPT_VPD */
687			int			enu_unused;
688		} siena;
689#endif	/* EFSYS_OPT_SIENA */
690		int	enu_unused;
691	} en_u;
692#if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
693	union en_arch {
694		struct {
695			int			ena_vi_base;
696			int			ena_vi_count;
697			int			ena_vi_shift;
698#if EFSYS_OPT_VPD
699			caddr_t			ena_svpd;
700			size_t			ena_svpd_length;
701#endif	/* EFSYS_OPT_VPD */
702			efx_piobuf_handle_t	ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
703			uint32_t		ena_piobuf_count;
704			uint32_t		ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
705			uint32_t		ena_pio_write_vi_base;
706			/* Memory BAR mapping regions */
707			uint32_t		ena_uc_mem_map_offset;
708			size_t			ena_uc_mem_map_size;
709			uint32_t		ena_wc_mem_map_offset;
710			size_t			ena_wc_mem_map_size;
711		} ef10;
712	} en_arch;
713#endif	/* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
714};
715
716
717#define	EFX_NIC_MAGIC	0x02121996
718
719typedef	boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
720    const efx_ev_callbacks_t *, void *);
721
722typedef struct efx_evq_rxq_state_s {
723	unsigned int			eers_rx_read_ptr;
724	unsigned int			eers_rx_mask;
725} efx_evq_rxq_state_t;
726
727struct efx_evq_s {
728	uint32_t			ee_magic;
729	efx_nic_t			*ee_enp;
730	unsigned int			ee_index;
731	unsigned int			ee_mask;
732	efsys_mem_t			*ee_esmp;
733#if EFSYS_OPT_QSTATS
734	uint32_t			ee_stat[EV_NQSTATS];
735#endif	/* EFSYS_OPT_QSTATS */
736
737	efx_ev_handler_t		ee_rx;
738	efx_ev_handler_t		ee_tx;
739	efx_ev_handler_t		ee_driver;
740	efx_ev_handler_t		ee_global;
741	efx_ev_handler_t		ee_drv_gen;
742#if EFSYS_OPT_MCDI
743	efx_ev_handler_t		ee_mcdi;
744#endif	/* EFSYS_OPT_MCDI */
745
746	efx_evq_rxq_state_t		ee_rxq_state[EFX_EV_RX_NLABELS];
747};
748
749#define	EFX_EVQ_MAGIC	0x08081997
750
751#define	EFX_EVQ_FALCON_TIMER_QUANTUM_NS	4968 /* 621 cycles */
752#define	EFX_EVQ_SIENA_TIMER_QUANTUM_NS	6144 /* 768 cycles */
753
754struct efx_rxq_s {
755	uint32_t			er_magic;
756	efx_nic_t			*er_enp;
757	efx_evq_t			*er_eep;
758	unsigned int			er_index;
759	unsigned int			er_label;
760	unsigned int			er_mask;
761	efsys_mem_t			*er_esmp;
762};
763
764#define	EFX_RXQ_MAGIC	0x15022005
765
766struct efx_txq_s {
767	uint32_t			et_magic;
768	efx_nic_t			*et_enp;
769	unsigned int			et_index;
770	unsigned int			et_mask;
771	efsys_mem_t			*et_esmp;
772#if EFSYS_OPT_HUNTINGTON
773	uint32_t			et_pio_bufnum;
774	uint32_t			et_pio_blknum;
775	uint32_t			et_pio_write_offset;
776	uint32_t			et_pio_offset;
777	size_t				et_pio_size;
778#endif
779#if EFSYS_OPT_QSTATS
780	uint32_t			et_stat[TX_NQSTATS];
781#endif	/* EFSYS_OPT_QSTATS */
782};
783
784#define	EFX_TXQ_MAGIC	0x05092005
785
786#define	EFX_MAC_ADDR_COPY(_dst, _src)					\
787	do {								\
788		(_dst)[0] = (_src)[0];					\
789		(_dst)[1] = (_src)[1];					\
790		(_dst)[2] = (_src)[2];					\
791		(_dst)[3] = (_src)[3];					\
792		(_dst)[4] = (_src)[4];					\
793		(_dst)[5] = (_src)[5];					\
794	_NOTE(CONSTANTCONDITION)					\
795	} while (B_FALSE)
796
797#define	EFX_MAC_BROADCAST_ADDR_SET(_dst)				\
798	do {								\
799		uint16_t *_d = (uint16_t *)(_dst);			\
800		_d[0] = 0xffff;						\
801		_d[1] = 0xffff;						\
802		_d[2] = 0xffff;						\
803	_NOTE(CONSTANTCONDITION)					\
804	} while (B_FALSE)
805
806#if EFSYS_OPT_CHECK_REG
807#define	EFX_CHECK_REG(_enp, _reg)					\
808	do {								\
809		const char *name = #_reg;				\
810		char min = name[4];					\
811		char max = name[5];					\
812		char rev;						\
813									\
814		switch ((_enp)->en_family) {				\
815		case EFX_FAMILY_FALCON:					\
816			rev = 'B';					\
817			break;						\
818									\
819		case EFX_FAMILY_SIENA:					\
820			rev = 'C';					\
821			break;						\
822									\
823		case EFX_FAMILY_HUNTINGTON:				\
824			rev = 'D';					\
825			break;						\
826									\
827		case EFX_FAMILY_MEDFORD:				\
828			rev = 'E';					\
829			break;						\
830									\
831		default:						\
832			rev = '?';					\
833			break;						\
834		}							\
835									\
836		EFSYS_ASSERT3S(rev, >=, min);				\
837		EFSYS_ASSERT3S(rev, <=, max);				\
838									\
839	_NOTE(CONSTANTCONDITION)					\
840	} while (B_FALSE)
841#else
842#define	EFX_CHECK_REG(_enp, _reg) do {					\
843	_NOTE(CONSTANTCONDITION)					\
844	} while(B_FALSE)
845#endif
846
847#define	EFX_BAR_READD(_enp, _reg, _edp, _lock)				\
848	do {								\
849		EFX_CHECK_REG((_enp), (_reg));				\
850		EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,		\
851		    (_edp), (_lock));					\
852		EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,	\
853		    uint32_t, _reg ## _OFST,				\
854		    uint32_t, (_edp)->ed_u32[0]);			\
855	_NOTE(CONSTANTCONDITION)					\
856	} while (B_FALSE)
857
858#define	EFX_BAR_WRITED(_enp, _reg, _edp, _lock)				\
859	do {								\
860		EFX_CHECK_REG((_enp), (_reg));				\
861		EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,	\
862		    uint32_t, _reg ## _OFST,				\
863		    uint32_t, (_edp)->ed_u32[0]);			\
864		EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,	\
865		    (_edp), (_lock));					\
866	_NOTE(CONSTANTCONDITION)					\
867	} while (B_FALSE)
868
869#define	EFX_BAR_READQ(_enp, _reg, _eqp)					\
870	do {								\
871		EFX_CHECK_REG((_enp), (_reg));				\
872		EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,		\
873		    (_eqp));						\
874		EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,	\
875		    uint32_t, _reg ## _OFST,				\
876		    uint32_t, (_eqp)->eq_u32[1],			\
877		    uint32_t, (_eqp)->eq_u32[0]);			\
878	_NOTE(CONSTANTCONDITION)					\
879	} while (B_FALSE)
880
881#define	EFX_BAR_WRITEQ(_enp, _reg, _eqp)				\
882	do {								\
883		EFX_CHECK_REG((_enp), (_reg));				\
884		EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,	\
885		    uint32_t, _reg ## _OFST,				\
886		    uint32_t, (_eqp)->eq_u32[1],			\
887		    uint32_t, (_eqp)->eq_u32[0]);			\
888		EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,	\
889		    (_eqp));						\
890	_NOTE(CONSTANTCONDITION)					\
891	} while (B_FALSE)
892
893#define	EFX_BAR_READO(_enp, _reg, _eop)					\
894	do {								\
895		EFX_CHECK_REG((_enp), (_reg));				\
896		EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,		\
897		    (_eop), B_TRUE);					\
898		EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,	\
899		    uint32_t, _reg ## _OFST,				\
900		    uint32_t, (_eop)->eo_u32[3],			\
901		    uint32_t, (_eop)->eo_u32[2],			\
902		    uint32_t, (_eop)->eo_u32[1],			\
903		    uint32_t, (_eop)->eo_u32[0]);			\
904	_NOTE(CONSTANTCONDITION)					\
905	} while (B_FALSE)
906
907#define	EFX_BAR_WRITEO(_enp, _reg, _eop)				\
908	do {								\
909		EFX_CHECK_REG((_enp), (_reg));				\
910		EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,	\
911		    uint32_t, _reg ## _OFST,				\
912		    uint32_t, (_eop)->eo_u32[3],			\
913		    uint32_t, (_eop)->eo_u32[2],			\
914		    uint32_t, (_eop)->eo_u32[1],			\
915		    uint32_t, (_eop)->eo_u32[0]);			\
916		EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,	\
917		    (_eop), B_TRUE);					\
918	_NOTE(CONSTANTCONDITION)					\
919	} while (B_FALSE)
920
921#define	EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)		\
922	do {								\
923		EFX_CHECK_REG((_enp), (_reg));				\
924		EFSYS_BAR_READD((_enp)->en_esbp,			\
925		    (_reg ## _OFST + ((_index) * _reg ## _STEP)),	\
926		    (_edp), (_lock));					\
927		EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,	\
928		    uint32_t, (_index),					\
929		    uint32_t, _reg ## _OFST,				\
930		    uint32_t, (_edp)->ed_u32[0]);			\
931	_NOTE(CONSTANTCONDITION)					\
932	} while (B_FALSE)
933
934#define	EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)		\
935	do {								\
936		EFX_CHECK_REG((_enp), (_reg));				\
937		EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,	\
938		    uint32_t, (_index),					\
939		    uint32_t, _reg ## _OFST,				\
940		    uint32_t, (_edp)->ed_u32[0]);			\
941		EFSYS_BAR_WRITED((_enp)->en_esbp,			\
942		    (_reg ## _OFST + ((_index) * _reg ## _STEP)),	\
943		    (_edp), (_lock));					\
944	_NOTE(CONSTANTCONDITION)					\
945	} while (B_FALSE)
946
947#define	EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock)		\
948	do {								\
949		EFX_CHECK_REG((_enp), (_reg));				\
950		EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,	\
951		    uint32_t, (_index),					\
952		    uint32_t, _reg ## _OFST,				\
953		    uint32_t, (_edp)->ed_u32[0]);			\
954		EFSYS_BAR_WRITED((_enp)->en_esbp,			\
955		    (_reg ## _OFST +					\
956		    (2 * sizeof (efx_dword_t)) + 			\
957		    ((_index) * _reg ## _STEP)),			\
958		    (_edp), (_lock));					\
959	_NOTE(CONSTANTCONDITION)					\
960	} while (B_FALSE)
961
962#define	EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)		\
963	do {								\
964		EFX_CHECK_REG((_enp), (_reg));				\
965		EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,	\
966		    uint32_t, (_index),					\
967		    uint32_t, _reg ## _OFST,				\
968		    uint32_t, (_edp)->ed_u32[0]);			\
969		EFSYS_BAR_WRITED((_enp)->en_esbp,			\
970		    (_reg ## _OFST +					\
971		    (3 * sizeof (efx_dword_t)) + 			\
972		    ((_index) * _reg ## _STEP)),			\
973		    (_edp), (_lock));					\
974	_NOTE(CONSTANTCONDITION)					\
975	} while (B_FALSE)
976
977#define	EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)			\
978	do {								\
979		EFX_CHECK_REG((_enp), (_reg));				\
980		EFSYS_BAR_READQ((_enp)->en_esbp,			\
981		    (_reg ## _OFST + ((_index) * _reg ## _STEP)),	\
982		    (_eqp));						\
983		EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,	\
984		    uint32_t, (_index),					\
985		    uint32_t, _reg ## _OFST,				\
986		    uint32_t, (_eqp)->eq_u32[1],			\
987		    uint32_t, (_eqp)->eq_u32[0]);			\
988	_NOTE(CONSTANTCONDITION)					\
989	} while (B_FALSE)
990
991#define	EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)			\
992	do {								\
993		EFX_CHECK_REG((_enp), (_reg));				\
994		EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,	\
995		    uint32_t, (_index),					\
996		    uint32_t, _reg ## _OFST,				\
997		    uint32_t, (_eqp)->eq_u32[1],			\
998		    uint32_t, (_eqp)->eq_u32[0]);			\
999		EFSYS_BAR_WRITEQ((_enp)->en_esbp,			\
1000		    (_reg ## _OFST + ((_index) * _reg ## _STEP)),	\
1001		    (_eqp));						\
1002	_NOTE(CONSTANTCONDITION)					\
1003	} while (B_FALSE)
1004
1005#define	EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)		\
1006	do {								\
1007		EFX_CHECK_REG((_enp), (_reg));				\
1008		EFSYS_BAR_READO((_enp)->en_esbp,			\
1009		    (_reg ## _OFST + ((_index) * _reg ## _STEP)),	\
1010		    (_eop), (_lock));					\
1011		EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,	\
1012		    uint32_t, (_index),					\
1013		    uint32_t, _reg ## _OFST,				\
1014		    uint32_t, (_eop)->eo_u32[3],			\
1015		    uint32_t, (_eop)->eo_u32[2],			\
1016		    uint32_t, (_eop)->eo_u32[1],			\
1017		    uint32_t, (_eop)->eo_u32[0]);			\
1018	_NOTE(CONSTANTCONDITION)					\
1019	} while (B_FALSE)
1020
1021#define	EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)		\
1022	do {								\
1023		EFX_CHECK_REG((_enp), (_reg));				\
1024		EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,	\
1025		    uint32_t, (_index),					\
1026		    uint32_t, _reg ## _OFST,				\
1027		    uint32_t, (_eop)->eo_u32[3],			\
1028		    uint32_t, (_eop)->eo_u32[2],			\
1029		    uint32_t, (_eop)->eo_u32[1],			\
1030		    uint32_t, (_eop)->eo_u32[0]);			\
1031		EFSYS_BAR_WRITEO((_enp)->en_esbp,			\
1032		    (_reg ## _OFST + ((_index) * _reg ## _STEP)),	\
1033		    (_eop), (_lock));					\
1034	_NOTE(CONSTANTCONDITION)					\
1035	} while (B_FALSE)
1036
1037/*
1038 * Allow drivers to perform optimised 128-bit doorbell writes.
1039 * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1040 * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1041 * the need for locking in the host, and are the only ones known to be safe to
1042 * use 128-bites write with.
1043 */
1044#define	EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop)		\
1045	do {								\
1046		EFX_CHECK_REG((_enp), (_reg));				\
1047		EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo,		\
1048		    const char *,					\
1049		    #_reg,						\
1050		    uint32_t, (_index),					\
1051		    uint32_t, _reg ## _OFST,				\
1052		    uint32_t, (_eop)->eo_u32[3],			\
1053		    uint32_t, (_eop)->eo_u32[2],			\
1054		    uint32_t, (_eop)->eo_u32[1],			\
1055		    uint32_t, (_eop)->eo_u32[0]);			\
1056		EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,		\
1057		    (_reg ## _OFST + ((_index) * _reg ## _STEP)),	\
1058		    (_eop));						\
1059	_NOTE(CONSTANTCONDITION)					\
1060	} while (B_FALSE)
1061
1062#define	EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)	\
1063	do {								\
1064		unsigned int _new = (_wptr);				\
1065		unsigned int _old = (_owptr);				\
1066									\
1067		if ((_new) >= (_old))					\
1068			EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),		\
1069			    (_old) * sizeof (efx_desc_t),		\
1070			    ((_new) - (_old)) * sizeof (efx_desc_t));	\
1071		else							\
1072			/*						\
1073			 * It is cheaper to sync entire map than sync	\
1074			 * two parts especially when offset/size are	\
1075			 * ignored and entire map is synced in any case.\
1076			 */						\
1077			EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),		\
1078			    0,						\
1079			    (_entries) * sizeof (efx_desc_t));		\
1080	_NOTE(CONSTANTCONDITION)					\
1081	} while (B_FALSE)
1082
1083extern	__checkReturn	efx_rc_t
1084efx_nic_biu_test(
1085	__in		efx_nic_t *enp);
1086
1087extern	__checkReturn	efx_rc_t
1088efx_mac_select(
1089	__in		efx_nic_t *enp);
1090
1091extern	void
1092efx_mac_multicast_hash_compute(
1093	__in_ecount(6*count)		uint8_t const *addrs,
1094	__in				int count,
1095	__out				efx_oword_t *hash_low,
1096	__out				efx_oword_t *hash_high);
1097
1098extern	__checkReturn	efx_rc_t
1099efx_phy_probe(
1100	__in		efx_nic_t *enp);
1101
1102extern			void
1103efx_phy_unprobe(
1104	__in		efx_nic_t *enp);
1105
1106#if EFSYS_OPT_VPD
1107
1108/* VPD utility functions */
1109
1110extern	__checkReturn		efx_rc_t
1111efx_vpd_hunk_length(
1112	__in_bcount(size)	caddr_t data,
1113	__in			size_t size,
1114	__out			size_t *lengthp);
1115
1116extern	__checkReturn		efx_rc_t
1117efx_vpd_hunk_verify(
1118	__in_bcount(size)	caddr_t data,
1119	__in			size_t size,
1120	__out_opt		boolean_t *cksummedp);
1121
1122extern	__checkReturn		efx_rc_t
1123efx_vpd_hunk_reinit(
1124	__in_bcount(size)	caddr_t data,
1125	__in			size_t size,
1126	__in			boolean_t wantpid);
1127
1128extern	__checkReturn		efx_rc_t
1129efx_vpd_hunk_get(
1130	__in_bcount(size)	caddr_t data,
1131	__in			size_t size,
1132	__in			efx_vpd_tag_t tag,
1133	__in			efx_vpd_keyword_t keyword,
1134	__out			unsigned int *payloadp,
1135	__out			uint8_t *paylenp);
1136
1137extern	__checkReturn			efx_rc_t
1138efx_vpd_hunk_next(
1139	__in_bcount(size)		caddr_t data,
1140	__in				size_t size,
1141	__out				efx_vpd_tag_t *tagp,
1142	__out				efx_vpd_keyword_t *keyword,
1143	__out_opt			unsigned int *payloadp,
1144	__out_opt			uint8_t *paylenp,
1145	__inout				unsigned int *contp);
1146
1147extern	__checkReturn		efx_rc_t
1148efx_vpd_hunk_set(
1149	__in_bcount(size)	caddr_t data,
1150	__in			size_t size,
1151	__in			efx_vpd_value_t *evvp);
1152
1153#endif	/* EFSYS_OPT_VPD */
1154
1155#if EFSYS_OPT_DIAG
1156
1157extern	efx_sram_pattern_fn_t	__efx_sram_pattern_fns[];
1158
1159typedef struct efx_register_set_s {
1160	unsigned int		address;
1161	unsigned int		step;
1162	unsigned int		rows;
1163	efx_oword_t		mask;
1164} efx_register_set_t;
1165
1166extern	__checkReturn	efx_rc_t
1167efx_nic_test_registers(
1168	__in		efx_nic_t *enp,
1169	__in		efx_register_set_t *rsp,
1170	__in		size_t count);
1171
1172extern	__checkReturn	efx_rc_t
1173efx_nic_test_tables(
1174	__in		efx_nic_t *enp,
1175	__in		efx_register_set_t *rsp,
1176	__in		efx_pattern_type_t pattern,
1177	__in		size_t count);
1178
1179#endif	/* EFSYS_OPT_DIAG */
1180
1181#if EFSYS_OPT_MCDI
1182
1183extern	__checkReturn		efx_rc_t
1184efx_mcdi_set_workaround(
1185	__in			efx_nic_t *enp,
1186	__in			uint32_t type,
1187	__in			boolean_t enabled,
1188	__out_opt		uint32_t *flagsp);
1189
1190extern	__checkReturn		efx_rc_t
1191efx_mcdi_get_workarounds(
1192	__in			efx_nic_t *enp,
1193	__out_opt		uint32_t *implementedp,
1194	__out_opt		uint32_t *enabledp);
1195
1196#endif /* EFSYS_OPT_MCDI */
1197
1198#ifdef	__cplusplus
1199}
1200#endif
1201
1202#endif	/* _SYS_EFX_IMPL_H */
1203