efx.h revision 294386 
1/*-
2 * Copyright (c) 2006-2015 Solarflare Communications Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 *    this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 *    this list of conditions and the following disclaimer in the documentation
12 *    and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
29 *
30 * $FreeBSD: stable/10/sys/dev/sfxge/common/efx.h 294386 2016-01-20 08:01:21Z arybchik $
31 */
32
33#ifndef	_SYS_EFX_H
34#define	_SYS_EFX_H
35
36#include "efsys.h"
37#include "efx_phy_ids.h"
38
39#ifdef	__cplusplus
40extern "C" {
41#endif
42
43#define	EFX_STATIC_ASSERT(_cond)		\
44	((void)sizeof(char[(_cond) ? 1 : -1]))
45
46#define	EFX_ARRAY_SIZE(_array)			\
47	(sizeof(_array) / sizeof((_array)[0]))
48
49#define	EFX_FIELD_OFFSET(_type, _field)		\
50	((size_t) &(((_type *)0)->_field))
51
52/* Return codes */
53
54typedef __success(return == 0) int efx_rc_t;
55
56
57/* Chip families */
58
59typedef enum efx_family_e {
60	EFX_FAMILY_INVALID,
61	EFX_FAMILY_FALCON,
62	EFX_FAMILY_SIENA,
63	EFX_FAMILY_HUNTINGTON,
64	EFX_FAMILY_MEDFORD,
65	EFX_FAMILY_NTYPES
66} efx_family_t;
67
68extern	__checkReturn	efx_rc_t
69efx_family(
70	__in		uint16_t venid,
71	__in		uint16_t devid,
72	__out		efx_family_t *efp);
73
74extern	__checkReturn	efx_rc_t
75efx_infer_family(
76	__in		efsys_bar_t *esbp,
77	__out		efx_family_t *efp);
78
79#define	EFX_PCI_VENID_SFC			0x1924
80
81#define	EFX_PCI_DEVID_FALCON			0x0710	/* SFC4000 */
82
83#define	EFX_PCI_DEVID_BETHPAGE			0x0803	/* SFC9020 */
84#define	EFX_PCI_DEVID_SIENA			0x0813	/* SFL9021 */
85#define	EFX_PCI_DEVID_SIENA_F1_UNINIT		0x0810
86
87#define	EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT	0x0901
88#define	EFX_PCI_DEVID_FARMINGDALE		0x0903	/* SFC9120 PF */
89#define	EFX_PCI_DEVID_GREENPORT			0x0923	/* SFC9140 PF */
90
91#define	EFX_PCI_DEVID_FARMINGDALE_VF		0x1903	/* SFC9120 VF */
92#define	EFX_PCI_DEVID_GREENPORT_VF		0x1923	/* SFC9140 VF */
93
94#define	EFX_PCI_DEVID_MEDFORD_PF_UNINIT		0x0913
95#define	EFX_PCI_DEVID_MEDFORD			0x0A03	/* SFC9240 PF */
96#define	EFX_PCI_DEVID_MEDFORD_VF		0x1A03	/* SFC9240 VF */
97
98#define	EFX_MEM_BAR	2
99
100/* Error codes */
101
102enum {
103	EFX_ERR_INVALID,
104	EFX_ERR_SRAM_OOB,
105	EFX_ERR_BUFID_DC_OOB,
106	EFX_ERR_MEM_PERR,
107	EFX_ERR_RBUF_OWN,
108	EFX_ERR_TBUF_OWN,
109	EFX_ERR_RDESQ_OWN,
110	EFX_ERR_TDESQ_OWN,
111	EFX_ERR_EVQ_OWN,
112	EFX_ERR_EVFF_OFLO,
113	EFX_ERR_ILL_ADDR,
114	EFX_ERR_SRAM_PERR,
115	EFX_ERR_NCODES
116};
117
118/* Calculate the IEEE 802.3 CRC32 of a MAC addr */
119extern	__checkReturn		uint32_t
120efx_crc32_calculate(
121	__in			uint32_t crc_init,
122	__in_ecount(length)	uint8_t const *input,
123	__in			int length);
124
125
126/* Type prototypes */
127
128typedef struct efx_rxq_s	efx_rxq_t;
129
130/* NIC */
131
132typedef struct efx_nic_s	efx_nic_t;
133
134#define	EFX_NIC_FUNC_PRIMARY	0x00000001
135#define	EFX_NIC_FUNC_LINKCTRL	0x00000002
136#define	EFX_NIC_FUNC_TRUSTED	0x00000004
137
138
139extern	__checkReturn	efx_rc_t
140efx_nic_create(
141	__in		efx_family_t family,
142	__in		efsys_identifier_t *esip,
143	__in		efsys_bar_t *esbp,
144	__in		efsys_lock_t *eslp,
145	__deref_out	efx_nic_t **enpp);
146
147extern	__checkReturn	efx_rc_t
148efx_nic_probe(
149	__in		efx_nic_t *enp);
150
151#if EFSYS_OPT_PCIE_TUNE
152
153extern	__checkReturn	efx_rc_t
154efx_nic_pcie_tune(
155	__in		efx_nic_t *enp,
156	unsigned int	nlanes);
157
158extern	__checkReturn	efx_rc_t
159efx_nic_pcie_extended_sync(
160	__in		efx_nic_t *enp);
161
162#endif	/* EFSYS_OPT_PCIE_TUNE */
163
164extern	__checkReturn	efx_rc_t
165efx_nic_init(
166	__in		efx_nic_t *enp);
167
168extern	__checkReturn	efx_rc_t
169efx_nic_reset(
170	__in		efx_nic_t *enp);
171
172#if EFSYS_OPT_DIAG
173
174extern	__checkReturn	efx_rc_t
175efx_nic_register_test(
176	__in		efx_nic_t *enp);
177
178#endif	/* EFSYS_OPT_DIAG */
179
180extern		void
181efx_nic_fini(
182	__in		efx_nic_t *enp);
183
184extern		void
185efx_nic_unprobe(
186	__in		efx_nic_t *enp);
187
188extern 		void
189efx_nic_destroy(
190	__in	efx_nic_t *enp);
191
192#if EFSYS_OPT_MCDI
193
194#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
195/* Huntington and Medford require MCDIv2 commands */
196#define	WITH_MCDI_V2 1
197#endif
198
199typedef struct efx_mcdi_req_s efx_mcdi_req_t;
200
201typedef enum efx_mcdi_exception_e {
202	EFX_MCDI_EXCEPTION_MC_REBOOT,
203	EFX_MCDI_EXCEPTION_MC_BADASSERT,
204} efx_mcdi_exception_t;
205
206#if EFSYS_OPT_MCDI_LOGGING
207typedef enum efx_log_msg_e
208{
209	EFX_LOG_INVALID,
210	EFX_LOG_MCDI_REQUEST,
211	EFX_LOG_MCDI_RESPONSE,
212} efx_log_msg_t;
213#endif /* EFSYS_OPT_MCDI_LOGGING */
214
215typedef struct efx_mcdi_transport_s {
216	void		*emt_context;
217	efsys_mem_t	*emt_dma_mem;
218	void		(*emt_execute)(void *, efx_mcdi_req_t *);
219	void		(*emt_ev_cpl)(void *);
220	void		(*emt_exception)(void *, efx_mcdi_exception_t);
221#if EFSYS_OPT_MCDI_LOGGING
222	void		(*emt_logger)(void *, efx_log_msg_t,
223					void *, size_t, void *, size_t);
224#endif /* EFSYS_OPT_MCDI_LOGGING */
225#if EFSYS_OPT_MCDI_PROXY_AUTH
226	void		(*emt_ev_proxy_response)(void *, uint32_t, efx_rc_t);
227#endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
228} efx_mcdi_transport_t;
229
230extern	__checkReturn	efx_rc_t
231efx_mcdi_init(
232	__in		efx_nic_t *enp,
233	__in		const efx_mcdi_transport_t *mtp);
234
235extern	__checkReturn	efx_rc_t
236efx_mcdi_reboot(
237	__in		efx_nic_t *enp);
238
239			void
240efx_mcdi_new_epoch(
241	__in		efx_nic_t *enp);
242
243extern			void
244efx_mcdi_request_start(
245	__in		efx_nic_t *enp,
246	__in		efx_mcdi_req_t *emrp,
247	__in		boolean_t ev_cpl);
248
249extern	__checkReturn	boolean_t
250efx_mcdi_request_poll(
251	__in		efx_nic_t *enp);
252
253extern	__checkReturn	boolean_t
254efx_mcdi_request_abort(
255	__in		efx_nic_t *enp);
256
257extern			void
258efx_mcdi_fini(
259	__in		efx_nic_t *enp);
260
261#endif	/* EFSYS_OPT_MCDI */
262
263/* INTR */
264
265#define	EFX_NINTR_FALCON 64
266#define	EFX_NINTR_SIENA 1024
267
268typedef enum efx_intr_type_e {
269	EFX_INTR_INVALID = 0,
270	EFX_INTR_LINE,
271	EFX_INTR_MESSAGE,
272	EFX_INTR_NTYPES
273} efx_intr_type_t;
274
275#define	EFX_INTR_SIZE	(sizeof (efx_oword_t))
276
277extern	__checkReturn	efx_rc_t
278efx_intr_init(
279	__in		efx_nic_t *enp,
280	__in		efx_intr_type_t type,
281	__in		efsys_mem_t *esmp);
282
283extern 			void
284efx_intr_enable(
285	__in		efx_nic_t *enp);
286
287extern 			void
288efx_intr_disable(
289	__in		efx_nic_t *enp);
290
291extern 			void
292efx_intr_disable_unlocked(
293	__in		efx_nic_t *enp);
294
295#define	EFX_INTR_NEVQS	32
296
297extern __checkReturn	efx_rc_t
298efx_intr_trigger(
299	__in		efx_nic_t *enp,
300	__in		unsigned int level);
301
302extern			void
303efx_intr_status_line(
304	__in		efx_nic_t *enp,
305	__out		boolean_t *fatalp,
306	__out		uint32_t *maskp);
307
308extern			void
309efx_intr_status_message(
310	__in		efx_nic_t *enp,
311	__in		unsigned int message,
312	__out		boolean_t *fatalp);
313
314extern			void
315efx_intr_fatal(
316	__in		efx_nic_t *enp);
317
318extern			void
319efx_intr_fini(
320	__in		efx_nic_t *enp);
321
322/* MAC */
323
324#if EFSYS_OPT_MAC_STATS
325
326/* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */
327typedef enum efx_mac_stat_e {
328	EFX_MAC_RX_OCTETS,
329	EFX_MAC_RX_PKTS,
330	EFX_MAC_RX_UNICST_PKTS,
331	EFX_MAC_RX_MULTICST_PKTS,
332	EFX_MAC_RX_BRDCST_PKTS,
333	EFX_MAC_RX_PAUSE_PKTS,
334	EFX_MAC_RX_LE_64_PKTS,
335	EFX_MAC_RX_65_TO_127_PKTS,
336	EFX_MAC_RX_128_TO_255_PKTS,
337	EFX_MAC_RX_256_TO_511_PKTS,
338	EFX_MAC_RX_512_TO_1023_PKTS,
339	EFX_MAC_RX_1024_TO_15XX_PKTS,
340	EFX_MAC_RX_GE_15XX_PKTS,
341	EFX_MAC_RX_ERRORS,
342	EFX_MAC_RX_FCS_ERRORS,
343	EFX_MAC_RX_DROP_EVENTS,
344	EFX_MAC_RX_FALSE_CARRIER_ERRORS,
345	EFX_MAC_RX_SYMBOL_ERRORS,
346	EFX_MAC_RX_ALIGN_ERRORS,
347	EFX_MAC_RX_INTERNAL_ERRORS,
348	EFX_MAC_RX_JABBER_PKTS,
349	EFX_MAC_RX_LANE0_CHAR_ERR,
350	EFX_MAC_RX_LANE1_CHAR_ERR,
351	EFX_MAC_RX_LANE2_CHAR_ERR,
352	EFX_MAC_RX_LANE3_CHAR_ERR,
353	EFX_MAC_RX_LANE0_DISP_ERR,
354	EFX_MAC_RX_LANE1_DISP_ERR,
355	EFX_MAC_RX_LANE2_DISP_ERR,
356	EFX_MAC_RX_LANE3_DISP_ERR,
357	EFX_MAC_RX_MATCH_FAULT,
358	EFX_MAC_RX_NODESC_DROP_CNT,
359	EFX_MAC_TX_OCTETS,
360	EFX_MAC_TX_PKTS,
361	EFX_MAC_TX_UNICST_PKTS,
362	EFX_MAC_TX_MULTICST_PKTS,
363	EFX_MAC_TX_BRDCST_PKTS,
364	EFX_MAC_TX_PAUSE_PKTS,
365	EFX_MAC_TX_LE_64_PKTS,
366	EFX_MAC_TX_65_TO_127_PKTS,
367	EFX_MAC_TX_128_TO_255_PKTS,
368	EFX_MAC_TX_256_TO_511_PKTS,
369	EFX_MAC_TX_512_TO_1023_PKTS,
370	EFX_MAC_TX_1024_TO_15XX_PKTS,
371	EFX_MAC_TX_GE_15XX_PKTS,
372	EFX_MAC_TX_ERRORS,
373	EFX_MAC_TX_SGL_COL_PKTS,
374	EFX_MAC_TX_MULT_COL_PKTS,
375	EFX_MAC_TX_EX_COL_PKTS,
376	EFX_MAC_TX_LATE_COL_PKTS,
377	EFX_MAC_TX_DEF_PKTS,
378	EFX_MAC_TX_EX_DEF_PKTS,
379	EFX_MAC_PM_TRUNC_BB_OVERFLOW,
380	EFX_MAC_PM_DISCARD_BB_OVERFLOW,
381	EFX_MAC_PM_TRUNC_VFIFO_FULL,
382	EFX_MAC_PM_DISCARD_VFIFO_FULL,
383	EFX_MAC_PM_TRUNC_QBB,
384	EFX_MAC_PM_DISCARD_QBB,
385	EFX_MAC_PM_DISCARD_MAPPING,
386	EFX_MAC_RXDP_Q_DISABLED_PKTS,
387	EFX_MAC_RXDP_DI_DROPPED_PKTS,
388	EFX_MAC_RXDP_STREAMING_PKTS,
389	EFX_MAC_RXDP_HLB_FETCH,
390	EFX_MAC_RXDP_HLB_WAIT,
391	EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
392	EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
393	EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
394	EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
395	EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
396	EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
397	EFX_MAC_VADAPTER_RX_BAD_PACKETS,
398	EFX_MAC_VADAPTER_RX_BAD_BYTES,
399	EFX_MAC_VADAPTER_RX_OVERFLOW,
400	EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
401	EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
402	EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
403	EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
404	EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
405	EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
406	EFX_MAC_VADAPTER_TX_BAD_PACKETS,
407	EFX_MAC_VADAPTER_TX_BAD_BYTES,
408	EFX_MAC_VADAPTER_TX_OVERFLOW,
409	EFX_MAC_NSTATS
410} efx_mac_stat_t;
411
412/* END MKCONFIG GENERATED EfxHeaderMacBlock */
413
414#endif	/* EFSYS_OPT_MAC_STATS */
415
416typedef enum efx_link_mode_e {
417	EFX_LINK_UNKNOWN = 0,
418	EFX_LINK_DOWN,
419	EFX_LINK_10HDX,
420	EFX_LINK_10FDX,
421	EFX_LINK_100HDX,
422	EFX_LINK_100FDX,
423	EFX_LINK_1000HDX,
424	EFX_LINK_1000FDX,
425	EFX_LINK_10000FDX,
426	EFX_LINK_40000FDX,
427	EFX_LINK_NMODES
428} efx_link_mode_t;
429
430#define	EFX_MAC_ADDR_LEN 6
431
432#define	EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t*)_address)[0] & 0x01)
433
434#define	EFX_MAC_MULTICAST_LIST_MAX	256
435
436#define	EFX_MAC_SDU_MAX	9202
437
438#define	EFX_MAC_PDU(_sdu) 				\
439	P2ROUNDUP(((_sdu)				\
440		    + /* EtherII */ 14			\
441		    + /* VLAN */ 4			\
442		    + /* CRC */ 4			\
443		    + /* bug16011 */ 16),		\
444		    (1 << 3))
445
446#define	EFX_MAC_PDU_MIN	60
447#define	EFX_MAC_PDU_MAX	EFX_MAC_PDU(EFX_MAC_SDU_MAX)
448
449extern	__checkReturn	efx_rc_t
450efx_mac_pdu_set(
451	__in		efx_nic_t *enp,
452	__in		size_t pdu);
453
454extern	__checkReturn	efx_rc_t
455efx_mac_addr_set(
456	__in		efx_nic_t *enp,
457	__in		uint8_t *addr);
458
459extern	__checkReturn			efx_rc_t
460efx_mac_filter_set(
461	__in				efx_nic_t *enp,
462	__in				boolean_t all_unicst,
463	__in				boolean_t mulcst,
464	__in				boolean_t all_mulcst,
465	__in				boolean_t brdcst);
466
467extern	__checkReturn	efx_rc_t
468efx_mac_multicast_list_set(
469	__in				efx_nic_t *enp,
470	__in_ecount(6*count)		uint8_t const *addrs,
471	__in				int count);
472
473extern	__checkReturn	efx_rc_t
474efx_mac_filter_default_rxq_set(
475	__in		efx_nic_t *enp,
476	__in		efx_rxq_t *erp,
477	__in		boolean_t using_rss);
478
479extern			void
480efx_mac_filter_default_rxq_clear(
481	__in		efx_nic_t *enp);
482
483extern	__checkReturn	efx_rc_t
484efx_mac_drain(
485	__in		efx_nic_t *enp,
486	__in		boolean_t enabled);
487
488extern	__checkReturn	efx_rc_t
489efx_mac_up(
490	__in		efx_nic_t *enp,
491	__out		boolean_t *mac_upp);
492
493#define	EFX_FCNTL_RESPOND	0x00000001
494#define	EFX_FCNTL_GENERATE	0x00000002
495
496extern	__checkReturn	efx_rc_t
497efx_mac_fcntl_set(
498	__in		efx_nic_t *enp,
499	__in		unsigned int fcntl,
500	__in		boolean_t autoneg);
501
502extern			void
503efx_mac_fcntl_get(
504	__in		efx_nic_t *enp,
505	__out		unsigned int *fcntl_wantedp,
506	__out		unsigned int *fcntl_linkp);
507
508
509#if EFSYS_OPT_MAC_STATS
510
511#if EFSYS_OPT_NAMES
512
513extern	__checkReturn			const char *
514efx_mac_stat_name(
515	__in				efx_nic_t *enp,
516	__in				unsigned int id);
517
518#endif	/* EFSYS_OPT_NAMES */
519
520#define	EFX_MAC_STATS_SIZE 0x400
521
522/*
523 * Upload mac statistics supported by the hardware into the given buffer.
524 *
525 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,
526 * and page aligned.
527 *
528 * The hardware will only DMA statistics that it understands (of course).
529 * Drivers should not make any assumptions about which statistics are
530 * supported, especially when the statistics are generated by firmware.
531 *
532 * Thus, drivers should zero this buffer before use, so that not-understood
533 * statistics read back as zero.
534 */
535extern	__checkReturn			efx_rc_t
536efx_mac_stats_upload(
537	__in				efx_nic_t *enp,
538	__in				efsys_mem_t *esmp);
539
540extern	__checkReturn			efx_rc_t
541efx_mac_stats_periodic(
542	__in				efx_nic_t *enp,
543	__in				efsys_mem_t *esmp,
544	__in				uint16_t period_ms,
545	__in				boolean_t events);
546
547extern	__checkReturn			efx_rc_t
548efx_mac_stats_update(
549	__in				efx_nic_t *enp,
550	__in				efsys_mem_t *esmp,
551	__inout_ecount(EFX_MAC_NSTATS)	efsys_stat_t *stat,
552	__inout_opt			uint32_t *generationp);
553
554#endif	/* EFSYS_OPT_MAC_STATS */
555
556/* MON */
557
558typedef enum efx_mon_type_e {
559	EFX_MON_INVALID = 0,
560	EFX_MON_NULL,
561	EFX_MON_LM87,
562	EFX_MON_MAX6647,
563	EFX_MON_SFC90X0,
564	EFX_MON_SFC91X0,
565	EFX_MON_SFC92X0,
566	EFX_MON_NTYPES
567} efx_mon_type_t;
568
569#if EFSYS_OPT_NAMES
570
571extern		const char *
572efx_mon_name(
573	__in	efx_nic_t *enp);
574
575#endif	/* EFSYS_OPT_NAMES */
576
577extern	__checkReturn	efx_rc_t
578efx_mon_init(
579	__in		efx_nic_t *enp);
580
581#if EFSYS_OPT_MON_STATS
582
583#define	EFX_MON_STATS_PAGE_SIZE 0x100
584#define	EFX_MON_MASK_ELEMENT_SIZE 32
585
586/* START MKCONFIG GENERATED MonitorHeaderStatsBlock c09b13f732431f23 */
587typedef enum efx_mon_stat_e {
588	EFX_MON_STAT_2_5V,
589	EFX_MON_STAT_VCCP1,
590	EFX_MON_STAT_VCC,
591	EFX_MON_STAT_5V,
592	EFX_MON_STAT_12V,
593	EFX_MON_STAT_VCCP2,
594	EFX_MON_STAT_EXT_TEMP,
595	EFX_MON_STAT_INT_TEMP,
596	EFX_MON_STAT_AIN1,
597	EFX_MON_STAT_AIN2,
598	EFX_MON_STAT_INT_COOLING,
599	EFX_MON_STAT_EXT_COOLING,
600	EFX_MON_STAT_1V,
601	EFX_MON_STAT_1_2V,
602	EFX_MON_STAT_1_8V,
603	EFX_MON_STAT_3_3V,
604	EFX_MON_STAT_1_2VA,
605	EFX_MON_STAT_VREF,
606	EFX_MON_STAT_VAOE,
607	EFX_MON_STAT_AOE_TEMP,
608	EFX_MON_STAT_PSU_AOE_TEMP,
609	EFX_MON_STAT_PSU_TEMP,
610	EFX_MON_STAT_FAN0,
611	EFX_MON_STAT_FAN1,
612	EFX_MON_STAT_FAN2,
613	EFX_MON_STAT_FAN3,
614	EFX_MON_STAT_FAN4,
615	EFX_MON_STAT_VAOE_IN,
616	EFX_MON_STAT_IAOE,
617	EFX_MON_STAT_IAOE_IN,
618	EFX_MON_STAT_NIC_POWER,
619	EFX_MON_STAT_0_9V,
620	EFX_MON_STAT_I0_9V,
621	EFX_MON_STAT_I1_2V,
622	EFX_MON_STAT_0_9V_ADC,
623	EFX_MON_STAT_INT_TEMP2,
624	EFX_MON_STAT_VREG_TEMP,
625	EFX_MON_STAT_VREG_0_9V_TEMP,
626	EFX_MON_STAT_VREG_1_2V_TEMP,
627	EFX_MON_STAT_INT_VPTAT,
628	EFX_MON_STAT_INT_ADC_TEMP,
629	EFX_MON_STAT_EXT_VPTAT,
630	EFX_MON_STAT_EXT_ADC_TEMP,
631	EFX_MON_STAT_AMBIENT_TEMP,
632	EFX_MON_STAT_AIRFLOW,
633	EFX_MON_STAT_VDD08D_VSS08D_CSR,
634	EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
635	EFX_MON_STAT_HOTPOINT_TEMP,
636	EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
637	EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
638	EFX_MON_STAT_MUM_VCC,
639	EFX_MON_STAT_0V9_A,
640	EFX_MON_STAT_I0V9_A,
641	EFX_MON_STAT_0V9_A_TEMP,
642	EFX_MON_STAT_0V9_B,
643	EFX_MON_STAT_I0V9_B,
644	EFX_MON_STAT_0V9_B_TEMP,
645	EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
646	EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
647	EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
648	EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
649	EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
650	EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
651	EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
652	EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
653	EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
654	EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
655	EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
656	EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
657	EFX_MON_STAT_SODIMM_VOUT,
658	EFX_MON_STAT_SODIMM_0_TEMP,
659	EFX_MON_STAT_SODIMM_1_TEMP,
660	EFX_MON_STAT_PHY0_VCC,
661	EFX_MON_STAT_PHY1_VCC,
662	EFX_MON_STAT_CONTROLLER_TDIODE_TEMP,
663	EFX_MON_NSTATS
664} efx_mon_stat_t;
665
666/* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
667
668typedef enum efx_mon_stat_state_e {
669	EFX_MON_STAT_STATE_OK = 0,
670	EFX_MON_STAT_STATE_WARNING = 1,
671	EFX_MON_STAT_STATE_FATAL = 2,
672	EFX_MON_STAT_STATE_BROKEN = 3,
673	EFX_MON_STAT_STATE_NO_READING = 4,
674} efx_mon_stat_state_t;
675
676typedef struct efx_mon_stat_value_s {
677	uint16_t	emsv_value;
678	uint16_t	emsv_state;
679} efx_mon_stat_value_t;
680
681#if EFSYS_OPT_NAMES
682
683extern					const char *
684efx_mon_stat_name(
685	__in				efx_nic_t *enp,
686	__in				efx_mon_stat_t id);
687
688#endif	/* EFSYS_OPT_NAMES */
689
690extern	__checkReturn			efx_rc_t
691efx_mon_stats_update(
692	__in				efx_nic_t *enp,
693	__in				efsys_mem_t *esmp,
694	__inout_ecount(EFX_MON_NSTATS)	efx_mon_stat_value_t *values);
695
696#endif	/* EFSYS_OPT_MON_STATS */
697
698extern		void
699efx_mon_fini(
700	__in	efx_nic_t *enp);
701
702/* PHY */
703
704#define	PMA_PMD_MMD	1
705#define	PCS_MMD		3
706#define	PHY_XS_MMD	4
707#define	DTE_XS_MMD	5
708#define	AN_MMD		7
709#define	CL22EXT_MMD	29
710
711#define	MAXMMD		((1 << 5) - 1)
712
713extern	__checkReturn	efx_rc_t
714efx_phy_verify(
715	__in		efx_nic_t *enp);
716
717#if EFSYS_OPT_PHY_LED_CONTROL
718
719typedef enum efx_phy_led_mode_e {
720	EFX_PHY_LED_DEFAULT = 0,
721	EFX_PHY_LED_OFF,
722	EFX_PHY_LED_ON,
723	EFX_PHY_LED_FLASH,
724	EFX_PHY_LED_NMODES
725} efx_phy_led_mode_t;
726
727extern	__checkReturn	efx_rc_t
728efx_phy_led_set(
729	__in	efx_nic_t *enp,
730	__in	efx_phy_led_mode_t mode);
731
732#endif	/* EFSYS_OPT_PHY_LED_CONTROL */
733
734extern	__checkReturn	efx_rc_t
735efx_port_init(
736	__in		efx_nic_t *enp);
737
738#if EFSYS_OPT_LOOPBACK
739
740typedef enum efx_loopback_type_e {
741	EFX_LOOPBACK_OFF = 0,
742	EFX_LOOPBACK_DATA = 1,
743	EFX_LOOPBACK_GMAC = 2,
744	EFX_LOOPBACK_XGMII = 3,
745	EFX_LOOPBACK_XGXS = 4,
746	EFX_LOOPBACK_XAUI = 5,
747	EFX_LOOPBACK_GMII = 6,
748	EFX_LOOPBACK_SGMII = 7,
749	EFX_LOOPBACK_XGBR = 8,
750	EFX_LOOPBACK_XFI = 9,
751	EFX_LOOPBACK_XAUI_FAR = 10,
752	EFX_LOOPBACK_GMII_FAR = 11,
753	EFX_LOOPBACK_SGMII_FAR = 12,
754	EFX_LOOPBACK_XFI_FAR = 13,
755	EFX_LOOPBACK_GPHY = 14,
756	EFX_LOOPBACK_PHY_XS = 15,
757	EFX_LOOPBACK_PCS = 16,
758	EFX_LOOPBACK_PMA_PMD = 17,
759	EFX_LOOPBACK_XPORT = 18,
760	EFX_LOOPBACK_XGMII_WS = 19,
761	EFX_LOOPBACK_XAUI_WS = 20,
762	EFX_LOOPBACK_XAUI_WS_FAR = 21,
763	EFX_LOOPBACK_XAUI_WS_NEAR = 22,
764	EFX_LOOPBACK_GMII_WS = 23,
765	EFX_LOOPBACK_XFI_WS = 24,
766	EFX_LOOPBACK_XFI_WS_FAR = 25,
767	EFX_LOOPBACK_PHYXS_WS = 26,
768	EFX_LOOPBACK_PMA_INT = 27,
769	EFX_LOOPBACK_SD_NEAR = 28,
770	EFX_LOOPBACK_SD_FAR = 29,
771	EFX_LOOPBACK_PMA_INT_WS = 30,
772	EFX_LOOPBACK_SD_FEP2_WS = 31,
773	EFX_LOOPBACK_SD_FEP1_5_WS = 32,
774	EFX_LOOPBACK_SD_FEP_WS = 33,
775	EFX_LOOPBACK_SD_FES_WS = 34,
776	EFX_LOOPBACK_NTYPES
777} efx_loopback_type_t;
778
779typedef enum efx_loopback_kind_e {
780	EFX_LOOPBACK_KIND_OFF = 0,
781	EFX_LOOPBACK_KIND_ALL,
782	EFX_LOOPBACK_KIND_MAC,
783	EFX_LOOPBACK_KIND_PHY,
784	EFX_LOOPBACK_NKINDS
785} efx_loopback_kind_t;
786
787extern			void
788efx_loopback_mask(
789	__in	efx_loopback_kind_t loopback_kind,
790	__out	efx_qword_t *maskp);
791
792extern	__checkReturn	efx_rc_t
793efx_port_loopback_set(
794	__in	efx_nic_t *enp,
795	__in	efx_link_mode_t link_mode,
796	__in	efx_loopback_type_t type);
797
798#if EFSYS_OPT_NAMES
799
800extern	__checkReturn	const char *
801efx_loopback_type_name(
802	__in		efx_nic_t *enp,
803	__in		efx_loopback_type_t type);
804
805#endif	/* EFSYS_OPT_NAMES */
806
807#endif	/* EFSYS_OPT_LOOPBACK */
808
809extern	__checkReturn	efx_rc_t
810efx_port_poll(
811	__in		efx_nic_t *enp,
812	__out_opt	efx_link_mode_t	*link_modep);
813
814extern 		void
815efx_port_fini(
816	__in	efx_nic_t *enp);
817
818typedef enum efx_phy_cap_type_e {
819	EFX_PHY_CAP_INVALID = 0,
820	EFX_PHY_CAP_10HDX,
821	EFX_PHY_CAP_10FDX,
822	EFX_PHY_CAP_100HDX,
823	EFX_PHY_CAP_100FDX,
824	EFX_PHY_CAP_1000HDX,
825	EFX_PHY_CAP_1000FDX,
826	EFX_PHY_CAP_10000FDX,
827	EFX_PHY_CAP_PAUSE,
828	EFX_PHY_CAP_ASYM,
829	EFX_PHY_CAP_AN,
830	EFX_PHY_CAP_40000FDX,
831	EFX_PHY_CAP_NTYPES
832} efx_phy_cap_type_t;
833
834
835#define	EFX_PHY_CAP_CURRENT	0x00000000
836#define	EFX_PHY_CAP_DEFAULT	0x00000001
837#define	EFX_PHY_CAP_PERM	0x00000002
838
839extern		void
840efx_phy_adv_cap_get(
841	__in		efx_nic_t *enp,
842	__in            uint32_t flag,
843	__out		uint32_t *maskp);
844
845extern	__checkReturn	efx_rc_t
846efx_phy_adv_cap_set(
847	__in		efx_nic_t *enp,
848	__in		uint32_t mask);
849
850extern			void
851efx_phy_lp_cap_get(
852	__in		efx_nic_t *enp,
853	__out		uint32_t *maskp);
854
855extern	__checkReturn	efx_rc_t
856efx_phy_oui_get(
857	__in		efx_nic_t *enp,
858	__out		uint32_t *ouip);
859
860typedef enum efx_phy_media_type_e {
861	EFX_PHY_MEDIA_INVALID = 0,
862	EFX_PHY_MEDIA_XAUI,
863	EFX_PHY_MEDIA_CX4,
864	EFX_PHY_MEDIA_KX4,
865	EFX_PHY_MEDIA_XFP,
866	EFX_PHY_MEDIA_SFP_PLUS,
867	EFX_PHY_MEDIA_BASE_T,
868	EFX_PHY_MEDIA_QSFP_PLUS,
869	EFX_PHY_MEDIA_NTYPES
870} efx_phy_media_type_t;
871
872/* Get the type of medium currently used.  If the board has ports for
873 * modules, a module is present, and we recognise the media type of
874 * the module, then this will be the media type of the module.
875 * Otherwise it will be the media type of the port.
876 */
877extern			void
878efx_phy_media_type_get(
879	__in		efx_nic_t *enp,
880	__out		efx_phy_media_type_t *typep);
881
882#if EFSYS_OPT_PHY_STATS
883
884/* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
885typedef enum efx_phy_stat_e {
886	EFX_PHY_STAT_OUI,
887	EFX_PHY_STAT_PMA_PMD_LINK_UP,
888	EFX_PHY_STAT_PMA_PMD_RX_FAULT,
889	EFX_PHY_STAT_PMA_PMD_TX_FAULT,
890	EFX_PHY_STAT_PMA_PMD_REV_A,
891	EFX_PHY_STAT_PMA_PMD_REV_B,
892	EFX_PHY_STAT_PMA_PMD_REV_C,
893	EFX_PHY_STAT_PMA_PMD_REV_D,
894	EFX_PHY_STAT_PCS_LINK_UP,
895	EFX_PHY_STAT_PCS_RX_FAULT,
896	EFX_PHY_STAT_PCS_TX_FAULT,
897	EFX_PHY_STAT_PCS_BER,
898	EFX_PHY_STAT_PCS_BLOCK_ERRORS,
899	EFX_PHY_STAT_PHY_XS_LINK_UP,
900	EFX_PHY_STAT_PHY_XS_RX_FAULT,
901	EFX_PHY_STAT_PHY_XS_TX_FAULT,
902	EFX_PHY_STAT_PHY_XS_ALIGN,
903	EFX_PHY_STAT_PHY_XS_SYNC_A,
904	EFX_PHY_STAT_PHY_XS_SYNC_B,
905	EFX_PHY_STAT_PHY_XS_SYNC_C,
906	EFX_PHY_STAT_PHY_XS_SYNC_D,
907	EFX_PHY_STAT_AN_LINK_UP,
908	EFX_PHY_STAT_AN_MASTER,
909	EFX_PHY_STAT_AN_LOCAL_RX_OK,
910	EFX_PHY_STAT_AN_REMOTE_RX_OK,
911	EFX_PHY_STAT_CL22EXT_LINK_UP,
912	EFX_PHY_STAT_SNR_A,
913	EFX_PHY_STAT_SNR_B,
914	EFX_PHY_STAT_SNR_C,
915	EFX_PHY_STAT_SNR_D,
916	EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
917	EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
918	EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
919	EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
920	EFX_PHY_STAT_AN_COMPLETE,
921	EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
922	EFX_PHY_STAT_PMA_PMD_REV_MINOR,
923	EFX_PHY_STAT_PMA_PMD_REV_MICRO,
924	EFX_PHY_STAT_PCS_FW_VERSION_0,
925	EFX_PHY_STAT_PCS_FW_VERSION_1,
926	EFX_PHY_STAT_PCS_FW_VERSION_2,
927	EFX_PHY_STAT_PCS_FW_VERSION_3,
928	EFX_PHY_STAT_PCS_FW_BUILD_YY,
929	EFX_PHY_STAT_PCS_FW_BUILD_MM,
930	EFX_PHY_STAT_PCS_FW_BUILD_DD,
931	EFX_PHY_STAT_PCS_OP_MODE,
932	EFX_PHY_NSTATS
933} efx_phy_stat_t;
934
935/* END MKCONFIG GENERATED PhyHeaderStatsBlock */
936
937#if EFSYS_OPT_NAMES
938
939extern					const char *
940efx_phy_stat_name(
941	__in				efx_nic_t *enp,
942	__in				efx_phy_stat_t stat);
943
944#endif	/* EFSYS_OPT_NAMES */
945
946#define	EFX_PHY_STATS_SIZE 0x100
947
948extern	__checkReturn			efx_rc_t
949efx_phy_stats_update(
950	__in				efx_nic_t *enp,
951	__in				efsys_mem_t *esmp,
952	__inout_ecount(EFX_PHY_NSTATS)	uint32_t *stat);
953
954#endif	/* EFSYS_OPT_PHY_STATS */
955
956#if EFSYS_OPT_PHY_PROPS
957
958#if EFSYS_OPT_NAMES
959
960extern		const char *
961efx_phy_prop_name(
962	__in	efx_nic_t *enp,
963	__in	unsigned int id);
964
965#endif	/* EFSYS_OPT_NAMES */
966
967#define	EFX_PHY_PROP_DEFAULT	0x00000001
968
969extern	__checkReturn	efx_rc_t
970efx_phy_prop_get(
971	__in		efx_nic_t *enp,
972	__in		unsigned int id,
973	__in		uint32_t flags,
974	__out		uint32_t *valp);
975
976extern	__checkReturn	efx_rc_t
977efx_phy_prop_set(
978	__in		efx_nic_t *enp,
979	__in		unsigned int id,
980	__in		uint32_t val);
981
982#endif	/* EFSYS_OPT_PHY_PROPS */
983
984#if EFSYS_OPT_BIST
985
986typedef enum efx_bist_type_e {
987	EFX_BIST_TYPE_UNKNOWN,
988	EFX_BIST_TYPE_PHY_NORMAL,
989	EFX_BIST_TYPE_PHY_CABLE_SHORT,
990	EFX_BIST_TYPE_PHY_CABLE_LONG,
991	EFX_BIST_TYPE_MC_MEM,	/* Test the MC DMEM and IMEM */
992	EFX_BIST_TYPE_SAT_MEM,	/* Test the DMEM and IMEM of satellite cpus*/
993	EFX_BIST_TYPE_REG,	/* Test the register memories */
994	EFX_BIST_TYPE_NTYPES,
995} efx_bist_type_t;
996
997typedef enum efx_bist_result_e {
998	EFX_BIST_RESULT_UNKNOWN,
999	EFX_BIST_RESULT_RUNNING,
1000	EFX_BIST_RESULT_PASSED,
1001	EFX_BIST_RESULT_FAILED,
1002} efx_bist_result_t;
1003
1004typedef enum efx_phy_cable_status_e {
1005	EFX_PHY_CABLE_STATUS_OK,
1006	EFX_PHY_CABLE_STATUS_INVALID,
1007	EFX_PHY_CABLE_STATUS_OPEN,
1008	EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1009	EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1010	EFX_PHY_CABLE_STATUS_BUSY,
1011} efx_phy_cable_status_t;
1012
1013typedef enum efx_bist_value_e {
1014	EFX_BIST_PHY_CABLE_LENGTH_A,
1015	EFX_BIST_PHY_CABLE_LENGTH_B,
1016	EFX_BIST_PHY_CABLE_LENGTH_C,
1017	EFX_BIST_PHY_CABLE_LENGTH_D,
1018	EFX_BIST_PHY_CABLE_STATUS_A,
1019	EFX_BIST_PHY_CABLE_STATUS_B,
1020	EFX_BIST_PHY_CABLE_STATUS_C,
1021	EFX_BIST_PHY_CABLE_STATUS_D,
1022	EFX_BIST_FAULT_CODE,
1023	/* Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1024	 * response. */
1025	EFX_BIST_MEM_TEST,
1026	EFX_BIST_MEM_ADDR,
1027	EFX_BIST_MEM_BUS,
1028	EFX_BIST_MEM_EXPECT,
1029	EFX_BIST_MEM_ACTUAL,
1030	EFX_BIST_MEM_ECC,
1031	EFX_BIST_MEM_ECC_PARITY,
1032	EFX_BIST_MEM_ECC_FATAL,
1033	EFX_BIST_NVALUES,
1034} efx_bist_value_t;
1035
1036extern	__checkReturn		efx_rc_t
1037efx_bist_enable_offline(
1038	__in			efx_nic_t *enp);
1039
1040extern	__checkReturn		efx_rc_t
1041efx_bist_start(
1042	__in			efx_nic_t *enp,
1043	__in			efx_bist_type_t type);
1044
1045extern	__checkReturn		efx_rc_t
1046efx_bist_poll(
1047	__in			efx_nic_t *enp,
1048	__in			efx_bist_type_t type,
1049	__out			efx_bist_result_t *resultp,
1050	__out_opt		uint32_t *value_maskp,
1051	__out_ecount_opt(count)	unsigned long *valuesp,
1052	__in			size_t count);
1053
1054extern				void
1055efx_bist_stop(
1056	__in			efx_nic_t *enp,
1057	__in			efx_bist_type_t type);
1058
1059#endif	/* EFSYS_OPT_BIST */
1060
1061#define	EFX_FEATURE_IPV6		0x00000001
1062#define	EFX_FEATURE_LFSR_HASH_INSERT	0x00000002
1063#define	EFX_FEATURE_LINK_EVENTS		0x00000004
1064#define	EFX_FEATURE_PERIODIC_MAC_STATS	0x00000008
1065#define	EFX_FEATURE_WOL			0x00000010
1066#define	EFX_FEATURE_MCDI		0x00000020
1067#define	EFX_FEATURE_LOOKAHEAD_SPLIT	0x00000040
1068#define	EFX_FEATURE_MAC_HEADER_FILTERS	0x00000080
1069#define	EFX_FEATURE_TURBO		0x00000100
1070#define	EFX_FEATURE_MCDI_DMA		0x00000200
1071#define	EFX_FEATURE_TX_SRC_FILTERS	0x00000400
1072#define	EFX_FEATURE_PIO_BUFFERS		0x00000800
1073#define	EFX_FEATURE_FW_ASSISTED_TSO	0x00001000
1074#define	EFX_FEATURE_FW_ASSISTED_TSO_V2	0x00002000
1075
1076typedef struct efx_nic_cfg_s {
1077	uint32_t		enc_board_type;
1078	uint32_t		enc_phy_type;
1079#if EFSYS_OPT_NAMES
1080	char			enc_phy_name[21];
1081#endif
1082	char			enc_phy_revision[21];
1083	efx_mon_type_t		enc_mon_type;
1084#if EFSYS_OPT_MON_STATS
1085	uint32_t		enc_mon_stat_dma_buf_size;
1086	uint32_t		enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1087#endif
1088	unsigned int		enc_features;
1089	uint8_t			enc_mac_addr[6];
1090	uint8_t			enc_port;	/* PHY port number */
1091	uint32_t		enc_func_flags;
1092	uint32_t		enc_intr_vec_base;
1093	uint32_t		enc_intr_limit;
1094	uint32_t		enc_evq_limit;
1095	uint32_t		enc_txq_limit;
1096	uint32_t		enc_rxq_limit;
1097	uint32_t		enc_buftbl_limit;
1098	uint32_t		enc_piobuf_limit;
1099	uint32_t		enc_piobuf_size;
1100	uint32_t		enc_piobuf_min_alloc_size;
1101	uint32_t		enc_evq_timer_quantum_ns;
1102	uint32_t		enc_evq_timer_max_us;
1103	uint32_t		enc_clk_mult;
1104	uint32_t		enc_rx_prefix_size;
1105	uint32_t		enc_rx_buf_align_start;
1106	uint32_t		enc_rx_buf_align_end;
1107#if EFSYS_OPT_LOOPBACK
1108	efx_qword_t		enc_loopback_types[EFX_LINK_NMODES];
1109#endif	/* EFSYS_OPT_LOOPBACK */
1110#if EFSYS_OPT_PHY_FLAGS
1111	uint32_t		enc_phy_flags_mask;
1112#endif	/* EFSYS_OPT_PHY_FLAGS */
1113#if EFSYS_OPT_PHY_LED_CONTROL
1114	uint32_t		enc_led_mask;
1115#endif	/* EFSYS_OPT_PHY_LED_CONTROL */
1116#if EFSYS_OPT_PHY_STATS
1117	uint64_t		enc_phy_stat_mask;
1118#endif	/* EFSYS_OPT_PHY_STATS */
1119#if EFSYS_OPT_PHY_PROPS
1120	unsigned int		enc_phy_nprops;
1121#endif	/* EFSYS_OPT_PHY_PROPS */
1122#if EFSYS_OPT_SIENA
1123	uint8_t			enc_mcdi_mdio_channel;
1124#if EFSYS_OPT_PHY_STATS
1125	uint32_t		enc_mcdi_phy_stat_mask;
1126#endif	/* EFSYS_OPT_PHY_STATS */
1127#endif /* EFSYS_OPT_SIENA */
1128#if (EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
1129#if EFSYS_OPT_MON_STATS
1130	uint32_t		*enc_mcdi_sensor_maskp;
1131	uint32_t		enc_mcdi_sensor_mask_size;
1132#endif	/* EFSYS_OPT_MON_STATS */
1133#endif	/* (EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
1134#if EFSYS_OPT_BIST
1135	uint32_t		enc_bist_mask;
1136#endif	/* EFSYS_OPT_BIST */
1137#if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
1138	uint32_t		enc_pf;
1139	uint32_t		enc_vf;
1140	uint32_t		enc_privilege_mask;
1141#endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
1142	boolean_t		enc_bug26807_workaround;
1143	boolean_t		enc_bug35388_workaround;
1144	boolean_t		enc_bug41750_workaround;
1145	boolean_t		enc_rx_batching_enabled;
1146	/* Maximum number of descriptors completed in an rx event. */
1147	uint32_t		enc_rx_batch_max;
1148        /* Number of rx descriptors the hardware requires for a push. */
1149        uint32_t		enc_rx_push_align;
1150	/*
1151	 * Maximum number of bytes into the packet the TCP header can start for
1152	 * the hardware to apply TSO packet edits.
1153	 */
1154	uint32_t                enc_tx_tso_tcp_header_offset_limit;
1155	boolean_t               enc_fw_assisted_tso_enabled;
1156	boolean_t               enc_fw_assisted_tso_v2_enabled;
1157	boolean_t               enc_hw_tx_insert_vlan_enabled;
1158	/* Datapath firmware vadapter/vport/vswitch support */
1159	boolean_t		enc_datapath_cap_evb;
1160	boolean_t               enc_rx_disable_scatter_supported;
1161	boolean_t               enc_allow_set_mac_with_installed_filters;
1162	/* External port identifier */
1163	uint8_t			enc_external_port;
1164	uint32_t		enc_mcdi_max_payload_length;
1165} efx_nic_cfg_t;
1166
1167#define	EFX_PCI_FUNCTION_IS_PF(_encp)	((_encp)->enc_vf == 0xffff)
1168#define	EFX_PCI_FUNCTION_IS_VF(_encp)	((_encp)->enc_vf != 0xffff)
1169
1170#define	EFX_PCI_FUNCTION(_encp)	\
1171	(EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1172
1173#define	EFX_PCI_VF_PARENT(_encp)	((_encp)->enc_pf)
1174
1175extern			const efx_nic_cfg_t *
1176efx_nic_cfg_get(
1177	__in		efx_nic_t *enp);
1178
1179/* Driver resource limits (minimum required/maximum usable). */
1180typedef struct efx_drv_limits_s
1181{
1182	uint32_t	edl_min_evq_count;
1183	uint32_t	edl_max_evq_count;
1184
1185	uint32_t	edl_min_rxq_count;
1186	uint32_t	edl_max_rxq_count;
1187
1188	uint32_t	edl_min_txq_count;
1189	uint32_t	edl_max_txq_count;
1190
1191	/* PIO blocks (sub-allocated from piobuf) */
1192	uint32_t	edl_min_pio_alloc_size;
1193	uint32_t	edl_max_pio_alloc_count;
1194} efx_drv_limits_t;
1195
1196extern	__checkReturn	efx_rc_t
1197efx_nic_set_drv_limits(
1198	__inout		efx_nic_t *enp,
1199	__in		efx_drv_limits_t *edlp);
1200
1201typedef enum efx_nic_region_e {
1202	EFX_REGION_VI,			/* Memory BAR UC mapping */
1203	EFX_REGION_PIO_WRITE_VI,	/* Memory BAR WC mapping */
1204} efx_nic_region_t;
1205
1206extern	__checkReturn	efx_rc_t
1207efx_nic_get_bar_region(
1208	__in		efx_nic_t *enp,
1209	__in		efx_nic_region_t region,
1210	__out		uint32_t *offsetp,
1211	__out		size_t *sizep);
1212
1213extern	__checkReturn	efx_rc_t
1214efx_nic_get_vi_pool(
1215	__in		efx_nic_t *enp,
1216	__out		uint32_t *evq_countp,
1217	__out		uint32_t *rxq_countp,
1218	__out		uint32_t *txq_countp);
1219
1220
1221#if EFSYS_OPT_VPD
1222
1223typedef enum efx_vpd_tag_e {
1224	EFX_VPD_ID = 0x02,
1225	EFX_VPD_END = 0x0f,
1226	EFX_VPD_RO = 0x10,
1227	EFX_VPD_RW = 0x11,
1228} efx_vpd_tag_t;
1229
1230typedef uint16_t efx_vpd_keyword_t;
1231
1232typedef struct efx_vpd_value_s {
1233	efx_vpd_tag_t		evv_tag;
1234	efx_vpd_keyword_t	evv_keyword;
1235	uint8_t			evv_length;
1236	uint8_t			evv_value[0x100];
1237} efx_vpd_value_t;
1238
1239
1240#define	EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1241
1242extern	__checkReturn		efx_rc_t
1243efx_vpd_init(
1244	__in			efx_nic_t *enp);
1245
1246extern	__checkReturn		efx_rc_t
1247efx_vpd_size(
1248	__in			efx_nic_t *enp,
1249	__out			size_t *sizep);
1250
1251extern	__checkReturn		efx_rc_t
1252efx_vpd_read(
1253	__in			efx_nic_t *enp,
1254	__out_bcount(size)	caddr_t data,
1255	__in			size_t size);
1256
1257extern	__checkReturn		efx_rc_t
1258efx_vpd_verify(
1259	__in			efx_nic_t *enp,
1260	__in_bcount(size)	caddr_t data,
1261	__in			size_t size);
1262
1263extern  __checkReturn		efx_rc_t
1264efx_vpd_reinit(
1265	__in			efx_nic_t *enp,
1266	__in_bcount(size)	caddr_t data,
1267	__in			size_t size);
1268
1269extern	__checkReturn		efx_rc_t
1270efx_vpd_get(
1271	__in			efx_nic_t *enp,
1272	__in_bcount(size)	caddr_t data,
1273	__in			size_t size,
1274	__inout			efx_vpd_value_t *evvp);
1275
1276extern	__checkReturn		efx_rc_t
1277efx_vpd_set(
1278	__in			efx_nic_t *enp,
1279	__inout_bcount(size)	caddr_t data,
1280	__in			size_t size,
1281	__in			efx_vpd_value_t *evvp);
1282
1283extern	__checkReturn		efx_rc_t
1284efx_vpd_next(
1285	__in			efx_nic_t *enp,
1286	__inout_bcount(size)	caddr_t data,
1287	__in			size_t size,
1288	__out			efx_vpd_value_t *evvp,
1289	__inout			unsigned int *contp);
1290
1291extern __checkReturn		efx_rc_t
1292efx_vpd_write(
1293	__in			efx_nic_t *enp,
1294	__in_bcount(size)	caddr_t data,
1295	__in			size_t size);
1296
1297extern				void
1298efx_vpd_fini(
1299	__in			efx_nic_t *enp);
1300
1301#endif	/* EFSYS_OPT_VPD */
1302
1303/* NVRAM */
1304
1305#if EFSYS_OPT_NVRAM
1306
1307typedef enum efx_nvram_type_e {
1308	EFX_NVRAM_INVALID = 0,
1309	EFX_NVRAM_BOOTROM,
1310	EFX_NVRAM_BOOTROM_CFG,
1311	EFX_NVRAM_MC_FIRMWARE,
1312	EFX_NVRAM_MC_GOLDEN,
1313	EFX_NVRAM_PHY,
1314	EFX_NVRAM_NULLPHY,
1315	EFX_NVRAM_FPGA,
1316	EFX_NVRAM_FCFW,
1317	EFX_NVRAM_CPLD,
1318	EFX_NVRAM_FPGA_BACKUP,
1319	EFX_NVRAM_DYNAMIC_CFG,
1320	EFX_NVRAM_LICENSE,
1321	EFX_NVRAM_NTYPES,
1322} efx_nvram_type_t;
1323
1324extern	__checkReturn		efx_rc_t
1325efx_nvram_init(
1326	__in			efx_nic_t *enp);
1327
1328#if EFSYS_OPT_DIAG
1329
1330extern	__checkReturn		efx_rc_t
1331efx_nvram_test(
1332	__in			efx_nic_t *enp);
1333
1334#endif	/* EFSYS_OPT_DIAG */
1335
1336extern	__checkReturn		efx_rc_t
1337efx_nvram_size(
1338	__in			efx_nic_t *enp,
1339	__in			efx_nvram_type_t type,
1340	__out			size_t *sizep);
1341
1342extern	__checkReturn		efx_rc_t
1343efx_nvram_rw_start(
1344	__in			efx_nic_t *enp,
1345	__in			efx_nvram_type_t type,
1346	__out_opt		size_t *pref_chunkp);
1347
1348extern				void
1349efx_nvram_rw_finish(
1350	__in			efx_nic_t *enp,
1351	__in			efx_nvram_type_t type);
1352
1353extern	__checkReturn		efx_rc_t
1354efx_nvram_get_version(
1355	__in			efx_nic_t *enp,
1356	__in			efx_nvram_type_t type,
1357	__out			uint32_t *subtypep,
1358	__out_ecount(4)		uint16_t version[4]);
1359
1360extern	__checkReturn		efx_rc_t
1361efx_nvram_read_chunk(
1362	__in			efx_nic_t *enp,
1363	__in			efx_nvram_type_t type,
1364	__in			unsigned int offset,
1365	__out_bcount(size)	caddr_t data,
1366	__in			size_t size);
1367
1368extern	__checkReturn		efx_rc_t
1369efx_nvram_set_version(
1370	__in			efx_nic_t *enp,
1371	__in			efx_nvram_type_t type,
1372	__in_ecount(4)		uint16_t version[4]);
1373
1374/* Validate contents of TLV formatted partition */
1375extern	__checkReturn		efx_rc_t
1376efx_nvram_tlv_validate(
1377	__in			efx_nic_t *enp,
1378	__in			uint32_t partn,
1379	__in_bcount(partn_size)	caddr_t partn_data,
1380	__in			size_t partn_size);
1381
1382extern	 __checkReturn		efx_rc_t
1383efx_nvram_erase(
1384	__in			efx_nic_t *enp,
1385	__in			efx_nvram_type_t type);
1386
1387extern	__checkReturn		efx_rc_t
1388efx_nvram_write_chunk(
1389	__in			efx_nic_t *enp,
1390	__in			efx_nvram_type_t type,
1391	__in			unsigned int offset,
1392	__in_bcount(size)	caddr_t data,
1393	__in			size_t size);
1394
1395extern				void
1396efx_nvram_fini(
1397	__in			efx_nic_t *enp);
1398
1399#endif	/* EFSYS_OPT_NVRAM */
1400
1401#if EFSYS_OPT_BOOTCFG
1402
1403extern				efx_rc_t
1404efx_bootcfg_read(
1405	__in			efx_nic_t *enp,
1406	__out_bcount(size)	caddr_t data,
1407	__in			size_t size);
1408
1409extern				efx_rc_t
1410efx_bootcfg_write(
1411	__in			efx_nic_t *enp,
1412	__in_bcount(size)	caddr_t data,
1413	__in			size_t size);
1414
1415#endif	/* EFSYS_OPT_BOOTCFG */
1416
1417#if EFSYS_OPT_WOL
1418
1419typedef enum efx_wol_type_e {
1420	EFX_WOL_TYPE_INVALID,
1421	EFX_WOL_TYPE_MAGIC,
1422	EFX_WOL_TYPE_BITMAP,
1423	EFX_WOL_TYPE_LINK,
1424	EFX_WOL_NTYPES,
1425} efx_wol_type_t;
1426
1427typedef enum efx_lightsout_offload_type_e {
1428	EFX_LIGHTSOUT_OFFLOAD_TYPE_INVALID,
1429	EFX_LIGHTSOUT_OFFLOAD_TYPE_ARP,
1430	EFX_LIGHTSOUT_OFFLOAD_TYPE_NS,
1431} efx_lightsout_offload_type_t;
1432
1433#define	EFX_WOL_BITMAP_MASK_SIZE    (48)
1434#define	EFX_WOL_BITMAP_VALUE_SIZE   (128)
1435
1436typedef union efx_wol_param_u {
1437	struct {
1438		uint8_t mac_addr[6];
1439	} ewp_magic;
1440	struct {
1441		uint8_t mask[EFX_WOL_BITMAP_MASK_SIZE];   /* 1 bit per byte */
1442		uint8_t value[EFX_WOL_BITMAP_VALUE_SIZE]; /* value to match */
1443		uint8_t value_len;
1444	} ewp_bitmap;
1445} efx_wol_param_t;
1446
1447typedef union efx_lightsout_offload_param_u {
1448	struct {
1449		uint8_t mac_addr[6];
1450		uint32_t ip;
1451	} elop_arp;
1452	struct {
1453		uint8_t mac_addr[6];
1454		uint32_t solicited_node[4];
1455		uint32_t ip[4];
1456	} elop_ns;
1457} efx_lightsout_offload_param_t;
1458
1459extern	__checkReturn	efx_rc_t
1460efx_wol_init(
1461	__in		efx_nic_t *enp);
1462
1463extern	__checkReturn	efx_rc_t
1464efx_wol_filter_clear(
1465	__in		efx_nic_t *enp);
1466
1467extern	__checkReturn	efx_rc_t
1468efx_wol_filter_add(
1469	__in		efx_nic_t *enp,
1470	__in		efx_wol_type_t type,
1471	__in		efx_wol_param_t *paramp,
1472	__out		uint32_t *filter_idp);
1473
1474extern	__checkReturn	efx_rc_t
1475efx_wol_filter_remove(
1476	__in		efx_nic_t *enp,
1477	__in		uint32_t filter_id);
1478
1479extern	__checkReturn	efx_rc_t
1480efx_lightsout_offload_add(
1481	__in		efx_nic_t *enp,
1482	__in		efx_lightsout_offload_type_t type,
1483	__in		efx_lightsout_offload_param_t *paramp,
1484	__out		uint32_t *filter_idp);
1485
1486extern	__checkReturn	efx_rc_t
1487efx_lightsout_offload_remove(
1488	__in		efx_nic_t *enp,
1489	__in		efx_lightsout_offload_type_t type,
1490	__in		uint32_t filter_id);
1491
1492extern			void
1493efx_wol_fini(
1494	__in		efx_nic_t *enp);
1495
1496#endif	/* EFSYS_OPT_WOL */
1497
1498#if EFSYS_OPT_DIAG
1499
1500typedef enum efx_pattern_type_t {
1501	EFX_PATTERN_BYTE_INCREMENT = 0,
1502	EFX_PATTERN_ALL_THE_SAME,
1503	EFX_PATTERN_BIT_ALTERNATE,
1504	EFX_PATTERN_BYTE_ALTERNATE,
1505	EFX_PATTERN_BYTE_CHANGING,
1506	EFX_PATTERN_BIT_SWEEP,
1507	EFX_PATTERN_NTYPES
1508} efx_pattern_type_t;
1509
1510typedef 		void
1511(*efx_sram_pattern_fn_t)(
1512	__in		size_t row,
1513	__in		boolean_t negate,
1514	__out		efx_qword_t *eqp);
1515
1516extern	__checkReturn	efx_rc_t
1517efx_sram_test(
1518	__in		efx_nic_t *enp,
1519	__in		efx_pattern_type_t type);
1520
1521#endif	/* EFSYS_OPT_DIAG */
1522
1523extern	__checkReturn	efx_rc_t
1524efx_sram_buf_tbl_set(
1525	__in		efx_nic_t *enp,
1526	__in		uint32_t id,
1527	__in		efsys_mem_t *esmp,
1528	__in		size_t n);
1529
1530extern		void
1531efx_sram_buf_tbl_clear(
1532	__in	efx_nic_t *enp,
1533	__in	uint32_t id,
1534	__in	size_t n);
1535
1536#define	EFX_BUF_TBL_SIZE	0x20000
1537
1538#define	EFX_BUF_SIZE		4096
1539
1540/* EV */
1541
1542typedef struct efx_evq_s	efx_evq_t;
1543
1544#if EFSYS_OPT_QSTATS
1545
1546/* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1547typedef enum efx_ev_qstat_e {
1548	EV_ALL,
1549	EV_RX,
1550	EV_RX_OK,
1551	EV_RX_FRM_TRUNC,
1552	EV_RX_TOBE_DISC,
1553	EV_RX_PAUSE_FRM_ERR,
1554	EV_RX_BUF_OWNER_ID_ERR,
1555	EV_RX_IPV4_HDR_CHKSUM_ERR,
1556	EV_RX_TCP_UDP_CHKSUM_ERR,
1557	EV_RX_ETH_CRC_ERR,
1558	EV_RX_IP_FRAG_ERR,
1559	EV_RX_MCAST_PKT,
1560	EV_RX_MCAST_HASH_MATCH,
1561	EV_RX_TCP_IPV4,
1562	EV_RX_TCP_IPV6,
1563	EV_RX_UDP_IPV4,
1564	EV_RX_UDP_IPV6,
1565	EV_RX_OTHER_IPV4,
1566	EV_RX_OTHER_IPV6,
1567	EV_RX_NON_IP,
1568	EV_RX_BATCH,
1569	EV_TX,
1570	EV_TX_WQ_FF_FULL,
1571	EV_TX_PKT_ERR,
1572	EV_TX_PKT_TOO_BIG,
1573	EV_TX_UNEXPECTED,
1574	EV_GLOBAL,
1575	EV_GLOBAL_MNT,
1576	EV_DRIVER,
1577	EV_DRIVER_SRM_UPD_DONE,
1578	EV_DRIVER_TX_DESCQ_FLS_DONE,
1579	EV_DRIVER_RX_DESCQ_FLS_DONE,
1580	EV_DRIVER_RX_DESCQ_FLS_FAILED,
1581	EV_DRIVER_RX_DSC_ERROR,
1582	EV_DRIVER_TX_DSC_ERROR,
1583	EV_DRV_GEN,
1584	EV_MCDI_RESPONSE,
1585	EV_NQSTATS
1586} efx_ev_qstat_t;
1587
1588/* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1589
1590#endif	/* EFSYS_OPT_QSTATS */
1591
1592extern	__checkReturn	efx_rc_t
1593efx_ev_init(
1594	__in		efx_nic_t *enp);
1595
1596extern		void
1597efx_ev_fini(
1598	__in		efx_nic_t *enp);
1599
1600#define	EFX_EVQ_MAXNEVS		32768
1601#define	EFX_EVQ_MINNEVS		512
1602
1603#define	EFX_EVQ_SIZE(_nevs)	((_nevs) * sizeof (efx_qword_t))
1604#define	EFX_EVQ_NBUFS(_nevs)	(EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1605
1606extern	__checkReturn	efx_rc_t
1607efx_ev_qcreate(
1608	__in		efx_nic_t *enp,
1609	__in		unsigned int index,
1610	__in		efsys_mem_t *esmp,
1611	__in		size_t n,
1612	__in		uint32_t id,
1613	__deref_out	efx_evq_t **eepp);
1614
1615extern		void
1616efx_ev_qpost(
1617	__in		efx_evq_t *eep,
1618	__in		uint16_t data);
1619
1620typedef __checkReturn	boolean_t
1621(*efx_initialized_ev_t)(
1622	__in_opt	void *arg);
1623
1624#define	EFX_PKT_UNICAST		0x0004
1625#define	EFX_PKT_START		0x0008
1626
1627#define	EFX_PKT_VLAN_TAGGED	0x0010
1628#define	EFX_CKSUM_TCPUDP	0x0020
1629#define	EFX_CKSUM_IPV4		0x0040
1630#define	EFX_PKT_CONT		0x0080
1631
1632#define	EFX_CHECK_VLAN		0x0100
1633#define	EFX_PKT_TCP		0x0200
1634#define	EFX_PKT_UDP		0x0400
1635#define	EFX_PKT_IPV4		0x0800
1636
1637#define	EFX_PKT_IPV6		0x1000
1638#define	EFX_PKT_PREFIX_LEN	0x2000
1639#define	EFX_ADDR_MISMATCH	0x4000
1640#define	EFX_DISCARD		0x8000
1641
1642#define	EFX_EV_RX_NLABELS	32
1643#define	EFX_EV_TX_NLABELS	32
1644
1645typedef	__checkReturn	boolean_t
1646(*efx_rx_ev_t)(
1647	__in_opt	void *arg,
1648	__in		uint32_t label,
1649	__in		uint32_t id,
1650	__in		uint32_t size,
1651	__in		uint16_t flags);
1652
1653typedef	__checkReturn	boolean_t
1654(*efx_tx_ev_t)(
1655	__in_opt	void *arg,
1656	__in		uint32_t label,
1657	__in		uint32_t id);
1658
1659#define	EFX_EXCEPTION_RX_RECOVERY	0x00000001
1660#define	EFX_EXCEPTION_RX_DSC_ERROR	0x00000002
1661#define	EFX_EXCEPTION_TX_DSC_ERROR	0x00000003
1662#define	EFX_EXCEPTION_UNKNOWN_SENSOREVT	0x00000004
1663#define	EFX_EXCEPTION_FWALERT_SRAM	0x00000005
1664#define	EFX_EXCEPTION_UNKNOWN_FWALERT	0x00000006
1665#define	EFX_EXCEPTION_RX_ERROR		0x00000007
1666#define	EFX_EXCEPTION_TX_ERROR		0x00000008
1667#define	EFX_EXCEPTION_EV_ERROR		0x00000009
1668
1669typedef	__checkReturn	boolean_t
1670(*efx_exception_ev_t)(
1671	__in_opt	void *arg,
1672	__in		uint32_t label,
1673	__in		uint32_t data);
1674
1675typedef	__checkReturn	boolean_t
1676(*efx_rxq_flush_done_ev_t)(
1677	__in_opt	void *arg,
1678	__in		uint32_t rxq_index);
1679
1680typedef	__checkReturn	boolean_t
1681(*efx_rxq_flush_failed_ev_t)(
1682	__in_opt	void *arg,
1683	__in		uint32_t rxq_index);
1684
1685typedef	__checkReturn	boolean_t
1686(*efx_txq_flush_done_ev_t)(
1687	__in_opt	void *arg,
1688	__in		uint32_t txq_index);
1689
1690typedef	__checkReturn	boolean_t
1691(*efx_software_ev_t)(
1692	__in_opt	void *arg,
1693	__in		uint16_t magic);
1694
1695typedef	__checkReturn	boolean_t
1696(*efx_sram_ev_t)(
1697	__in_opt	void *arg,
1698	__in		uint32_t code);
1699
1700#define	EFX_SRAM_CLEAR		0
1701#define	EFX_SRAM_UPDATE		1
1702#define	EFX_SRAM_ILLEGAL_CLEAR	2
1703
1704typedef	__checkReturn	boolean_t
1705(*efx_wake_up_ev_t)(
1706	__in_opt	void *arg,
1707	__in		uint32_t label);
1708
1709typedef	__checkReturn	boolean_t
1710(*efx_timer_ev_t)(
1711	__in_opt	void *arg,
1712	__in		uint32_t label);
1713
1714typedef __checkReturn	boolean_t
1715(*efx_link_change_ev_t)(
1716	__in_opt	void *arg,
1717	__in		efx_link_mode_t	link_mode);
1718
1719#if EFSYS_OPT_MON_STATS
1720
1721typedef __checkReturn	boolean_t
1722(*efx_monitor_ev_t)(
1723	__in_opt	void *arg,
1724	__in		efx_mon_stat_t id,
1725	__in		efx_mon_stat_value_t value);
1726
1727#endif	/* EFSYS_OPT_MON_STATS */
1728
1729#if EFSYS_OPT_MAC_STATS
1730
1731typedef __checkReturn	boolean_t
1732(*efx_mac_stats_ev_t)(
1733	__in_opt	void *arg,
1734	__in		uint32_t generation
1735	);
1736
1737#endif	/* EFSYS_OPT_MAC_STATS */
1738
1739typedef struct efx_ev_callbacks_s {
1740	efx_initialized_ev_t		eec_initialized;
1741	efx_rx_ev_t			eec_rx;
1742	efx_tx_ev_t			eec_tx;
1743	efx_exception_ev_t		eec_exception;
1744	efx_rxq_flush_done_ev_t		eec_rxq_flush_done;
1745	efx_rxq_flush_failed_ev_t	eec_rxq_flush_failed;
1746	efx_txq_flush_done_ev_t		eec_txq_flush_done;
1747	efx_software_ev_t		eec_software;
1748	efx_sram_ev_t			eec_sram;
1749	efx_wake_up_ev_t		eec_wake_up;
1750	efx_timer_ev_t			eec_timer;
1751	efx_link_change_ev_t		eec_link_change;
1752#if EFSYS_OPT_MON_STATS
1753	efx_monitor_ev_t		eec_monitor;
1754#endif	/* EFSYS_OPT_MON_STATS */
1755#if EFSYS_OPT_MAC_STATS
1756	efx_mac_stats_ev_t		eec_mac_stats;
1757#endif	/* EFSYS_OPT_MAC_STATS */
1758} efx_ev_callbacks_t;
1759
1760extern	__checkReturn	boolean_t
1761efx_ev_qpending(
1762	__in		efx_evq_t *eep,
1763	__in		unsigned int count);
1764
1765#if EFSYS_OPT_EV_PREFETCH
1766
1767extern			void
1768efx_ev_qprefetch(
1769	__in		efx_evq_t *eep,
1770	__in		unsigned int count);
1771
1772#endif	/* EFSYS_OPT_EV_PREFETCH */
1773
1774extern			void
1775efx_ev_qpoll(
1776	__in		efx_evq_t *eep,
1777	__inout		unsigned int *countp,
1778	__in		const efx_ev_callbacks_t *eecp,
1779	__in_opt	void *arg);
1780
1781extern	__checkReturn	efx_rc_t
1782efx_ev_qmoderate(
1783	__in		efx_evq_t *eep,
1784	__in		unsigned int us);
1785
1786extern	__checkReturn	efx_rc_t
1787efx_ev_qprime(
1788	__in		efx_evq_t *eep,
1789	__in		unsigned int count);
1790
1791#if EFSYS_OPT_QSTATS
1792
1793#if EFSYS_OPT_NAMES
1794
1795extern		const char *
1796efx_ev_qstat_name(
1797	__in	efx_nic_t *enp,
1798	__in	unsigned int id);
1799
1800#endif	/* EFSYS_OPT_NAMES */
1801
1802extern					void
1803efx_ev_qstats_update(
1804	__in				efx_evq_t *eep,
1805	__inout_ecount(EV_NQSTATS)	efsys_stat_t *stat);
1806
1807#endif	/* EFSYS_OPT_QSTATS */
1808
1809extern		void
1810efx_ev_qdestroy(
1811	__in	efx_evq_t *eep);
1812
1813/* RX */
1814
1815extern	__checkReturn	efx_rc_t
1816efx_rx_init(
1817	__inout		efx_nic_t *enp);
1818
1819extern		void
1820efx_rx_fini(
1821	__in		efx_nic_t *enp);
1822
1823#if EFSYS_OPT_RX_SCATTER
1824	__checkReturn	efx_rc_t
1825efx_rx_scatter_enable(
1826	__in		efx_nic_t *enp,
1827	__in		unsigned int buf_size);
1828#endif	/* EFSYS_OPT_RX_SCATTER */
1829
1830#if EFSYS_OPT_RX_SCALE
1831
1832typedef enum efx_rx_hash_alg_e {
1833	EFX_RX_HASHALG_LFSR = 0,
1834	EFX_RX_HASHALG_TOEPLITZ
1835} efx_rx_hash_alg_t;
1836
1837typedef enum efx_rx_hash_type_e {
1838	EFX_RX_HASH_IPV4 = 0,
1839	EFX_RX_HASH_TCPIPV4,
1840	EFX_RX_HASH_IPV6,
1841	EFX_RX_HASH_TCPIPV6,
1842} efx_rx_hash_type_t;
1843
1844typedef enum efx_rx_hash_support_e {
1845	EFX_RX_HASH_UNAVAILABLE = 0,	/* Hardware hash not inserted */
1846	EFX_RX_HASH_AVAILABLE		/* Insert hash with/without RSS */
1847} efx_rx_hash_support_t;
1848
1849#define	EFX_RSS_TBL_SIZE	128	/* Rows in RX indirection table */
1850#define	EFX_MAXRSS	    	64	/* RX indirection entry range */
1851#define	EFX_MAXRSS_LEGACY   	16 	/* See bug16611 and bug17213 */
1852
1853typedef enum efx_rx_scale_support_e {
1854	EFX_RX_SCALE_UNAVAILABLE = 0,	/* Not supported */
1855	EFX_RX_SCALE_EXCLUSIVE,		/* Writable key/indirection table */
1856	EFX_RX_SCALE_SHARED		/* Read-only key/indirection table */
1857} efx_rx_scale_support_t;
1858
1859extern	__checkReturn	efx_rc_t
1860efx_rx_hash_support_get(
1861	__in		efx_nic_t *enp,
1862	__out		efx_rx_hash_support_t *supportp);
1863
1864
1865extern	__checkReturn	efx_rc_t
1866efx_rx_scale_support_get(
1867	__in		efx_nic_t *enp,
1868	__out		efx_rx_scale_support_t *supportp);
1869
1870extern	__checkReturn	efx_rc_t
1871efx_rx_scale_mode_set(
1872	__in	efx_nic_t *enp,
1873	__in	efx_rx_hash_alg_t alg,
1874	__in	efx_rx_hash_type_t type,
1875	__in	boolean_t insert);
1876
1877extern	__checkReturn	efx_rc_t
1878efx_rx_scale_tbl_set(
1879	__in		efx_nic_t *enp,
1880	__in_ecount(n)	unsigned int *table,
1881	__in		size_t n);
1882
1883extern	__checkReturn	efx_rc_t
1884efx_rx_scale_key_set(
1885	__in		efx_nic_t *enp,
1886	__in_ecount(n)	uint8_t *key,
1887	__in		size_t n);
1888
1889extern	__checkReturn	uint32_t
1890efx_psuedo_hdr_hash_get(
1891	__in		efx_nic_t *enp,
1892	__in		efx_rx_hash_alg_t func,
1893	__in		uint8_t *buffer);
1894
1895#endif	/* EFSYS_OPT_RX_SCALE */
1896
1897extern	__checkReturn	efx_rc_t
1898efx_psuedo_hdr_pkt_length_get(
1899	__in		efx_nic_t *enp,
1900	__in		uint8_t *buffer,
1901	__out		uint16_t *pkt_lengthp);
1902
1903#define	EFX_RXQ_MAXNDESCS		4096
1904#define	EFX_RXQ_MINNDESCS		512
1905
1906#define	EFX_RXQ_SIZE(_ndescs)		((_ndescs) * sizeof (efx_qword_t))
1907#define	EFX_RXQ_NBUFS(_ndescs)		(EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1908#define	EFX_RXQ_LIMIT(_ndescs)		((_ndescs) - 16)
1909#define	EFX_RXQ_DC_NDESCS(_dcsize)	(8 << _dcsize)
1910
1911typedef enum efx_rxq_type_e {
1912	EFX_RXQ_TYPE_DEFAULT,
1913	EFX_RXQ_TYPE_SCATTER,
1914	EFX_RXQ_NTYPES
1915} efx_rxq_type_t;
1916
1917extern	__checkReturn	efx_rc_t
1918efx_rx_qcreate(
1919	__in		efx_nic_t *enp,
1920	__in		unsigned int index,
1921	__in		unsigned int label,
1922	__in		efx_rxq_type_t type,
1923	__in		efsys_mem_t *esmp,
1924	__in		size_t n,
1925	__in		uint32_t id,
1926	__in		efx_evq_t *eep,
1927	__deref_out	efx_rxq_t **erpp);
1928
1929typedef struct efx_buffer_s {
1930	efsys_dma_addr_t	eb_addr;
1931	size_t			eb_size;
1932	boolean_t		eb_eop;
1933} efx_buffer_t;
1934
1935typedef struct efx_desc_s {
1936	efx_qword_t ed_eq;
1937} efx_desc_t;
1938
1939extern			void
1940efx_rx_qpost(
1941	__in		efx_rxq_t *erp,
1942	__in_ecount(n)	efsys_dma_addr_t *addrp,
1943	__in		size_t size,
1944	__in		unsigned int n,
1945	__in		unsigned int completed,
1946	__in		unsigned int added);
1947
1948extern		void
1949efx_rx_qpush(
1950	__in	efx_rxq_t *erp,
1951	__in	unsigned int added,
1952	__inout	unsigned int *pushedp);
1953
1954extern	__checkReturn	efx_rc_t
1955efx_rx_qflush(
1956	__in	efx_rxq_t *erp);
1957
1958extern		void
1959efx_rx_qenable(
1960	__in	efx_rxq_t *erp);
1961
1962extern		void
1963efx_rx_qdestroy(
1964	__in	efx_rxq_t *erp);
1965
1966/* TX */
1967
1968typedef struct efx_txq_s	efx_txq_t;
1969
1970#if EFSYS_OPT_QSTATS
1971
1972/* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
1973typedef enum efx_tx_qstat_e {
1974	TX_POST,
1975	TX_POST_PIO,
1976	TX_NQSTATS
1977} efx_tx_qstat_t;
1978
1979/* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
1980
1981#endif	/* EFSYS_OPT_QSTATS */
1982
1983extern	__checkReturn	efx_rc_t
1984efx_tx_init(
1985	__in		efx_nic_t *enp);
1986
1987extern		void
1988efx_tx_fini(
1989	__in	efx_nic_t *enp);
1990
1991#define	EFX_BUG35388_WORKAROUND(_encp)					\
1992	(((_encp) == NULL) ? 1 : ((_encp)->enc_bug35388_workaround != 0))
1993
1994#define	EFX_TXQ_MAXNDESCS(_encp)					\
1995	((EFX_BUG35388_WORKAROUND(_encp)) ? 2048 : 4096)
1996
1997#define	EFX_TXQ_MINNDESCS		512
1998
1999#define	EFX_TXQ_SIZE(_ndescs)		((_ndescs) * sizeof (efx_qword_t))
2000#define	EFX_TXQ_NBUFS(_ndescs)		(EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2001#define	EFX_TXQ_LIMIT(_ndescs)		((_ndescs) - 16)
2002#define	EFX_TXQ_DC_NDESCS(_dcsize)	(8 << _dcsize)
2003
2004#define	EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2005
2006#define	EFX_TXQ_CKSUM_IPV4	0x0001
2007#define	EFX_TXQ_CKSUM_TCPUDP	0x0002
2008#define	EFX_TXQ_FATSOV2		0x0004
2009
2010extern	__checkReturn	efx_rc_t
2011efx_tx_qcreate(
2012	__in		efx_nic_t *enp,
2013	__in		unsigned int index,
2014	__in		unsigned int label,
2015	__in		efsys_mem_t *esmp,
2016	__in		size_t n,
2017	__in		uint32_t id,
2018	__in		uint16_t flags,
2019	__in		efx_evq_t *eep,
2020	__deref_out	efx_txq_t **etpp,
2021	__out		unsigned int *addedp);
2022
2023extern	__checkReturn	efx_rc_t
2024efx_tx_qpost(
2025	__in		efx_txq_t *etp,
2026	__in_ecount(n)	efx_buffer_t *eb,
2027	__in		unsigned int n,
2028	__in		unsigned int completed,
2029	__inout		unsigned int *addedp);
2030
2031extern	__checkReturn	efx_rc_t
2032efx_tx_qpace(
2033	__in		efx_txq_t *etp,
2034	__in		unsigned int ns);
2035
2036extern			void
2037efx_tx_qpush(
2038	__in		efx_txq_t *etp,
2039	__in		unsigned int added,
2040	__in		unsigned int pushed);
2041
2042extern	__checkReturn	efx_rc_t
2043efx_tx_qflush(
2044	__in		efx_txq_t *etp);
2045
2046extern			void
2047efx_tx_qenable(
2048	__in		efx_txq_t *etp);
2049
2050extern	__checkReturn	efx_rc_t
2051efx_tx_qpio_enable(
2052	__in		efx_txq_t *etp);
2053
2054extern			void
2055efx_tx_qpio_disable(
2056	__in		efx_txq_t *etp);
2057
2058extern	__checkReturn	efx_rc_t
2059efx_tx_qpio_write(
2060	__in			efx_txq_t *etp,
2061	__in_ecount(buf_length)	uint8_t *buffer,
2062	__in			size_t buf_length,
2063	__in                    size_t pio_buf_offset);
2064
2065extern	__checkReturn	efx_rc_t
2066efx_tx_qpio_post(
2067	__in			efx_txq_t *etp,
2068	__in			size_t pkt_length,
2069	__in			unsigned int completed,
2070	__inout			unsigned int *addedp);
2071
2072extern	__checkReturn	efx_rc_t
2073efx_tx_qdesc_post(
2074	__in		efx_txq_t *etp,
2075	__in_ecount(n)	efx_desc_t *ed,
2076	__in		unsigned int n,
2077	__in		unsigned int completed,
2078	__inout		unsigned int *addedp);
2079
2080extern	void
2081efx_tx_qdesc_dma_create(
2082	__in	efx_txq_t *etp,
2083	__in	efsys_dma_addr_t addr,
2084	__in	size_t size,
2085	__in	boolean_t eop,
2086	__out	efx_desc_t *edp);
2087
2088extern	void
2089efx_tx_qdesc_tso_create(
2090	__in	efx_txq_t *etp,
2091	__in	uint16_t ipv4_id,
2092	__in	uint32_t tcp_seq,
2093	__in	uint8_t  tcp_flags,
2094	__out	efx_desc_t *edp);
2095
2096/* Number of FATSOv2 option descriptors */
2097#define	EFX_TX_FATSOV2_OPT_NDESCS		2
2098
2099/* Maximum number of DMA segments per TSO packet (not superframe) */
2100#define	EFX_TX_FATSOV2_DMA_SEGS_PER_PKT_MAX	24
2101
2102extern	void
2103efx_tx_qdesc_tso2_create(
2104	__in			efx_txq_t *etp,
2105	__in			uint16_t ipv4_id,
2106	__in			uint32_t tcp_seq,
2107	__in			uint16_t tcp_mss,
2108	__out_ecount(count)	efx_desc_t *edp,
2109	__in			int count);
2110
2111extern	void
2112efx_tx_qdesc_vlantci_create(
2113	__in	efx_txq_t *etp,
2114	__in	uint16_t tci,
2115	__out	efx_desc_t *edp);
2116
2117#if EFSYS_OPT_QSTATS
2118
2119#if EFSYS_OPT_NAMES
2120
2121extern		const char *
2122efx_tx_qstat_name(
2123	__in	efx_nic_t *etp,
2124	__in	unsigned int id);
2125
2126#endif	/* EFSYS_OPT_NAMES */
2127
2128extern					void
2129efx_tx_qstats_update(
2130	__in				efx_txq_t *etp,
2131	__inout_ecount(TX_NQSTATS)	efsys_stat_t *stat);
2132
2133#endif	/* EFSYS_OPT_QSTATS */
2134
2135extern		void
2136efx_tx_qdestroy(
2137	__in	efx_txq_t *etp);
2138
2139
2140/* FILTER */
2141
2142#if EFSYS_OPT_FILTER
2143
2144#define	EFX_ETHER_TYPE_IPV4 0x0800
2145#define	EFX_ETHER_TYPE_IPV6 0x86DD
2146
2147#define	EFX_IPPROTO_TCP 6
2148#define	EFX_IPPROTO_UDP 17
2149
2150typedef enum efx_filter_flag_e {
2151	EFX_FILTER_FLAG_RX_RSS = 0x01,		/* use RSS to spread across
2152						 * multiple queues */
2153	EFX_FILTER_FLAG_RX_SCATTER = 0x02,	/* enable RX scatter */
2154	EFX_FILTER_FLAG_RX_OVER_AUTO = 0x04,	/* Override an automatic filter
2155						 * (priority EFX_FILTER_PRI_AUTO).
2156						 * May only be set by the filter
2157						 * implementation for each type.
2158						 * A removal request will
2159						 * restore the automatic filter
2160						 * in its place. */
2161	EFX_FILTER_FLAG_RX = 0x08,		/* Filter is for RX */
2162	EFX_FILTER_FLAG_TX = 0x10,		/* Filter is for TX */
2163} efx_filter_flag_t;
2164
2165typedef enum efx_filter_match_flags_e {
2166	EFX_FILTER_MATCH_REM_HOST = 0x0001,	/* Match by remote IP host
2167						 * address */
2168	EFX_FILTER_MATCH_LOC_HOST = 0x0002,	/* Match by local IP host
2169						 * address */
2170	EFX_FILTER_MATCH_REM_MAC = 0x0004,	/* Match by remote MAC address */
2171	EFX_FILTER_MATCH_REM_PORT = 0x0008,	/* Match by remote TCP/UDP port */
2172	EFX_FILTER_MATCH_LOC_MAC = 0x0010,	/* Match by remote TCP/UDP port */
2173	EFX_FILTER_MATCH_LOC_PORT = 0x0020,	/* Match by local TCP/UDP port */
2174	EFX_FILTER_MATCH_ETHER_TYPE = 0x0040,	/* Match by Ether-type */
2175	EFX_FILTER_MATCH_INNER_VID = 0x0080,	/* Match by inner VLAN ID */
2176	EFX_FILTER_MATCH_OUTER_VID = 0x0100,	/* Match by outer VLAN ID */
2177	EFX_FILTER_MATCH_IP_PROTO = 0x0200,	/* Match by IP transport
2178						 * protocol */
2179	EFX_FILTER_MATCH_LOC_MAC_IG = 0x0400,	/* Match by local MAC address
2180						 * I/G bit. Used for RX default
2181						 * unicast and multicast/
2182						 * broadcast filters. */
2183} efx_filter_match_flags_t;
2184
2185typedef enum efx_filter_priority_s {
2186	EFX_FILTER_PRI_HINT = 0,	/* Performance hint */
2187	EFX_FILTER_PRI_AUTO,		/* Automatic filter based on device
2188					 * address list or hardware
2189					 * requirements. This may only be used
2190					 * by the filter implementation for
2191					 * each NIC type. */
2192	EFX_FILTER_PRI_MANUAL,		/* Manually configured filter */
2193	EFX_FILTER_PRI_REQUIRED,	/* Required for correct behaviour of the
2194					 * client (e.g. SR-IOV, HyperV VMQ etc.)
2195					 */
2196} efx_filter_priority_t;
2197
2198/*
2199 * FIXME: All these fields are assumed to be in little-endian byte order.
2200 * It may be better for some to be big-endian. See bug42804.
2201 */
2202
2203typedef struct efx_filter_spec_s {
2204	uint32_t	efs_match_flags:12;
2205	uint32_t	efs_priority:2;
2206	uint32_t	efs_flags:6;
2207	uint32_t	efs_dmaq_id:12;
2208	uint32_t	efs_rss_context;
2209	uint16_t	efs_outer_vid;
2210	uint16_t	efs_inner_vid;
2211	uint8_t		efs_loc_mac[EFX_MAC_ADDR_LEN];
2212	uint8_t		efs_rem_mac[EFX_MAC_ADDR_LEN];
2213	uint16_t	efs_ether_type;
2214	uint8_t		efs_ip_proto;
2215	uint16_t	efs_loc_port;
2216	uint16_t	efs_rem_port;
2217	efx_oword_t	efs_rem_host;
2218	efx_oword_t	efs_loc_host;
2219} efx_filter_spec_t;
2220
2221
2222/* Default values for use in filter specifications */
2223#define	EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT	0xffffffff
2224#define	EFX_FILTER_SPEC_RX_DMAQ_ID_DROP		0xfff
2225#define	EFX_FILTER_SPEC_VID_UNSPEC		0xffff
2226
2227extern	__checkReturn	efx_rc_t
2228efx_filter_init(
2229	__in		efx_nic_t *enp);
2230
2231extern			void
2232efx_filter_fini(
2233	__in		efx_nic_t *enp);
2234
2235extern	__checkReturn	efx_rc_t
2236efx_filter_insert(
2237	__in		efx_nic_t *enp,
2238	__inout		efx_filter_spec_t *spec);
2239
2240extern	__checkReturn	efx_rc_t
2241efx_filter_remove(
2242	__in		efx_nic_t *enp,
2243	__inout		efx_filter_spec_t *spec);
2244
2245extern	__checkReturn	efx_rc_t
2246efx_filter_restore(
2247	__in		efx_nic_t *enp);
2248
2249extern	__checkReturn	efx_rc_t
2250efx_filter_supported_filters(
2251	__in		efx_nic_t *enp,
2252	__out		uint32_t *list,
2253	__out		size_t *length);
2254
2255extern			void
2256efx_filter_spec_init_rx(
2257	__out		efx_filter_spec_t *spec,
2258	__in		efx_filter_priority_t priority,
2259	__in		efx_filter_flag_t flags,
2260	__in		efx_rxq_t *erp);
2261
2262extern			void
2263efx_filter_spec_init_tx(
2264	__out		efx_filter_spec_t *spec,
2265	__in		efx_txq_t *etp);
2266
2267extern	__checkReturn	efx_rc_t
2268efx_filter_spec_set_ipv4_local(
2269	__inout		efx_filter_spec_t *spec,
2270	__in		uint8_t proto,
2271	__in		uint32_t host,
2272	__in		uint16_t port);
2273
2274extern	__checkReturn	efx_rc_t
2275efx_filter_spec_set_ipv4_full(
2276	__inout		efx_filter_spec_t *spec,
2277	__in		uint8_t proto,
2278	__in		uint32_t lhost,
2279	__in		uint16_t lport,
2280	__in		uint32_t rhost,
2281	__in		uint16_t rport);
2282
2283extern	__checkReturn	efx_rc_t
2284efx_filter_spec_set_eth_local(
2285	__inout		efx_filter_spec_t *spec,
2286	__in		uint16_t vid,
2287	__in		const uint8_t *addr);
2288
2289extern	__checkReturn	efx_rc_t
2290efx_filter_spec_set_uc_def(
2291	__inout		efx_filter_spec_t *spec);
2292
2293extern	__checkReturn	efx_rc_t
2294efx_filter_spec_set_mc_def(
2295	__inout		efx_filter_spec_t *spec);
2296
2297#endif	/* EFSYS_OPT_FILTER */
2298
2299/* HASH */
2300
2301extern	__checkReturn		uint32_t
2302efx_hash_dwords(
2303	__in_ecount(count)	uint32_t const *input,
2304	__in			size_t count,
2305	__in			uint32_t init);
2306
2307extern	__checkReturn		uint32_t
2308efx_hash_bytes(
2309	__in_ecount(length)	uint8_t const *input,
2310	__in			size_t length,
2311	__in			uint32_t init);
2312
2313#if EFSYS_OPT_LICENSING
2314
2315/* LICENSING */
2316
2317typedef struct efx_key_stats_s {
2318	uint32_t	eks_valid;
2319	uint32_t	eks_invalid;
2320	uint32_t	eks_blacklisted;
2321	uint32_t	eks_unverifiable;
2322	uint32_t	eks_wrong_node;
2323	uint32_t	eks_licensed_apps_lo;
2324	uint32_t	eks_licensed_apps_hi;
2325	uint32_t	eks_licensed_features_lo;
2326	uint32_t	eks_licensed_features_hi;
2327} efx_key_stats_t;
2328
2329extern	__checkReturn		efx_rc_t
2330efx_lic_init(
2331	__in			efx_nic_t *enp);
2332
2333extern				void
2334efx_lic_fini(
2335	__in			efx_nic_t *enp);
2336
2337extern	__checkReturn	efx_rc_t
2338efx_lic_update_licenses(
2339	__in		efx_nic_t *enp);
2340
2341extern	__checkReturn	efx_rc_t
2342efx_lic_get_key_stats(
2343	__in		efx_nic_t *enp,
2344	__out		efx_key_stats_t *ksp);
2345
2346extern	__checkReturn	efx_rc_t
2347efx_lic_app_state(
2348	__in		efx_nic_t *enp,
2349	__in		uint64_t app_id,
2350	__out		boolean_t *licensedp);
2351
2352extern	__checkReturn	efx_rc_t
2353efx_lic_get_id(
2354	__in		efx_nic_t *enp,
2355	__in		size_t buffer_size,
2356	__out		uint32_t *typep,
2357	__out		size_t *lengthp,
2358	__out_opt	uint8_t *bufferp);
2359
2360
2361#endif	/* EFSYS_OPT_LICENSING */
2362
2363
2364
2365#ifdef	__cplusplus
2366}
2367#endif
2368
2369#endif	/* _SYS_EFX_H */
2370