efx.h revision 284555 
1/*-
2 * Copyright (c) 2006-2015 Solarflare Communications Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
7 *
8 * 1. Redistributions of source code must retain the above copyright notice,
9 *    this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 *    this list of conditions and the following disclaimer in the documentation
12 *    and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
25 *
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
29 *
30 * $FreeBSD: stable/10/sys/dev/sfxge/common/efx.h 284555 2015-06-18 15:46:39Z arybchik $
31 */
32
33#ifndef	_SYS_EFX_H
34#define	_SYS_EFX_H
35
36#include "efsys.h"
37#include "efx_phy_ids.h"
38
39#ifdef	__cplusplus
40extern "C" {
41#endif
42
43#define	EFX_STATIC_ASSERT(_cond) ((void)sizeof(char[(_cond) ? 1 : -1]))
44
45#define	EFX_ARRAY_SIZE(_array) (sizeof(_array) / sizeof((_array)[0]))
46
47#define	EFX_FIELD_OFFSET(_type, _field) ((size_t) &(((_type *)0)->_field))
48
49typedef enum efx_family_e {
50	EFX_FAMILY_INVALID,
51	EFX_FAMILY_FALCON,
52	EFX_FAMILY_SIENA,
53	EFX_FAMILY_HUNTINGTON,
54	EFX_FAMILY_NTYPES
55} efx_family_t;
56
57extern	__checkReturn	int
58efx_family(
59	__in		uint16_t venid,
60	__in		uint16_t devid,
61	__out		efx_family_t *efp);
62
63extern	__checkReturn	int
64efx_infer_family(
65	__in		efsys_bar_t *esbp,
66	__out		efx_family_t *efp);
67
68#define	EFX_PCI_VENID_SFC			0x1924
69
70#define	EFX_PCI_DEVID_FALCON			0x0710	/* SFC4000 */
71
72#define	EFX_PCI_DEVID_BETHPAGE			0x0803	/* SFC9020 */
73#define	EFX_PCI_DEVID_SIENA			0x0813	/* SFL9021 */
74#define	EFX_PCI_DEVID_SIENA_F1_UNINIT		0x0810
75
76#define	EFX_PCI_DEVID_HUNTINGTON_PF_UNINIT	0x0901
77#define	EFX_PCI_DEVID_FARMINGDALE		0x0903	/* SFC9120 PF */
78#define	EFX_PCI_DEVID_HUNTINGTON		0x0913	/* SFL9122 PF */
79#define	EFX_PCI_DEVID_GREENPORT			0x0923	/* SFC9140 PF */
80
81#define	EFX_PCI_DEVID_FARMINGDALE_VF		0x1903	/* SFC9120 VF */
82#define	EFX_PCI_DEVID_HUNTINGTON_VF		0x1913	/* SFL9122 VF */
83#define	EFX_PCI_DEVID_GREENPORT_VF		0x1923	/* SFC9140 VF */
84
85
86#define	EFX_MEM_BAR	2
87
88/* Error codes */
89
90enum {
91	EFX_ERR_INVALID,
92	EFX_ERR_SRAM_OOB,
93	EFX_ERR_BUFID_DC_OOB,
94	EFX_ERR_MEM_PERR,
95	EFX_ERR_RBUF_OWN,
96	EFX_ERR_TBUF_OWN,
97	EFX_ERR_RDESQ_OWN,
98	EFX_ERR_TDESQ_OWN,
99	EFX_ERR_EVQ_OWN,
100	EFX_ERR_EVFF_OFLO,
101	EFX_ERR_ILL_ADDR,
102	EFX_ERR_SRAM_PERR,
103	EFX_ERR_NCODES
104};
105
106/* Calculate the IEEE 802.3 CRC32 of a MAC addr */
107extern	__checkReturn		uint32_t
108efx_crc32_calculate(
109	__in			uint32_t crc_init,
110	__in_ecount(length)	uint8_t const *input,
111	__in			int length);
112
113
114/* Type prototypes */
115
116typedef struct efx_rxq_s	efx_rxq_t;
117
118/* NIC */
119
120typedef struct efx_nic_s	efx_nic_t;
121
122#define	EFX_NIC_FUNC_PRIMARY	0x00000001
123#define	EFX_NIC_FUNC_LINKCTRL	0x00000002
124#define	EFX_NIC_FUNC_TRUSTED	0x00000004
125
126
127extern	__checkReturn	int
128efx_nic_create(
129	__in		efx_family_t family,
130	__in		efsys_identifier_t *esip,
131	__in		efsys_bar_t *esbp,
132	__in		efsys_lock_t *eslp,
133	__deref_out	efx_nic_t **enpp);
134
135extern	__checkReturn	int
136efx_nic_probe(
137	__in		efx_nic_t *enp);
138
139#if EFSYS_OPT_PCIE_TUNE
140
141extern	__checkReturn	int
142efx_nic_pcie_tune(
143	__in		efx_nic_t *enp,
144	unsigned int	nlanes);
145
146extern	__checkReturn	int
147efx_nic_pcie_extended_sync(
148	__in		efx_nic_t *enp);
149
150#endif	/* EFSYS_OPT_PCIE_TUNE */
151
152extern 	__checkReturn	int
153efx_nic_init(
154	__in		efx_nic_t *enp);
155
156extern	__checkReturn	int
157efx_nic_reset(
158	__in		efx_nic_t *enp);
159
160#if EFSYS_OPT_DIAG
161
162extern	__checkReturn	int
163efx_nic_register_test(
164	__in		efx_nic_t *enp);
165
166#endif	/* EFSYS_OPT_DIAG */
167
168extern		void
169efx_nic_fini(
170	__in		efx_nic_t *enp);
171
172extern		void
173efx_nic_unprobe(
174	__in		efx_nic_t *enp);
175
176extern 		void
177efx_nic_destroy(
178	__in	efx_nic_t *enp);
179
180#if EFSYS_OPT_MCDI
181
182#if EFSYS_OPT_HUNTINGTON
183/* Huntington requires MCDIv2 commands */
184#define	WITH_MCDI_V2 1
185#endif
186
187typedef struct efx_mcdi_req_s efx_mcdi_req_t;
188
189typedef enum efx_mcdi_exception_e {
190	EFX_MCDI_EXCEPTION_MC_REBOOT,
191	EFX_MCDI_EXCEPTION_MC_BADASSERT,
192} efx_mcdi_exception_t;
193
194typedef struct efx_mcdi_transport_s {
195	void		*emt_context;
196	efsys_mem_t	*emt_dma_mem;
197	void		(*emt_execute)(void *, efx_mcdi_req_t *);
198	void		(*emt_ev_cpl)(void *);
199	void		(*emt_exception)(void *, efx_mcdi_exception_t);
200} efx_mcdi_transport_t;
201
202extern	__checkReturn	int
203efx_mcdi_init(
204	__in		efx_nic_t *enp,
205	__in		const efx_mcdi_transport_t *mtp);
206
207extern	__checkReturn	int
208efx_mcdi_reboot(
209	__in		efx_nic_t *enp);
210
211			void
212efx_mcdi_new_epoch(
213	__in		efx_nic_t *enp);
214
215extern			void
216efx_mcdi_request_start(
217	__in		efx_nic_t *enp,
218	__in		efx_mcdi_req_t *emrp,
219	__in		boolean_t ev_cpl);
220
221extern	__checkReturn	boolean_t
222efx_mcdi_request_poll(
223	__in		efx_nic_t *enp);
224
225extern	__checkReturn	boolean_t
226efx_mcdi_request_abort(
227	__in		efx_nic_t *enp);
228
229extern			void
230efx_mcdi_fini(
231	__in		efx_nic_t *enp);
232
233#endif	/* EFSYS_OPT_MCDI */
234
235/* INTR */
236
237#define	EFX_NINTR_FALCON 64
238#define	EFX_NINTR_SIENA 1024
239
240typedef enum efx_intr_type_e {
241	EFX_INTR_INVALID = 0,
242	EFX_INTR_LINE,
243	EFX_INTR_MESSAGE,
244	EFX_INTR_NTYPES
245} efx_intr_type_t;
246
247#define	EFX_INTR_SIZE	(sizeof (efx_oword_t))
248
249extern	__checkReturn	int
250efx_intr_init(
251	__in		efx_nic_t *enp,
252	__in		efx_intr_type_t type,
253	__in		efsys_mem_t *esmp);
254
255extern 			void
256efx_intr_enable(
257	__in		efx_nic_t *enp);
258
259extern 			void
260efx_intr_disable(
261	__in		efx_nic_t *enp);
262
263extern 			void
264efx_intr_disable_unlocked(
265	__in		efx_nic_t *enp);
266
267#define	EFX_INTR_NEVQS	32
268
269extern __checkReturn	int
270efx_intr_trigger(
271	__in		efx_nic_t *enp,
272	__in		unsigned int level);
273
274extern			void
275efx_intr_status_line(
276	__in		efx_nic_t *enp,
277	__out		boolean_t *fatalp,
278	__out		uint32_t *maskp);
279
280extern			void
281efx_intr_status_message(
282	__in		efx_nic_t *enp,
283	__in		unsigned int message,
284	__out		boolean_t *fatalp);
285
286extern			void
287efx_intr_fatal(
288	__in		efx_nic_t *enp);
289
290extern			void
291efx_intr_fini(
292	__in		efx_nic_t *enp);
293
294/* MAC */
295
296#if EFSYS_OPT_MAC_STATS
297
298/* START MKCONFIG GENERATED EfxHeaderMacBlock e323546097fd7c65 */
299typedef enum efx_mac_stat_e {
300	EFX_MAC_RX_OCTETS,
301	EFX_MAC_RX_PKTS,
302	EFX_MAC_RX_UNICST_PKTS,
303	EFX_MAC_RX_MULTICST_PKTS,
304	EFX_MAC_RX_BRDCST_PKTS,
305	EFX_MAC_RX_PAUSE_PKTS,
306	EFX_MAC_RX_LE_64_PKTS,
307	EFX_MAC_RX_65_TO_127_PKTS,
308	EFX_MAC_RX_128_TO_255_PKTS,
309	EFX_MAC_RX_256_TO_511_PKTS,
310	EFX_MAC_RX_512_TO_1023_PKTS,
311	EFX_MAC_RX_1024_TO_15XX_PKTS,
312	EFX_MAC_RX_GE_15XX_PKTS,
313	EFX_MAC_RX_ERRORS,
314	EFX_MAC_RX_FCS_ERRORS,
315	EFX_MAC_RX_DROP_EVENTS,
316	EFX_MAC_RX_FALSE_CARRIER_ERRORS,
317	EFX_MAC_RX_SYMBOL_ERRORS,
318	EFX_MAC_RX_ALIGN_ERRORS,
319	EFX_MAC_RX_INTERNAL_ERRORS,
320	EFX_MAC_RX_JABBER_PKTS,
321	EFX_MAC_RX_LANE0_CHAR_ERR,
322	EFX_MAC_RX_LANE1_CHAR_ERR,
323	EFX_MAC_RX_LANE2_CHAR_ERR,
324	EFX_MAC_RX_LANE3_CHAR_ERR,
325	EFX_MAC_RX_LANE0_DISP_ERR,
326	EFX_MAC_RX_LANE1_DISP_ERR,
327	EFX_MAC_RX_LANE2_DISP_ERR,
328	EFX_MAC_RX_LANE3_DISP_ERR,
329	EFX_MAC_RX_MATCH_FAULT,
330	EFX_MAC_RX_NODESC_DROP_CNT,
331	EFX_MAC_TX_OCTETS,
332	EFX_MAC_TX_PKTS,
333	EFX_MAC_TX_UNICST_PKTS,
334	EFX_MAC_TX_MULTICST_PKTS,
335	EFX_MAC_TX_BRDCST_PKTS,
336	EFX_MAC_TX_PAUSE_PKTS,
337	EFX_MAC_TX_LE_64_PKTS,
338	EFX_MAC_TX_65_TO_127_PKTS,
339	EFX_MAC_TX_128_TO_255_PKTS,
340	EFX_MAC_TX_256_TO_511_PKTS,
341	EFX_MAC_TX_512_TO_1023_PKTS,
342	EFX_MAC_TX_1024_TO_15XX_PKTS,
343	EFX_MAC_TX_GE_15XX_PKTS,
344	EFX_MAC_TX_ERRORS,
345	EFX_MAC_TX_SGL_COL_PKTS,
346	EFX_MAC_TX_MULT_COL_PKTS,
347	EFX_MAC_TX_EX_COL_PKTS,
348	EFX_MAC_TX_LATE_COL_PKTS,
349	EFX_MAC_TX_DEF_PKTS,
350	EFX_MAC_TX_EX_DEF_PKTS,
351	EFX_MAC_PM_TRUNC_BB_OVERFLOW,
352	EFX_MAC_PM_DISCARD_BB_OVERFLOW,
353	EFX_MAC_PM_TRUNC_VFIFO_FULL,
354	EFX_MAC_PM_DISCARD_VFIFO_FULL,
355	EFX_MAC_PM_TRUNC_QBB,
356	EFX_MAC_PM_DISCARD_QBB,
357	EFX_MAC_PM_DISCARD_MAPPING,
358	EFX_MAC_RXDP_Q_DISABLED_PKTS,
359	EFX_MAC_RXDP_DI_DROPPED_PKTS,
360	EFX_MAC_RXDP_STREAMING_PKTS,
361	EFX_MAC_RXDP_HLB_FETCH,
362	EFX_MAC_RXDP_HLB_WAIT,
363	EFX_MAC_VADAPTER_RX_UNICAST_PACKETS,
364	EFX_MAC_VADAPTER_RX_UNICAST_BYTES,
365	EFX_MAC_VADAPTER_RX_MULTICAST_PACKETS,
366	EFX_MAC_VADAPTER_RX_MULTICAST_BYTES,
367	EFX_MAC_VADAPTER_RX_BROADCAST_PACKETS,
368	EFX_MAC_VADAPTER_RX_BROADCAST_BYTES,
369	EFX_MAC_VADAPTER_RX_BAD_PACKETS,
370	EFX_MAC_VADAPTER_RX_BAD_BYTES,
371	EFX_MAC_VADAPTER_RX_OVERFLOW,
372	EFX_MAC_VADAPTER_TX_UNICAST_PACKETS,
373	EFX_MAC_VADAPTER_TX_UNICAST_BYTES,
374	EFX_MAC_VADAPTER_TX_MULTICAST_PACKETS,
375	EFX_MAC_VADAPTER_TX_MULTICAST_BYTES,
376	EFX_MAC_VADAPTER_TX_BROADCAST_PACKETS,
377	EFX_MAC_VADAPTER_TX_BROADCAST_BYTES,
378	EFX_MAC_VADAPTER_TX_BAD_PACKETS,
379	EFX_MAC_VADAPTER_TX_BAD_BYTES,
380	EFX_MAC_VADAPTER_TX_OVERFLOW,
381	EFX_MAC_NSTATS
382} efx_mac_stat_t;
383
384/* END MKCONFIG GENERATED EfxHeaderMacBlock */
385
386#endif	/* EFSYS_OPT_MAC_STATS */
387
388typedef enum efx_link_mode_e {
389	EFX_LINK_UNKNOWN = 0,
390	EFX_LINK_DOWN,
391	EFX_LINK_10HDX,
392	EFX_LINK_10FDX,
393	EFX_LINK_100HDX,
394	EFX_LINK_100FDX,
395	EFX_LINK_1000HDX,
396	EFX_LINK_1000FDX,
397	EFX_LINK_10000FDX,
398	EFX_LINK_40000FDX,
399	EFX_LINK_NMODES
400} efx_link_mode_t;
401
402#define	EFX_MAC_ADDR_LEN 6
403
404#define	EFX_MAC_ADDR_IS_MULTICAST(_address) (((uint8_t*)_address)[0] & 0x01)
405
406#define	EFX_MAC_MULTICAST_LIST_MAX	256
407
408#define	EFX_MAC_SDU_MAX	9202
409
410#define	EFX_MAC_PDU(_sdu) 				\
411	P2ROUNDUP(((_sdu)				\
412		    + /* EtherII */ 14			\
413		    + /* VLAN */ 4			\
414		    + /* CRC */ 4			\
415		    + /* bug16011 */ 16),		\
416		    (1 << 3))
417
418#define	EFX_MAC_PDU_MIN	60
419#define	EFX_MAC_PDU_MAX	EFX_MAC_PDU(EFX_MAC_SDU_MAX)
420
421extern	__checkReturn	int
422efx_mac_pdu_set(
423	__in		efx_nic_t *enp,
424	__in		size_t pdu);
425
426extern	__checkReturn	int
427efx_mac_addr_set(
428	__in		efx_nic_t *enp,
429	__in		uint8_t *addr);
430
431extern	__checkReturn			int
432efx_mac_filter_set(
433	__in				efx_nic_t *enp,
434	__in				boolean_t all_unicst,
435	__in				boolean_t mulcst,
436	__in				boolean_t all_mulcst,
437	__in				boolean_t brdcst);
438
439extern	__checkReturn	int
440efx_mac_multicast_list_set(
441	__in				efx_nic_t *enp,
442	__in_ecount(6*count)		uint8_t const *addrs,
443	__in				int count);
444
445extern	__checkReturn	int
446efx_mac_filter_default_rxq_set(
447	__in		efx_nic_t *enp,
448	__in		efx_rxq_t *erp,
449	__in		boolean_t using_rss);
450
451extern			void
452efx_mac_filter_default_rxq_clear(
453	__in		efx_nic_t *enp);
454
455extern	__checkReturn	int
456efx_mac_drain(
457	__in		efx_nic_t *enp,
458	__in		boolean_t enabled);
459
460extern	__checkReturn	int
461efx_mac_up(
462	__in		efx_nic_t *enp,
463	__out		boolean_t *mac_upp);
464
465#define	EFX_FCNTL_RESPOND	0x00000001
466#define	EFX_FCNTL_GENERATE	0x00000002
467
468extern	__checkReturn	int
469efx_mac_fcntl_set(
470	__in		efx_nic_t *enp,
471	__in		unsigned int fcntl,
472	__in		boolean_t autoneg);
473
474extern			void
475efx_mac_fcntl_get(
476	__in		efx_nic_t *enp,
477	__out		unsigned int *fcntl_wantedp,
478	__out		unsigned int *fcntl_linkp);
479
480#define	EFX_MAC_HASH_BITS	(1 << 8)
481
482extern	__checkReturn			int
483efx_pktfilter_init(
484	__in				efx_nic_t *enp);
485
486extern					void
487efx_pktfilter_fini(
488	__in				efx_nic_t *enp);
489
490extern	__checkReturn			int
491efx_pktfilter_set(
492	__in		efx_nic_t *enp,
493	__in		boolean_t unicst,
494	__in		boolean_t brdcst);
495
496extern	__checkReturn			int
497efx_mac_hash_set(
498	__in				efx_nic_t *enp,
499	__in_ecount(EFX_MAC_HASH_BITS)	unsigned int const *bucket);
500
501#if EFSYS_OPT_MCAST_FILTER_LIST
502extern	__checkReturn			int
503efx_pktfilter_mcast_list_set(
504	__in				efx_nic_t *enp,
505	__in				uint8_t const *addrs,
506	__in				int count);
507#endif /* EFSYS_OPT_MCAST_FILTER_LIST */
508
509extern	__checkReturn			int
510efx_pktfilter_mcast_all(
511	__in				efx_nic_t *enp);
512
513#if EFSYS_OPT_MAC_STATS
514
515#if EFSYS_OPT_NAMES
516
517extern	__checkReturn			const char *
518efx_mac_stat_name(
519	__in				efx_nic_t *enp,
520	__in				unsigned int id);
521
522#endif	/* EFSYS_OPT_NAMES */
523
524#define	EFX_MAC_STATS_SIZE 0x400
525
526/*
527 * Upload mac statistics supported by the hardware into the given buffer.
528 *
529 * The reference buffer must be at least %EFX_MAC_STATS_SIZE bytes,
530 * and page aligned.
531 *
532 * The hardware will only DMA statistics that it understands (of course).
533 * Drivers should not make any assumptions about which statistics are
534 * supported, especially when the statistics are generated by firmware.
535 *
536 * Thus, drivers should zero this buffer before use, so that not-understood
537 * statistics read back as zero.
538 */
539extern	__checkReturn			int
540efx_mac_stats_upload(
541	__in				efx_nic_t *enp,
542	__in				efsys_mem_t *esmp);
543
544extern	__checkReturn			int
545efx_mac_stats_periodic(
546	__in				efx_nic_t *enp,
547	__in				efsys_mem_t *esmp,
548	__in				uint16_t period_ms,
549	__in				boolean_t events);
550
551extern	__checkReturn			int
552efx_mac_stats_update(
553	__in				efx_nic_t *enp,
554	__in				efsys_mem_t *esmp,
555	__inout_ecount(EFX_MAC_NSTATS)	efsys_stat_t *stat,
556	__out_opt			uint32_t *generationp);
557
558#endif	/* EFSYS_OPT_MAC_STATS */
559
560/* MON */
561
562typedef enum efx_mon_type_e {
563	EFX_MON_INVALID = 0,
564	EFX_MON_NULL,
565	EFX_MON_LM87,
566	EFX_MON_MAX6647,
567	EFX_MON_SFC90X0,
568	EFX_MON_SFC91X0,
569	EFX_MON_NTYPES
570} efx_mon_type_t;
571
572#if EFSYS_OPT_NAMES
573
574extern		const char *
575efx_mon_name(
576	__in	efx_nic_t *enp);
577
578#endif	/* EFSYS_OPT_NAMES */
579
580extern	__checkReturn	int
581efx_mon_init(
582	__in		efx_nic_t *enp);
583
584#if EFSYS_OPT_MON_STATS
585
586#define	EFX_MON_STATS_PAGE_SIZE 0x100
587#define	EFX_MON_MASK_ELEMENT_SIZE 32
588
589/* START MKCONFIG GENERATED MonitorHeaderStatsBlock c79c86b62a144846 */
590typedef enum efx_mon_stat_e {
591	EFX_MON_STAT_2_5V,
592	EFX_MON_STAT_VCCP1,
593	EFX_MON_STAT_VCC,
594	EFX_MON_STAT_5V,
595	EFX_MON_STAT_12V,
596	EFX_MON_STAT_VCCP2,
597	EFX_MON_STAT_EXT_TEMP,
598	EFX_MON_STAT_INT_TEMP,
599	EFX_MON_STAT_AIN1,
600	EFX_MON_STAT_AIN2,
601	EFX_MON_STAT_INT_COOLING,
602	EFX_MON_STAT_EXT_COOLING,
603	EFX_MON_STAT_1V,
604	EFX_MON_STAT_1_2V,
605	EFX_MON_STAT_1_8V,
606	EFX_MON_STAT_3_3V,
607	EFX_MON_STAT_1_2VA,
608	EFX_MON_STAT_VREF,
609	EFX_MON_STAT_VAOE,
610	EFX_MON_STAT_AOE_TEMP,
611	EFX_MON_STAT_PSU_AOE_TEMP,
612	EFX_MON_STAT_PSU_TEMP,
613	EFX_MON_STAT_FAN0,
614	EFX_MON_STAT_FAN1,
615	EFX_MON_STAT_FAN2,
616	EFX_MON_STAT_FAN3,
617	EFX_MON_STAT_FAN4,
618	EFX_MON_STAT_VAOE_IN,
619	EFX_MON_STAT_IAOE,
620	EFX_MON_STAT_IAOE_IN,
621	EFX_MON_STAT_NIC_POWER,
622	EFX_MON_STAT_0_9V,
623	EFX_MON_STAT_I0_9V,
624	EFX_MON_STAT_I1_2V,
625	EFX_MON_STAT_0_9V_ADC,
626	EFX_MON_STAT_INT_TEMP2,
627	EFX_MON_STAT_VREG_TEMP,
628	EFX_MON_STAT_VREG_0_9V_TEMP,
629	EFX_MON_STAT_VREG_1_2V_TEMP,
630	EFX_MON_STAT_INT_VPTAT,
631	EFX_MON_STAT_INT_ADC_TEMP,
632	EFX_MON_STAT_EXT_VPTAT,
633	EFX_MON_STAT_EXT_ADC_TEMP,
634	EFX_MON_STAT_AMBIENT_TEMP,
635	EFX_MON_STAT_AIRFLOW,
636	EFX_MON_STAT_VDD08D_VSS08D_CSR,
637	EFX_MON_STAT_VDD08D_VSS08D_CSR_EXTADC,
638	EFX_MON_STAT_HOTPOINT_TEMP,
639	EFX_MON_STAT_PHY_POWER_SWITCH_PORT0,
640	EFX_MON_STAT_PHY_POWER_SWITCH_PORT1,
641	EFX_MON_STAT_MUM_VCC,
642	EFX_MON_STAT_0V9_A,
643	EFX_MON_STAT_I0V9_A,
644	EFX_MON_STAT_0V9_A_TEMP,
645	EFX_MON_STAT_0V9_B,
646	EFX_MON_STAT_I0V9_B,
647	EFX_MON_STAT_0V9_B_TEMP,
648	EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY,
649	EFX_MON_STAT_CCOM_AVREG_1V2_SUPPLY_EXT_ADC,
650	EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY,
651	EFX_MON_STAT_CCOM_AVREG_1V8_SUPPLY_EXT_ADC,
652	EFX_MON_STAT_CONTROLLER_MASTER_VPTAT,
653	EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP,
654	EFX_MON_STAT_CONTROLLER_MASTER_VPTAT_EXT_ADC,
655	EFX_MON_STAT_CONTROLLER_MASTER_INTERNAL_TEMP_EXT_ADC,
656	EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT,
657	EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP,
658	EFX_MON_STAT_CONTROLLER_SLAVE_VPTAT_EXT_ADC,
659	EFX_MON_STAT_CONTROLLER_SLAVE_INTERNAL_TEMP_EXT_ADC,
660	EFX_MON_NSTATS
661} efx_mon_stat_t;
662
663/* END MKCONFIG GENERATED MonitorHeaderStatsBlock */
664
665typedef enum efx_mon_stat_state_e {
666	EFX_MON_STAT_STATE_OK = 0,
667	EFX_MON_STAT_STATE_WARNING = 1,
668	EFX_MON_STAT_STATE_FATAL = 2,
669	EFX_MON_STAT_STATE_BROKEN = 3,
670	EFX_MON_STAT_STATE_NO_READING = 4,
671} efx_mon_stat_state_t;
672
673typedef struct efx_mon_stat_value_s {
674	uint16_t	emsv_value;
675	uint16_t	emsv_state;
676} efx_mon_stat_value_t;
677
678#if EFSYS_OPT_NAMES
679
680extern					const char *
681efx_mon_stat_name(
682	__in				efx_nic_t *enp,
683	__in				efx_mon_stat_t id);
684
685#endif	/* EFSYS_OPT_NAMES */
686
687extern	__checkReturn			int
688efx_mon_stats_update(
689	__in				efx_nic_t *enp,
690	__in				efsys_mem_t *esmp,
691	__out_ecount(EFX_MON_NSTATS)	efx_mon_stat_value_t *values);
692
693#endif	/* EFSYS_OPT_MON_STATS */
694
695extern		void
696efx_mon_fini(
697	__in	efx_nic_t *enp);
698
699/* PHY */
700
701#define	PMA_PMD_MMD	1
702#define	PCS_MMD		3
703#define	PHY_XS_MMD	4
704#define	DTE_XS_MMD	5
705#define	AN_MMD		7
706#define	CL22EXT_MMD	29
707
708#define	MAXMMD		((1 << 5) - 1)
709
710extern	__checkReturn	int
711efx_phy_verify(
712	__in		efx_nic_t *enp);
713
714#if EFSYS_OPT_PHY_LED_CONTROL
715
716typedef enum efx_phy_led_mode_e {
717	EFX_PHY_LED_DEFAULT = 0,
718	EFX_PHY_LED_OFF,
719	EFX_PHY_LED_ON,
720	EFX_PHY_LED_FLASH,
721	EFX_PHY_LED_NMODES
722} efx_phy_led_mode_t;
723
724extern	__checkReturn	int
725efx_phy_led_set(
726	__in	efx_nic_t *enp,
727	__in	efx_phy_led_mode_t mode);
728
729#endif	/* EFSYS_OPT_PHY_LED_CONTROL */
730
731extern	__checkReturn	int
732efx_port_init(
733	__in		efx_nic_t *enp);
734
735#if EFSYS_OPT_LOOPBACK
736
737typedef enum efx_loopback_type_e {
738	EFX_LOOPBACK_OFF = 0,
739	EFX_LOOPBACK_DATA = 1,
740	EFX_LOOPBACK_GMAC = 2,
741	EFX_LOOPBACK_XGMII = 3,
742	EFX_LOOPBACK_XGXS = 4,
743	EFX_LOOPBACK_XAUI = 5,
744	EFX_LOOPBACK_GMII = 6,
745	EFX_LOOPBACK_SGMII = 7,
746	EFX_LOOPBACK_XGBR = 8,
747	EFX_LOOPBACK_XFI = 9,
748	EFX_LOOPBACK_XAUI_FAR = 10,
749	EFX_LOOPBACK_GMII_FAR = 11,
750	EFX_LOOPBACK_SGMII_FAR = 12,
751	EFX_LOOPBACK_XFI_FAR = 13,
752	EFX_LOOPBACK_GPHY = 14,
753	EFX_LOOPBACK_PHY_XS = 15,
754	EFX_LOOPBACK_PCS = 16,
755	EFX_LOOPBACK_PMA_PMD = 17,
756	EFX_LOOPBACK_XPORT = 18,
757	EFX_LOOPBACK_XGMII_WS = 19,
758	EFX_LOOPBACK_XAUI_WS = 20,
759	EFX_LOOPBACK_XAUI_WS_FAR = 21,
760	EFX_LOOPBACK_XAUI_WS_NEAR = 22,
761	EFX_LOOPBACK_GMII_WS = 23,
762	EFX_LOOPBACK_XFI_WS = 24,
763	EFX_LOOPBACK_XFI_WS_FAR = 25,
764	EFX_LOOPBACK_PHYXS_WS = 26,
765	EFX_LOOPBACK_PMA_INT = 27,
766	EFX_LOOPBACK_SD_NEAR = 28,
767	EFX_LOOPBACK_SD_FAR = 29,
768	EFX_LOOPBACK_PMA_INT_WS = 30,
769	EFX_LOOPBACK_SD_FEP2_WS = 31,
770	EFX_LOOPBACK_SD_FEP1_5_WS = 32,
771	EFX_LOOPBACK_SD_FEP_WS = 33,
772	EFX_LOOPBACK_SD_FES_WS = 34,
773	EFX_LOOPBACK_NTYPES
774} efx_loopback_type_t;
775
776typedef enum efx_loopback_kind_e {
777	EFX_LOOPBACK_KIND_OFF = 0,
778	EFX_LOOPBACK_KIND_ALL,
779	EFX_LOOPBACK_KIND_MAC,
780	EFX_LOOPBACK_KIND_PHY,
781	EFX_LOOPBACK_NKINDS
782} efx_loopback_kind_t;
783
784extern			void
785efx_loopback_mask(
786	__in	efx_loopback_kind_t loopback_kind,
787	__out	efx_qword_t *maskp);
788
789extern	__checkReturn	int
790efx_port_loopback_set(
791	__in	efx_nic_t *enp,
792	__in	efx_link_mode_t link_mode,
793	__in	efx_loopback_type_t type);
794
795#if EFSYS_OPT_NAMES
796
797extern	__checkReturn	const char *
798efx_loopback_type_name(
799	__in		efx_nic_t *enp,
800	__in		efx_loopback_type_t type);
801
802#endif	/* EFSYS_OPT_NAMES */
803
804#endif	/* EFSYS_OPT_LOOPBACK */
805
806extern	__checkReturn	int
807efx_port_poll(
808	__in		efx_nic_t *enp,
809	__out_opt	efx_link_mode_t	*link_modep);
810
811extern 		void
812efx_port_fini(
813	__in	efx_nic_t *enp);
814
815typedef enum efx_phy_cap_type_e {
816	EFX_PHY_CAP_INVALID = 0,
817	EFX_PHY_CAP_10HDX,
818	EFX_PHY_CAP_10FDX,
819	EFX_PHY_CAP_100HDX,
820	EFX_PHY_CAP_100FDX,
821	EFX_PHY_CAP_1000HDX,
822	EFX_PHY_CAP_1000FDX,
823	EFX_PHY_CAP_10000FDX,
824	EFX_PHY_CAP_PAUSE,
825	EFX_PHY_CAP_ASYM,
826	EFX_PHY_CAP_AN,
827	EFX_PHY_CAP_40000FDX,
828	EFX_PHY_CAP_NTYPES
829} efx_phy_cap_type_t;
830
831
832#define	EFX_PHY_CAP_CURRENT	0x00000000
833#define	EFX_PHY_CAP_DEFAULT	0x00000001
834#define	EFX_PHY_CAP_PERM	0x00000002
835
836extern		void
837efx_phy_adv_cap_get(
838	__in		efx_nic_t *enp,
839	__in            uint32_t flag,
840	__out		uint32_t *maskp);
841
842extern	__checkReturn	int
843efx_phy_adv_cap_set(
844	__in		efx_nic_t *enp,
845	__in		uint32_t mask);
846
847extern			void
848efx_phy_lp_cap_get(
849	__in		efx_nic_t *enp,
850	__out		uint32_t *maskp);
851
852extern	__checkReturn	int
853efx_phy_oui_get(
854	__in		efx_nic_t *enp,
855	__out		uint32_t *ouip);
856
857typedef enum efx_phy_media_type_e {
858	EFX_PHY_MEDIA_INVALID = 0,
859	EFX_PHY_MEDIA_XAUI,
860	EFX_PHY_MEDIA_CX4,
861	EFX_PHY_MEDIA_KX4,
862	EFX_PHY_MEDIA_XFP,
863	EFX_PHY_MEDIA_SFP_PLUS,
864	EFX_PHY_MEDIA_BASE_T,
865	EFX_PHY_MEDIA_QSFP_PLUS,
866	EFX_PHY_MEDIA_NTYPES
867} efx_phy_media_type_t;
868
869/* Get the type of medium currently used.  If the board has ports for
870 * modules, a module is present, and we recognise the media type of
871 * the module, then this will be the media type of the module.
872 * Otherwise it will be the media type of the port.
873 */
874extern			void
875efx_phy_media_type_get(
876	__in		efx_nic_t *enp,
877	__out		efx_phy_media_type_t *typep);
878
879#if EFSYS_OPT_PHY_STATS
880
881/* START MKCONFIG GENERATED PhyHeaderStatsBlock 30ed56ad501f8e36 */
882typedef enum efx_phy_stat_e {
883	EFX_PHY_STAT_OUI,
884	EFX_PHY_STAT_PMA_PMD_LINK_UP,
885	EFX_PHY_STAT_PMA_PMD_RX_FAULT,
886	EFX_PHY_STAT_PMA_PMD_TX_FAULT,
887	EFX_PHY_STAT_PMA_PMD_REV_A,
888	EFX_PHY_STAT_PMA_PMD_REV_B,
889	EFX_PHY_STAT_PMA_PMD_REV_C,
890	EFX_PHY_STAT_PMA_PMD_REV_D,
891	EFX_PHY_STAT_PCS_LINK_UP,
892	EFX_PHY_STAT_PCS_RX_FAULT,
893	EFX_PHY_STAT_PCS_TX_FAULT,
894	EFX_PHY_STAT_PCS_BER,
895	EFX_PHY_STAT_PCS_BLOCK_ERRORS,
896	EFX_PHY_STAT_PHY_XS_LINK_UP,
897	EFX_PHY_STAT_PHY_XS_RX_FAULT,
898	EFX_PHY_STAT_PHY_XS_TX_FAULT,
899	EFX_PHY_STAT_PHY_XS_ALIGN,
900	EFX_PHY_STAT_PHY_XS_SYNC_A,
901	EFX_PHY_STAT_PHY_XS_SYNC_B,
902	EFX_PHY_STAT_PHY_XS_SYNC_C,
903	EFX_PHY_STAT_PHY_XS_SYNC_D,
904	EFX_PHY_STAT_AN_LINK_UP,
905	EFX_PHY_STAT_AN_MASTER,
906	EFX_PHY_STAT_AN_LOCAL_RX_OK,
907	EFX_PHY_STAT_AN_REMOTE_RX_OK,
908	EFX_PHY_STAT_CL22EXT_LINK_UP,
909	EFX_PHY_STAT_SNR_A,
910	EFX_PHY_STAT_SNR_B,
911	EFX_PHY_STAT_SNR_C,
912	EFX_PHY_STAT_SNR_D,
913	EFX_PHY_STAT_PMA_PMD_SIGNAL_A,
914	EFX_PHY_STAT_PMA_PMD_SIGNAL_B,
915	EFX_PHY_STAT_PMA_PMD_SIGNAL_C,
916	EFX_PHY_STAT_PMA_PMD_SIGNAL_D,
917	EFX_PHY_STAT_AN_COMPLETE,
918	EFX_PHY_STAT_PMA_PMD_REV_MAJOR,
919	EFX_PHY_STAT_PMA_PMD_REV_MINOR,
920	EFX_PHY_STAT_PMA_PMD_REV_MICRO,
921	EFX_PHY_STAT_PCS_FW_VERSION_0,
922	EFX_PHY_STAT_PCS_FW_VERSION_1,
923	EFX_PHY_STAT_PCS_FW_VERSION_2,
924	EFX_PHY_STAT_PCS_FW_VERSION_3,
925	EFX_PHY_STAT_PCS_FW_BUILD_YY,
926	EFX_PHY_STAT_PCS_FW_BUILD_MM,
927	EFX_PHY_STAT_PCS_FW_BUILD_DD,
928	EFX_PHY_STAT_PCS_OP_MODE,
929	EFX_PHY_NSTATS
930} efx_phy_stat_t;
931
932/* END MKCONFIG GENERATED PhyHeaderStatsBlock */
933
934#if EFSYS_OPT_NAMES
935
936extern					const char *
937efx_phy_stat_name(
938	__in				efx_nic_t *enp,
939	__in				efx_phy_stat_t stat);
940
941#endif	/* EFSYS_OPT_NAMES */
942
943#define	EFX_PHY_STATS_SIZE 0x100
944
945extern	__checkReturn			int
946efx_phy_stats_update(
947	__in				efx_nic_t *enp,
948	__in				efsys_mem_t *esmp,
949	__out_ecount(EFX_PHY_NSTATS)	uint32_t *stat);
950
951#endif	/* EFSYS_OPT_PHY_STATS */
952
953#if EFSYS_OPT_PHY_PROPS
954
955#if EFSYS_OPT_NAMES
956
957extern		const char *
958efx_phy_prop_name(
959	__in	efx_nic_t *enp,
960	__in	unsigned int id);
961
962#endif	/* EFSYS_OPT_NAMES */
963
964#define	EFX_PHY_PROP_DEFAULT	0x00000001
965
966extern	__checkReturn	int
967efx_phy_prop_get(
968	__in		efx_nic_t *enp,
969	__in		unsigned int id,
970	__in		uint32_t flags,
971	__out		uint32_t *valp);
972
973extern	__checkReturn	int
974efx_phy_prop_set(
975	__in		efx_nic_t *enp,
976	__in		unsigned int id,
977	__in		uint32_t val);
978
979#endif	/* EFSYS_OPT_PHY_PROPS */
980
981#if EFSYS_OPT_BIST
982
983typedef enum efx_bist_type_e {
984	EFX_BIST_TYPE_UNKNOWN,
985	EFX_BIST_TYPE_PHY_NORMAL,
986	EFX_BIST_TYPE_PHY_CABLE_SHORT,
987	EFX_BIST_TYPE_PHY_CABLE_LONG,
988	EFX_BIST_TYPE_MC_MEM,	/* Test the MC DMEM and IMEM */
989	EFX_BIST_TYPE_SAT_MEM,	/* Test the DMEM and IMEM of satellite cpus*/
990	EFX_BIST_TYPE_REG,	/* Test the register memories */
991	EFX_BIST_TYPE_NTYPES,
992} efx_bist_type_t;
993
994typedef enum efx_bist_result_e {
995	EFX_BIST_RESULT_UNKNOWN,
996	EFX_BIST_RESULT_RUNNING,
997	EFX_BIST_RESULT_PASSED,
998	EFX_BIST_RESULT_FAILED,
999} efx_bist_result_t;
1000
1001typedef enum efx_phy_cable_status_e {
1002	EFX_PHY_CABLE_STATUS_OK,
1003	EFX_PHY_CABLE_STATUS_INVALID,
1004	EFX_PHY_CABLE_STATUS_OPEN,
1005	EFX_PHY_CABLE_STATUS_INTRAPAIRSHORT,
1006	EFX_PHY_CABLE_STATUS_INTERPAIRSHORT,
1007	EFX_PHY_CABLE_STATUS_BUSY,
1008} efx_phy_cable_status_t;
1009
1010typedef enum efx_bist_value_e {
1011	EFX_BIST_PHY_CABLE_LENGTH_A,
1012	EFX_BIST_PHY_CABLE_LENGTH_B,
1013	EFX_BIST_PHY_CABLE_LENGTH_C,
1014	EFX_BIST_PHY_CABLE_LENGTH_D,
1015	EFX_BIST_PHY_CABLE_STATUS_A,
1016	EFX_BIST_PHY_CABLE_STATUS_B,
1017	EFX_BIST_PHY_CABLE_STATUS_C,
1018	EFX_BIST_PHY_CABLE_STATUS_D,
1019	EFX_BIST_FAULT_CODE,
1020	/* Memory BIST specific values. These match to the MC_CMD_BIST_POLL
1021	 * response. */
1022	EFX_BIST_MEM_TEST,
1023	EFX_BIST_MEM_ADDR,
1024	EFX_BIST_MEM_BUS,
1025	EFX_BIST_MEM_EXPECT,
1026	EFX_BIST_MEM_ACTUAL,
1027	EFX_BIST_MEM_ECC,
1028	EFX_BIST_MEM_ECC_PARITY,
1029	EFX_BIST_MEM_ECC_FATAL,
1030	EFX_BIST_NVALUES,
1031} efx_bist_value_t;
1032
1033extern	__checkReturn		int
1034efx_bist_enable_offline(
1035	__in			efx_nic_t *enp);
1036
1037extern	__checkReturn		int
1038efx_bist_start(
1039	__in			efx_nic_t *enp,
1040	__in			efx_bist_type_t type);
1041
1042extern	__checkReturn		int
1043efx_bist_poll(
1044	__in			efx_nic_t *enp,
1045	__in			efx_bist_type_t type,
1046	__out			efx_bist_result_t *resultp,
1047	__out_opt		uint32_t *value_maskp,
1048	__out_ecount_opt(count)	unsigned long *valuesp,
1049	__in			size_t count);
1050
1051extern				void
1052efx_bist_stop(
1053	__in			efx_nic_t *enp,
1054	__in			efx_bist_type_t type);
1055
1056#endif	/* EFSYS_OPT_BIST */
1057
1058#define	EFX_FEATURE_IPV6		0x00000001
1059#define	EFX_FEATURE_LFSR_HASH_INSERT	0x00000002
1060#define	EFX_FEATURE_LINK_EVENTS		0x00000004
1061#define	EFX_FEATURE_PERIODIC_MAC_STATS	0x00000008
1062#define	EFX_FEATURE_WOL			0x00000010
1063#define	EFX_FEATURE_MCDI		0x00000020
1064#define	EFX_FEATURE_LOOKAHEAD_SPLIT	0x00000040
1065#define	EFX_FEATURE_MAC_HEADER_FILTERS	0x00000080
1066#define	EFX_FEATURE_TURBO		0x00000100
1067#define	EFX_FEATURE_MCDI_DMA		0x00000200
1068#define	EFX_FEATURE_TX_SRC_FILTERS	0x00000400
1069#define	EFX_FEATURE_PIO_BUFFERS		0x00000800
1070#define	EFX_FEATURE_FW_ASSISTED_TSO	0x00001000
1071
1072typedef struct efx_nic_cfg_s {
1073	uint32_t		enc_board_type;
1074	uint32_t		enc_phy_type;
1075#if EFSYS_OPT_NAMES
1076	char			enc_phy_name[21];
1077#endif
1078	char			enc_phy_revision[21];
1079	efx_mon_type_t		enc_mon_type;
1080#if EFSYS_OPT_MON_STATS
1081	uint32_t		enc_mon_stat_dma_buf_size;
1082	uint32_t		enc_mon_stat_mask[(EFX_MON_NSTATS + 31) / 32];
1083#endif
1084	unsigned int		enc_features;
1085	uint8_t			enc_mac_addr[6];
1086	uint8_t			enc_port;	/* PHY port number */
1087	uint32_t		enc_func_flags;
1088	uint32_t		enc_intr_vec_base;
1089	uint32_t		enc_intr_limit;
1090	uint32_t		enc_evq_limit;
1091	uint32_t		enc_txq_limit;
1092	uint32_t		enc_rxq_limit;
1093	uint32_t		enc_buftbl_limit;
1094	uint32_t		enc_piobuf_limit;
1095	uint32_t		enc_piobuf_size;
1096	uint32_t		enc_evq_timer_quantum_ns;
1097	uint32_t		enc_evq_timer_max_us;
1098	uint32_t		enc_clk_mult;
1099	uint32_t		enc_rx_prefix_size;
1100	uint32_t		enc_rx_buf_align_start;
1101	uint32_t		enc_rx_buf_align_end;
1102#if EFSYS_OPT_LOOPBACK
1103	efx_qword_t		enc_loopback_types[EFX_LINK_NMODES];
1104#endif	/* EFSYS_OPT_LOOPBACK */
1105#if EFSYS_OPT_PHY_FLAGS
1106	uint32_t		enc_phy_flags_mask;
1107#endif	/* EFSYS_OPT_PHY_FLAGS */
1108#if EFSYS_OPT_PHY_LED_CONTROL
1109	uint32_t		enc_led_mask;
1110#endif	/* EFSYS_OPT_PHY_LED_CONTROL */
1111#if EFSYS_OPT_PHY_STATS
1112	uint64_t		enc_phy_stat_mask;
1113#endif	/* EFSYS_OPT_PHY_STATS */
1114#if EFSYS_OPT_PHY_PROPS
1115	unsigned int		enc_phy_nprops;
1116#endif	/* EFSYS_OPT_PHY_PROPS */
1117#if EFSYS_OPT_SIENA
1118	uint8_t			enc_mcdi_mdio_channel;
1119#if EFSYS_OPT_PHY_STATS
1120	uint32_t		enc_mcdi_phy_stat_mask;
1121#endif	/* EFSYS_OPT_PHY_STATS */
1122#endif /* EFSYS_OPT_SIENA */
1123#if (EFSYS_OPT_SIENA || EFSYS_OPT_HUNTINGTON)
1124#if EFSYS_OPT_MON_STATS
1125	uint32_t		*enc_mcdi_sensor_maskp;
1126	uint32_t		enc_mcdi_sensor_mask_size;
1127#endif	/* EFSYS_OPT_MON_STATS */
1128#endif	/* (EFSYS_OPT_SIENA | EFSYS_OPT_HUNTINGTON) */
1129#if EFSYS_OPT_BIST
1130	uint32_t		enc_bist_mask;
1131#endif	/* EFSYS_OPT_BIST */
1132#if EFSYS_OPT_HUNTINGTON
1133	uint32_t		enc_pf;
1134	uint32_t		enc_vf;
1135	uint32_t		enc_privilege_mask;
1136#endif /* EFSYS_OPT_HUNTINGTON */
1137	boolean_t		enc_bug26807_workaround;
1138	boolean_t		enc_bug35388_workaround;
1139	boolean_t		enc_bug41750_workaround;
1140	boolean_t		enc_rx_batching_enabled;
1141	/* Maximum number of descriptors completed in an rx event. */
1142	uint32_t		enc_rx_batch_max;
1143        /* Number of rx descriptors the hardware requires for a push. */
1144        uint32_t		enc_rx_push_align;
1145	/*
1146	 * Maximum number of bytes into the packet the TCP header can start for
1147	 * the hardware to apply TSO packet edits.
1148	 */
1149	uint32_t                enc_tx_tso_tcp_header_offset_limit;
1150	boolean_t               enc_fw_assisted_tso_enabled;
1151	boolean_t               enc_hw_tx_insert_vlan_enabled;
1152	/* Datapath firmware vadapter/vport/vswitch support */
1153	boolean_t		enc_datapath_cap_evb;
1154	/* External port identifier */
1155	uint8_t			enc_external_port;
1156} efx_nic_cfg_t;
1157
1158#define	EFX_PCI_FUNCTION_IS_PF(_encp)	((_encp)->enc_vf == 0xffff)
1159#define	EFX_PCI_FUNCTION_IS_VF(_encp)	((_encp)->enc_vf != 0xffff)
1160
1161#define	EFX_PCI_FUNCTION(_encp)	\
1162	(EFX_PCI_FUNCTION_IS_PF(_encp) ? (_encp)->enc_pf : (_encp)->enc_vf)
1163
1164#define	EFX_PCI_VF_PARENT(_encp)	((_encp)->enc_pf)
1165
1166extern			const efx_nic_cfg_t *
1167efx_nic_cfg_get(
1168	__in		efx_nic_t *enp);
1169
1170/* Driver resource limits (minimum required/maximum usable). */
1171typedef struct efx_drv_limits_s
1172{
1173	uint32_t	edl_min_evq_count;
1174	uint32_t	edl_max_evq_count;
1175
1176	uint32_t	edl_min_rxq_count;
1177	uint32_t	edl_max_rxq_count;
1178
1179	uint32_t	edl_min_txq_count;
1180	uint32_t	edl_max_txq_count;
1181
1182	/* PIO blocks (sub-allocated from piobuf) */
1183	uint32_t	edl_min_pio_alloc_size;
1184	uint32_t	edl_max_pio_alloc_count;
1185} efx_drv_limits_t;
1186
1187extern	__checkReturn	int
1188efx_nic_set_drv_limits(
1189	__inout		efx_nic_t *enp,
1190	__in		efx_drv_limits_t *edlp);
1191
1192typedef enum efx_nic_region_e {
1193	EFX_REGION_VI,			/* Memory BAR UC mapping */
1194	EFX_REGION_PIO_WRITE_VI,	/* Memory BAR WC mapping */
1195} efx_nic_region_t;
1196
1197extern	__checkReturn	int
1198efx_nic_get_bar_region(
1199	__in		efx_nic_t *enp,
1200	__in		efx_nic_region_t region,
1201	__out		uint32_t *offsetp,
1202	__out		size_t *sizep);
1203
1204extern	__checkReturn	int
1205efx_nic_get_vi_pool(
1206	__in		efx_nic_t *enp,
1207	__out		uint32_t *evq_countp,
1208	__out		uint32_t *rxq_countp,
1209	__out		uint32_t *txq_countp);
1210
1211
1212#if EFSYS_OPT_VPD
1213
1214typedef enum efx_vpd_tag_e {
1215	EFX_VPD_ID = 0x02,
1216	EFX_VPD_END = 0x0f,
1217	EFX_VPD_RO = 0x10,
1218	EFX_VPD_RW = 0x11,
1219} efx_vpd_tag_t;
1220
1221typedef uint16_t efx_vpd_keyword_t;
1222
1223typedef struct efx_vpd_value_s {
1224	efx_vpd_tag_t		evv_tag;
1225	efx_vpd_keyword_t	evv_keyword;
1226	uint8_t			evv_length;
1227	uint8_t			evv_value[0x100];
1228} efx_vpd_value_t;
1229
1230
1231#define	EFX_VPD_KEYWORD(x, y) ((x) | ((y) << 8))
1232
1233extern	__checkReturn		int
1234efx_vpd_init(
1235	__in			efx_nic_t *enp);
1236
1237extern	__checkReturn		int
1238efx_vpd_size(
1239	__in			efx_nic_t *enp,
1240	__out			size_t *sizep);
1241
1242extern	__checkReturn		int
1243efx_vpd_read(
1244	__in			efx_nic_t *enp,
1245	__out_bcount(size)	caddr_t data,
1246	__in			size_t size);
1247
1248extern	__checkReturn		int
1249efx_vpd_verify(
1250	__in			efx_nic_t *enp,
1251	__in_bcount(size)	caddr_t data,
1252	__in			size_t size);
1253
1254extern  __checkReturn		int
1255efx_vpd_reinit(
1256	__in			efx_nic_t *enp,
1257	__in_bcount(size)	caddr_t data,
1258	__in			size_t size);
1259
1260extern	__checkReturn		int
1261efx_vpd_get(
1262	__in			efx_nic_t *enp,
1263	__in_bcount(size)	caddr_t data,
1264	__in			size_t size,
1265	__inout			efx_vpd_value_t *evvp);
1266
1267extern	__checkReturn		int
1268efx_vpd_set(
1269	__in			efx_nic_t *enp,
1270	__inout_bcount(size)	caddr_t data,
1271	__in			size_t size,
1272	__in			efx_vpd_value_t *evvp);
1273
1274extern	__checkReturn		int
1275efx_vpd_next(
1276	__in			efx_nic_t *enp,
1277	__inout_bcount(size)	caddr_t data,
1278	__in			size_t size,
1279	__out			efx_vpd_value_t *evvp,
1280	__inout			unsigned int *contp);
1281
1282extern __checkReturn		int
1283efx_vpd_write(
1284	__in			efx_nic_t *enp,
1285	__in_bcount(size)	caddr_t data,
1286	__in			size_t size);
1287
1288extern				void
1289efx_vpd_fini(
1290	__in			efx_nic_t *enp);
1291
1292#endif	/* EFSYS_OPT_VPD */
1293
1294/* NVRAM */
1295
1296#if EFSYS_OPT_NVRAM
1297
1298typedef enum efx_nvram_type_e {
1299	EFX_NVRAM_INVALID = 0,
1300	EFX_NVRAM_BOOTROM,
1301	EFX_NVRAM_BOOTROM_CFG,
1302	EFX_NVRAM_MC_FIRMWARE,
1303	EFX_NVRAM_MC_GOLDEN,
1304	EFX_NVRAM_PHY,
1305	EFX_NVRAM_NULLPHY,
1306	EFX_NVRAM_FPGA,
1307	EFX_NVRAM_FCFW,
1308	EFX_NVRAM_CPLD,
1309	EFX_NVRAM_FPGA_BACKUP,
1310	EFX_NVRAM_DYNAMIC_CFG,
1311	EFX_NVRAM_NTYPES,
1312} efx_nvram_type_t;
1313
1314extern	__checkReturn		int
1315efx_nvram_init(
1316	__in			efx_nic_t *enp);
1317
1318#if EFSYS_OPT_DIAG
1319
1320extern	__checkReturn		int
1321efx_nvram_test(
1322	__in			efx_nic_t *enp);
1323
1324#endif	/* EFSYS_OPT_DIAG */
1325
1326extern	__checkReturn		int
1327efx_nvram_size(
1328	__in			efx_nic_t *enp,
1329	__in			efx_nvram_type_t type,
1330	__out			size_t *sizep);
1331
1332extern	__checkReturn		int
1333efx_nvram_rw_start(
1334	__in			efx_nic_t *enp,
1335	__in			efx_nvram_type_t type,
1336	__out_opt		size_t *pref_chunkp);
1337
1338extern				void
1339efx_nvram_rw_finish(
1340	__in			efx_nic_t *enp,
1341	__in			efx_nvram_type_t type);
1342
1343extern	__checkReturn		int
1344efx_nvram_get_version(
1345	__in			efx_nic_t *enp,
1346	__in			efx_nvram_type_t type,
1347	__out			uint32_t *subtypep,
1348	__out_ecount(4)		uint16_t version[4]);
1349
1350extern	__checkReturn		int
1351efx_nvram_read_chunk(
1352	__in			efx_nic_t *enp,
1353	__in			efx_nvram_type_t type,
1354	__in			unsigned int offset,
1355	__out_bcount(size)	caddr_t data,
1356	__in			size_t size);
1357
1358extern	__checkReturn		int
1359efx_nvram_set_version(
1360	__in			efx_nic_t *enp,
1361	__in			efx_nvram_type_t type,
1362	__in_ecount(4)		uint16_t version[4]);
1363
1364/* Validate contents of TLV formatted partition */
1365extern	__checkReturn		int
1366efx_nvram_tlv_validate(
1367	__in			efx_nic_t *enp,
1368	__in			uint32_t partn,
1369	__in_bcount(partn_size)	caddr_t partn_data,
1370	__in			size_t partn_size);
1371
1372extern	 __checkReturn		int
1373efx_nvram_erase(
1374	__in			efx_nic_t *enp,
1375	__in			efx_nvram_type_t type);
1376
1377extern	__checkReturn		int
1378efx_nvram_write_chunk(
1379	__in			efx_nic_t *enp,
1380	__in			efx_nvram_type_t type,
1381	__in			unsigned int offset,
1382	__in_bcount(size)	caddr_t data,
1383	__in			size_t size);
1384
1385extern				void
1386efx_nvram_fini(
1387	__in			efx_nic_t *enp);
1388
1389#endif	/* EFSYS_OPT_NVRAM */
1390
1391#if EFSYS_OPT_BOOTCFG
1392
1393extern				int
1394efx_bootcfg_read(
1395	__in			efx_nic_t *enp,
1396	__out_bcount(size)	caddr_t data,
1397	__in			size_t size);
1398
1399extern				int
1400efx_bootcfg_write(
1401	__in			efx_nic_t *enp,
1402	__in_bcount(size)	caddr_t data,
1403	__in			size_t size);
1404
1405#endif	/* EFSYS_OPT_BOOTCFG */
1406
1407#if EFSYS_OPT_WOL
1408
1409typedef enum efx_wol_type_e {
1410	EFX_WOL_TYPE_INVALID,
1411	EFX_WOL_TYPE_MAGIC,
1412	EFX_WOL_TYPE_BITMAP,
1413	EFX_WOL_TYPE_LINK,
1414	EFX_WOL_NTYPES,
1415} efx_wol_type_t;
1416
1417typedef enum efx_lightsout_offload_type_e {
1418	EFX_LIGHTSOUT_OFFLOAD_TYPE_INVALID,
1419	EFX_LIGHTSOUT_OFFLOAD_TYPE_ARP,
1420	EFX_LIGHTSOUT_OFFLOAD_TYPE_NS,
1421} efx_lightsout_offload_type_t;
1422
1423#define	EFX_WOL_BITMAP_MASK_SIZE    (48)
1424#define	EFX_WOL_BITMAP_VALUE_SIZE   (128)
1425
1426typedef union efx_wol_param_u {
1427	struct {
1428		uint8_t mac_addr[6];
1429	} ewp_magic;
1430	struct {
1431		uint8_t mask[EFX_WOL_BITMAP_MASK_SIZE];   /* 1 bit per byte */
1432		uint8_t value[EFX_WOL_BITMAP_VALUE_SIZE]; /* value to match */
1433		uint8_t value_len;
1434	} ewp_bitmap;
1435} efx_wol_param_t;
1436
1437typedef union efx_lightsout_offload_param_u {
1438	struct {
1439		uint8_t mac_addr[6];
1440		uint32_t ip;
1441	} elop_arp;
1442	struct {
1443		uint8_t mac_addr[6];
1444		uint32_t solicited_node[4];
1445		uint32_t ip[4];
1446	} elop_ns;
1447} efx_lightsout_offload_param_t;
1448
1449extern	__checkReturn	int
1450efx_wol_init(
1451	__in		efx_nic_t *enp);
1452
1453extern	__checkReturn	int
1454efx_wol_filter_clear(
1455	__in		efx_nic_t *enp);
1456
1457extern	__checkReturn	int
1458efx_wol_filter_add(
1459	__in		efx_nic_t *enp,
1460	__in		efx_wol_type_t type,
1461	__in		efx_wol_param_t *paramp,
1462	__out		uint32_t *filter_idp);
1463
1464extern	__checkReturn	int
1465efx_wol_filter_remove(
1466	__in		efx_nic_t *enp,
1467	__in		uint32_t filter_id);
1468
1469extern	__checkReturn	int
1470efx_lightsout_offload_add(
1471	__in		efx_nic_t *enp,
1472	__in		efx_lightsout_offload_type_t type,
1473	__in		efx_lightsout_offload_param_t *paramp,
1474	__out		uint32_t *filter_idp);
1475
1476extern	__checkReturn	int
1477efx_lightsout_offload_remove(
1478	__in		efx_nic_t *enp,
1479	__in		efx_lightsout_offload_type_t type,
1480	__in		uint32_t filter_id);
1481
1482extern			void
1483efx_wol_fini(
1484	__in		efx_nic_t *enp);
1485
1486#endif	/* EFSYS_OPT_WOL */
1487
1488#if EFSYS_OPT_DIAG
1489
1490typedef enum efx_pattern_type_t {
1491	EFX_PATTERN_BYTE_INCREMENT = 0,
1492	EFX_PATTERN_ALL_THE_SAME,
1493	EFX_PATTERN_BIT_ALTERNATE,
1494	EFX_PATTERN_BYTE_ALTERNATE,
1495	EFX_PATTERN_BYTE_CHANGING,
1496	EFX_PATTERN_BIT_SWEEP,
1497	EFX_PATTERN_NTYPES
1498} efx_pattern_type_t;
1499
1500typedef 		void
1501(*efx_sram_pattern_fn_t)(
1502	__in		size_t row,
1503	__in		boolean_t negate,
1504	__out		efx_qword_t *eqp);
1505
1506extern	__checkReturn	int
1507efx_sram_test(
1508	__in		efx_nic_t *enp,
1509	__in		efx_pattern_type_t type);
1510
1511#endif	/* EFSYS_OPT_DIAG */
1512
1513extern	__checkReturn	int
1514efx_sram_buf_tbl_set(
1515	__in		efx_nic_t *enp,
1516	__in		uint32_t id,
1517	__in		efsys_mem_t *esmp,
1518	__in		size_t n);
1519
1520extern		void
1521efx_sram_buf_tbl_clear(
1522	__in	efx_nic_t *enp,
1523	__in	uint32_t id,
1524	__in	size_t n);
1525
1526#define	EFX_BUF_TBL_SIZE	0x20000
1527
1528#define	EFX_BUF_SIZE		4096
1529
1530/* EV */
1531
1532typedef struct efx_evq_s	efx_evq_t;
1533
1534#if EFSYS_OPT_QSTATS
1535
1536/* START MKCONFIG GENERATED EfxHeaderEventQueueBlock 6f3843f5fe7cc843 */
1537typedef enum efx_ev_qstat_e {
1538	EV_ALL,
1539	EV_RX,
1540	EV_RX_OK,
1541	EV_RX_FRM_TRUNC,
1542	EV_RX_TOBE_DISC,
1543	EV_RX_PAUSE_FRM_ERR,
1544	EV_RX_BUF_OWNER_ID_ERR,
1545	EV_RX_IPV4_HDR_CHKSUM_ERR,
1546	EV_RX_TCP_UDP_CHKSUM_ERR,
1547	EV_RX_ETH_CRC_ERR,
1548	EV_RX_IP_FRAG_ERR,
1549	EV_RX_MCAST_PKT,
1550	EV_RX_MCAST_HASH_MATCH,
1551	EV_RX_TCP_IPV4,
1552	EV_RX_TCP_IPV6,
1553	EV_RX_UDP_IPV4,
1554	EV_RX_UDP_IPV6,
1555	EV_RX_OTHER_IPV4,
1556	EV_RX_OTHER_IPV6,
1557	EV_RX_NON_IP,
1558	EV_RX_BATCH,
1559	EV_TX,
1560	EV_TX_WQ_FF_FULL,
1561	EV_TX_PKT_ERR,
1562	EV_TX_PKT_TOO_BIG,
1563	EV_TX_UNEXPECTED,
1564	EV_GLOBAL,
1565	EV_GLOBAL_MNT,
1566	EV_DRIVER,
1567	EV_DRIVER_SRM_UPD_DONE,
1568	EV_DRIVER_TX_DESCQ_FLS_DONE,
1569	EV_DRIVER_RX_DESCQ_FLS_DONE,
1570	EV_DRIVER_RX_DESCQ_FLS_FAILED,
1571	EV_DRIVER_RX_DSC_ERROR,
1572	EV_DRIVER_TX_DSC_ERROR,
1573	EV_DRV_GEN,
1574	EV_MCDI_RESPONSE,
1575	EV_NQSTATS
1576} efx_ev_qstat_t;
1577
1578/* END MKCONFIG GENERATED EfxHeaderEventQueueBlock */
1579
1580#endif	/* EFSYS_OPT_QSTATS */
1581
1582extern	__checkReturn	int
1583efx_ev_init(
1584	__in		efx_nic_t *enp);
1585
1586extern		void
1587efx_ev_fini(
1588	__in		efx_nic_t *enp);
1589
1590#define	EFX_EVQ_MAXNEVS		32768
1591#define	EFX_EVQ_MINNEVS		512
1592
1593#define	EFX_EVQ_SIZE(_nevs)	((_nevs) * sizeof (efx_qword_t))
1594#define	EFX_EVQ_NBUFS(_nevs)	(EFX_EVQ_SIZE(_nevs) / EFX_BUF_SIZE)
1595
1596extern	__checkReturn	int
1597efx_ev_qcreate(
1598	__in		efx_nic_t *enp,
1599	__in		unsigned int index,
1600	__in		efsys_mem_t *esmp,
1601	__in		size_t n,
1602	__in		uint32_t id,
1603	__deref_out	efx_evq_t **eepp);
1604
1605extern		void
1606efx_ev_qpost(
1607	__in		efx_evq_t *eep,
1608	__in		uint16_t data);
1609
1610typedef __checkReturn	boolean_t
1611(*efx_initialized_ev_t)(
1612	__in_opt	void *arg);
1613
1614#define	EFX_PKT_UNICAST		0x0004
1615#define	EFX_PKT_START		0x0008
1616
1617#define	EFX_PKT_VLAN_TAGGED	0x0010
1618#define	EFX_CKSUM_TCPUDP	0x0020
1619#define	EFX_CKSUM_IPV4		0x0040
1620#define	EFX_PKT_CONT		0x0080
1621
1622#define	EFX_CHECK_VLAN		0x0100
1623#define	EFX_PKT_TCP		0x0200
1624#define	EFX_PKT_UDP		0x0400
1625#define	EFX_PKT_IPV4		0x0800
1626
1627#define	EFX_PKT_IPV6		0x1000
1628#define	EFX_PKT_PREFIX_LEN	0x2000
1629#define	EFX_ADDR_MISMATCH	0x4000
1630#define	EFX_DISCARD		0x8000
1631
1632#define	EFX_EV_RX_NLABELS	32
1633#define	EFX_EV_TX_NLABELS	32
1634
1635typedef	__checkReturn	boolean_t
1636(*efx_rx_ev_t)(
1637	__in_opt	void *arg,
1638	__in		uint32_t label,
1639	__in		uint32_t id,
1640	__in		uint32_t size,
1641	__in		uint16_t flags);
1642
1643typedef	__checkReturn	boolean_t
1644(*efx_tx_ev_t)(
1645	__in_opt	void *arg,
1646	__in		uint32_t label,
1647	__in		uint32_t id);
1648
1649#define	EFX_EXCEPTION_RX_RECOVERY	0x00000001
1650#define	EFX_EXCEPTION_RX_DSC_ERROR	0x00000002
1651#define	EFX_EXCEPTION_TX_DSC_ERROR	0x00000003
1652#define	EFX_EXCEPTION_UNKNOWN_SENSOREVT	0x00000004
1653#define	EFX_EXCEPTION_FWALERT_SRAM	0x00000005
1654#define	EFX_EXCEPTION_UNKNOWN_FWALERT	0x00000006
1655#define	EFX_EXCEPTION_RX_ERROR		0x00000007
1656#define	EFX_EXCEPTION_TX_ERROR		0x00000008
1657#define	EFX_EXCEPTION_EV_ERROR		0x00000009
1658
1659typedef	__checkReturn	boolean_t
1660(*efx_exception_ev_t)(
1661	__in_opt	void *arg,
1662	__in		uint32_t label,
1663	__in		uint32_t data);
1664
1665typedef	__checkReturn	boolean_t
1666(*efx_rxq_flush_done_ev_t)(
1667	__in_opt	void *arg,
1668	__in		uint32_t rxq_index);
1669
1670typedef	__checkReturn	boolean_t
1671(*efx_rxq_flush_failed_ev_t)(
1672	__in_opt	void *arg,
1673	__in		uint32_t rxq_index);
1674
1675typedef	__checkReturn	boolean_t
1676(*efx_txq_flush_done_ev_t)(
1677	__in_opt	void *arg,
1678	__in		uint32_t txq_index);
1679
1680typedef	__checkReturn	boolean_t
1681(*efx_software_ev_t)(
1682	__in_opt	void *arg,
1683	__in		uint16_t magic);
1684
1685typedef	__checkReturn	boolean_t
1686(*efx_sram_ev_t)(
1687	__in_opt	void *arg,
1688	__in		uint32_t code);
1689
1690#define	EFX_SRAM_CLEAR		0
1691#define	EFX_SRAM_UPDATE		1
1692#define	EFX_SRAM_ILLEGAL_CLEAR	2
1693
1694typedef	__checkReturn	boolean_t
1695(*efx_wake_up_ev_t)(
1696	__in_opt	void *arg,
1697	__in		uint32_t label);
1698
1699typedef	__checkReturn	boolean_t
1700(*efx_timer_ev_t)(
1701	__in_opt	void *arg,
1702	__in		uint32_t label);
1703
1704typedef __checkReturn	boolean_t
1705(*efx_link_change_ev_t)(
1706	__in_opt	void *arg,
1707	__in		efx_link_mode_t	link_mode);
1708
1709#if EFSYS_OPT_MON_STATS
1710
1711typedef __checkReturn	boolean_t
1712(*efx_monitor_ev_t)(
1713	__in_opt	void *arg,
1714	__in		efx_mon_stat_t id,
1715	__in		efx_mon_stat_value_t value);
1716
1717#endif	/* EFSYS_OPT_MON_STATS */
1718
1719#if EFSYS_OPT_MAC_STATS
1720
1721typedef __checkReturn	boolean_t
1722(*efx_mac_stats_ev_t)(
1723	__in_opt	void *arg,
1724	__in		uint32_t generation
1725	);
1726
1727#endif	/* EFSYS_OPT_MAC_STATS */
1728
1729typedef struct efx_ev_callbacks_s {
1730	efx_initialized_ev_t		eec_initialized;
1731	efx_rx_ev_t			eec_rx;
1732	efx_tx_ev_t			eec_tx;
1733	efx_exception_ev_t		eec_exception;
1734	efx_rxq_flush_done_ev_t		eec_rxq_flush_done;
1735	efx_rxq_flush_failed_ev_t	eec_rxq_flush_failed;
1736	efx_txq_flush_done_ev_t		eec_txq_flush_done;
1737	efx_software_ev_t		eec_software;
1738	efx_sram_ev_t			eec_sram;
1739	efx_wake_up_ev_t		eec_wake_up;
1740	efx_timer_ev_t			eec_timer;
1741	efx_link_change_ev_t		eec_link_change;
1742#if EFSYS_OPT_MON_STATS
1743	efx_monitor_ev_t		eec_monitor;
1744#endif	/* EFSYS_OPT_MON_STATS */
1745#if EFSYS_OPT_MAC_STATS
1746	efx_mac_stats_ev_t		eec_mac_stats;
1747#endif	/* EFSYS_OPT_MAC_STATS */
1748} efx_ev_callbacks_t;
1749
1750extern	__checkReturn	boolean_t
1751efx_ev_qpending(
1752	__in		efx_evq_t *eep,
1753	__in		unsigned int count);
1754
1755#if EFSYS_OPT_EV_PREFETCH
1756
1757extern			void
1758efx_ev_qprefetch(
1759	__in		efx_evq_t *eep,
1760	__in		unsigned int count);
1761
1762#endif	/* EFSYS_OPT_EV_PREFETCH */
1763
1764extern			void
1765efx_ev_qpoll(
1766	__in		efx_evq_t *eep,
1767	__inout		unsigned int *countp,
1768	__in		const efx_ev_callbacks_t *eecp,
1769	__in_opt	void *arg);
1770
1771extern	__checkReturn	int
1772efx_ev_qmoderate(
1773	__in		efx_evq_t *eep,
1774	__in		unsigned int us);
1775
1776extern	__checkReturn	int
1777efx_ev_qprime(
1778	__in		efx_evq_t *eep,
1779	__in		unsigned int count);
1780
1781#if EFSYS_OPT_QSTATS
1782
1783#if EFSYS_OPT_NAMES
1784
1785extern		const char *
1786efx_ev_qstat_name(
1787	__in	efx_nic_t *enp,
1788	__in	unsigned int id);
1789
1790#endif	/* EFSYS_OPT_NAMES */
1791
1792extern					void
1793efx_ev_qstats_update(
1794	__in				efx_evq_t *eep,
1795	__inout_ecount(EV_NQSTATS)	efsys_stat_t *stat);
1796
1797#endif	/* EFSYS_OPT_QSTATS */
1798
1799extern		void
1800efx_ev_qdestroy(
1801	__in	efx_evq_t *eep);
1802
1803/* RX */
1804
1805extern	__checkReturn	int
1806efx_rx_init(
1807	__inout		efx_nic_t *enp);
1808
1809extern		void
1810efx_rx_fini(
1811	__in		efx_nic_t *enp);
1812
1813#if EFSYS_OPT_RX_HDR_SPLIT
1814	__checkReturn	int
1815efx_rx_hdr_split_enable(
1816	__in		efx_nic_t *enp,
1817	__in		unsigned int hdr_buf_size,
1818	__in		unsigned int pld_buf_size);
1819
1820#endif	/* EFSYS_OPT_RX_HDR_SPLIT */
1821
1822#if EFSYS_OPT_RX_SCATTER
1823	__checkReturn	int
1824efx_rx_scatter_enable(
1825	__in		efx_nic_t *enp,
1826	__in		unsigned int buf_size);
1827#endif	/* EFSYS_OPT_RX_SCATTER */
1828
1829#if EFSYS_OPT_RX_SCALE
1830
1831typedef enum efx_rx_hash_alg_e {
1832	EFX_RX_HASHALG_LFSR = 0,
1833	EFX_RX_HASHALG_TOEPLITZ
1834} efx_rx_hash_alg_t;
1835
1836typedef enum efx_rx_hash_type_e {
1837	EFX_RX_HASH_IPV4 = 0,
1838	EFX_RX_HASH_TCPIPV4,
1839	EFX_RX_HASH_IPV6,
1840	EFX_RX_HASH_TCPIPV6,
1841} efx_rx_hash_type_t;
1842
1843typedef enum efx_rx_hash_support_e {
1844	EFX_RX_HASH_UNAVAILABLE = 0,	/* Hardware hash not inserted */
1845	EFX_RX_HASH_AVAILABLE		/* Insert hash with/without RSS */
1846} efx_rx_hash_support_t;
1847
1848#define	EFX_RSS_TBL_SIZE	128	/* Rows in RX indirection table */
1849#define	EFX_MAXRSS	    	64	/* RX indirection entry range */
1850#define	EFX_MAXRSS_LEGACY   	16 	/* See bug16611 and bug17213 */
1851
1852typedef enum efx_rx_scale_support_e {
1853	EFX_RX_SCALE_UNAVAILABLE = 0,	/* Not supported */
1854	EFX_RX_SCALE_EXCLUSIVE,		/* Writable key/indirection table */
1855	EFX_RX_SCALE_SHARED		/* Read-only key/indirection table */
1856} efx_rx_scale_support_t;
1857
1858 extern	__checkReturn	int
1859efx_rx_hash_support_get(
1860	__in		efx_nic_t *enp,
1861	__out		efx_rx_hash_support_t *supportp);
1862
1863
1864extern	__checkReturn	int
1865efx_rx_scale_support_get(
1866	__in		efx_nic_t *enp,
1867	__out		efx_rx_scale_support_t *supportp);
1868
1869extern	__checkReturn	int
1870efx_rx_scale_mode_set(
1871	__in	efx_nic_t *enp,
1872	__in	efx_rx_hash_alg_t alg,
1873	__in	efx_rx_hash_type_t type,
1874	__in	boolean_t insert);
1875
1876extern	__checkReturn	int
1877efx_rx_scale_tbl_set(
1878	__in		efx_nic_t *enp,
1879	__in_ecount(n)	unsigned int *table,
1880	__in		size_t n);
1881
1882extern	__checkReturn	int
1883efx_rx_scale_key_set(
1884	__in		efx_nic_t *enp,
1885	__in_ecount(n)	uint8_t *key,
1886	__in		size_t n);
1887
1888extern uint32_t
1889efx_psuedo_hdr_hash_get(
1890	__in		efx_nic_t *enp,
1891	__in		efx_rx_hash_alg_t func,
1892	__in		uint8_t *buffer);
1893
1894#endif	/* EFSYS_OPT_RX_SCALE */
1895
1896extern	__checkReturn	int
1897efx_psuedo_hdr_pkt_length_get(
1898	__in		efx_nic_t *enp,
1899	__in		uint8_t *buffer,
1900	__out		uint16_t *pkt_lengthp);
1901
1902#define	EFX_RXQ_MAXNDESCS		4096
1903#define	EFX_RXQ_MINNDESCS		512
1904
1905#define	EFX_RXQ_SIZE(_ndescs)		((_ndescs) * sizeof (efx_qword_t))
1906#define	EFX_RXQ_NBUFS(_ndescs)		(EFX_RXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
1907#define	EFX_RXQ_LIMIT(_ndescs)		((_ndescs) - 16)
1908#define	EFX_RXQ_DC_NDESCS(_dcsize)	(8 << _dcsize)
1909
1910typedef enum efx_rxq_type_e {
1911	EFX_RXQ_TYPE_DEFAULT,
1912	EFX_RXQ_TYPE_SPLIT_HEADER,
1913	EFX_RXQ_TYPE_SPLIT_PAYLOAD,
1914	EFX_RXQ_TYPE_SCATTER,
1915	EFX_RXQ_NTYPES
1916} efx_rxq_type_t;
1917
1918extern	__checkReturn	int
1919efx_rx_qcreate(
1920	__in		efx_nic_t *enp,
1921	__in		unsigned int index,
1922	__in		unsigned int label,
1923	__in		efx_rxq_type_t type,
1924	__in		efsys_mem_t *esmp,
1925	__in		size_t n,
1926	__in		uint32_t id,
1927	__in		efx_evq_t *eep,
1928	__deref_out	efx_rxq_t **erpp);
1929
1930typedef struct efx_buffer_s {
1931	efsys_dma_addr_t	eb_addr;
1932	size_t			eb_size;
1933	boolean_t		eb_eop;
1934} efx_buffer_t;
1935
1936typedef struct efx_desc_s {
1937	efx_qword_t ed_eq;
1938} efx_desc_t;
1939
1940extern			void
1941efx_rx_qpost(
1942	__in		efx_rxq_t *erp,
1943	__in_ecount(n)	efsys_dma_addr_t *addrp,
1944	__in		size_t size,
1945	__in		unsigned int n,
1946	__in		unsigned int completed,
1947	__in		unsigned int added);
1948
1949extern		void
1950efx_rx_qpush(
1951	__in	efx_rxq_t *erp,
1952	__in	unsigned int added,
1953	__inout	unsigned int *pushedp);
1954
1955extern	__checkReturn	int
1956efx_rx_qflush(
1957	__in	efx_rxq_t *erp);
1958
1959extern		void
1960efx_rx_qenable(
1961	__in	efx_rxq_t *erp);
1962
1963extern		void
1964efx_rx_qdestroy(
1965	__in	efx_rxq_t *erp);
1966
1967/* TX */
1968
1969typedef struct efx_txq_s	efx_txq_t;
1970
1971#if EFSYS_OPT_QSTATS
1972
1973/* START MKCONFIG GENERATED EfxHeaderTransmitQueueBlock 12dff8778598b2db */
1974typedef enum efx_tx_qstat_e {
1975	TX_POST,
1976	TX_POST_PIO,
1977	TX_NQSTATS
1978} efx_tx_qstat_t;
1979
1980/* END MKCONFIG GENERATED EfxHeaderTransmitQueueBlock */
1981
1982#endif	/* EFSYS_OPT_QSTATS */
1983
1984extern	__checkReturn	int
1985efx_tx_init(
1986	__in		efx_nic_t *enp);
1987
1988extern		void
1989efx_tx_fini(
1990	__in	efx_nic_t *enp);
1991
1992#define	EFX_BUG35388_WORKAROUND(_encp)					\
1993	(((_encp) == NULL) ? 1 : ((_encp)->enc_bug35388_workaround != 0))
1994
1995#define	EFX_TXQ_MAXNDESCS(_encp)					\
1996	((EFX_BUG35388_WORKAROUND(_encp)) ? 2048 : 4096)
1997
1998#define	EFX_TXQ_MINNDESCS		512
1999
2000#define	EFX_TXQ_SIZE(_ndescs)		((_ndescs) * sizeof (efx_qword_t))
2001#define	EFX_TXQ_NBUFS(_ndescs)		(EFX_TXQ_SIZE(_ndescs) / EFX_BUF_SIZE)
2002#define	EFX_TXQ_LIMIT(_ndescs)		((_ndescs) - 16)
2003#define	EFX_TXQ_DC_NDESCS(_dcsize)	(8 << _dcsize)
2004
2005#define	EFX_TXQ_MAX_BUFS 8 /* Maximum independent of EFX_BUG35388_WORKAROUND. */
2006
2007extern	__checkReturn	int
2008efx_tx_qcreate(
2009	__in		efx_nic_t *enp,
2010	__in		unsigned int index,
2011	__in		unsigned int label,
2012	__in		efsys_mem_t *esmp,
2013	__in		size_t n,
2014	__in		uint32_t id,
2015	__in		uint16_t flags,
2016	__in		efx_evq_t *eep,
2017	__deref_out	efx_txq_t **etpp,
2018	__out		unsigned int *addedp);
2019
2020extern	__checkReturn	int
2021efx_tx_qpost(
2022	__in		efx_txq_t *etp,
2023	__in_ecount(n)	efx_buffer_t *eb,
2024	__in		unsigned int n,
2025	__in		unsigned int completed,
2026	__inout		unsigned int *addedp);
2027
2028extern	__checkReturn	int
2029efx_tx_qpace(
2030	__in		efx_txq_t *etp,
2031	__in		unsigned int ns);
2032
2033extern			void
2034efx_tx_qpush(
2035	__in		efx_txq_t *etp,
2036	__in		unsigned int added,
2037	__in		unsigned int pushed);
2038
2039extern	__checkReturn	int
2040efx_tx_qflush(
2041	__in		efx_txq_t *etp);
2042
2043extern			void
2044efx_tx_qenable(
2045	__in		efx_txq_t *etp);
2046
2047extern	__checkReturn	int
2048efx_tx_qpio_enable(
2049	__in		efx_txq_t *etp);
2050
2051extern			void
2052efx_tx_qpio_disable(
2053	__in		efx_txq_t *etp);
2054
2055extern	__checkReturn	int
2056efx_tx_qpio_write(
2057	__in			efx_txq_t *etp,
2058	__in_ecount(buf_length)	uint8_t *buffer,
2059	__in			size_t buf_length,
2060	__in                    size_t pio_buf_offset);
2061
2062extern	__checkReturn	int
2063efx_tx_qpio_post(
2064	__in			efx_txq_t *etp,
2065	__in			size_t pkt_length,
2066	__in			unsigned int completed,
2067	__inout			unsigned int *addedp);
2068
2069extern	__checkReturn	int
2070efx_tx_qdesc_post(
2071	__in		efx_txq_t *etp,
2072	__in_ecount(n)	efx_desc_t *ed,
2073	__in		unsigned int n,
2074	__in		unsigned int completed,
2075	__inout		unsigned int *addedp);
2076
2077extern	void
2078efx_tx_qdesc_dma_create(
2079	__in	efx_txq_t *etp,
2080	__in	efsys_dma_addr_t addr,
2081	__in	size_t size,
2082	__in	boolean_t eop,
2083	__out	efx_desc_t *edp);
2084
2085extern	void
2086efx_tx_qdesc_tso_create(
2087	__in	efx_txq_t *etp,
2088	__in	uint16_t ipv4_id,
2089	__in	uint32_t tcp_seq,
2090	__in	uint8_t  tcp_flags,
2091	__out	efx_desc_t *edp);
2092
2093extern	void
2094efx_tx_qdesc_vlantci_create(
2095	__in	efx_txq_t *etp,
2096	__in	uint16_t tci,
2097	__out	efx_desc_t *edp);
2098
2099#if EFSYS_OPT_QSTATS
2100
2101#if EFSYS_OPT_NAMES
2102
2103extern		const char *
2104efx_tx_qstat_name(
2105	__in	efx_nic_t *etp,
2106	__in	unsigned int id);
2107
2108#endif	/* EFSYS_OPT_NAMES */
2109
2110extern					void
2111efx_tx_qstats_update(
2112	__in				efx_txq_t *etp,
2113	__inout_ecount(TX_NQSTATS)	efsys_stat_t *stat);
2114
2115#endif	/* EFSYS_OPT_QSTATS */
2116
2117extern		void
2118efx_tx_qdestroy(
2119	__in	efx_txq_t *etp);
2120
2121
2122/* FILTER */
2123
2124#if EFSYS_OPT_FILTER
2125
2126#define	EFX_ETHER_TYPE_IPV4 0x0800
2127#define	EFX_ETHER_TYPE_IPV6 0x86DD
2128
2129#define	EFX_IPPROTO_TCP 6
2130#define	EFX_IPPROTO_UDP 17
2131
2132typedef enum efx_filter_flag_e {
2133	EFX_FILTER_FLAG_RX_RSS = 0x01,		/* use RSS to spread across
2134						 * multiple queues */
2135	EFX_FILTER_FLAG_RX_SCATTER = 0x02,	/* enable RX scatter */
2136	EFX_FILTER_FLAG_RX_OVER_AUTO = 0x04,	/* Override an automatic filter
2137						 * (priority EFX_FILTER_PRI_AUTO).
2138						 * May only be set by the filter
2139						 * implementation for each type.
2140						 * A removal request will
2141						 * restore the automatic filter
2142						 * in its place. */
2143	EFX_FILTER_FLAG_RX = 0x08,		/* Filter is for RX */
2144	EFX_FILTER_FLAG_TX = 0x10,		/* Filter is for TX */
2145} efx_filter_flag_t;
2146
2147typedef enum efx_filter_match_flags_e {
2148	EFX_FILTER_MATCH_REM_HOST = 0x0001,	/* Match by remote IP host
2149						 * address */
2150	EFX_FILTER_MATCH_LOC_HOST = 0x0002,	/* Match by local IP host
2151						 * address */
2152	EFX_FILTER_MATCH_REM_MAC = 0x0004,	/* Match by remote MAC address */
2153	EFX_FILTER_MATCH_REM_PORT = 0x0008,	/* Match by remote TCP/UDP port */
2154	EFX_FILTER_MATCH_LOC_MAC = 0x0010,	/* Match by remote TCP/UDP port */
2155	EFX_FILTER_MATCH_LOC_PORT = 0x0020,	/* Match by local TCP/UDP port */
2156	EFX_FILTER_MATCH_ETHER_TYPE = 0x0040,	/* Match by Ether-type */
2157	EFX_FILTER_MATCH_INNER_VID = 0x0080,	/* Match by inner VLAN ID */
2158	EFX_FILTER_MATCH_OUTER_VID = 0x0100,	/* Match by outer VLAN ID */
2159	EFX_FILTER_MATCH_IP_PROTO = 0x0200,	/* Match by IP transport
2160						 * protocol */
2161	EFX_FILTER_MATCH_LOC_MAC_IG = 0x0400,	/* Match by local MAC address
2162						 * I/G bit. Used for RX default
2163						 * unicast and multicast/
2164						 * broadcast filters. */
2165} efx_filter_match_flags_t;
2166
2167typedef enum efx_filter_priority_s {
2168	EFX_FILTER_PRI_HINT = 0,	/* Performance hint */
2169	EFX_FILTER_PRI_AUTO,		/* Automatic filter based on device
2170					 * address list or hardware
2171					 * requirements. This may only be used
2172					 * by the filter implementation for
2173					 * each NIC type. */
2174	EFX_FILTER_PRI_MANUAL,		/* Manually configured filter */
2175	EFX_FILTER_PRI_REQUIRED,	/* Required for correct behaviour of the
2176					 * client (e.g. SR-IOV, HyperV VMQ etc.)
2177					 */
2178} efx_filter_priority_t;
2179
2180/*
2181 * FIXME: All these fields are assumed to be in little-endian byte order.
2182 * It may be better for some to be big-endian. See bug42804.
2183 */
2184
2185typedef struct efx_filter_spec_s {
2186	uint32_t	efs_match_flags:12;
2187	uint32_t	efs_priority:2;
2188	uint32_t	efs_flags:6;
2189	uint32_t	efs_dmaq_id:12;
2190	uint32_t	efs_rss_context;
2191	uint16_t	efs_outer_vid;
2192	uint16_t	efs_inner_vid;
2193	uint8_t		efs_loc_mac[EFX_MAC_ADDR_LEN];
2194	uint8_t		efs_rem_mac[EFX_MAC_ADDR_LEN];
2195	uint16_t	efs_ether_type;
2196	uint8_t		efs_ip_proto;
2197	uint16_t	efs_loc_port;
2198	uint16_t	efs_rem_port;
2199	efx_oword_t	efs_rem_host;
2200	efx_oword_t	efs_loc_host;
2201} efx_filter_spec_t;
2202
2203
2204/* Default values for use in filter specifications */
2205#define	EFX_FILTER_SPEC_RSS_CONTEXT_DEFAULT	0xffffffff
2206#define	EFX_FILTER_SPEC_RX_DMAQ_ID_DROP		0xfff
2207#define	EFX_FILTER_SPEC_VID_UNSPEC		0xffff
2208
2209extern	__checkReturn	int
2210efx_filter_init(
2211	__in		efx_nic_t *enp);
2212
2213extern			void
2214efx_filter_fini(
2215	__in		efx_nic_t *enp);
2216
2217extern	__checkReturn	int
2218efx_filter_insert(
2219	__in		efx_nic_t *enp,
2220	__inout		efx_filter_spec_t *spec);
2221
2222extern	__checkReturn	int
2223efx_filter_remove(
2224	__in		efx_nic_t *enp,
2225	__inout		efx_filter_spec_t *spec);
2226
2227extern	__checkReturn	int
2228efx_filter_restore(
2229	__in		efx_nic_t *enp);
2230
2231extern	__checkReturn	int
2232efx_filter_supported_filters(
2233	__in		efx_nic_t *enp,
2234	__out		uint32_t *list,
2235	__out		size_t *length);
2236
2237extern			void
2238efx_filter_spec_init_rx(
2239	__inout		efx_filter_spec_t *spec,
2240	__in		efx_filter_priority_t priority,
2241	__in		efx_filter_flag_t flags,
2242	__in		efx_rxq_t *erp);
2243
2244extern			void
2245efx_filter_spec_init_tx(
2246	__inout		efx_filter_spec_t *spec,
2247	__in		efx_txq_t *etp);
2248
2249extern	__checkReturn	int
2250efx_filter_spec_set_ipv4_local(
2251	__inout		efx_filter_spec_t *spec,
2252	__in		uint8_t proto,
2253	__in		uint32_t host,
2254	__in		uint16_t port);
2255
2256extern	__checkReturn	int
2257efx_filter_spec_set_ipv4_full(
2258	__inout		efx_filter_spec_t *spec,
2259	__in		uint8_t proto,
2260	__in		uint32_t lhost,
2261	__in		uint16_t lport,
2262	__in		uint32_t rhost,
2263	__in		uint16_t rport);
2264
2265extern	__checkReturn	int
2266efx_filter_spec_set_eth_local(
2267	__inout		efx_filter_spec_t *spec,
2268	__in		uint16_t vid,
2269	__in		const uint8_t *addr);
2270
2271extern	__checkReturn	int
2272efx_filter_spec_set_uc_def(
2273	__inout		efx_filter_spec_t *spec);
2274
2275extern	__checkReturn	int
2276efx_filter_spec_set_mc_def(
2277	__inout		efx_filter_spec_t *spec);
2278
2279#endif	/* EFSYS_OPT_FILTER */
2280
2281/* HASH */
2282
2283extern	__checkReturn		uint32_t
2284efx_hash_dwords(
2285	__in_ecount(count)	uint32_t const *input,
2286	__in			size_t count,
2287	__in			uint32_t init);
2288
2289extern	__checkReturn		uint32_t
2290efx_hash_bytes(
2291	__in_ecount(length)	uint8_t const *input,
2292	__in			size_t length,
2293	__in			uint32_t init);
2294
2295
2296#ifdef	__cplusplus
2297}
2298#endif
2299
2300#endif	/* _SYS_EFX_H */
2301