if_re.c revision 262151
1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: stable/10/sys/dev/re/if_re.c 262151 2014-02-18 05:01:04Z luigi $"); 35 36/* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111#ifdef HAVE_KERNEL_OPTION_HEADERS 112#include "opt_device_polling.h" 113#endif 114 115#include <sys/param.h> 116#include <sys/endian.h> 117#include <sys/systm.h> 118#include <sys/sockio.h> 119#include <sys/mbuf.h> 120#include <sys/malloc.h> 121#include <sys/module.h> 122#include <sys/kernel.h> 123#include <sys/socket.h> 124#include <sys/lock.h> 125#include <sys/mutex.h> 126#include <sys/sysctl.h> 127#include <sys/taskqueue.h> 128 129#include <net/if.h> 130#include <net/if_arp.h> 131#include <net/ethernet.h> 132#include <net/if_dl.h> 133#include <net/if_media.h> 134#include <net/if_types.h> 135#include <net/if_vlan_var.h> 136 137#include <net/bpf.h> 138 139#include <machine/bus.h> 140#include <machine/resource.h> 141#include <sys/bus.h> 142#include <sys/rman.h> 143 144#include <dev/mii/mii.h> 145#include <dev/mii/miivar.h> 146 147#include <dev/pci/pcireg.h> 148#include <dev/pci/pcivar.h> 149 150#include <pci/if_rlreg.h> 151 152MODULE_DEPEND(re, pci, 1, 1, 1); 153MODULE_DEPEND(re, ether, 1, 1, 1); 154MODULE_DEPEND(re, miibus, 1, 1, 1); 155 156/* "device miibus" required. See GENERIC if you get errors here. */ 157#include "miibus_if.h" 158 159/* Tunables. */ 160static int intr_filter = 0; 161TUNABLE_INT("hw.re.intr_filter", &intr_filter); 162static int msi_disable = 0; 163TUNABLE_INT("hw.re.msi_disable", &msi_disable); 164static int msix_disable = 0; 165TUNABLE_INT("hw.re.msix_disable", &msix_disable); 166static int prefer_iomap = 0; 167TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap); 168 169#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 170 171/* 172 * Various supported device vendors/types and their names. 173 */ 174static const struct rl_type re_devs[] = { 175 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 176 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 177 { DLINK_VENDORID, DLINK_DEVICEID_530T_REVC, 0, 178 "D-Link DGE-530(T) Gigabit Ethernet Adapter" }, 179 { RT_VENDORID, RT_DEVICEID_8139, 0, 180 "RealTek 8139C+ 10/100BaseTX" }, 181 { RT_VENDORID, RT_DEVICEID_8101E, 0, 182 "RealTek 810xE PCIe 10/100baseTX" }, 183 { RT_VENDORID, RT_DEVICEID_8168, 0, 184 "RealTek 8168/8111 B/C/CP/D/DP/E/F/G PCIe Gigabit Ethernet" }, 185 { RT_VENDORID, RT_DEVICEID_8169, 0, 186 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 187 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 188 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 189 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 190 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 191 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 192 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 193 { USR_VENDORID, USR_DEVICEID_997902, 0, 194 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 195}; 196 197static const struct rl_hwrev re_hwrevs[] = { 198 { RL_HWREV_8139, RL_8139, "", RL_MTU }, 199 { RL_HWREV_8139A, RL_8139, "A", RL_MTU }, 200 { RL_HWREV_8139AG, RL_8139, "A-G", RL_MTU }, 201 { RL_HWREV_8139B, RL_8139, "B", RL_MTU }, 202 { RL_HWREV_8130, RL_8139, "8130", RL_MTU }, 203 { RL_HWREV_8139C, RL_8139, "C", RL_MTU }, 204 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C", RL_MTU }, 205 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+", RL_MTU }, 206 { RL_HWREV_8168B_SPIN1, RL_8169, "8168", RL_JUMBO_MTU }, 207 { RL_HWREV_8169, RL_8169, "8169", RL_JUMBO_MTU }, 208 { RL_HWREV_8169S, RL_8169, "8169S", RL_JUMBO_MTU }, 209 { RL_HWREV_8110S, RL_8169, "8110S", RL_JUMBO_MTU }, 210 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB", RL_JUMBO_MTU }, 211 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 212 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL", RL_JUMBO_MTU }, 213 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 214 { RL_HWREV_8100, RL_8139, "8100", RL_MTU }, 215 { RL_HWREV_8101, RL_8139, "8101", RL_MTU }, 216 { RL_HWREV_8100E, RL_8169, "8100E", RL_MTU }, 217 { RL_HWREV_8101E, RL_8169, "8101E", RL_MTU }, 218 { RL_HWREV_8102E, RL_8169, "8102E", RL_MTU }, 219 { RL_HWREV_8102EL, RL_8169, "8102EL", RL_MTU }, 220 { RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL", RL_MTU }, 221 { RL_HWREV_8103E, RL_8169, "8103E", RL_MTU }, 222 { RL_HWREV_8401E, RL_8169, "8401E", RL_MTU }, 223 { RL_HWREV_8402, RL_8169, "8402", RL_MTU }, 224 { RL_HWREV_8105E, RL_8169, "8105E", RL_MTU }, 225 { RL_HWREV_8105E_SPIN1, RL_8169, "8105E", RL_MTU }, 226 { RL_HWREV_8106E, RL_8169, "8106E", RL_MTU }, 227 { RL_HWREV_8168B_SPIN2, RL_8169, "8168", RL_JUMBO_MTU }, 228 { RL_HWREV_8168B_SPIN3, RL_8169, "8168", RL_JUMBO_MTU }, 229 { RL_HWREV_8168C, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 230 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 231 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP", RL_JUMBO_MTU_6K }, 232 { RL_HWREV_8168D, RL_8169, "8168D/8111D", RL_JUMBO_MTU_9K }, 233 { RL_HWREV_8168DP, RL_8169, "8168DP/8111DP", RL_JUMBO_MTU_9K }, 234 { RL_HWREV_8168E, RL_8169, "8168E/8111E", RL_JUMBO_MTU_9K}, 235 { RL_HWREV_8168E_VL, RL_8169, "8168E/8111E-VL", RL_JUMBO_MTU_6K}, 236 { RL_HWREV_8168EP, RL_8169, "8168EP/8111EP", RL_JUMBO_MTU_9K}, 237 { RL_HWREV_8168F, RL_8169, "8168F/8111F", RL_JUMBO_MTU_9K}, 238 { RL_HWREV_8168G, RL_8169, "8168G/8111G", RL_JUMBO_MTU_9K}, 239 { RL_HWREV_8168GU, RL_8169, "8168GU/8111GU", RL_JUMBO_MTU_9K}, 240 { RL_HWREV_8411, RL_8169, "8411", RL_JUMBO_MTU_9K}, 241 { RL_HWREV_8411B, RL_8169, "8411B", RL_JUMBO_MTU_9K}, 242 { 0, 0, NULL, 0 } 243}; 244 245static int re_probe (device_t); 246static int re_attach (device_t); 247static int re_detach (device_t); 248 249static int re_encap (struct rl_softc *, struct mbuf **); 250 251static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 252static int re_allocmem (device_t, struct rl_softc *); 253static __inline void re_discard_rxbuf 254 (struct rl_softc *, int); 255static int re_newbuf (struct rl_softc *, int); 256static int re_jumbo_newbuf (struct rl_softc *, int); 257static int re_rx_list_init (struct rl_softc *); 258static int re_jrx_list_init (struct rl_softc *); 259static int re_tx_list_init (struct rl_softc *); 260#ifdef RE_FIXUP_RX 261static __inline void re_fixup_rx 262 (struct mbuf *); 263#endif 264static int re_rxeof (struct rl_softc *, int *); 265static void re_txeof (struct rl_softc *); 266#ifdef DEVICE_POLLING 267static int re_poll (struct ifnet *, enum poll_cmd, int); 268static int re_poll_locked (struct ifnet *, enum poll_cmd, int); 269#endif 270static int re_intr (void *); 271static void re_intr_msi (void *); 272static void re_tick (void *); 273static void re_int_task (void *, int); 274static void re_start (struct ifnet *); 275static void re_start_locked (struct ifnet *); 276static int re_ioctl (struct ifnet *, u_long, caddr_t); 277static void re_init (void *); 278static void re_init_locked (struct rl_softc *); 279static void re_stop (struct rl_softc *); 280static void re_watchdog (struct rl_softc *); 281static int re_suspend (device_t); 282static int re_resume (device_t); 283static int re_shutdown (device_t); 284static int re_ifmedia_upd (struct ifnet *); 285static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 286 287static void re_eeprom_putbyte (struct rl_softc *, int); 288static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 289static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 290static int re_gmii_readreg (device_t, int, int); 291static int re_gmii_writereg (device_t, int, int, int); 292 293static int re_miibus_readreg (device_t, int, int); 294static int re_miibus_writereg (device_t, int, int, int); 295static void re_miibus_statchg (device_t); 296 297static void re_set_jumbo (struct rl_softc *, int); 298static void re_set_rxmode (struct rl_softc *); 299static void re_reset (struct rl_softc *); 300static void re_setwol (struct rl_softc *); 301static void re_clrwol (struct rl_softc *); 302static void re_set_linkspeed (struct rl_softc *); 303 304#ifdef DEV_NETMAP /* see ixgbe.c for details */ 305#include <dev/netmap/if_re_netmap.h> 306#endif /* !DEV_NETMAP */ 307 308#ifdef RE_DIAG 309static int re_diag (struct rl_softc *); 310#endif 311 312static void re_add_sysctls (struct rl_softc *); 313static int re_sysctl_stats (SYSCTL_HANDLER_ARGS); 314static int sysctl_int_range (SYSCTL_HANDLER_ARGS, int, int); 315static int sysctl_hw_re_int_mod (SYSCTL_HANDLER_ARGS); 316 317static device_method_t re_methods[] = { 318 /* Device interface */ 319 DEVMETHOD(device_probe, re_probe), 320 DEVMETHOD(device_attach, re_attach), 321 DEVMETHOD(device_detach, re_detach), 322 DEVMETHOD(device_suspend, re_suspend), 323 DEVMETHOD(device_resume, re_resume), 324 DEVMETHOD(device_shutdown, re_shutdown), 325 326 /* MII interface */ 327 DEVMETHOD(miibus_readreg, re_miibus_readreg), 328 DEVMETHOD(miibus_writereg, re_miibus_writereg), 329 DEVMETHOD(miibus_statchg, re_miibus_statchg), 330 331 DEVMETHOD_END 332}; 333 334static driver_t re_driver = { 335 "re", 336 re_methods, 337 sizeof(struct rl_softc) 338}; 339 340static devclass_t re_devclass; 341 342DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 343DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 344 345#define EE_SET(x) \ 346 CSR_WRITE_1(sc, RL_EECMD, \ 347 CSR_READ_1(sc, RL_EECMD) | x) 348 349#define EE_CLR(x) \ 350 CSR_WRITE_1(sc, RL_EECMD, \ 351 CSR_READ_1(sc, RL_EECMD) & ~x) 352 353/* 354 * Send a read command and address to the EEPROM, check for ACK. 355 */ 356static void 357re_eeprom_putbyte(struct rl_softc *sc, int addr) 358{ 359 int d, i; 360 361 d = addr | (RL_9346_READ << sc->rl_eewidth); 362 363 /* 364 * Feed in each bit and strobe the clock. 365 */ 366 367 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 368 if (d & i) { 369 EE_SET(RL_EE_DATAIN); 370 } else { 371 EE_CLR(RL_EE_DATAIN); 372 } 373 DELAY(100); 374 EE_SET(RL_EE_CLK); 375 DELAY(150); 376 EE_CLR(RL_EE_CLK); 377 DELAY(100); 378 } 379} 380 381/* 382 * Read a word of data stored in the EEPROM at address 'addr.' 383 */ 384static void 385re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 386{ 387 int i; 388 u_int16_t word = 0; 389 390 /* 391 * Send address of word we want to read. 392 */ 393 re_eeprom_putbyte(sc, addr); 394 395 /* 396 * Start reading bits from EEPROM. 397 */ 398 for (i = 0x8000; i; i >>= 1) { 399 EE_SET(RL_EE_CLK); 400 DELAY(100); 401 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 402 word |= i; 403 EE_CLR(RL_EE_CLK); 404 DELAY(100); 405 } 406 407 *dest = word; 408} 409 410/* 411 * Read a sequence of words from the EEPROM. 412 */ 413static void 414re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 415{ 416 int i; 417 u_int16_t word = 0, *ptr; 418 419 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 420 421 DELAY(100); 422 423 for (i = 0; i < cnt; i++) { 424 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 425 re_eeprom_getword(sc, off + i, &word); 426 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 427 ptr = (u_int16_t *)(dest + (i * 2)); 428 *ptr = word; 429 } 430 431 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 432} 433 434static int 435re_gmii_readreg(device_t dev, int phy, int reg) 436{ 437 struct rl_softc *sc; 438 u_int32_t rval; 439 int i; 440 441 sc = device_get_softc(dev); 442 443 /* Let the rgephy driver read the GMEDIASTAT register */ 444 445 if (reg == RL_GMEDIASTAT) { 446 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 447 return (rval); 448 } 449 450 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 451 452 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 453 rval = CSR_READ_4(sc, RL_PHYAR); 454 if (rval & RL_PHYAR_BUSY) 455 break; 456 DELAY(25); 457 } 458 459 if (i == RL_PHY_TIMEOUT) { 460 device_printf(sc->rl_dev, "PHY read failed\n"); 461 return (0); 462 } 463 464 /* 465 * Controller requires a 20us delay to process next MDIO request. 466 */ 467 DELAY(20); 468 469 return (rval & RL_PHYAR_PHYDATA); 470} 471 472static int 473re_gmii_writereg(device_t dev, int phy, int reg, int data) 474{ 475 struct rl_softc *sc; 476 u_int32_t rval; 477 int i; 478 479 sc = device_get_softc(dev); 480 481 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 482 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 483 484 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 485 rval = CSR_READ_4(sc, RL_PHYAR); 486 if (!(rval & RL_PHYAR_BUSY)) 487 break; 488 DELAY(25); 489 } 490 491 if (i == RL_PHY_TIMEOUT) { 492 device_printf(sc->rl_dev, "PHY write failed\n"); 493 return (0); 494 } 495 496 /* 497 * Controller requires a 20us delay to process next MDIO request. 498 */ 499 DELAY(20); 500 501 return (0); 502} 503 504static int 505re_miibus_readreg(device_t dev, int phy, int reg) 506{ 507 struct rl_softc *sc; 508 u_int16_t rval = 0; 509 u_int16_t re8139_reg = 0; 510 511 sc = device_get_softc(dev); 512 513 if (sc->rl_type == RL_8169) { 514 rval = re_gmii_readreg(dev, phy, reg); 515 return (rval); 516 } 517 518 switch (reg) { 519 case MII_BMCR: 520 re8139_reg = RL_BMCR; 521 break; 522 case MII_BMSR: 523 re8139_reg = RL_BMSR; 524 break; 525 case MII_ANAR: 526 re8139_reg = RL_ANAR; 527 break; 528 case MII_ANER: 529 re8139_reg = RL_ANER; 530 break; 531 case MII_ANLPAR: 532 re8139_reg = RL_LPAR; 533 break; 534 case MII_PHYIDR1: 535 case MII_PHYIDR2: 536 return (0); 537 /* 538 * Allow the rlphy driver to read the media status 539 * register. If we have a link partner which does not 540 * support NWAY, this is the register which will tell 541 * us the results of parallel detection. 542 */ 543 case RL_MEDIASTAT: 544 rval = CSR_READ_1(sc, RL_MEDIASTAT); 545 return (rval); 546 default: 547 device_printf(sc->rl_dev, "bad phy register\n"); 548 return (0); 549 } 550 rval = CSR_READ_2(sc, re8139_reg); 551 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 552 /* 8139C+ has different bit layout. */ 553 rval &= ~(BMCR_LOOP | BMCR_ISO); 554 } 555 return (rval); 556} 557 558static int 559re_miibus_writereg(device_t dev, int phy, int reg, int data) 560{ 561 struct rl_softc *sc; 562 u_int16_t re8139_reg = 0; 563 int rval = 0; 564 565 sc = device_get_softc(dev); 566 567 if (sc->rl_type == RL_8169) { 568 rval = re_gmii_writereg(dev, phy, reg, data); 569 return (rval); 570 } 571 572 switch (reg) { 573 case MII_BMCR: 574 re8139_reg = RL_BMCR; 575 if (sc->rl_type == RL_8139CPLUS) { 576 /* 8139C+ has different bit layout. */ 577 data &= ~(BMCR_LOOP | BMCR_ISO); 578 } 579 break; 580 case MII_BMSR: 581 re8139_reg = RL_BMSR; 582 break; 583 case MII_ANAR: 584 re8139_reg = RL_ANAR; 585 break; 586 case MII_ANER: 587 re8139_reg = RL_ANER; 588 break; 589 case MII_ANLPAR: 590 re8139_reg = RL_LPAR; 591 break; 592 case MII_PHYIDR1: 593 case MII_PHYIDR2: 594 return (0); 595 break; 596 default: 597 device_printf(sc->rl_dev, "bad phy register\n"); 598 return (0); 599 } 600 CSR_WRITE_2(sc, re8139_reg, data); 601 return (0); 602} 603 604static void 605re_miibus_statchg(device_t dev) 606{ 607 struct rl_softc *sc; 608 struct ifnet *ifp; 609 struct mii_data *mii; 610 611 sc = device_get_softc(dev); 612 mii = device_get_softc(sc->rl_miibus); 613 ifp = sc->rl_ifp; 614 if (mii == NULL || ifp == NULL || 615 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 616 return; 617 618 sc->rl_flags &= ~RL_FLAG_LINK; 619 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 620 (IFM_ACTIVE | IFM_AVALID)) { 621 switch (IFM_SUBTYPE(mii->mii_media_active)) { 622 case IFM_10_T: 623 case IFM_100_TX: 624 sc->rl_flags |= RL_FLAG_LINK; 625 break; 626 case IFM_1000_T: 627 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 628 break; 629 sc->rl_flags |= RL_FLAG_LINK; 630 break; 631 default: 632 break; 633 } 634 } 635 /* 636 * RealTek controllers does not provide any interface to 637 * Tx/Rx MACs for resolved speed, duplex and flow-control 638 * parameters. 639 */ 640} 641 642/* 643 * Set the RX configuration and 64-bit multicast hash filter. 644 */ 645static void 646re_set_rxmode(struct rl_softc *sc) 647{ 648 struct ifnet *ifp; 649 struct ifmultiaddr *ifma; 650 uint32_t hashes[2] = { 0, 0 }; 651 uint32_t h, rxfilt; 652 653 RL_LOCK_ASSERT(sc); 654 655 ifp = sc->rl_ifp; 656 657 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD; 658 659 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 660 if (ifp->if_flags & IFF_PROMISC) 661 rxfilt |= RL_RXCFG_RX_ALLPHYS; 662 /* 663 * Unlike other hardwares, we have to explicitly set 664 * RL_RXCFG_RX_MULTI to receive multicast frames in 665 * promiscuous mode. 666 */ 667 rxfilt |= RL_RXCFG_RX_MULTI; 668 hashes[0] = hashes[1] = 0xffffffff; 669 goto done; 670 } 671 672 if_maddr_rlock(ifp); 673 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 674 if (ifma->ifma_addr->sa_family != AF_LINK) 675 continue; 676 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 677 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 678 if (h < 32) 679 hashes[0] |= (1 << h); 680 else 681 hashes[1] |= (1 << (h - 32)); 682 } 683 if_maddr_runlock(ifp); 684 685 if (hashes[0] != 0 || hashes[1] != 0) { 686 /* 687 * For some unfathomable reason, RealTek decided to 688 * reverse the order of the multicast hash registers 689 * in the PCI Express parts. This means we have to 690 * write the hash pattern in reverse order for those 691 * devices. 692 */ 693 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) { 694 h = bswap32(hashes[0]); 695 hashes[0] = bswap32(hashes[1]); 696 hashes[1] = h; 697 } 698 rxfilt |= RL_RXCFG_RX_MULTI; 699 } 700 701done: 702 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 703 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 704 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 705} 706 707static void 708re_reset(struct rl_softc *sc) 709{ 710 int i; 711 712 RL_LOCK_ASSERT(sc); 713 714 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 715 716 for (i = 0; i < RL_TIMEOUT; i++) { 717 DELAY(10); 718 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 719 break; 720 } 721 if (i == RL_TIMEOUT) 722 device_printf(sc->rl_dev, "reset never completed!\n"); 723 724 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0) 725 CSR_WRITE_1(sc, 0x82, 1); 726 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169S) 727 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0); 728} 729 730#ifdef RE_DIAG 731 732/* 733 * The following routine is designed to test for a defect on some 734 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 735 * lines connected to the bus, however for a 32-bit only card, they 736 * should be pulled high. The result of this defect is that the 737 * NIC will not work right if you plug it into a 64-bit slot: DMA 738 * operations will be done with 64-bit transfers, which will fail 739 * because the 64-bit data lines aren't connected. 740 * 741 * There's no way to work around this (short of talking a soldering 742 * iron to the board), however we can detect it. The method we use 743 * here is to put the NIC into digital loopback mode, set the receiver 744 * to promiscuous mode, and then try to send a frame. We then compare 745 * the frame data we sent to what was received. If the data matches, 746 * then the NIC is working correctly, otherwise we know the user has 747 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 748 * slot. In the latter case, there's no way the NIC can work correctly, 749 * so we print out a message on the console and abort the device attach. 750 */ 751 752static int 753re_diag(struct rl_softc *sc) 754{ 755 struct ifnet *ifp = sc->rl_ifp; 756 struct mbuf *m0; 757 struct ether_header *eh; 758 struct rl_desc *cur_rx; 759 u_int16_t status; 760 u_int32_t rxstat; 761 int total_len, i, error = 0, phyaddr; 762 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 763 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 764 765 /* Allocate a single mbuf */ 766 MGETHDR(m0, M_NOWAIT, MT_DATA); 767 if (m0 == NULL) 768 return (ENOBUFS); 769 770 RL_LOCK(sc); 771 772 /* 773 * Initialize the NIC in test mode. This sets the chip up 774 * so that it can send and receive frames, but performs the 775 * following special functions: 776 * - Puts receiver in promiscuous mode 777 * - Enables digital loopback mode 778 * - Leaves interrupts turned off 779 */ 780 781 ifp->if_flags |= IFF_PROMISC; 782 sc->rl_testmode = 1; 783 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 784 re_init_locked(sc); 785 sc->rl_flags |= RL_FLAG_LINK; 786 if (sc->rl_type == RL_8169) 787 phyaddr = 1; 788 else 789 phyaddr = 0; 790 791 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 792 for (i = 0; i < RL_TIMEOUT; i++) { 793 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 794 if (!(status & BMCR_RESET)) 795 break; 796 } 797 798 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 799 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 800 801 DELAY(100000); 802 803 /* Put some data in the mbuf */ 804 805 eh = mtod(m0, struct ether_header *); 806 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 807 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 808 eh->ether_type = htons(ETHERTYPE_IP); 809 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 810 811 /* 812 * Queue the packet, start transmission. 813 * Note: IF_HANDOFF() ultimately calls re_start() for us. 814 */ 815 816 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 817 RL_UNLOCK(sc); 818 /* XXX: re_diag must not be called when in ALTQ mode */ 819 IF_HANDOFF(&ifp->if_snd, m0, ifp); 820 RL_LOCK(sc); 821 m0 = NULL; 822 823 /* Wait for it to propagate through the chip */ 824 825 DELAY(100000); 826 for (i = 0; i < RL_TIMEOUT; i++) { 827 status = CSR_READ_2(sc, RL_ISR); 828 CSR_WRITE_2(sc, RL_ISR, status); 829 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 830 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 831 break; 832 DELAY(10); 833 } 834 835 if (i == RL_TIMEOUT) { 836 device_printf(sc->rl_dev, 837 "diagnostic failed, failed to receive packet in" 838 " loopback mode\n"); 839 error = EIO; 840 goto done; 841 } 842 843 /* 844 * The packet should have been dumped into the first 845 * entry in the RX DMA ring. Grab it from there. 846 */ 847 848 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 849 sc->rl_ldata.rl_rx_list_map, 850 BUS_DMASYNC_POSTREAD); 851 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 852 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 853 BUS_DMASYNC_POSTREAD); 854 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 855 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 856 857 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 858 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 859 eh = mtod(m0, struct ether_header *); 860 861 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 862 total_len = RL_RXBYTES(cur_rx); 863 rxstat = le32toh(cur_rx->rl_cmdstat); 864 865 if (total_len != ETHER_MIN_LEN) { 866 device_printf(sc->rl_dev, 867 "diagnostic failed, received short packet\n"); 868 error = EIO; 869 goto done; 870 } 871 872 /* Test that the received packet data matches what we sent. */ 873 874 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 875 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 876 ntohs(eh->ether_type) != ETHERTYPE_IP) { 877 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 878 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 879 dst, ":", src, ":", ETHERTYPE_IP); 880 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 881 eh->ether_dhost, ":", eh->ether_shost, ":", 882 ntohs(eh->ether_type)); 883 device_printf(sc->rl_dev, "You may have a defective 32-bit " 884 "NIC plugged into a 64-bit PCI slot.\n"); 885 device_printf(sc->rl_dev, "Please re-install the NIC in a " 886 "32-bit slot for proper operation.\n"); 887 device_printf(sc->rl_dev, "Read the re(4) man page for more " 888 "details.\n"); 889 error = EIO; 890 } 891 892done: 893 /* Turn interface off, release resources */ 894 895 sc->rl_testmode = 0; 896 sc->rl_flags &= ~RL_FLAG_LINK; 897 ifp->if_flags &= ~IFF_PROMISC; 898 re_stop(sc); 899 if (m0 != NULL) 900 m_freem(m0); 901 902 RL_UNLOCK(sc); 903 904 return (error); 905} 906 907#endif 908 909/* 910 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 911 * IDs against our list and return a device name if we find a match. 912 */ 913static int 914re_probe(device_t dev) 915{ 916 const struct rl_type *t; 917 uint16_t devid, vendor; 918 uint16_t revid, sdevid; 919 int i; 920 921 vendor = pci_get_vendor(dev); 922 devid = pci_get_device(dev); 923 revid = pci_get_revid(dev); 924 sdevid = pci_get_subdevice(dev); 925 926 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 927 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 928 /* 929 * Only attach to rev. 3 of the Linksys EG1032 adapter. 930 * Rev. 2 is supported by sk(4). 931 */ 932 return (ENXIO); 933 } 934 } 935 936 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 937 if (revid != 0x20) { 938 /* 8139, let rl(4) take care of this device. */ 939 return (ENXIO); 940 } 941 } 942 943 t = re_devs; 944 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 945 if (vendor == t->rl_vid && devid == t->rl_did) { 946 device_set_desc(dev, t->rl_name); 947 return (BUS_PROBE_DEFAULT); 948 } 949 } 950 951 return (ENXIO); 952} 953 954/* 955 * Map a single buffer address. 956 */ 957 958static void 959re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 960{ 961 bus_addr_t *addr; 962 963 if (error) 964 return; 965 966 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 967 addr = arg; 968 *addr = segs->ds_addr; 969} 970 971static int 972re_allocmem(device_t dev, struct rl_softc *sc) 973{ 974 bus_addr_t lowaddr; 975 bus_size_t rx_list_size, tx_list_size; 976 int error; 977 int i; 978 979 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 980 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 981 982 /* 983 * Allocate the parent bus DMA tag appropriate for PCI. 984 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 985 * register should be set. However some RealTek chips are known 986 * to be buggy on DAC handling, therefore disable DAC by limiting 987 * DMA address space to 32bit. PCIe variants of RealTek chips 988 * may not have the limitation. 989 */ 990 lowaddr = BUS_SPACE_MAXADDR; 991 if ((sc->rl_flags & RL_FLAG_PCIE) == 0) 992 lowaddr = BUS_SPACE_MAXADDR_32BIT; 993 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 994 lowaddr, BUS_SPACE_MAXADDR, NULL, NULL, 995 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 996 NULL, NULL, &sc->rl_parent_tag); 997 if (error) { 998 device_printf(dev, "could not allocate parent DMA tag\n"); 999 return (error); 1000 } 1001 1002 /* 1003 * Allocate map for TX mbufs. 1004 */ 1005 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 1006 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1007 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 1008 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 1009 if (error) { 1010 device_printf(dev, "could not allocate TX DMA tag\n"); 1011 return (error); 1012 } 1013 1014 /* 1015 * Allocate map for RX mbufs. 1016 */ 1017 1018 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1019 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 1020 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1021 MJUM9BYTES, 1, MJUM9BYTES, 0, NULL, NULL, 1022 &sc->rl_ldata.rl_jrx_mtag); 1023 if (error) { 1024 device_printf(dev, 1025 "could not allocate jumbo RX DMA tag\n"); 1026 return (error); 1027 } 1028 } 1029 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 1030 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1031 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 1032 if (error) { 1033 device_printf(dev, "could not allocate RX DMA tag\n"); 1034 return (error); 1035 } 1036 1037 /* 1038 * Allocate map for TX descriptor list. 1039 */ 1040 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1041 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1042 NULL, tx_list_size, 1, tx_list_size, 0, 1043 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1044 if (error) { 1045 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1046 return (error); 1047 } 1048 1049 /* Allocate DMA'able memory for the TX ring */ 1050 1051 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1052 (void **)&sc->rl_ldata.rl_tx_list, 1053 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1054 &sc->rl_ldata.rl_tx_list_map); 1055 if (error) { 1056 device_printf(dev, "could not allocate TX DMA ring\n"); 1057 return (error); 1058 } 1059 1060 /* Load the map for the TX ring. */ 1061 1062 sc->rl_ldata.rl_tx_list_addr = 0; 1063 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1064 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1065 tx_list_size, re_dma_map_addr, 1066 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1067 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1068 device_printf(dev, "could not load TX DMA ring\n"); 1069 return (ENOMEM); 1070 } 1071 1072 /* Create DMA maps for TX buffers */ 1073 1074 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1075 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1076 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1077 if (error) { 1078 device_printf(dev, "could not create DMA map for TX\n"); 1079 return (error); 1080 } 1081 } 1082 1083 /* 1084 * Allocate map for RX descriptor list. 1085 */ 1086 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1087 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1088 NULL, rx_list_size, 1, rx_list_size, 0, 1089 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1090 if (error) { 1091 device_printf(dev, "could not create RX DMA ring tag\n"); 1092 return (error); 1093 } 1094 1095 /* Allocate DMA'able memory for the RX ring */ 1096 1097 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1098 (void **)&sc->rl_ldata.rl_rx_list, 1099 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1100 &sc->rl_ldata.rl_rx_list_map); 1101 if (error) { 1102 device_printf(dev, "could not allocate RX DMA ring\n"); 1103 return (error); 1104 } 1105 1106 /* Load the map for the RX ring. */ 1107 1108 sc->rl_ldata.rl_rx_list_addr = 0; 1109 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1110 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1111 rx_list_size, re_dma_map_addr, 1112 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1113 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1114 device_printf(dev, "could not load RX DMA ring\n"); 1115 return (ENOMEM); 1116 } 1117 1118 /* Create DMA maps for RX buffers */ 1119 1120 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1121 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1122 &sc->rl_ldata.rl_jrx_sparemap); 1123 if (error) { 1124 device_printf(dev, 1125 "could not create spare DMA map for jumbo RX\n"); 1126 return (error); 1127 } 1128 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1129 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1130 &sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1131 if (error) { 1132 device_printf(dev, 1133 "could not create DMA map for jumbo RX\n"); 1134 return (error); 1135 } 1136 } 1137 } 1138 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1139 &sc->rl_ldata.rl_rx_sparemap); 1140 if (error) { 1141 device_printf(dev, "could not create spare DMA map for RX\n"); 1142 return (error); 1143 } 1144 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1145 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1146 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1147 if (error) { 1148 device_printf(dev, "could not create DMA map for RX\n"); 1149 return (error); 1150 } 1151 } 1152 1153 /* Create DMA map for statistics. */ 1154 error = bus_dma_tag_create(sc->rl_parent_tag, RL_DUMP_ALIGN, 0, 1155 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1156 sizeof(struct rl_stats), 1, sizeof(struct rl_stats), 0, NULL, NULL, 1157 &sc->rl_ldata.rl_stag); 1158 if (error) { 1159 device_printf(dev, "could not create statistics DMA tag\n"); 1160 return (error); 1161 } 1162 /* Allocate DMA'able memory for statistics. */ 1163 error = bus_dmamem_alloc(sc->rl_ldata.rl_stag, 1164 (void **)&sc->rl_ldata.rl_stats, 1165 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1166 &sc->rl_ldata.rl_smap); 1167 if (error) { 1168 device_printf(dev, 1169 "could not allocate statistics DMA memory\n"); 1170 return (error); 1171 } 1172 /* Load the map for statistics. */ 1173 sc->rl_ldata.rl_stats_addr = 0; 1174 error = bus_dmamap_load(sc->rl_ldata.rl_stag, sc->rl_ldata.rl_smap, 1175 sc->rl_ldata.rl_stats, sizeof(struct rl_stats), re_dma_map_addr, 1176 &sc->rl_ldata.rl_stats_addr, BUS_DMA_NOWAIT); 1177 if (error != 0 || sc->rl_ldata.rl_stats_addr == 0) { 1178 device_printf(dev, "could not load statistics DMA memory\n"); 1179 return (ENOMEM); 1180 } 1181 1182 return (0); 1183} 1184 1185/* 1186 * Attach the interface. Allocate softc structures, do ifmedia 1187 * setup and ethernet/BPF attach. 1188 */ 1189static int 1190re_attach(device_t dev) 1191{ 1192 u_char eaddr[ETHER_ADDR_LEN]; 1193 u_int16_t as[ETHER_ADDR_LEN / 2]; 1194 struct rl_softc *sc; 1195 struct ifnet *ifp; 1196 const struct rl_hwrev *hw_rev; 1197 u_int32_t cap, ctl; 1198 int hwrev; 1199 u_int16_t devid, re_did = 0; 1200 int error = 0, i, phy, rid; 1201 int msic, msixc, reg; 1202 uint8_t cfg; 1203 1204 sc = device_get_softc(dev); 1205 sc->rl_dev = dev; 1206 1207 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1208 MTX_DEF); 1209 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1210 1211 /* 1212 * Map control/status registers. 1213 */ 1214 pci_enable_busmaster(dev); 1215 1216 devid = pci_get_device(dev); 1217 /* 1218 * Prefer memory space register mapping over IO space. 1219 * Because RTL8169SC does not seem to work when memory mapping 1220 * is used always activate io mapping. 1221 */ 1222 if (devid == RT_DEVICEID_8169SC) 1223 prefer_iomap = 1; 1224 if (prefer_iomap == 0) { 1225 sc->rl_res_id = PCIR_BAR(1); 1226 sc->rl_res_type = SYS_RES_MEMORY; 1227 /* RTL8168/8101E seems to use different BARs. */ 1228 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1229 sc->rl_res_id = PCIR_BAR(2); 1230 } else { 1231 sc->rl_res_id = PCIR_BAR(0); 1232 sc->rl_res_type = SYS_RES_IOPORT; 1233 } 1234 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1235 &sc->rl_res_id, RF_ACTIVE); 1236 if (sc->rl_res == NULL && prefer_iomap == 0) { 1237 sc->rl_res_id = PCIR_BAR(0); 1238 sc->rl_res_type = SYS_RES_IOPORT; 1239 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1240 &sc->rl_res_id, RF_ACTIVE); 1241 } 1242 if (sc->rl_res == NULL) { 1243 device_printf(dev, "couldn't map ports/memory\n"); 1244 error = ENXIO; 1245 goto fail; 1246 } 1247 1248 sc->rl_btag = rman_get_bustag(sc->rl_res); 1249 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1250 1251 msic = pci_msi_count(dev); 1252 msixc = pci_msix_count(dev); 1253 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 1254 sc->rl_flags |= RL_FLAG_PCIE; 1255 sc->rl_expcap = reg; 1256 } 1257 if (bootverbose) { 1258 device_printf(dev, "MSI count : %d\n", msic); 1259 device_printf(dev, "MSI-X count : %d\n", msixc); 1260 } 1261 if (msix_disable > 0) 1262 msixc = 0; 1263 if (msi_disable > 0) 1264 msic = 0; 1265 /* Prefer MSI-X to MSI. */ 1266 if (msixc > 0) { 1267 msixc = 1; 1268 rid = PCIR_BAR(4); 1269 sc->rl_res_pba = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1270 &rid, RF_ACTIVE); 1271 if (sc->rl_res_pba == NULL) { 1272 device_printf(sc->rl_dev, 1273 "could not allocate MSI-X PBA resource\n"); 1274 } 1275 if (sc->rl_res_pba != NULL && 1276 pci_alloc_msix(dev, &msixc) == 0) { 1277 if (msixc == 1) { 1278 device_printf(dev, "Using %d MSI-X message\n", 1279 msixc); 1280 sc->rl_flags |= RL_FLAG_MSIX; 1281 } else 1282 pci_release_msi(dev); 1283 } 1284 if ((sc->rl_flags & RL_FLAG_MSIX) == 0) { 1285 if (sc->rl_res_pba != NULL) 1286 bus_release_resource(dev, SYS_RES_MEMORY, rid, 1287 sc->rl_res_pba); 1288 sc->rl_res_pba = NULL; 1289 msixc = 0; 1290 } 1291 } 1292 /* Prefer MSI to INTx. */ 1293 if (msixc == 0 && msic > 0) { 1294 msic = 1; 1295 if (pci_alloc_msi(dev, &msic) == 0) { 1296 if (msic == RL_MSI_MESSAGES) { 1297 device_printf(dev, "Using %d MSI message\n", 1298 msic); 1299 sc->rl_flags |= RL_FLAG_MSI; 1300 /* Explicitly set MSI enable bit. */ 1301 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1302 cfg = CSR_READ_1(sc, RL_CFG2); 1303 cfg |= RL_CFG2_MSI; 1304 CSR_WRITE_1(sc, RL_CFG2, cfg); 1305 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1306 } else 1307 pci_release_msi(dev); 1308 } 1309 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1310 msic = 0; 1311 } 1312 1313 /* Allocate interrupt */ 1314 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) { 1315 rid = 0; 1316 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1317 RF_SHAREABLE | RF_ACTIVE); 1318 if (sc->rl_irq[0] == NULL) { 1319 device_printf(dev, "couldn't allocate IRQ resources\n"); 1320 error = ENXIO; 1321 goto fail; 1322 } 1323 } else { 1324 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1325 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1326 SYS_RES_IRQ, &rid, RF_ACTIVE); 1327 if (sc->rl_irq[i] == NULL) { 1328 device_printf(dev, 1329 "couldn't allocate IRQ resources for " 1330 "message %d\n", rid); 1331 error = ENXIO; 1332 goto fail; 1333 } 1334 } 1335 } 1336 1337 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1338 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1339 cfg = CSR_READ_1(sc, RL_CFG2); 1340 if ((cfg & RL_CFG2_MSI) != 0) { 1341 device_printf(dev, "turning off MSI enable bit.\n"); 1342 cfg &= ~RL_CFG2_MSI; 1343 CSR_WRITE_1(sc, RL_CFG2, cfg); 1344 } 1345 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1346 } 1347 1348 /* Disable ASPM L0S/L1. */ 1349 if (sc->rl_expcap != 0) { 1350 cap = pci_read_config(dev, sc->rl_expcap + 1351 PCIER_LINK_CAP, 2); 1352 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 1353 ctl = pci_read_config(dev, sc->rl_expcap + 1354 PCIER_LINK_CTL, 2); 1355 if ((ctl & PCIEM_LINK_CTL_ASPMC) != 0) { 1356 ctl &= ~PCIEM_LINK_CTL_ASPMC; 1357 pci_write_config(dev, sc->rl_expcap + 1358 PCIER_LINK_CTL, ctl, 2); 1359 device_printf(dev, "ASPM disabled\n"); 1360 } 1361 } else 1362 device_printf(dev, "no ASPM capability\n"); 1363 } 1364 1365 hw_rev = re_hwrevs; 1366 hwrev = CSR_READ_4(sc, RL_TXCFG); 1367 switch (hwrev & 0x70000000) { 1368 case 0x00000000: 1369 case 0x10000000: 1370 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000); 1371 hwrev &= (RL_TXCFG_HWREV | 0x80000000); 1372 break; 1373 default: 1374 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1375 sc->rl_macrev = hwrev & 0x00700000; 1376 hwrev &= RL_TXCFG_HWREV; 1377 break; 1378 } 1379 device_printf(dev, "MAC rev. 0x%08x\n", sc->rl_macrev); 1380 while (hw_rev->rl_desc != NULL) { 1381 if (hw_rev->rl_rev == hwrev) { 1382 sc->rl_type = hw_rev->rl_type; 1383 sc->rl_hwrev = hw_rev; 1384 break; 1385 } 1386 hw_rev++; 1387 } 1388 if (hw_rev->rl_desc == NULL) { 1389 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1390 error = ENXIO; 1391 goto fail; 1392 } 1393 1394 switch (hw_rev->rl_rev) { 1395 case RL_HWREV_8139CPLUS: 1396 sc->rl_flags |= RL_FLAG_FASTETHER | RL_FLAG_AUTOPAD; 1397 break; 1398 case RL_HWREV_8100E: 1399 case RL_HWREV_8101E: 1400 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_FASTETHER; 1401 break; 1402 case RL_HWREV_8102E: 1403 case RL_HWREV_8102EL: 1404 case RL_HWREV_8102EL_SPIN1: 1405 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1406 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1407 RL_FLAG_AUTOPAD; 1408 break; 1409 case RL_HWREV_8103E: 1410 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1411 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1412 RL_FLAG_AUTOPAD | RL_FLAG_MACSLEEP; 1413 break; 1414 case RL_HWREV_8401E: 1415 case RL_HWREV_8105E: 1416 case RL_HWREV_8105E_SPIN1: 1417 case RL_HWREV_8106E: 1418 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1419 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1420 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD; 1421 break; 1422 case RL_HWREV_8402: 1423 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1424 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1425 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | 1426 RL_FLAG_CMDSTOP_WAIT_TXQ; 1427 break; 1428 case RL_HWREV_8168B_SPIN1: 1429 case RL_HWREV_8168B_SPIN2: 1430 sc->rl_flags |= RL_FLAG_WOLRXENB; 1431 /* FALLTHROUGH */ 1432 case RL_HWREV_8168B_SPIN3: 1433 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT; 1434 break; 1435 case RL_HWREV_8168C_SPIN2: 1436 sc->rl_flags |= RL_FLAG_MACSLEEP; 1437 /* FALLTHROUGH */ 1438 case RL_HWREV_8168C: 1439 if (sc->rl_macrev == 0x00200000) 1440 sc->rl_flags |= RL_FLAG_MACSLEEP; 1441 /* FALLTHROUGH */ 1442 case RL_HWREV_8168CP: 1443 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1444 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1445 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK; 1446 break; 1447 case RL_HWREV_8168D: 1448 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1449 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1450 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1451 RL_FLAG_WOL_MANLINK; 1452 break; 1453 case RL_HWREV_8168DP: 1454 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1455 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_AUTOPAD | 1456 RL_FLAG_JUMBOV2 | RL_FLAG_WAIT_TXPOLL | RL_FLAG_WOL_MANLINK; 1457 break; 1458 case RL_HWREV_8168E: 1459 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1460 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1461 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1462 RL_FLAG_WOL_MANLINK; 1463 break; 1464 case RL_HWREV_8168E_VL: 1465 case RL_HWREV_8168EP: 1466 case RL_HWREV_8168F: 1467 case RL_HWREV_8168G: 1468 case RL_HWREV_8411: 1469 case RL_HWREV_8411B: 1470 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1471 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1472 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1473 RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK; 1474 break; 1475 case RL_HWREV_8168GU: 1476 if (pci_get_device(dev) == RT_DEVICEID_8101E) { 1477 /* RTL8106EUS */ 1478 sc->rl_flags |= RL_FLAG_FASTETHER; 1479 } else 1480 sc->rl_flags |= RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK; 1481 1482 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1483 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1484 RL_FLAG_AUTOPAD | RL_FLAG_CMDSTOP_WAIT_TXQ; 1485 break; 1486 case RL_HWREV_8169_8110SB: 1487 case RL_HWREV_8169_8110SBL: 1488 case RL_HWREV_8169_8110SC: 1489 case RL_HWREV_8169_8110SCE: 1490 sc->rl_flags |= RL_FLAG_PHYWAKE; 1491 /* FALLTHROUGH */ 1492 case RL_HWREV_8169: 1493 case RL_HWREV_8169S: 1494 case RL_HWREV_8110S: 1495 sc->rl_flags |= RL_FLAG_MACRESET; 1496 break; 1497 default: 1498 break; 1499 } 1500 1501 if (sc->rl_hwrev->rl_rev == RL_HWREV_8139CPLUS) { 1502 sc->rl_cfg0 = RL_8139_CFG0; 1503 sc->rl_cfg1 = RL_8139_CFG1; 1504 sc->rl_cfg2 = 0; 1505 sc->rl_cfg3 = RL_8139_CFG3; 1506 sc->rl_cfg4 = RL_8139_CFG4; 1507 sc->rl_cfg5 = RL_8139_CFG5; 1508 } else { 1509 sc->rl_cfg0 = RL_CFG0; 1510 sc->rl_cfg1 = RL_CFG1; 1511 sc->rl_cfg2 = RL_CFG2; 1512 sc->rl_cfg3 = RL_CFG3; 1513 sc->rl_cfg4 = RL_CFG4; 1514 sc->rl_cfg5 = RL_CFG5; 1515 } 1516 1517 /* Reset the adapter. */ 1518 RL_LOCK(sc); 1519 re_reset(sc); 1520 RL_UNLOCK(sc); 1521 1522 /* Enable PME. */ 1523 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1524 cfg = CSR_READ_1(sc, sc->rl_cfg1); 1525 cfg |= RL_CFG1_PME; 1526 CSR_WRITE_1(sc, sc->rl_cfg1, cfg); 1527 cfg = CSR_READ_1(sc, sc->rl_cfg5); 1528 cfg &= RL_CFG5_PME_STS; 1529 CSR_WRITE_1(sc, sc->rl_cfg5, cfg); 1530 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1531 1532 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1533 /* 1534 * XXX Should have a better way to extract station 1535 * address from EEPROM. 1536 */ 1537 for (i = 0; i < ETHER_ADDR_LEN; i++) 1538 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1539 } else { 1540 sc->rl_eewidth = RL_9356_ADDR_LEN; 1541 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1542 if (re_did != 0x8129) 1543 sc->rl_eewidth = RL_9346_ADDR_LEN; 1544 1545 /* 1546 * Get station address from the EEPROM. 1547 */ 1548 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1549 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1550 as[i] = le16toh(as[i]); 1551 bcopy(as, eaddr, ETHER_ADDR_LEN); 1552 } 1553 1554 if (sc->rl_type == RL_8169) { 1555 /* Set RX length mask and number of descriptors. */ 1556 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1557 sc->rl_txstart = RL_GTXSTART; 1558 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1559 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1560 } else { 1561 /* Set RX length mask and number of descriptors. */ 1562 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1563 sc->rl_txstart = RL_TXSTART; 1564 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1565 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1566 } 1567 1568 error = re_allocmem(dev, sc); 1569 if (error) 1570 goto fail; 1571 re_add_sysctls(sc); 1572 1573 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1574 if (ifp == NULL) { 1575 device_printf(dev, "can not if_alloc()\n"); 1576 error = ENOSPC; 1577 goto fail; 1578 } 1579 1580 /* Take controller out of deep sleep mode. */ 1581 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 1582 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 1583 CSR_WRITE_1(sc, RL_GPIO, 1584 CSR_READ_1(sc, RL_GPIO) | 0x01); 1585 else 1586 CSR_WRITE_1(sc, RL_GPIO, 1587 CSR_READ_1(sc, RL_GPIO) & ~0x01); 1588 } 1589 1590 /* Take PHY out of power down mode. */ 1591 if ((sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) { 1592 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80); 1593 if (hw_rev->rl_rev == RL_HWREV_8401E) 1594 CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08); 1595 } 1596 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1597 re_gmii_writereg(dev, 1, 0x1f, 0); 1598 re_gmii_writereg(dev, 1, 0x0e, 0); 1599 } 1600 1601 ifp->if_softc = sc; 1602 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1603 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1604 ifp->if_ioctl = re_ioctl; 1605 ifp->if_start = re_start; 1606 /* 1607 * RTL8168/8111C generates wrong IP checksummed frame if the 1608 * packet has IP options so disable TX IP checksum offloading. 1609 */ 1610 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168C || 1611 sc->rl_hwrev->rl_rev == RL_HWREV_8168C_SPIN2 || 1612 sc->rl_hwrev->rl_rev == RL_HWREV_8168CP) 1613 ifp->if_hwassist = CSUM_TCP | CSUM_UDP; 1614 else 1615 ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP; 1616 ifp->if_hwassist |= CSUM_TSO; 1617 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 1618 ifp->if_capenable = ifp->if_capabilities; 1619 ifp->if_init = re_init; 1620 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1621 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1622 IFQ_SET_READY(&ifp->if_snd); 1623 1624 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1625 1626#define RE_PHYAD_INTERNAL 0 1627 1628 /* Do MII setup. */ 1629 phy = RE_PHYAD_INTERNAL; 1630 if (sc->rl_type == RL_8169) 1631 phy = 1; 1632 error = mii_attach(dev, &sc->rl_miibus, ifp, re_ifmedia_upd, 1633 re_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, MIIF_DOPAUSE); 1634 if (error != 0) { 1635 device_printf(dev, "attaching PHYs failed\n"); 1636 goto fail; 1637 } 1638 1639 /* 1640 * Call MI attach routine. 1641 */ 1642 ether_ifattach(ifp, eaddr); 1643 1644 /* VLAN capability setup */ 1645 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1646 if (ifp->if_capabilities & IFCAP_HWCSUM) 1647 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1648 /* Enable WOL if PM is supported. */ 1649 if (pci_find_cap(sc->rl_dev, PCIY_PMG, ®) == 0) 1650 ifp->if_capabilities |= IFCAP_WOL; 1651 ifp->if_capenable = ifp->if_capabilities; 1652 ifp->if_capenable &= ~(IFCAP_WOL_UCAST | IFCAP_WOL_MCAST); 1653 /* 1654 * Don't enable TSO by default. It is known to generate 1655 * corrupted TCP segments(bad TCP options) under certain 1656 * circumstances. 1657 */ 1658 ifp->if_hwassist &= ~CSUM_TSO; 1659 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 1660#ifdef DEVICE_POLLING 1661 ifp->if_capabilities |= IFCAP_POLLING; 1662#endif 1663 /* 1664 * Tell the upper layer(s) we support long frames. 1665 * Must appear after the call to ether_ifattach() because 1666 * ether_ifattach() sets ifi_hdrlen to the default value. 1667 */ 1668 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1669 1670#ifdef DEV_NETMAP 1671 re_netmap_attach(sc); 1672#endif /* DEV_NETMAP */ 1673#ifdef RE_DIAG 1674 /* 1675 * Perform hardware diagnostic on the original RTL8169. 1676 * Some 32-bit cards were incorrectly wired and would 1677 * malfunction if plugged into a 64-bit slot. 1678 */ 1679 1680 if (hwrev == RL_HWREV_8169) { 1681 error = re_diag(sc); 1682 if (error) { 1683 device_printf(dev, 1684 "attach aborted due to hardware diag failure\n"); 1685 ether_ifdetach(ifp); 1686 goto fail; 1687 } 1688 } 1689#endif 1690 1691#ifdef RE_TX_MODERATION 1692 intr_filter = 1; 1693#endif 1694 /* Hook interrupt last to avoid having to lock softc */ 1695 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 1696 intr_filter == 0) { 1697 error = bus_setup_intr(dev, sc->rl_irq[0], 1698 INTR_TYPE_NET | INTR_MPSAFE, NULL, re_intr_msi, sc, 1699 &sc->rl_intrhand[0]); 1700 } else { 1701 error = bus_setup_intr(dev, sc->rl_irq[0], 1702 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1703 &sc->rl_intrhand[0]); 1704 } 1705 if (error) { 1706 device_printf(dev, "couldn't set up irq\n"); 1707 ether_ifdetach(ifp); 1708 } 1709 1710fail: 1711 1712 if (error) 1713 re_detach(dev); 1714 1715 return (error); 1716} 1717 1718/* 1719 * Shutdown hardware and free up resources. This can be called any 1720 * time after the mutex has been initialized. It is called in both 1721 * the error case in attach and the normal detach case so it needs 1722 * to be careful about only freeing resources that have actually been 1723 * allocated. 1724 */ 1725static int 1726re_detach(device_t dev) 1727{ 1728 struct rl_softc *sc; 1729 struct ifnet *ifp; 1730 int i, rid; 1731 1732 sc = device_get_softc(dev); 1733 ifp = sc->rl_ifp; 1734 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1735 1736 /* These should only be active if attach succeeded */ 1737 if (device_is_attached(dev)) { 1738#ifdef DEVICE_POLLING 1739 if (ifp->if_capenable & IFCAP_POLLING) 1740 ether_poll_deregister(ifp); 1741#endif 1742 RL_LOCK(sc); 1743#if 0 1744 sc->suspended = 1; 1745#endif 1746 re_stop(sc); 1747 RL_UNLOCK(sc); 1748 callout_drain(&sc->rl_stat_callout); 1749 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1750 /* 1751 * Force off the IFF_UP flag here, in case someone 1752 * still had a BPF descriptor attached to this 1753 * interface. If they do, ether_ifdetach() will cause 1754 * the BPF code to try and clear the promisc mode 1755 * flag, which will bubble down to re_ioctl(), 1756 * which will try to call re_init() again. This will 1757 * turn the NIC back on and restart the MII ticker, 1758 * which will panic the system when the kernel tries 1759 * to invoke the re_tick() function that isn't there 1760 * anymore. 1761 */ 1762 ifp->if_flags &= ~IFF_UP; 1763 ether_ifdetach(ifp); 1764 } 1765 if (sc->rl_miibus) 1766 device_delete_child(dev, sc->rl_miibus); 1767 bus_generic_detach(dev); 1768 1769 /* 1770 * The rest is resource deallocation, so we should already be 1771 * stopped here. 1772 */ 1773 1774 if (sc->rl_intrhand[0] != NULL) { 1775 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]); 1776 sc->rl_intrhand[0] = NULL; 1777 } 1778 if (ifp != NULL) { 1779#ifdef DEV_NETMAP 1780 netmap_detach(ifp); 1781#endif /* DEV_NETMAP */ 1782 if_free(ifp); 1783 } 1784 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 1785 rid = 0; 1786 else 1787 rid = 1; 1788 if (sc->rl_irq[0] != NULL) { 1789 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->rl_irq[0]); 1790 sc->rl_irq[0] = NULL; 1791 } 1792 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0) 1793 pci_release_msi(dev); 1794 if (sc->rl_res_pba) { 1795 rid = PCIR_BAR(4); 1796 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->rl_res_pba); 1797 } 1798 if (sc->rl_res) 1799 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1800 sc->rl_res); 1801 1802 /* Unload and free the RX DMA ring memory and map */ 1803 1804 if (sc->rl_ldata.rl_rx_list_tag) { 1805 if (sc->rl_ldata.rl_rx_list_map) 1806 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1807 sc->rl_ldata.rl_rx_list_map); 1808 if (sc->rl_ldata.rl_rx_list_map && sc->rl_ldata.rl_rx_list) 1809 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1810 sc->rl_ldata.rl_rx_list, 1811 sc->rl_ldata.rl_rx_list_map); 1812 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1813 } 1814 1815 /* Unload and free the TX DMA ring memory and map */ 1816 1817 if (sc->rl_ldata.rl_tx_list_tag) { 1818 if (sc->rl_ldata.rl_tx_list_map) 1819 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1820 sc->rl_ldata.rl_tx_list_map); 1821 if (sc->rl_ldata.rl_tx_list_map && sc->rl_ldata.rl_tx_list) 1822 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1823 sc->rl_ldata.rl_tx_list, 1824 sc->rl_ldata.rl_tx_list_map); 1825 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1826 } 1827 1828 /* Destroy all the RX and TX buffer maps */ 1829 1830 if (sc->rl_ldata.rl_tx_mtag) { 1831 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1832 if (sc->rl_ldata.rl_tx_desc[i].tx_dmamap) 1833 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1834 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1835 } 1836 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1837 } 1838 if (sc->rl_ldata.rl_rx_mtag) { 1839 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1840 if (sc->rl_ldata.rl_rx_desc[i].rx_dmamap) 1841 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1842 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1843 } 1844 if (sc->rl_ldata.rl_rx_sparemap) 1845 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1846 sc->rl_ldata.rl_rx_sparemap); 1847 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1848 } 1849 if (sc->rl_ldata.rl_jrx_mtag) { 1850 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1851 if (sc->rl_ldata.rl_jrx_desc[i].rx_dmamap) 1852 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1853 sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1854 } 1855 if (sc->rl_ldata.rl_jrx_sparemap) 1856 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1857 sc->rl_ldata.rl_jrx_sparemap); 1858 bus_dma_tag_destroy(sc->rl_ldata.rl_jrx_mtag); 1859 } 1860 /* Unload and free the stats buffer and map */ 1861 1862 if (sc->rl_ldata.rl_stag) { 1863 if (sc->rl_ldata.rl_smap) 1864 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1865 sc->rl_ldata.rl_smap); 1866 if (sc->rl_ldata.rl_smap && sc->rl_ldata.rl_stats) 1867 bus_dmamem_free(sc->rl_ldata.rl_stag, 1868 sc->rl_ldata.rl_stats, sc->rl_ldata.rl_smap); 1869 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1870 } 1871 1872 if (sc->rl_parent_tag) 1873 bus_dma_tag_destroy(sc->rl_parent_tag); 1874 1875 mtx_destroy(&sc->rl_mtx); 1876 1877 return (0); 1878} 1879 1880static __inline void 1881re_discard_rxbuf(struct rl_softc *sc, int idx) 1882{ 1883 struct rl_desc *desc; 1884 struct rl_rxdesc *rxd; 1885 uint32_t cmdstat; 1886 1887 if (sc->rl_ifp->if_mtu > RL_MTU && 1888 (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 1889 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 1890 else 1891 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1892 desc = &sc->rl_ldata.rl_rx_list[idx]; 1893 desc->rl_vlanctl = 0; 1894 cmdstat = rxd->rx_size; 1895 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1896 cmdstat |= RL_RDESC_CMD_EOR; 1897 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1898} 1899 1900static int 1901re_newbuf(struct rl_softc *sc, int idx) 1902{ 1903 struct mbuf *m; 1904 struct rl_rxdesc *rxd; 1905 bus_dma_segment_t segs[1]; 1906 bus_dmamap_t map; 1907 struct rl_desc *desc; 1908 uint32_t cmdstat; 1909 int error, nsegs; 1910 1911 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1912 if (m == NULL) 1913 return (ENOBUFS); 1914 1915 m->m_len = m->m_pkthdr.len = MCLBYTES; 1916#ifdef RE_FIXUP_RX 1917 /* 1918 * This is part of an evil trick to deal with non-x86 platforms. 1919 * The RealTek chip requires RX buffers to be aligned on 64-bit 1920 * boundaries, but that will hose non-x86 machines. To get around 1921 * this, we leave some empty space at the start of each buffer 1922 * and for non-x86 hosts, we copy the buffer back six bytes 1923 * to achieve word alignment. This is slightly more efficient 1924 * than allocating a new buffer, copying the contents, and 1925 * discarding the old buffer. 1926 */ 1927 m_adj(m, RE_ETHER_ALIGN); 1928#endif 1929 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1930 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1931 if (error != 0) { 1932 m_freem(m); 1933 return (ENOBUFS); 1934 } 1935 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1936 1937 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1938 if (rxd->rx_m != NULL) { 1939 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1940 BUS_DMASYNC_POSTREAD); 1941 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1942 } 1943 1944 rxd->rx_m = m; 1945 map = rxd->rx_dmamap; 1946 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1947 rxd->rx_size = segs[0].ds_len; 1948 sc->rl_ldata.rl_rx_sparemap = map; 1949 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1950 BUS_DMASYNC_PREREAD); 1951 1952 desc = &sc->rl_ldata.rl_rx_list[idx]; 1953 desc->rl_vlanctl = 0; 1954 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1955 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1956 cmdstat = segs[0].ds_len; 1957 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1958 cmdstat |= RL_RDESC_CMD_EOR; 1959 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1960 1961 return (0); 1962} 1963 1964static int 1965re_jumbo_newbuf(struct rl_softc *sc, int idx) 1966{ 1967 struct mbuf *m; 1968 struct rl_rxdesc *rxd; 1969 bus_dma_segment_t segs[1]; 1970 bus_dmamap_t map; 1971 struct rl_desc *desc; 1972 uint32_t cmdstat; 1973 int error, nsegs; 1974 1975 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1976 if (m == NULL) 1977 return (ENOBUFS); 1978 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1979#ifdef RE_FIXUP_RX 1980 m_adj(m, RE_ETHER_ALIGN); 1981#endif 1982 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_jrx_mtag, 1983 sc->rl_ldata.rl_jrx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1984 if (error != 0) { 1985 m_freem(m); 1986 return (ENOBUFS); 1987 } 1988 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1989 1990 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 1991 if (rxd->rx_m != NULL) { 1992 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 1993 BUS_DMASYNC_POSTREAD); 1994 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap); 1995 } 1996 1997 rxd->rx_m = m; 1998 map = rxd->rx_dmamap; 1999 rxd->rx_dmamap = sc->rl_ldata.rl_jrx_sparemap; 2000 rxd->rx_size = segs[0].ds_len; 2001 sc->rl_ldata.rl_jrx_sparemap = map; 2002 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 2003 BUS_DMASYNC_PREREAD); 2004 2005 desc = &sc->rl_ldata.rl_rx_list[idx]; 2006 desc->rl_vlanctl = 0; 2007 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 2008 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 2009 cmdstat = segs[0].ds_len; 2010 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 2011 cmdstat |= RL_RDESC_CMD_EOR; 2012 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 2013 2014 return (0); 2015} 2016 2017#ifdef RE_FIXUP_RX 2018static __inline void 2019re_fixup_rx(struct mbuf *m) 2020{ 2021 int i; 2022 uint16_t *src, *dst; 2023 2024 src = mtod(m, uint16_t *); 2025 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 2026 2027 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2028 *dst++ = *src++; 2029 2030 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 2031} 2032#endif 2033 2034static int 2035re_tx_list_init(struct rl_softc *sc) 2036{ 2037 struct rl_desc *desc; 2038 int i; 2039 2040 RL_LOCK_ASSERT(sc); 2041 2042 bzero(sc->rl_ldata.rl_tx_list, 2043 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 2044 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 2045 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 2046#ifdef DEV_NETMAP 2047 re_netmap_tx_init(sc); 2048#endif /* DEV_NETMAP */ 2049 /* Set EOR. */ 2050 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 2051 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 2052 2053 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2054 sc->rl_ldata.rl_tx_list_map, 2055 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2056 2057 sc->rl_ldata.rl_tx_prodidx = 0; 2058 sc->rl_ldata.rl_tx_considx = 0; 2059 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 2060 2061 return (0); 2062} 2063 2064static int 2065re_rx_list_init(struct rl_softc *sc) 2066{ 2067 int error, i; 2068 2069 bzero(sc->rl_ldata.rl_rx_list, 2070 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2071 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2072 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 2073 if ((error = re_newbuf(sc, i)) != 0) 2074 return (error); 2075 } 2076#ifdef DEV_NETMAP 2077 re_netmap_rx_init(sc); 2078#endif /* DEV_NETMAP */ 2079 2080 /* Flush the RX descriptors */ 2081 2082 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2083 sc->rl_ldata.rl_rx_list_map, 2084 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2085 2086 sc->rl_ldata.rl_rx_prodidx = 0; 2087 sc->rl_head = sc->rl_tail = NULL; 2088 sc->rl_int_rx_act = 0; 2089 2090 return (0); 2091} 2092 2093static int 2094re_jrx_list_init(struct rl_softc *sc) 2095{ 2096 int error, i; 2097 2098 bzero(sc->rl_ldata.rl_rx_list, 2099 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2100 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2101 sc->rl_ldata.rl_jrx_desc[i].rx_m = NULL; 2102 if ((error = re_jumbo_newbuf(sc, i)) != 0) 2103 return (error); 2104 } 2105 2106 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2107 sc->rl_ldata.rl_rx_list_map, 2108 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2109 2110 sc->rl_ldata.rl_rx_prodidx = 0; 2111 sc->rl_head = sc->rl_tail = NULL; 2112 sc->rl_int_rx_act = 0; 2113 2114 return (0); 2115} 2116 2117/* 2118 * RX handler for C+ and 8169. For the gigE chips, we support 2119 * the reception of jumbo frames that have been fragmented 2120 * across multiple 2K mbuf cluster buffers. 2121 */ 2122static int 2123re_rxeof(struct rl_softc *sc, int *rx_npktsp) 2124{ 2125 struct mbuf *m; 2126 struct ifnet *ifp; 2127 int i, rxerr, total_len; 2128 struct rl_desc *cur_rx; 2129 u_int32_t rxstat, rxvlan; 2130 int jumbo, maxpkt = 16, rx_npkts = 0; 2131 2132 RL_LOCK_ASSERT(sc); 2133 2134 ifp = sc->rl_ifp; 2135#ifdef DEV_NETMAP 2136 if (netmap_rx_irq(ifp, 0, &rx_npkts)) 2137 return 0; 2138#endif /* DEV_NETMAP */ 2139 if (ifp->if_mtu > RL_MTU && (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 2140 jumbo = 1; 2141 else 2142 jumbo = 0; 2143 2144 /* Invalidate the descriptor memory */ 2145 2146 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2147 sc->rl_ldata.rl_rx_list_map, 2148 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2149 2150 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 2151 i = RL_RX_DESC_NXT(sc, i)) { 2152 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2153 break; 2154 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 2155 rxstat = le32toh(cur_rx->rl_cmdstat); 2156 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 2157 break; 2158 total_len = rxstat & sc->rl_rxlenmask; 2159 rxvlan = le32toh(cur_rx->rl_vlanctl); 2160 if (jumbo != 0) 2161 m = sc->rl_ldata.rl_jrx_desc[i].rx_m; 2162 else 2163 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 2164 2165 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 2166 (rxstat & (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) != 2167 (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) { 2168 /* 2169 * RTL8168C or later controllers do not 2170 * support multi-fragment packet. 2171 */ 2172 re_discard_rxbuf(sc, i); 2173 continue; 2174 } else if ((rxstat & RL_RDESC_STAT_EOF) == 0) { 2175 if (re_newbuf(sc, i) != 0) { 2176 /* 2177 * If this is part of a multi-fragment packet, 2178 * discard all the pieces. 2179 */ 2180 if (sc->rl_head != NULL) { 2181 m_freem(sc->rl_head); 2182 sc->rl_head = sc->rl_tail = NULL; 2183 } 2184 re_discard_rxbuf(sc, i); 2185 continue; 2186 } 2187 m->m_len = RE_RX_DESC_BUFLEN; 2188 if (sc->rl_head == NULL) 2189 sc->rl_head = sc->rl_tail = m; 2190 else { 2191 m->m_flags &= ~M_PKTHDR; 2192 sc->rl_tail->m_next = m; 2193 sc->rl_tail = m; 2194 } 2195 continue; 2196 } 2197 2198 /* 2199 * NOTE: for the 8139C+, the frame length field 2200 * is always 12 bits in size, but for the gigE chips, 2201 * it is 13 bits (since the max RX frame length is 16K). 2202 * Unfortunately, all 32 bits in the status word 2203 * were already used, so to make room for the extra 2204 * length bit, RealTek took out the 'frame alignment 2205 * error' bit and shifted the other status bits 2206 * over one slot. The OWN, EOR, FS and LS bits are 2207 * still in the same places. We have already extracted 2208 * the frame length and checked the OWN bit, so rather 2209 * than using an alternate bit mapping, we shift the 2210 * status bits one space to the right so we can evaluate 2211 * them using the 8169 status as though it was in the 2212 * same format as that of the 8139C+. 2213 */ 2214 if (sc->rl_type == RL_8169) 2215 rxstat >>= 1; 2216 2217 /* 2218 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 2219 * set, but if CRC is clear, it will still be a valid frame. 2220 */ 2221 if ((rxstat & RL_RDESC_STAT_RXERRSUM) != 0) { 2222 rxerr = 1; 2223 if ((sc->rl_flags & RL_FLAG_JUMBOV2) == 0 && 2224 total_len > 8191 && 2225 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT) 2226 rxerr = 0; 2227 if (rxerr != 0) { 2228 ifp->if_ierrors++; 2229 /* 2230 * If this is part of a multi-fragment packet, 2231 * discard all the pieces. 2232 */ 2233 if (sc->rl_head != NULL) { 2234 m_freem(sc->rl_head); 2235 sc->rl_head = sc->rl_tail = NULL; 2236 } 2237 re_discard_rxbuf(sc, i); 2238 continue; 2239 } 2240 } 2241 2242 /* 2243 * If allocating a replacement mbuf fails, 2244 * reload the current one. 2245 */ 2246 if (jumbo != 0) 2247 rxerr = re_jumbo_newbuf(sc, i); 2248 else 2249 rxerr = re_newbuf(sc, i); 2250 if (rxerr != 0) { 2251 ifp->if_iqdrops++; 2252 if (sc->rl_head != NULL) { 2253 m_freem(sc->rl_head); 2254 sc->rl_head = sc->rl_tail = NULL; 2255 } 2256 re_discard_rxbuf(sc, i); 2257 continue; 2258 } 2259 2260 if (sc->rl_head != NULL) { 2261 if (jumbo != 0) 2262 m->m_len = total_len; 2263 else { 2264 m->m_len = total_len % RE_RX_DESC_BUFLEN; 2265 if (m->m_len == 0) 2266 m->m_len = RE_RX_DESC_BUFLEN; 2267 } 2268 /* 2269 * Special case: if there's 4 bytes or less 2270 * in this buffer, the mbuf can be discarded: 2271 * the last 4 bytes is the CRC, which we don't 2272 * care about anyway. 2273 */ 2274 if (m->m_len <= ETHER_CRC_LEN) { 2275 sc->rl_tail->m_len -= 2276 (ETHER_CRC_LEN - m->m_len); 2277 m_freem(m); 2278 } else { 2279 m->m_len -= ETHER_CRC_LEN; 2280 m->m_flags &= ~M_PKTHDR; 2281 sc->rl_tail->m_next = m; 2282 } 2283 m = sc->rl_head; 2284 sc->rl_head = sc->rl_tail = NULL; 2285 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 2286 } else 2287 m->m_pkthdr.len = m->m_len = 2288 (total_len - ETHER_CRC_LEN); 2289 2290#ifdef RE_FIXUP_RX 2291 re_fixup_rx(m); 2292#endif 2293 ifp->if_ipackets++; 2294 m->m_pkthdr.rcvif = ifp; 2295 2296 /* Do RX checksumming if enabled */ 2297 2298 if (ifp->if_capenable & IFCAP_RXCSUM) { 2299 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2300 /* Check IP header checksum */ 2301 if (rxstat & RL_RDESC_STAT_PROTOID) 2302 m->m_pkthdr.csum_flags |= 2303 CSUM_IP_CHECKED; 2304 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 2305 m->m_pkthdr.csum_flags |= 2306 CSUM_IP_VALID; 2307 2308 /* Check TCP/UDP checksum */ 2309 if ((RL_TCPPKT(rxstat) && 2310 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2311 (RL_UDPPKT(rxstat) && 2312 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2313 m->m_pkthdr.csum_flags |= 2314 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2315 m->m_pkthdr.csum_data = 0xffff; 2316 } 2317 } else { 2318 /* 2319 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 2320 */ 2321 if ((rxstat & RL_RDESC_STAT_PROTOID) && 2322 (rxvlan & RL_RDESC_IPV4)) 2323 m->m_pkthdr.csum_flags |= 2324 CSUM_IP_CHECKED; 2325 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 2326 (rxvlan & RL_RDESC_IPV4)) 2327 m->m_pkthdr.csum_flags |= 2328 CSUM_IP_VALID; 2329 if (((rxstat & RL_RDESC_STAT_TCP) && 2330 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2331 ((rxstat & RL_RDESC_STAT_UDP) && 2332 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2333 m->m_pkthdr.csum_flags |= 2334 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2335 m->m_pkthdr.csum_data = 0xffff; 2336 } 2337 } 2338 } 2339 maxpkt--; 2340 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 2341 m->m_pkthdr.ether_vtag = 2342 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA)); 2343 m->m_flags |= M_VLANTAG; 2344 } 2345 RL_UNLOCK(sc); 2346 (*ifp->if_input)(ifp, m); 2347 RL_LOCK(sc); 2348 rx_npkts++; 2349 } 2350 2351 /* Flush the RX DMA ring */ 2352 2353 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2354 sc->rl_ldata.rl_rx_list_map, 2355 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2356 2357 sc->rl_ldata.rl_rx_prodidx = i; 2358 2359 if (rx_npktsp != NULL) 2360 *rx_npktsp = rx_npkts; 2361 if (maxpkt) 2362 return (EAGAIN); 2363 2364 return (0); 2365} 2366 2367static void 2368re_txeof(struct rl_softc *sc) 2369{ 2370 struct ifnet *ifp; 2371 struct rl_txdesc *txd; 2372 u_int32_t txstat; 2373 int cons; 2374 2375 cons = sc->rl_ldata.rl_tx_considx; 2376 if (cons == sc->rl_ldata.rl_tx_prodidx) 2377 return; 2378 2379 ifp = sc->rl_ifp; 2380#ifdef DEV_NETMAP 2381 if (netmap_tx_irq(ifp, 0)) 2382 return; 2383#endif /* DEV_NETMAP */ 2384 /* Invalidate the TX descriptor list */ 2385 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2386 sc->rl_ldata.rl_tx_list_map, 2387 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2388 2389 for (; cons != sc->rl_ldata.rl_tx_prodidx; 2390 cons = RL_TX_DESC_NXT(sc, cons)) { 2391 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 2392 if (txstat & RL_TDESC_STAT_OWN) 2393 break; 2394 /* 2395 * We only stash mbufs in the last descriptor 2396 * in a fragment chain, which also happens to 2397 * be the only place where the TX status bits 2398 * are valid. 2399 */ 2400 if (txstat & RL_TDESC_CMD_EOF) { 2401 txd = &sc->rl_ldata.rl_tx_desc[cons]; 2402 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2403 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2404 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2405 txd->tx_dmamap); 2406 KASSERT(txd->tx_m != NULL, 2407 ("%s: freeing NULL mbufs!", __func__)); 2408 m_freem(txd->tx_m); 2409 txd->tx_m = NULL; 2410 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 2411 RL_TDESC_STAT_COLCNT)) 2412 ifp->if_collisions++; 2413 if (txstat & RL_TDESC_STAT_TXERRSUM) 2414 ifp->if_oerrors++; 2415 else 2416 ifp->if_opackets++; 2417 } 2418 sc->rl_ldata.rl_tx_free++; 2419 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2420 } 2421 sc->rl_ldata.rl_tx_considx = cons; 2422 2423 /* No changes made to the TX ring, so no flush needed */ 2424 2425 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 2426#ifdef RE_TX_MODERATION 2427 /* 2428 * If not all descriptors have been reaped yet, reload 2429 * the timer so that we will eventually get another 2430 * interrupt that will cause us to re-enter this routine. 2431 * This is done in case the transmitter has gone idle. 2432 */ 2433 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2434#endif 2435 } else 2436 sc->rl_watchdog_timer = 0; 2437} 2438 2439static void 2440re_tick(void *xsc) 2441{ 2442 struct rl_softc *sc; 2443 struct mii_data *mii; 2444 2445 sc = xsc; 2446 2447 RL_LOCK_ASSERT(sc); 2448 2449 mii = device_get_softc(sc->rl_miibus); 2450 mii_tick(mii); 2451 if ((sc->rl_flags & RL_FLAG_LINK) == 0) 2452 re_miibus_statchg(sc->rl_dev); 2453 /* 2454 * Reclaim transmitted frames here. Technically it is not 2455 * necessary to do here but it ensures periodic reclamation 2456 * regardless of Tx completion interrupt which seems to be 2457 * lost on PCIe based controllers under certain situations. 2458 */ 2459 re_txeof(sc); 2460 re_watchdog(sc); 2461 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2462} 2463 2464#ifdef DEVICE_POLLING 2465static int 2466re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2467{ 2468 struct rl_softc *sc = ifp->if_softc; 2469 int rx_npkts = 0; 2470 2471 RL_LOCK(sc); 2472 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2473 rx_npkts = re_poll_locked(ifp, cmd, count); 2474 RL_UNLOCK(sc); 2475 return (rx_npkts); 2476} 2477 2478static int 2479re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2480{ 2481 struct rl_softc *sc = ifp->if_softc; 2482 int rx_npkts; 2483 2484 RL_LOCK_ASSERT(sc); 2485 2486 sc->rxcycles = count; 2487 re_rxeof(sc, &rx_npkts); 2488 re_txeof(sc); 2489 2490 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2491 re_start_locked(ifp); 2492 2493 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2494 u_int16_t status; 2495 2496 status = CSR_READ_2(sc, RL_ISR); 2497 if (status == 0xffff) 2498 return (rx_npkts); 2499 if (status) 2500 CSR_WRITE_2(sc, RL_ISR, status); 2501 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2502 (sc->rl_flags & RL_FLAG_PCIE)) 2503 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2504 2505 /* 2506 * XXX check behaviour on receiver stalls. 2507 */ 2508 2509 if (status & RL_ISR_SYSTEM_ERR) { 2510 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2511 re_init_locked(sc); 2512 } 2513 } 2514 return (rx_npkts); 2515} 2516#endif /* DEVICE_POLLING */ 2517 2518static int 2519re_intr(void *arg) 2520{ 2521 struct rl_softc *sc; 2522 uint16_t status; 2523 2524 sc = arg; 2525 2526 status = CSR_READ_2(sc, RL_ISR); 2527 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2528 return (FILTER_STRAY); 2529 CSR_WRITE_2(sc, RL_IMR, 0); 2530 2531 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2532 2533 return (FILTER_HANDLED); 2534} 2535 2536static void 2537re_int_task(void *arg, int npending) 2538{ 2539 struct rl_softc *sc; 2540 struct ifnet *ifp; 2541 u_int16_t status; 2542 int rval = 0; 2543 2544 sc = arg; 2545 ifp = sc->rl_ifp; 2546 2547 RL_LOCK(sc); 2548 2549 status = CSR_READ_2(sc, RL_ISR); 2550 CSR_WRITE_2(sc, RL_ISR, status); 2551 2552 if (sc->suspended || 2553 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2554 RL_UNLOCK(sc); 2555 return; 2556 } 2557 2558#ifdef DEVICE_POLLING 2559 if (ifp->if_capenable & IFCAP_POLLING) { 2560 RL_UNLOCK(sc); 2561 return; 2562 } 2563#endif 2564 2565 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2566 rval = re_rxeof(sc, NULL); 2567 2568 /* 2569 * Some chips will ignore a second TX request issued 2570 * while an existing transmission is in progress. If 2571 * the transmitter goes idle but there are still 2572 * packets waiting to be sent, we need to restart the 2573 * channel here to flush them out. This only seems to 2574 * be required with the PCIe devices. 2575 */ 2576 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2577 (sc->rl_flags & RL_FLAG_PCIE)) 2578 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2579 if (status & ( 2580#ifdef RE_TX_MODERATION 2581 RL_ISR_TIMEOUT_EXPIRED| 2582#else 2583 RL_ISR_TX_OK| 2584#endif 2585 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2586 re_txeof(sc); 2587 2588 if (status & RL_ISR_SYSTEM_ERR) { 2589 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2590 re_init_locked(sc); 2591 } 2592 2593 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2594 re_start_locked(ifp); 2595 2596 RL_UNLOCK(sc); 2597 2598 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2599 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2600 return; 2601 } 2602 2603 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2604} 2605 2606static void 2607re_intr_msi(void *xsc) 2608{ 2609 struct rl_softc *sc; 2610 struct ifnet *ifp; 2611 uint16_t intrs, status; 2612 2613 sc = xsc; 2614 RL_LOCK(sc); 2615 2616 ifp = sc->rl_ifp; 2617#ifdef DEVICE_POLLING 2618 if (ifp->if_capenable & IFCAP_POLLING) { 2619 RL_UNLOCK(sc); 2620 return; 2621 } 2622#endif 2623 /* Disable interrupts. */ 2624 CSR_WRITE_2(sc, RL_IMR, 0); 2625 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2626 RL_UNLOCK(sc); 2627 return; 2628 } 2629 2630 intrs = RL_INTRS_CPLUS; 2631 status = CSR_READ_2(sc, RL_ISR); 2632 CSR_WRITE_2(sc, RL_ISR, status); 2633 if (sc->rl_int_rx_act > 0) { 2634 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2635 RL_ISR_RX_OVERRUN); 2636 status &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2637 RL_ISR_RX_OVERRUN); 2638 } 2639 2640 if (status & (RL_ISR_TIMEOUT_EXPIRED | RL_ISR_RX_OK | RL_ISR_RX_ERR | 2641 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) { 2642 re_rxeof(sc, NULL); 2643 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2644 if (sc->rl_int_rx_mod != 0 && 2645 (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR | 2646 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) != 0) { 2647 /* Rearm one-shot timer. */ 2648 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2649 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | 2650 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN); 2651 sc->rl_int_rx_act = 1; 2652 } else { 2653 intrs |= RL_ISR_RX_OK | RL_ISR_RX_ERR | 2654 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN; 2655 sc->rl_int_rx_act = 0; 2656 } 2657 } 2658 } 2659 2660 /* 2661 * Some chips will ignore a second TX request issued 2662 * while an existing transmission is in progress. If 2663 * the transmitter goes idle but there are still 2664 * packets waiting to be sent, we need to restart the 2665 * channel here to flush them out. This only seems to 2666 * be required with the PCIe devices. 2667 */ 2668 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2669 (sc->rl_flags & RL_FLAG_PCIE)) 2670 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2671 if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR | RL_ISR_TX_DESC_UNAVAIL)) 2672 re_txeof(sc); 2673 2674 if (status & RL_ISR_SYSTEM_ERR) { 2675 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2676 re_init_locked(sc); 2677 } 2678 2679 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2680 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2681 re_start_locked(ifp); 2682 CSR_WRITE_2(sc, RL_IMR, intrs); 2683 } 2684 RL_UNLOCK(sc); 2685} 2686 2687static int 2688re_encap(struct rl_softc *sc, struct mbuf **m_head) 2689{ 2690 struct rl_txdesc *txd, *txd_last; 2691 bus_dma_segment_t segs[RL_NTXSEGS]; 2692 bus_dmamap_t map; 2693 struct mbuf *m_new; 2694 struct rl_desc *desc; 2695 int nsegs, prod; 2696 int i, error, ei, si; 2697 int padlen; 2698 uint32_t cmdstat, csum_flags, vlanctl; 2699 2700 RL_LOCK_ASSERT(sc); 2701 M_ASSERTPKTHDR((*m_head)); 2702 2703 /* 2704 * With some of the RealTek chips, using the checksum offload 2705 * support in conjunction with the autopadding feature results 2706 * in the transmission of corrupt frames. For example, if we 2707 * need to send a really small IP fragment that's less than 60 2708 * bytes in size, and IP header checksumming is enabled, the 2709 * resulting ethernet frame that appears on the wire will 2710 * have garbled payload. To work around this, if TX IP checksum 2711 * offload is enabled, we always manually pad short frames out 2712 * to the minimum ethernet frame size. 2713 */ 2714 if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 && 2715 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2716 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2717 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2718 if (M_WRITABLE(*m_head) == 0) { 2719 /* Get a writable copy. */ 2720 m_new = m_dup(*m_head, M_NOWAIT); 2721 m_freem(*m_head); 2722 if (m_new == NULL) { 2723 *m_head = NULL; 2724 return (ENOBUFS); 2725 } 2726 *m_head = m_new; 2727 } 2728 if ((*m_head)->m_next != NULL || 2729 M_TRAILINGSPACE(*m_head) < padlen) { 2730 m_new = m_defrag(*m_head, M_NOWAIT); 2731 if (m_new == NULL) { 2732 m_freem(*m_head); 2733 *m_head = NULL; 2734 return (ENOBUFS); 2735 } 2736 } else 2737 m_new = *m_head; 2738 2739 /* 2740 * Manually pad short frames, and zero the pad space 2741 * to avoid leaking data. 2742 */ 2743 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2744 m_new->m_pkthdr.len += padlen; 2745 m_new->m_len = m_new->m_pkthdr.len; 2746 *m_head = m_new; 2747 } 2748 2749 prod = sc->rl_ldata.rl_tx_prodidx; 2750 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2751 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2752 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2753 if (error == EFBIG) { 2754 m_new = m_collapse(*m_head, M_NOWAIT, RL_NTXSEGS); 2755 if (m_new == NULL) { 2756 m_freem(*m_head); 2757 *m_head = NULL; 2758 return (ENOBUFS); 2759 } 2760 *m_head = m_new; 2761 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2762 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2763 if (error != 0) { 2764 m_freem(*m_head); 2765 *m_head = NULL; 2766 return (error); 2767 } 2768 } else if (error != 0) 2769 return (error); 2770 if (nsegs == 0) { 2771 m_freem(*m_head); 2772 *m_head = NULL; 2773 return (EIO); 2774 } 2775 2776 /* Check for number of available descriptors. */ 2777 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2778 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2779 return (ENOBUFS); 2780 } 2781 2782 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2783 BUS_DMASYNC_PREWRITE); 2784 2785 /* 2786 * Set up checksum offload. Note: checksum offload bits must 2787 * appear in all descriptors of a multi-descriptor transmit 2788 * attempt. This is according to testing done with an 8169 2789 * chip. This is a requirement. 2790 */ 2791 vlanctl = 0; 2792 csum_flags = 0; 2793 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2794 if ((sc->rl_flags & RL_FLAG_DESCV2) != 0) { 2795 csum_flags |= RL_TDESC_CMD_LGSEND; 2796 vlanctl |= ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2797 RL_TDESC_CMD_MSSVALV2_SHIFT); 2798 } else { 2799 csum_flags |= RL_TDESC_CMD_LGSEND | 2800 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2801 RL_TDESC_CMD_MSSVAL_SHIFT); 2802 } 2803 } else { 2804 /* 2805 * Unconditionally enable IP checksum if TCP or UDP 2806 * checksum is required. Otherwise, TCP/UDP checksum 2807 * doesn't make effects. 2808 */ 2809 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2810 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2811 csum_flags |= RL_TDESC_CMD_IPCSUM; 2812 if (((*m_head)->m_pkthdr.csum_flags & 2813 CSUM_TCP) != 0) 2814 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2815 if (((*m_head)->m_pkthdr.csum_flags & 2816 CSUM_UDP) != 0) 2817 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2818 } else { 2819 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2820 if (((*m_head)->m_pkthdr.csum_flags & 2821 CSUM_TCP) != 0) 2822 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2823 if (((*m_head)->m_pkthdr.csum_flags & 2824 CSUM_UDP) != 0) 2825 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2826 } 2827 } 2828 } 2829 2830 /* 2831 * Set up hardware VLAN tagging. Note: vlan tag info must 2832 * appear in all descriptors of a multi-descriptor 2833 * transmission attempt. 2834 */ 2835 if ((*m_head)->m_flags & M_VLANTAG) 2836 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) | 2837 RL_TDESC_VLANCTL_TAG; 2838 2839 si = prod; 2840 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2841 desc = &sc->rl_ldata.rl_tx_list[prod]; 2842 desc->rl_vlanctl = htole32(vlanctl); 2843 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2844 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2845 cmdstat = segs[i].ds_len; 2846 if (i != 0) 2847 cmdstat |= RL_TDESC_CMD_OWN; 2848 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2849 cmdstat |= RL_TDESC_CMD_EOR; 2850 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2851 sc->rl_ldata.rl_tx_free--; 2852 } 2853 /* Update producer index. */ 2854 sc->rl_ldata.rl_tx_prodidx = prod; 2855 2856 /* Set EOF on the last descriptor. */ 2857 ei = RL_TX_DESC_PRV(sc, prod); 2858 desc = &sc->rl_ldata.rl_tx_list[ei]; 2859 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2860 2861 desc = &sc->rl_ldata.rl_tx_list[si]; 2862 /* Set SOF and transfer ownership of packet to the chip. */ 2863 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2864 2865 /* 2866 * Insure that the map for this transmission 2867 * is placed at the array index of the last descriptor 2868 * in this chain. (Swap last and first dmamaps.) 2869 */ 2870 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2871 map = txd->tx_dmamap; 2872 txd->tx_dmamap = txd_last->tx_dmamap; 2873 txd_last->tx_dmamap = map; 2874 txd_last->tx_m = *m_head; 2875 2876 return (0); 2877} 2878 2879static void 2880re_start(struct ifnet *ifp) 2881{ 2882 struct rl_softc *sc; 2883 2884 sc = ifp->if_softc; 2885 RL_LOCK(sc); 2886 re_start_locked(ifp); 2887 RL_UNLOCK(sc); 2888} 2889 2890/* 2891 * Main transmit routine for C+ and gigE NICs. 2892 */ 2893static void 2894re_start_locked(struct ifnet *ifp) 2895{ 2896 struct rl_softc *sc; 2897 struct mbuf *m_head; 2898 int queued; 2899 2900 sc = ifp->if_softc; 2901 2902#ifdef DEV_NETMAP 2903 /* XXX is this necessary ? */ 2904 if (ifp->if_capenable & IFCAP_NETMAP) { 2905 struct netmap_kring *kring = &NA(ifp)->tx_rings[0]; 2906 if (sc->rl_ldata.rl_tx_prodidx != kring->nr_hwcur) { 2907 /* kick the tx unit */ 2908 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2909#ifdef RE_TX_MODERATION 2910 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2911#endif 2912 sc->rl_watchdog_timer = 5; 2913 } 2914 return; 2915 } 2916#endif /* DEV_NETMAP */ 2917 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2918 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) 2919 return; 2920 2921 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2922 sc->rl_ldata.rl_tx_free > 1;) { 2923 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2924 if (m_head == NULL) 2925 break; 2926 2927 if (re_encap(sc, &m_head) != 0) { 2928 if (m_head == NULL) 2929 break; 2930 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2931 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2932 break; 2933 } 2934 2935 /* 2936 * If there's a BPF listener, bounce a copy of this frame 2937 * to him. 2938 */ 2939 ETHER_BPF_MTAP(ifp, m_head); 2940 2941 queued++; 2942 } 2943 2944 if (queued == 0) { 2945#ifdef RE_TX_MODERATION 2946 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2947 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2948#endif 2949 return; 2950 } 2951 2952 /* Flush the TX descriptors */ 2953 2954 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2955 sc->rl_ldata.rl_tx_list_map, 2956 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2957 2958 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2959 2960#ifdef RE_TX_MODERATION 2961 /* 2962 * Use the countdown timer for interrupt moderation. 2963 * 'TX done' interrupts are disabled. Instead, we reset the 2964 * countdown timer, which will begin counting until it hits 2965 * the value in the TIMERINT register, and then trigger an 2966 * interrupt. Each time we write to the TIMERCNT register, 2967 * the timer count is reset to 0. 2968 */ 2969 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2970#endif 2971 2972 /* 2973 * Set a timeout in case the chip goes out to lunch. 2974 */ 2975 sc->rl_watchdog_timer = 5; 2976} 2977 2978static void 2979re_set_jumbo(struct rl_softc *sc, int jumbo) 2980{ 2981 2982 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168E_VL) { 2983 pci_set_max_read_req(sc->rl_dev, 4096); 2984 return; 2985 } 2986 2987 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2988 if (jumbo != 0) { 2989 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) | 2990 RL_CFG3_JUMBO_EN0); 2991 switch (sc->rl_hwrev->rl_rev) { 2992 case RL_HWREV_8168DP: 2993 break; 2994 case RL_HWREV_8168E: 2995 CSR_WRITE_1(sc, sc->rl_cfg4, 2996 CSR_READ_1(sc, sc->rl_cfg4) | 0x01); 2997 break; 2998 default: 2999 CSR_WRITE_1(sc, sc->rl_cfg4, 3000 CSR_READ_1(sc, sc->rl_cfg4) | RL_CFG4_JUMBO_EN1); 3001 } 3002 } else { 3003 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) & 3004 ~RL_CFG3_JUMBO_EN0); 3005 switch (sc->rl_hwrev->rl_rev) { 3006 case RL_HWREV_8168DP: 3007 break; 3008 case RL_HWREV_8168E: 3009 CSR_WRITE_1(sc, sc->rl_cfg4, 3010 CSR_READ_1(sc, sc->rl_cfg4) & ~0x01); 3011 break; 3012 default: 3013 CSR_WRITE_1(sc, sc->rl_cfg4, 3014 CSR_READ_1(sc, sc->rl_cfg4) & ~RL_CFG4_JUMBO_EN1); 3015 } 3016 } 3017 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3018 3019 switch (sc->rl_hwrev->rl_rev) { 3020 case RL_HWREV_8168DP: 3021 pci_set_max_read_req(sc->rl_dev, 4096); 3022 break; 3023 default: 3024 if (jumbo != 0) 3025 pci_set_max_read_req(sc->rl_dev, 512); 3026 else 3027 pci_set_max_read_req(sc->rl_dev, 4096); 3028 } 3029} 3030 3031static void 3032re_init(void *xsc) 3033{ 3034 struct rl_softc *sc = xsc; 3035 3036 RL_LOCK(sc); 3037 re_init_locked(sc); 3038 RL_UNLOCK(sc); 3039} 3040 3041static void 3042re_init_locked(struct rl_softc *sc) 3043{ 3044 struct ifnet *ifp = sc->rl_ifp; 3045 struct mii_data *mii; 3046 uint32_t reg; 3047 uint16_t cfg; 3048 union { 3049 uint32_t align_dummy; 3050 u_char eaddr[ETHER_ADDR_LEN]; 3051 } eaddr; 3052 3053 RL_LOCK_ASSERT(sc); 3054 3055 mii = device_get_softc(sc->rl_miibus); 3056 3057 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3058 return; 3059 3060 /* 3061 * Cancel pending I/O and free all RX/TX buffers. 3062 */ 3063 re_stop(sc); 3064 3065 /* Put controller into known state. */ 3066 re_reset(sc); 3067 3068 /* 3069 * For C+ mode, initialize the RX descriptors and mbufs. 3070 */ 3071 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3072 if (ifp->if_mtu > RL_MTU) { 3073 if (re_jrx_list_init(sc) != 0) { 3074 device_printf(sc->rl_dev, 3075 "no memory for jumbo RX buffers\n"); 3076 re_stop(sc); 3077 return; 3078 } 3079 /* Disable checksum offloading for jumbo frames. */ 3080 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_TSO4); 3081 ifp->if_hwassist &= ~(RE_CSUM_FEATURES | CSUM_TSO); 3082 } else { 3083 if (re_rx_list_init(sc) != 0) { 3084 device_printf(sc->rl_dev, 3085 "no memory for RX buffers\n"); 3086 re_stop(sc); 3087 return; 3088 } 3089 } 3090 re_set_jumbo(sc, ifp->if_mtu > RL_MTU); 3091 } else { 3092 if (re_rx_list_init(sc) != 0) { 3093 device_printf(sc->rl_dev, "no memory for RX buffers\n"); 3094 re_stop(sc); 3095 return; 3096 } 3097 if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3098 pci_get_device(sc->rl_dev) != RT_DEVICEID_8101E) { 3099 if (ifp->if_mtu > RL_MTU) 3100 pci_set_max_read_req(sc->rl_dev, 512); 3101 else 3102 pci_set_max_read_req(sc->rl_dev, 4096); 3103 } 3104 } 3105 re_tx_list_init(sc); 3106 3107 /* 3108 * Enable C+ RX and TX mode, as well as VLAN stripping and 3109 * RX checksum offload. We must configure the C+ register 3110 * before all others. 3111 */ 3112 cfg = RL_CPLUSCMD_PCI_MRW; 3113 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3114 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 3115 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3116 cfg |= RL_CPLUSCMD_VLANSTRIP; 3117 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 3118 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 3119 /* XXX magic. */ 3120 cfg |= 0x0001; 3121 } else 3122 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 3123 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 3124 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SC || 3125 sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) { 3126 reg = 0x000fff00; 3127 if ((CSR_READ_1(sc, sc->rl_cfg2) & RL_CFG2_PCI66MHZ) != 0) 3128 reg |= 0x000000ff; 3129 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) 3130 reg |= 0x00f00000; 3131 CSR_WRITE_4(sc, 0x7c, reg); 3132 /* Disable interrupt mitigation. */ 3133 CSR_WRITE_2(sc, 0xe2, 0); 3134 } 3135 /* 3136 * Disable TSO if interface MTU size is greater than MSS 3137 * allowed in controller. 3138 */ 3139 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) { 3140 ifp->if_capenable &= ~IFCAP_TSO4; 3141 ifp->if_hwassist &= ~CSUM_TSO; 3142 } 3143 3144 /* 3145 * Init our MAC address. Even though the chipset 3146 * documentation doesn't mention it, we need to enter "Config 3147 * register write enable" mode to modify the ID registers. 3148 */ 3149 /* Copy MAC address on stack to align. */ 3150 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 3151 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 3152 CSR_WRITE_4(sc, RL_IDR0, 3153 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 3154 CSR_WRITE_4(sc, RL_IDR4, 3155 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 3156 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3157 3158 /* 3159 * Load the addresses of the RX and TX lists into the chip. 3160 */ 3161 3162 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 3163 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 3164 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 3165 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 3166 3167 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 3168 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 3169 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 3170 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 3171 3172 /* 3173 * Enable transmit and receive. 3174 */ 3175 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 3176 3177 /* 3178 * Set the initial TX configuration. 3179 */ 3180 if (sc->rl_testmode) { 3181 if (sc->rl_type == RL_8169) 3182 CSR_WRITE_4(sc, RL_TXCFG, 3183 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 3184 else 3185 CSR_WRITE_4(sc, RL_TXCFG, 3186 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 3187 } else 3188 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 3189 3190 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 3191 3192 /* 3193 * Set the initial RX configuration. 3194 */ 3195 re_set_rxmode(sc); 3196 3197 /* Configure interrupt moderation. */ 3198 if (sc->rl_type == RL_8169) { 3199 /* Magic from vendor. */ 3200 CSR_WRITE_2(sc, RL_INTRMOD, 0x5100); 3201 } 3202 3203#ifdef DEVICE_POLLING 3204 /* 3205 * Disable interrupts if we are polling. 3206 */ 3207 if (ifp->if_capenable & IFCAP_POLLING) 3208 CSR_WRITE_2(sc, RL_IMR, 0); 3209 else /* otherwise ... */ 3210#endif 3211 3212 /* 3213 * Enable interrupts. 3214 */ 3215 if (sc->rl_testmode) 3216 CSR_WRITE_2(sc, RL_IMR, 0); 3217 else 3218 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3219 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 3220 3221 /* Set initial TX threshold */ 3222 sc->rl_txthresh = RL_TX_THRESH_INIT; 3223 3224 /* Start RX/TX process. */ 3225 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 3226#ifdef notdef 3227 /* Enable receiver and transmitter. */ 3228 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 3229#endif 3230 3231 /* 3232 * Initialize the timer interrupt register so that 3233 * a timer interrupt will be generated once the timer 3234 * reaches a certain number of ticks. The timer is 3235 * reloaded on each transmit. 3236 */ 3237#ifdef RE_TX_MODERATION 3238 /* 3239 * Use timer interrupt register to moderate TX interrupt 3240 * moderation, which dramatically improves TX frame rate. 3241 */ 3242 if (sc->rl_type == RL_8169) 3243 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 3244 else 3245 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 3246#else 3247 /* 3248 * Use timer interrupt register to moderate RX interrupt 3249 * moderation. 3250 */ 3251 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 3252 intr_filter == 0) { 3253 if (sc->rl_type == RL_8169) 3254 CSR_WRITE_4(sc, RL_TIMERINT_8169, 3255 RL_USECS(sc->rl_int_rx_mod)); 3256 } else { 3257 if (sc->rl_type == RL_8169) 3258 CSR_WRITE_4(sc, RL_TIMERINT_8169, RL_USECS(0)); 3259 } 3260#endif 3261 3262 /* 3263 * For 8169 gigE NICs, set the max allowed RX packet 3264 * size so we can receive jumbo frames. 3265 */ 3266 if (sc->rl_type == RL_8169) { 3267 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3268 /* 3269 * For controllers that use new jumbo frame scheme, 3270 * set maximum size of jumbo frame depending on 3271 * controller revisions. 3272 */ 3273 if (ifp->if_mtu > RL_MTU) 3274 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3275 sc->rl_hwrev->rl_max_mtu + 3276 ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN + 3277 ETHER_CRC_LEN); 3278 else 3279 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3280 RE_RX_DESC_BUFLEN); 3281 } else if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3282 sc->rl_hwrev->rl_max_mtu == RL_MTU) { 3283 /* RTL810x has no jumbo frame support. */ 3284 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN); 3285 } else 3286 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 3287 } 3288 3289 if (sc->rl_testmode) 3290 return; 3291 3292 CSR_WRITE_1(sc, sc->rl_cfg1, CSR_READ_1(sc, sc->rl_cfg1) | 3293 RL_CFG1_DRVLOAD); 3294 3295 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3296 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3297 3298 sc->rl_flags &= ~RL_FLAG_LINK; 3299 mii_mediachg(mii); 3300 3301 sc->rl_watchdog_timer = 0; 3302 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 3303} 3304 3305/* 3306 * Set media options. 3307 */ 3308static int 3309re_ifmedia_upd(struct ifnet *ifp) 3310{ 3311 struct rl_softc *sc; 3312 struct mii_data *mii; 3313 int error; 3314 3315 sc = ifp->if_softc; 3316 mii = device_get_softc(sc->rl_miibus); 3317 RL_LOCK(sc); 3318 error = mii_mediachg(mii); 3319 RL_UNLOCK(sc); 3320 3321 return (error); 3322} 3323 3324/* 3325 * Report current media status. 3326 */ 3327static void 3328re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3329{ 3330 struct rl_softc *sc; 3331 struct mii_data *mii; 3332 3333 sc = ifp->if_softc; 3334 mii = device_get_softc(sc->rl_miibus); 3335 3336 RL_LOCK(sc); 3337 mii_pollstat(mii); 3338 ifmr->ifm_active = mii->mii_media_active; 3339 ifmr->ifm_status = mii->mii_media_status; 3340 RL_UNLOCK(sc); 3341} 3342 3343static int 3344re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3345{ 3346 struct rl_softc *sc = ifp->if_softc; 3347 struct ifreq *ifr = (struct ifreq *) data; 3348 struct mii_data *mii; 3349 uint32_t rev; 3350 int error = 0; 3351 3352 switch (command) { 3353 case SIOCSIFMTU: 3354 if (ifr->ifr_mtu < ETHERMIN || 3355 ifr->ifr_mtu > sc->rl_hwrev->rl_max_mtu || 3356 ((sc->rl_flags & RL_FLAG_FASTETHER) != 0 && 3357 ifr->ifr_mtu > RL_MTU)) { 3358 error = EINVAL; 3359 break; 3360 } 3361 RL_LOCK(sc); 3362 if (ifp->if_mtu != ifr->ifr_mtu) { 3363 ifp->if_mtu = ifr->ifr_mtu; 3364 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3365 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3366 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3367 re_init_locked(sc); 3368 } 3369 if (ifp->if_mtu > RL_TSO_MTU && 3370 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3371 ifp->if_capenable &= ~(IFCAP_TSO4 | 3372 IFCAP_VLAN_HWTSO); 3373 ifp->if_hwassist &= ~CSUM_TSO; 3374 } 3375 VLAN_CAPABILITIES(ifp); 3376 } 3377 RL_UNLOCK(sc); 3378 break; 3379 case SIOCSIFFLAGS: 3380 RL_LOCK(sc); 3381 if ((ifp->if_flags & IFF_UP) != 0) { 3382 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3383 if (((ifp->if_flags ^ sc->rl_if_flags) 3384 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 3385 re_set_rxmode(sc); 3386 } else 3387 re_init_locked(sc); 3388 } else { 3389 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3390 re_stop(sc); 3391 } 3392 sc->rl_if_flags = ifp->if_flags; 3393 RL_UNLOCK(sc); 3394 break; 3395 case SIOCADDMULTI: 3396 case SIOCDELMULTI: 3397 RL_LOCK(sc); 3398 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3399 re_set_rxmode(sc); 3400 RL_UNLOCK(sc); 3401 break; 3402 case SIOCGIFMEDIA: 3403 case SIOCSIFMEDIA: 3404 mii = device_get_softc(sc->rl_miibus); 3405 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3406 break; 3407 case SIOCSIFCAP: 3408 { 3409 int mask, reinit; 3410 3411 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3412 reinit = 0; 3413#ifdef DEVICE_POLLING 3414 if (mask & IFCAP_POLLING) { 3415 if (ifr->ifr_reqcap & IFCAP_POLLING) { 3416 error = ether_poll_register(re_poll, ifp); 3417 if (error) 3418 return (error); 3419 RL_LOCK(sc); 3420 /* Disable interrupts */ 3421 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3422 ifp->if_capenable |= IFCAP_POLLING; 3423 RL_UNLOCK(sc); 3424 } else { 3425 error = ether_poll_deregister(ifp); 3426 /* Enable interrupts. */ 3427 RL_LOCK(sc); 3428 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3429 ifp->if_capenable &= ~IFCAP_POLLING; 3430 RL_UNLOCK(sc); 3431 } 3432 } 3433#endif /* DEVICE_POLLING */ 3434 RL_LOCK(sc); 3435 if ((mask & IFCAP_TXCSUM) != 0 && 3436 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3437 ifp->if_capenable ^= IFCAP_TXCSUM; 3438 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) { 3439 rev = sc->rl_hwrev->rl_rev; 3440 if (rev == RL_HWREV_8168C || 3441 rev == RL_HWREV_8168C_SPIN2 || 3442 rev == RL_HWREV_8168CP) 3443 ifp->if_hwassist |= CSUM_TCP | CSUM_UDP; 3444 else 3445 ifp->if_hwassist |= RE_CSUM_FEATURES; 3446 } else 3447 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 3448 reinit = 1; 3449 } 3450 if ((mask & IFCAP_RXCSUM) != 0 && 3451 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 3452 ifp->if_capenable ^= IFCAP_RXCSUM; 3453 reinit = 1; 3454 } 3455 if ((mask & IFCAP_TSO4) != 0 && 3456 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 3457 ifp->if_capenable ^= IFCAP_TSO4; 3458 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 3459 ifp->if_hwassist |= CSUM_TSO; 3460 else 3461 ifp->if_hwassist &= ~CSUM_TSO; 3462 if (ifp->if_mtu > RL_TSO_MTU && 3463 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3464 ifp->if_capenable &= ~IFCAP_TSO4; 3465 ifp->if_hwassist &= ~CSUM_TSO; 3466 } 3467 } 3468 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 3469 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 3470 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 3471 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3472 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 3473 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3474 /* TSO over VLAN requires VLAN hardware tagging. */ 3475 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 3476 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 3477 reinit = 1; 3478 } 3479 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3480 (mask & (IFCAP_HWCSUM | IFCAP_TSO4 | 3481 IFCAP_VLAN_HWTSO)) != 0) 3482 reinit = 1; 3483 if ((mask & IFCAP_WOL) != 0 && 3484 (ifp->if_capabilities & IFCAP_WOL) != 0) { 3485 if ((mask & IFCAP_WOL_UCAST) != 0) 3486 ifp->if_capenable ^= IFCAP_WOL_UCAST; 3487 if ((mask & IFCAP_WOL_MCAST) != 0) 3488 ifp->if_capenable ^= IFCAP_WOL_MCAST; 3489 if ((mask & IFCAP_WOL_MAGIC) != 0) 3490 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3491 } 3492 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) { 3493 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3494 re_init_locked(sc); 3495 } 3496 RL_UNLOCK(sc); 3497 VLAN_CAPABILITIES(ifp); 3498 } 3499 break; 3500 default: 3501 error = ether_ioctl(ifp, command, data); 3502 break; 3503 } 3504 3505 return (error); 3506} 3507 3508static void 3509re_watchdog(struct rl_softc *sc) 3510{ 3511 struct ifnet *ifp; 3512 3513 RL_LOCK_ASSERT(sc); 3514 3515 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 3516 return; 3517 3518 ifp = sc->rl_ifp; 3519 re_txeof(sc); 3520 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) { 3521 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 3522 "-- recovering\n"); 3523 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3524 re_start_locked(ifp); 3525 return; 3526 } 3527 3528 if_printf(ifp, "watchdog timeout\n"); 3529 ifp->if_oerrors++; 3530 3531 re_rxeof(sc, NULL); 3532 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3533 re_init_locked(sc); 3534 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3535 re_start_locked(ifp); 3536} 3537 3538/* 3539 * Stop the adapter and free any mbufs allocated to the 3540 * RX and TX lists. 3541 */ 3542static void 3543re_stop(struct rl_softc *sc) 3544{ 3545 int i; 3546 struct ifnet *ifp; 3547 struct rl_txdesc *txd; 3548 struct rl_rxdesc *rxd; 3549 3550 RL_LOCK_ASSERT(sc); 3551 3552 ifp = sc->rl_ifp; 3553 3554 sc->rl_watchdog_timer = 0; 3555 callout_stop(&sc->rl_stat_callout); 3556 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3557 3558 /* 3559 * Disable accepting frames to put RX MAC into idle state. 3560 * Otherwise it's possible to get frames while stop command 3561 * execution is in progress and controller can DMA the frame 3562 * to already freed RX buffer during that period. 3563 */ 3564 CSR_WRITE_4(sc, RL_RXCFG, CSR_READ_4(sc, RL_RXCFG) & 3565 ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_MULTI | 3566 RL_RXCFG_RX_BROAD)); 3567 3568 if ((sc->rl_flags & RL_FLAG_WAIT_TXPOLL) != 0) { 3569 for (i = RL_TIMEOUT; i > 0; i--) { 3570 if ((CSR_READ_1(sc, sc->rl_txstart) & 3571 RL_TXSTART_START) == 0) 3572 break; 3573 DELAY(20); 3574 } 3575 if (i == 0) 3576 device_printf(sc->rl_dev, 3577 "stopping TX poll timed out!\n"); 3578 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3579 } else if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) { 3580 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB | 3581 RL_CMD_RX_ENB); 3582 if ((sc->rl_flags & RL_FLAG_CMDSTOP_WAIT_TXQ) != 0) { 3583 for (i = RL_TIMEOUT; i > 0; i--) { 3584 if ((CSR_READ_4(sc, RL_TXCFG) & 3585 RL_TXCFG_QUEUE_EMPTY) != 0) 3586 break; 3587 DELAY(100); 3588 } 3589 if (i == 0) 3590 device_printf(sc->rl_dev, 3591 "stopping TXQ timed out!\n"); 3592 } 3593 } else 3594 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3595 DELAY(1000); 3596 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3597 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 3598 3599 if (sc->rl_head != NULL) { 3600 m_freem(sc->rl_head); 3601 sc->rl_head = sc->rl_tail = NULL; 3602 } 3603 3604 /* Free the TX list buffers. */ 3605 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 3606 txd = &sc->rl_ldata.rl_tx_desc[i]; 3607 if (txd->tx_m != NULL) { 3608 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 3609 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3610 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 3611 txd->tx_dmamap); 3612 m_freem(txd->tx_m); 3613 txd->tx_m = NULL; 3614 } 3615 } 3616 3617 /* Free the RX list buffers. */ 3618 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3619 rxd = &sc->rl_ldata.rl_rx_desc[i]; 3620 if (rxd->rx_m != NULL) { 3621 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 3622 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3623 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 3624 rxd->rx_dmamap); 3625 m_freem(rxd->rx_m); 3626 rxd->rx_m = NULL; 3627 } 3628 } 3629 3630 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3631 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3632 rxd = &sc->rl_ldata.rl_jrx_desc[i]; 3633 if (rxd->rx_m != NULL) { 3634 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, 3635 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3636 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, 3637 rxd->rx_dmamap); 3638 m_freem(rxd->rx_m); 3639 rxd->rx_m = NULL; 3640 } 3641 } 3642 } 3643} 3644 3645/* 3646 * Device suspend routine. Stop the interface and save some PCI 3647 * settings in case the BIOS doesn't restore them properly on 3648 * resume. 3649 */ 3650static int 3651re_suspend(device_t dev) 3652{ 3653 struct rl_softc *sc; 3654 3655 sc = device_get_softc(dev); 3656 3657 RL_LOCK(sc); 3658 re_stop(sc); 3659 re_setwol(sc); 3660 sc->suspended = 1; 3661 RL_UNLOCK(sc); 3662 3663 return (0); 3664} 3665 3666/* 3667 * Device resume routine. Restore some PCI settings in case the BIOS 3668 * doesn't, re-enable busmastering, and restart the interface if 3669 * appropriate. 3670 */ 3671static int 3672re_resume(device_t dev) 3673{ 3674 struct rl_softc *sc; 3675 struct ifnet *ifp; 3676 3677 sc = device_get_softc(dev); 3678 3679 RL_LOCK(sc); 3680 3681 ifp = sc->rl_ifp; 3682 /* Take controller out of sleep mode. */ 3683 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3684 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3685 CSR_WRITE_1(sc, RL_GPIO, 3686 CSR_READ_1(sc, RL_GPIO) | 0x01); 3687 } 3688 3689 /* 3690 * Clear WOL matching such that normal Rx filtering 3691 * wouldn't interfere with WOL patterns. 3692 */ 3693 re_clrwol(sc); 3694 3695 /* reinitialize interface if necessary */ 3696 if (ifp->if_flags & IFF_UP) 3697 re_init_locked(sc); 3698 3699 sc->suspended = 0; 3700 RL_UNLOCK(sc); 3701 3702 return (0); 3703} 3704 3705/* 3706 * Stop all chip I/O so that the kernel's probe routines don't 3707 * get confused by errant DMAs when rebooting. 3708 */ 3709static int 3710re_shutdown(device_t dev) 3711{ 3712 struct rl_softc *sc; 3713 3714 sc = device_get_softc(dev); 3715 3716 RL_LOCK(sc); 3717 re_stop(sc); 3718 /* 3719 * Mark interface as down since otherwise we will panic if 3720 * interrupt comes in later on, which can happen in some 3721 * cases. 3722 */ 3723 sc->rl_ifp->if_flags &= ~IFF_UP; 3724 re_setwol(sc); 3725 RL_UNLOCK(sc); 3726 3727 return (0); 3728} 3729 3730static void 3731re_set_linkspeed(struct rl_softc *sc) 3732{ 3733 struct mii_softc *miisc; 3734 struct mii_data *mii; 3735 int aneg, i, phyno; 3736 3737 RL_LOCK_ASSERT(sc); 3738 3739 mii = device_get_softc(sc->rl_miibus); 3740 mii_pollstat(mii); 3741 aneg = 0; 3742 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 3743 (IFM_ACTIVE | IFM_AVALID)) { 3744 switch IFM_SUBTYPE(mii->mii_media_active) { 3745 case IFM_10_T: 3746 case IFM_100_TX: 3747 return; 3748 case IFM_1000_T: 3749 aneg++; 3750 break; 3751 default: 3752 break; 3753 } 3754 } 3755 miisc = LIST_FIRST(&mii->mii_phys); 3756 phyno = miisc->mii_phy; 3757 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 3758 PHY_RESET(miisc); 3759 re_miibus_writereg(sc->rl_dev, phyno, MII_100T2CR, 0); 3760 re_miibus_writereg(sc->rl_dev, phyno, 3761 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 3762 re_miibus_writereg(sc->rl_dev, phyno, 3763 MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 3764 DELAY(1000); 3765 if (aneg != 0) { 3766 /* 3767 * Poll link state until re(4) get a 10/100Mbps link. 3768 */ 3769 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 3770 mii_pollstat(mii); 3771 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 3772 == (IFM_ACTIVE | IFM_AVALID)) { 3773 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3774 case IFM_10_T: 3775 case IFM_100_TX: 3776 return; 3777 default: 3778 break; 3779 } 3780 } 3781 RL_UNLOCK(sc); 3782 pause("relnk", hz); 3783 RL_LOCK(sc); 3784 } 3785 if (i == MII_ANEGTICKS_GIGE) 3786 device_printf(sc->rl_dev, 3787 "establishing a link failed, WOL may not work!"); 3788 } 3789 /* 3790 * No link, force MAC to have 100Mbps, full-duplex link. 3791 * MAC does not require reprogramming on resolved speed/duplex, 3792 * so this is just for completeness. 3793 */ 3794 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 3795 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 3796} 3797 3798static void 3799re_setwol(struct rl_softc *sc) 3800{ 3801 struct ifnet *ifp; 3802 int pmc; 3803 uint16_t pmstat; 3804 uint8_t v; 3805 3806 RL_LOCK_ASSERT(sc); 3807 3808 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3809 return; 3810 3811 ifp = sc->rl_ifp; 3812 /* Put controller into sleep mode. */ 3813 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3814 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3815 CSR_WRITE_1(sc, RL_GPIO, 3816 CSR_READ_1(sc, RL_GPIO) & ~0x01); 3817 } 3818 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 3819 re_set_rxmode(sc); 3820 if ((sc->rl_flags & RL_FLAG_WOL_MANLINK) != 0) 3821 re_set_linkspeed(sc); 3822 if ((sc->rl_flags & RL_FLAG_WOLRXENB) != 0) 3823 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB); 3824 } 3825 /* Enable config register write. */ 3826 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3827 3828 /* Enable PME. */ 3829 v = CSR_READ_1(sc, sc->rl_cfg1); 3830 v &= ~RL_CFG1_PME; 3831 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3832 v |= RL_CFG1_PME; 3833 CSR_WRITE_1(sc, sc->rl_cfg1, v); 3834 3835 v = CSR_READ_1(sc, sc->rl_cfg3); 3836 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3837 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3838 v |= RL_CFG3_WOL_MAGIC; 3839 CSR_WRITE_1(sc, sc->rl_cfg3, v); 3840 3841 v = CSR_READ_1(sc, sc->rl_cfg5); 3842 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST | 3843 RL_CFG5_WOL_LANWAKE); 3844 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 3845 v |= RL_CFG5_WOL_UCAST; 3846 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 3847 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3848 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3849 v |= RL_CFG5_WOL_LANWAKE; 3850 CSR_WRITE_1(sc, sc->rl_cfg5, v); 3851 3852 /* Config register write done. */ 3853 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3854 3855 if ((ifp->if_capenable & IFCAP_WOL) == 0 && 3856 (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) 3857 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80); 3858 /* 3859 * It seems that hardware resets its link speed to 100Mbps in 3860 * power down mode so switching to 100Mbps in driver is not 3861 * needed. 3862 */ 3863 3864 /* Request PME if WOL is requested. */ 3865 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3866 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3867 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3868 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3869 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3870} 3871 3872static void 3873re_clrwol(struct rl_softc *sc) 3874{ 3875 int pmc; 3876 uint8_t v; 3877 3878 RL_LOCK_ASSERT(sc); 3879 3880 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3881 return; 3882 3883 /* Enable config register write. */ 3884 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3885 3886 v = CSR_READ_1(sc, sc->rl_cfg3); 3887 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3888 CSR_WRITE_1(sc, sc->rl_cfg3, v); 3889 3890 /* Config register write done. */ 3891 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3892 3893 v = CSR_READ_1(sc, sc->rl_cfg5); 3894 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3895 v &= ~RL_CFG5_WOL_LANWAKE; 3896 CSR_WRITE_1(sc, sc->rl_cfg5, v); 3897} 3898 3899static void 3900re_add_sysctls(struct rl_softc *sc) 3901{ 3902 struct sysctl_ctx_list *ctx; 3903 struct sysctl_oid_list *children; 3904 int error; 3905 3906 ctx = device_get_sysctl_ctx(sc->rl_dev); 3907 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev)); 3908 3909 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "stats", 3910 CTLTYPE_INT | CTLFLAG_RW, sc, 0, re_sysctl_stats, "I", 3911 "Statistics Information"); 3912 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 3913 return; 3914 3915 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "int_rx_mod", 3916 CTLTYPE_INT | CTLFLAG_RW, &sc->rl_int_rx_mod, 0, 3917 sysctl_hw_re_int_mod, "I", "re RX interrupt moderation"); 3918 /* Pull in device tunables. */ 3919 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3920 error = resource_int_value(device_get_name(sc->rl_dev), 3921 device_get_unit(sc->rl_dev), "int_rx_mod", &sc->rl_int_rx_mod); 3922 if (error == 0) { 3923 if (sc->rl_int_rx_mod < RL_TIMER_MIN || 3924 sc->rl_int_rx_mod > RL_TIMER_MAX) { 3925 device_printf(sc->rl_dev, "int_rx_mod value out of " 3926 "range; using default: %d\n", 3927 RL_TIMER_DEFAULT); 3928 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3929 } 3930 } 3931 3932} 3933 3934static int 3935re_sysctl_stats(SYSCTL_HANDLER_ARGS) 3936{ 3937 struct rl_softc *sc; 3938 struct rl_stats *stats; 3939 int error, i, result; 3940 3941 result = -1; 3942 error = sysctl_handle_int(oidp, &result, 0, req); 3943 if (error || req->newptr == NULL) 3944 return (error); 3945 3946 if (result == 1) { 3947 sc = (struct rl_softc *)arg1; 3948 RL_LOCK(sc); 3949 if ((sc->rl_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 3950 RL_UNLOCK(sc); 3951 goto done; 3952 } 3953 bus_dmamap_sync(sc->rl_ldata.rl_stag, 3954 sc->rl_ldata.rl_smap, BUS_DMASYNC_PREREAD); 3955 CSR_WRITE_4(sc, RL_DUMPSTATS_HI, 3956 RL_ADDR_HI(sc->rl_ldata.rl_stats_addr)); 3957 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 3958 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr)); 3959 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 3960 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr | 3961 RL_DUMPSTATS_START)); 3962 for (i = RL_TIMEOUT; i > 0; i--) { 3963 if ((CSR_READ_4(sc, RL_DUMPSTATS_LO) & 3964 RL_DUMPSTATS_START) == 0) 3965 break; 3966 DELAY(1000); 3967 } 3968 bus_dmamap_sync(sc->rl_ldata.rl_stag, 3969 sc->rl_ldata.rl_smap, BUS_DMASYNC_POSTREAD); 3970 RL_UNLOCK(sc); 3971 if (i == 0) { 3972 device_printf(sc->rl_dev, 3973 "DUMP statistics request timed out\n"); 3974 return (ETIMEDOUT); 3975 } 3976done: 3977 stats = sc->rl_ldata.rl_stats; 3978 printf("%s statistics:\n", device_get_nameunit(sc->rl_dev)); 3979 printf("Tx frames : %ju\n", 3980 (uintmax_t)le64toh(stats->rl_tx_pkts)); 3981 printf("Rx frames : %ju\n", 3982 (uintmax_t)le64toh(stats->rl_rx_pkts)); 3983 printf("Tx errors : %ju\n", 3984 (uintmax_t)le64toh(stats->rl_tx_errs)); 3985 printf("Rx errors : %u\n", 3986 le32toh(stats->rl_rx_errs)); 3987 printf("Rx missed frames : %u\n", 3988 (uint32_t)le16toh(stats->rl_missed_pkts)); 3989 printf("Rx frame alignment errs : %u\n", 3990 (uint32_t)le16toh(stats->rl_rx_framealign_errs)); 3991 printf("Tx single collisions : %u\n", 3992 le32toh(stats->rl_tx_onecoll)); 3993 printf("Tx multiple collisions : %u\n", 3994 le32toh(stats->rl_tx_multicolls)); 3995 printf("Rx unicast frames : %ju\n", 3996 (uintmax_t)le64toh(stats->rl_rx_ucasts)); 3997 printf("Rx broadcast frames : %ju\n", 3998 (uintmax_t)le64toh(stats->rl_rx_bcasts)); 3999 printf("Rx multicast frames : %u\n", 4000 le32toh(stats->rl_rx_mcasts)); 4001 printf("Tx aborts : %u\n", 4002 (uint32_t)le16toh(stats->rl_tx_aborts)); 4003 printf("Tx underruns : %u\n", 4004 (uint32_t)le16toh(stats->rl_rx_underruns)); 4005 } 4006 4007 return (error); 4008} 4009 4010static int 4011sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4012{ 4013 int error, value; 4014 4015 if (arg1 == NULL) 4016 return (EINVAL); 4017 value = *(int *)arg1; 4018 error = sysctl_handle_int(oidp, &value, 0, req); 4019 if (error || req->newptr == NULL) 4020 return (error); 4021 if (value < low || value > high) 4022 return (EINVAL); 4023 *(int *)arg1 = value; 4024 4025 return (0); 4026} 4027 4028static int 4029sysctl_hw_re_int_mod(SYSCTL_HANDLER_ARGS) 4030{ 4031 4032 return (sysctl_int_range(oidp, arg1, arg2, req, RL_TIMER_MIN, 4033 RL_TIMER_MAX)); 4034} 4035