if_re.c revision 257615
1/*- 2 * Copyright (c) 1997, 1998-2003 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: stable/10/sys/dev/re/if_re.c 257615 2013-11-04 05:56:02Z yongari $"); 35 36/* 37 * RealTek 8139C+/8169/8169S/8110S/8168/8111/8101E PCI NIC driver 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * This driver is designed to support RealTek's next generation of 46 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 47 * seven devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 48 * RTL8110S, the RTL8168, the RTL8111 and the RTL8101E. 49 * 50 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 51 * with the older 8139 family, however it also supports a special 52 * C+ mode of operation that provides several new performance enhancing 53 * features. These include: 54 * 55 * o Descriptor based DMA mechanism. Each descriptor represents 56 * a single packet fragment. Data buffers may be aligned on 57 * any byte boundary. 58 * 59 * o 64-bit DMA 60 * 61 * o TCP/IP checksum offload for both RX and TX 62 * 63 * o High and normal priority transmit DMA rings 64 * 65 * o VLAN tag insertion and extraction 66 * 67 * o TCP large send (segmentation offload) 68 * 69 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 70 * programming API is fairly straightforward. The RX filtering, EEPROM 71 * access and PHY access is the same as it is on the older 8139 series 72 * chips. 73 * 74 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 75 * same programming API and feature set as the 8139C+ with the following 76 * differences and additions: 77 * 78 * o 1000Mbps mode 79 * 80 * o Jumbo frames 81 * 82 * o GMII and TBI ports/registers for interfacing with copper 83 * or fiber PHYs 84 * 85 * o RX and TX DMA rings can have up to 1024 descriptors 86 * (the 8139C+ allows a maximum of 64) 87 * 88 * o Slight differences in register layout from the 8139C+ 89 * 90 * The TX start and timer interrupt registers are at different locations 91 * on the 8169 than they are on the 8139C+. Also, the status word in the 92 * RX descriptor has a slightly different bit layout. The 8169 does not 93 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 94 * copper gigE PHY. 95 * 96 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 97 * (the 'S' stands for 'single-chip'). These devices have the same 98 * programming API as the older 8169, but also have some vendor-specific 99 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 100 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 101 * 102 * This driver takes advantage of the RX and TX checksum offload and 103 * VLAN tag insertion/extraction features. It also implements TX 104 * interrupt moderation using the timer interrupt registers, which 105 * significantly reduces TX interrupt load. There is also support 106 * for jumbo frames, however the 8169/8169S/8110S can not transmit 107 * jumbo frames larger than 7440, so the max MTU possible with this 108 * driver is 7422 bytes. 109 */ 110 111#ifdef HAVE_KERNEL_OPTION_HEADERS 112#include "opt_device_polling.h" 113#endif 114 115#include <sys/param.h> 116#include <sys/endian.h> 117#include <sys/systm.h> 118#include <sys/sockio.h> 119#include <sys/mbuf.h> 120#include <sys/malloc.h> 121#include <sys/module.h> 122#include <sys/kernel.h> 123#include <sys/socket.h> 124#include <sys/lock.h> 125#include <sys/mutex.h> 126#include <sys/sysctl.h> 127#include <sys/taskqueue.h> 128 129#include <net/if.h> 130#include <net/if_arp.h> 131#include <net/ethernet.h> 132#include <net/if_dl.h> 133#include <net/if_media.h> 134#include <net/if_types.h> 135#include <net/if_vlan_var.h> 136 137#include <net/bpf.h> 138 139#include <machine/bus.h> 140#include <machine/resource.h> 141#include <sys/bus.h> 142#include <sys/rman.h> 143 144#include <dev/mii/mii.h> 145#include <dev/mii/miivar.h> 146 147#include <dev/pci/pcireg.h> 148#include <dev/pci/pcivar.h> 149 150#include <pci/if_rlreg.h> 151 152MODULE_DEPEND(re, pci, 1, 1, 1); 153MODULE_DEPEND(re, ether, 1, 1, 1); 154MODULE_DEPEND(re, miibus, 1, 1, 1); 155 156/* "device miibus" required. See GENERIC if you get errors here. */ 157#include "miibus_if.h" 158 159/* Tunables. */ 160static int intr_filter = 0; 161TUNABLE_INT("hw.re.intr_filter", &intr_filter); 162static int msi_disable = 0; 163TUNABLE_INT("hw.re.msi_disable", &msi_disable); 164static int msix_disable = 0; 165TUNABLE_INT("hw.re.msix_disable", &msix_disable); 166static int prefer_iomap = 0; 167TUNABLE_INT("hw.re.prefer_iomap", &prefer_iomap); 168 169#define RE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 170 171/* 172 * Various supported device vendors/types and their names. 173 */ 174static const struct rl_type re_devs[] = { 175 { DLINK_VENDORID, DLINK_DEVICEID_528T, 0, 176 "D-Link DGE-528(T) Gigabit Ethernet Adapter" }, 177 { DLINK_VENDORID, DLINK_DEVICEID_530T_REVC, 0, 178 "D-Link DGE-530(T) Gigabit Ethernet Adapter" }, 179 { RT_VENDORID, RT_DEVICEID_8139, 0, 180 "RealTek 8139C+ 10/100BaseTX" }, 181 { RT_VENDORID, RT_DEVICEID_8101E, 0, 182 "RealTek 810xE PCIe 10/100baseTX" }, 183 { RT_VENDORID, RT_DEVICEID_8168, 0, 184 "RealTek 8168/8111 B/C/CP/D/DP/E/F/G PCIe Gigabit Ethernet" }, 185 { RT_VENDORID, RT_DEVICEID_8169, 0, 186 "RealTek 8169/8169S/8169SB(L)/8110S/8110SB(L) Gigabit Ethernet" }, 187 { RT_VENDORID, RT_DEVICEID_8169SC, 0, 188 "RealTek 8169SC/8110SC Single-chip Gigabit Ethernet" }, 189 { COREGA_VENDORID, COREGA_DEVICEID_CGLAPCIGT, 0, 190 "Corega CG-LAPCIGT (RTL8169S) Gigabit Ethernet" }, 191 { LINKSYS_VENDORID, LINKSYS_DEVICEID_EG1032, 0, 192 "Linksys EG1032 (RTL8169S) Gigabit Ethernet" }, 193 { USR_VENDORID, USR_DEVICEID_997902, 0, 194 "US Robotics 997902 (RTL8169S) Gigabit Ethernet" } 195}; 196 197static const struct rl_hwrev re_hwrevs[] = { 198 { RL_HWREV_8139, RL_8139, "", RL_MTU }, 199 { RL_HWREV_8139A, RL_8139, "A", RL_MTU }, 200 { RL_HWREV_8139AG, RL_8139, "A-G", RL_MTU }, 201 { RL_HWREV_8139B, RL_8139, "B", RL_MTU }, 202 { RL_HWREV_8130, RL_8139, "8130", RL_MTU }, 203 { RL_HWREV_8139C, RL_8139, "C", RL_MTU }, 204 { RL_HWREV_8139D, RL_8139, "8139D/8100B/8100C", RL_MTU }, 205 { RL_HWREV_8139CPLUS, RL_8139CPLUS, "C+", RL_MTU }, 206 { RL_HWREV_8168B_SPIN1, RL_8169, "8168", RL_JUMBO_MTU }, 207 { RL_HWREV_8169, RL_8169, "8169", RL_JUMBO_MTU }, 208 { RL_HWREV_8169S, RL_8169, "8169S", RL_JUMBO_MTU }, 209 { RL_HWREV_8110S, RL_8169, "8110S", RL_JUMBO_MTU }, 210 { RL_HWREV_8169_8110SB, RL_8169, "8169SB/8110SB", RL_JUMBO_MTU }, 211 { RL_HWREV_8169_8110SC, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 212 { RL_HWREV_8169_8110SBL, RL_8169, "8169SBL/8110SBL", RL_JUMBO_MTU }, 213 { RL_HWREV_8169_8110SCE, RL_8169, "8169SC/8110SC", RL_JUMBO_MTU }, 214 { RL_HWREV_8100, RL_8139, "8100", RL_MTU }, 215 { RL_HWREV_8101, RL_8139, "8101", RL_MTU }, 216 { RL_HWREV_8100E, RL_8169, "8100E", RL_MTU }, 217 { RL_HWREV_8101E, RL_8169, "8101E", RL_MTU }, 218 { RL_HWREV_8102E, RL_8169, "8102E", RL_MTU }, 219 { RL_HWREV_8102EL, RL_8169, "8102EL", RL_MTU }, 220 { RL_HWREV_8102EL_SPIN1, RL_8169, "8102EL", RL_MTU }, 221 { RL_HWREV_8103E, RL_8169, "8103E", RL_MTU }, 222 { RL_HWREV_8401E, RL_8169, "8401E", RL_MTU }, 223 { RL_HWREV_8402, RL_8169, "8402", RL_MTU }, 224 { RL_HWREV_8105E, RL_8169, "8105E", RL_MTU }, 225 { RL_HWREV_8105E_SPIN1, RL_8169, "8105E", RL_MTU }, 226 { RL_HWREV_8106E, RL_8169, "8106E", RL_MTU }, 227 { RL_HWREV_8168B_SPIN2, RL_8169, "8168", RL_JUMBO_MTU }, 228 { RL_HWREV_8168B_SPIN3, RL_8169, "8168", RL_JUMBO_MTU }, 229 { RL_HWREV_8168C, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 230 { RL_HWREV_8168C_SPIN2, RL_8169, "8168C/8111C", RL_JUMBO_MTU_6K }, 231 { RL_HWREV_8168CP, RL_8169, "8168CP/8111CP", RL_JUMBO_MTU_6K }, 232 { RL_HWREV_8168D, RL_8169, "8168D/8111D", RL_JUMBO_MTU_9K }, 233 { RL_HWREV_8168DP, RL_8169, "8168DP/8111DP", RL_JUMBO_MTU_9K }, 234 { RL_HWREV_8168E, RL_8169, "8168E/8111E", RL_JUMBO_MTU_9K}, 235 { RL_HWREV_8168E_VL, RL_8169, "8168E/8111E-VL", RL_JUMBO_MTU_6K}, 236 { RL_HWREV_8168F, RL_8169, "8168F/8111F", RL_JUMBO_MTU_9K}, 237 { RL_HWREV_8168G, RL_8169, "8168G/8111G", RL_JUMBO_MTU_9K}, 238 { RL_HWREV_8168GU, RL_8169, "8168GU/8111GU", RL_JUMBO_MTU_9K}, 239 { RL_HWREV_8411, RL_8169, "8411", RL_JUMBO_MTU_9K}, 240 { RL_HWREV_8411B, RL_8169, "8411B", RL_JUMBO_MTU_9K}, 241 { 0, 0, NULL, 0 } 242}; 243 244static int re_probe (device_t); 245static int re_attach (device_t); 246static int re_detach (device_t); 247 248static int re_encap (struct rl_softc *, struct mbuf **); 249 250static void re_dma_map_addr (void *, bus_dma_segment_t *, int, int); 251static int re_allocmem (device_t, struct rl_softc *); 252static __inline void re_discard_rxbuf 253 (struct rl_softc *, int); 254static int re_newbuf (struct rl_softc *, int); 255static int re_jumbo_newbuf (struct rl_softc *, int); 256static int re_rx_list_init (struct rl_softc *); 257static int re_jrx_list_init (struct rl_softc *); 258static int re_tx_list_init (struct rl_softc *); 259#ifdef RE_FIXUP_RX 260static __inline void re_fixup_rx 261 (struct mbuf *); 262#endif 263static int re_rxeof (struct rl_softc *, int *); 264static void re_txeof (struct rl_softc *); 265#ifdef DEVICE_POLLING 266static int re_poll (struct ifnet *, enum poll_cmd, int); 267static int re_poll_locked (struct ifnet *, enum poll_cmd, int); 268#endif 269static int re_intr (void *); 270static void re_intr_msi (void *); 271static void re_tick (void *); 272static void re_int_task (void *, int); 273static void re_start (struct ifnet *); 274static void re_start_locked (struct ifnet *); 275static int re_ioctl (struct ifnet *, u_long, caddr_t); 276static void re_init (void *); 277static void re_init_locked (struct rl_softc *); 278static void re_stop (struct rl_softc *); 279static void re_watchdog (struct rl_softc *); 280static int re_suspend (device_t); 281static int re_resume (device_t); 282static int re_shutdown (device_t); 283static int re_ifmedia_upd (struct ifnet *); 284static void re_ifmedia_sts (struct ifnet *, struct ifmediareq *); 285 286static void re_eeprom_putbyte (struct rl_softc *, int); 287static void re_eeprom_getword (struct rl_softc *, int, u_int16_t *); 288static void re_read_eeprom (struct rl_softc *, caddr_t, int, int); 289static int re_gmii_readreg (device_t, int, int); 290static int re_gmii_writereg (device_t, int, int, int); 291 292static int re_miibus_readreg (device_t, int, int); 293static int re_miibus_writereg (device_t, int, int, int); 294static void re_miibus_statchg (device_t); 295 296static void re_set_jumbo (struct rl_softc *, int); 297static void re_set_rxmode (struct rl_softc *); 298static void re_reset (struct rl_softc *); 299static void re_setwol (struct rl_softc *); 300static void re_clrwol (struct rl_softc *); 301static void re_set_linkspeed (struct rl_softc *); 302 303#ifdef DEV_NETMAP /* see ixgbe.c for details */ 304#include <dev/netmap/if_re_netmap.h> 305#endif /* !DEV_NETMAP */ 306 307#ifdef RE_DIAG 308static int re_diag (struct rl_softc *); 309#endif 310 311static void re_add_sysctls (struct rl_softc *); 312static int re_sysctl_stats (SYSCTL_HANDLER_ARGS); 313static int sysctl_int_range (SYSCTL_HANDLER_ARGS, int, int); 314static int sysctl_hw_re_int_mod (SYSCTL_HANDLER_ARGS); 315 316static device_method_t re_methods[] = { 317 /* Device interface */ 318 DEVMETHOD(device_probe, re_probe), 319 DEVMETHOD(device_attach, re_attach), 320 DEVMETHOD(device_detach, re_detach), 321 DEVMETHOD(device_suspend, re_suspend), 322 DEVMETHOD(device_resume, re_resume), 323 DEVMETHOD(device_shutdown, re_shutdown), 324 325 /* MII interface */ 326 DEVMETHOD(miibus_readreg, re_miibus_readreg), 327 DEVMETHOD(miibus_writereg, re_miibus_writereg), 328 DEVMETHOD(miibus_statchg, re_miibus_statchg), 329 330 DEVMETHOD_END 331}; 332 333static driver_t re_driver = { 334 "re", 335 re_methods, 336 sizeof(struct rl_softc) 337}; 338 339static devclass_t re_devclass; 340 341DRIVER_MODULE(re, pci, re_driver, re_devclass, 0, 0); 342DRIVER_MODULE(miibus, re, miibus_driver, miibus_devclass, 0, 0); 343 344#define EE_SET(x) \ 345 CSR_WRITE_1(sc, RL_EECMD, \ 346 CSR_READ_1(sc, RL_EECMD) | x) 347 348#define EE_CLR(x) \ 349 CSR_WRITE_1(sc, RL_EECMD, \ 350 CSR_READ_1(sc, RL_EECMD) & ~x) 351 352/* 353 * Send a read command and address to the EEPROM, check for ACK. 354 */ 355static void 356re_eeprom_putbyte(struct rl_softc *sc, int addr) 357{ 358 int d, i; 359 360 d = addr | (RL_9346_READ << sc->rl_eewidth); 361 362 /* 363 * Feed in each bit and strobe the clock. 364 */ 365 366 for (i = 1 << (sc->rl_eewidth + 3); i; i >>= 1) { 367 if (d & i) { 368 EE_SET(RL_EE_DATAIN); 369 } else { 370 EE_CLR(RL_EE_DATAIN); 371 } 372 DELAY(100); 373 EE_SET(RL_EE_CLK); 374 DELAY(150); 375 EE_CLR(RL_EE_CLK); 376 DELAY(100); 377 } 378} 379 380/* 381 * Read a word of data stored in the EEPROM at address 'addr.' 382 */ 383static void 384re_eeprom_getword(struct rl_softc *sc, int addr, u_int16_t *dest) 385{ 386 int i; 387 u_int16_t word = 0; 388 389 /* 390 * Send address of word we want to read. 391 */ 392 re_eeprom_putbyte(sc, addr); 393 394 /* 395 * Start reading bits from EEPROM. 396 */ 397 for (i = 0x8000; i; i >>= 1) { 398 EE_SET(RL_EE_CLK); 399 DELAY(100); 400 if (CSR_READ_1(sc, RL_EECMD) & RL_EE_DATAOUT) 401 word |= i; 402 EE_CLR(RL_EE_CLK); 403 DELAY(100); 404 } 405 406 *dest = word; 407} 408 409/* 410 * Read a sequence of words from the EEPROM. 411 */ 412static void 413re_read_eeprom(struct rl_softc *sc, caddr_t dest, int off, int cnt) 414{ 415 int i; 416 u_int16_t word = 0, *ptr; 417 418 CSR_SETBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 419 420 DELAY(100); 421 422 for (i = 0; i < cnt; i++) { 423 CSR_SETBIT_1(sc, RL_EECMD, RL_EE_SEL); 424 re_eeprom_getword(sc, off + i, &word); 425 CSR_CLRBIT_1(sc, RL_EECMD, RL_EE_SEL); 426 ptr = (u_int16_t *)(dest + (i * 2)); 427 *ptr = word; 428 } 429 430 CSR_CLRBIT_1(sc, RL_EECMD, RL_EEMODE_PROGRAM); 431} 432 433static int 434re_gmii_readreg(device_t dev, int phy, int reg) 435{ 436 struct rl_softc *sc; 437 u_int32_t rval; 438 int i; 439 440 sc = device_get_softc(dev); 441 442 /* Let the rgephy driver read the GMEDIASTAT register */ 443 444 if (reg == RL_GMEDIASTAT) { 445 rval = CSR_READ_1(sc, RL_GMEDIASTAT); 446 return (rval); 447 } 448 449 CSR_WRITE_4(sc, RL_PHYAR, reg << 16); 450 451 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 452 rval = CSR_READ_4(sc, RL_PHYAR); 453 if (rval & RL_PHYAR_BUSY) 454 break; 455 DELAY(25); 456 } 457 458 if (i == RL_PHY_TIMEOUT) { 459 device_printf(sc->rl_dev, "PHY read failed\n"); 460 return (0); 461 } 462 463 /* 464 * Controller requires a 20us delay to process next MDIO request. 465 */ 466 DELAY(20); 467 468 return (rval & RL_PHYAR_PHYDATA); 469} 470 471static int 472re_gmii_writereg(device_t dev, int phy, int reg, int data) 473{ 474 struct rl_softc *sc; 475 u_int32_t rval; 476 int i; 477 478 sc = device_get_softc(dev); 479 480 CSR_WRITE_4(sc, RL_PHYAR, (reg << 16) | 481 (data & RL_PHYAR_PHYDATA) | RL_PHYAR_BUSY); 482 483 for (i = 0; i < RL_PHY_TIMEOUT; i++) { 484 rval = CSR_READ_4(sc, RL_PHYAR); 485 if (!(rval & RL_PHYAR_BUSY)) 486 break; 487 DELAY(25); 488 } 489 490 if (i == RL_PHY_TIMEOUT) { 491 device_printf(sc->rl_dev, "PHY write failed\n"); 492 return (0); 493 } 494 495 /* 496 * Controller requires a 20us delay to process next MDIO request. 497 */ 498 DELAY(20); 499 500 return (0); 501} 502 503static int 504re_miibus_readreg(device_t dev, int phy, int reg) 505{ 506 struct rl_softc *sc; 507 u_int16_t rval = 0; 508 u_int16_t re8139_reg = 0; 509 510 sc = device_get_softc(dev); 511 512 if (sc->rl_type == RL_8169) { 513 rval = re_gmii_readreg(dev, phy, reg); 514 return (rval); 515 } 516 517 switch (reg) { 518 case MII_BMCR: 519 re8139_reg = RL_BMCR; 520 break; 521 case MII_BMSR: 522 re8139_reg = RL_BMSR; 523 break; 524 case MII_ANAR: 525 re8139_reg = RL_ANAR; 526 break; 527 case MII_ANER: 528 re8139_reg = RL_ANER; 529 break; 530 case MII_ANLPAR: 531 re8139_reg = RL_LPAR; 532 break; 533 case MII_PHYIDR1: 534 case MII_PHYIDR2: 535 return (0); 536 /* 537 * Allow the rlphy driver to read the media status 538 * register. If we have a link partner which does not 539 * support NWAY, this is the register which will tell 540 * us the results of parallel detection. 541 */ 542 case RL_MEDIASTAT: 543 rval = CSR_READ_1(sc, RL_MEDIASTAT); 544 return (rval); 545 default: 546 device_printf(sc->rl_dev, "bad phy register\n"); 547 return (0); 548 } 549 rval = CSR_READ_2(sc, re8139_reg); 550 if (sc->rl_type == RL_8139CPLUS && re8139_reg == RL_BMCR) { 551 /* 8139C+ has different bit layout. */ 552 rval &= ~(BMCR_LOOP | BMCR_ISO); 553 } 554 return (rval); 555} 556 557static int 558re_miibus_writereg(device_t dev, int phy, int reg, int data) 559{ 560 struct rl_softc *sc; 561 u_int16_t re8139_reg = 0; 562 int rval = 0; 563 564 sc = device_get_softc(dev); 565 566 if (sc->rl_type == RL_8169) { 567 rval = re_gmii_writereg(dev, phy, reg, data); 568 return (rval); 569 } 570 571 switch (reg) { 572 case MII_BMCR: 573 re8139_reg = RL_BMCR; 574 if (sc->rl_type == RL_8139CPLUS) { 575 /* 8139C+ has different bit layout. */ 576 data &= ~(BMCR_LOOP | BMCR_ISO); 577 } 578 break; 579 case MII_BMSR: 580 re8139_reg = RL_BMSR; 581 break; 582 case MII_ANAR: 583 re8139_reg = RL_ANAR; 584 break; 585 case MII_ANER: 586 re8139_reg = RL_ANER; 587 break; 588 case MII_ANLPAR: 589 re8139_reg = RL_LPAR; 590 break; 591 case MII_PHYIDR1: 592 case MII_PHYIDR2: 593 return (0); 594 break; 595 default: 596 device_printf(sc->rl_dev, "bad phy register\n"); 597 return (0); 598 } 599 CSR_WRITE_2(sc, re8139_reg, data); 600 return (0); 601} 602 603static void 604re_miibus_statchg(device_t dev) 605{ 606 struct rl_softc *sc; 607 struct ifnet *ifp; 608 struct mii_data *mii; 609 610 sc = device_get_softc(dev); 611 mii = device_get_softc(sc->rl_miibus); 612 ifp = sc->rl_ifp; 613 if (mii == NULL || ifp == NULL || 614 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 615 return; 616 617 sc->rl_flags &= ~RL_FLAG_LINK; 618 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 619 (IFM_ACTIVE | IFM_AVALID)) { 620 switch (IFM_SUBTYPE(mii->mii_media_active)) { 621 case IFM_10_T: 622 case IFM_100_TX: 623 sc->rl_flags |= RL_FLAG_LINK; 624 break; 625 case IFM_1000_T: 626 if ((sc->rl_flags & RL_FLAG_FASTETHER) != 0) 627 break; 628 sc->rl_flags |= RL_FLAG_LINK; 629 break; 630 default: 631 break; 632 } 633 } 634 /* 635 * RealTek controllers does not provide any interface to 636 * Tx/Rx MACs for resolved speed, duplex and flow-control 637 * parameters. 638 */ 639} 640 641/* 642 * Set the RX configuration and 64-bit multicast hash filter. 643 */ 644static void 645re_set_rxmode(struct rl_softc *sc) 646{ 647 struct ifnet *ifp; 648 struct ifmultiaddr *ifma; 649 uint32_t hashes[2] = { 0, 0 }; 650 uint32_t h, rxfilt; 651 652 RL_LOCK_ASSERT(sc); 653 654 ifp = sc->rl_ifp; 655 656 rxfilt = RL_RXCFG_CONFIG | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_BROAD; 657 658 if (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC)) { 659 if (ifp->if_flags & IFF_PROMISC) 660 rxfilt |= RL_RXCFG_RX_ALLPHYS; 661 /* 662 * Unlike other hardwares, we have to explicitly set 663 * RL_RXCFG_RX_MULTI to receive multicast frames in 664 * promiscuous mode. 665 */ 666 rxfilt |= RL_RXCFG_RX_MULTI; 667 hashes[0] = hashes[1] = 0xffffffff; 668 goto done; 669 } 670 671 if_maddr_rlock(ifp); 672 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 673 if (ifma->ifma_addr->sa_family != AF_LINK) 674 continue; 675 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 676 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 677 if (h < 32) 678 hashes[0] |= (1 << h); 679 else 680 hashes[1] |= (1 << (h - 32)); 681 } 682 if_maddr_runlock(ifp); 683 684 if (hashes[0] != 0 || hashes[1] != 0) { 685 /* 686 * For some unfathomable reason, RealTek decided to 687 * reverse the order of the multicast hash registers 688 * in the PCI Express parts. This means we have to 689 * write the hash pattern in reverse order for those 690 * devices. 691 */ 692 if ((sc->rl_flags & RL_FLAG_PCIE) != 0) { 693 h = bswap32(hashes[0]); 694 hashes[0] = bswap32(hashes[1]); 695 hashes[1] = h; 696 } 697 rxfilt |= RL_RXCFG_RX_MULTI; 698 } 699 700done: 701 CSR_WRITE_4(sc, RL_MAR0, hashes[0]); 702 CSR_WRITE_4(sc, RL_MAR4, hashes[1]); 703 CSR_WRITE_4(sc, RL_RXCFG, rxfilt); 704} 705 706static void 707re_reset(struct rl_softc *sc) 708{ 709 int i; 710 711 RL_LOCK_ASSERT(sc); 712 713 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RESET); 714 715 for (i = 0; i < RL_TIMEOUT; i++) { 716 DELAY(10); 717 if (!(CSR_READ_1(sc, RL_COMMAND) & RL_CMD_RESET)) 718 break; 719 } 720 if (i == RL_TIMEOUT) 721 device_printf(sc->rl_dev, "reset never completed!\n"); 722 723 if ((sc->rl_flags & RL_FLAG_MACRESET) != 0) 724 CSR_WRITE_1(sc, 0x82, 1); 725 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169S) 726 re_gmii_writereg(sc->rl_dev, 1, 0x0b, 0); 727} 728 729#ifdef RE_DIAG 730 731/* 732 * The following routine is designed to test for a defect on some 733 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 734 * lines connected to the bus, however for a 32-bit only card, they 735 * should be pulled high. The result of this defect is that the 736 * NIC will not work right if you plug it into a 64-bit slot: DMA 737 * operations will be done with 64-bit transfers, which will fail 738 * because the 64-bit data lines aren't connected. 739 * 740 * There's no way to work around this (short of talking a soldering 741 * iron to the board), however we can detect it. The method we use 742 * here is to put the NIC into digital loopback mode, set the receiver 743 * to promiscuous mode, and then try to send a frame. We then compare 744 * the frame data we sent to what was received. If the data matches, 745 * then the NIC is working correctly, otherwise we know the user has 746 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 747 * slot. In the latter case, there's no way the NIC can work correctly, 748 * so we print out a message on the console and abort the device attach. 749 */ 750 751static int 752re_diag(struct rl_softc *sc) 753{ 754 struct ifnet *ifp = sc->rl_ifp; 755 struct mbuf *m0; 756 struct ether_header *eh; 757 struct rl_desc *cur_rx; 758 u_int16_t status; 759 u_int32_t rxstat; 760 int total_len, i, error = 0, phyaddr; 761 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 762 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 763 764 /* Allocate a single mbuf */ 765 MGETHDR(m0, M_NOWAIT, MT_DATA); 766 if (m0 == NULL) 767 return (ENOBUFS); 768 769 RL_LOCK(sc); 770 771 /* 772 * Initialize the NIC in test mode. This sets the chip up 773 * so that it can send and receive frames, but performs the 774 * following special functions: 775 * - Puts receiver in promiscuous mode 776 * - Enables digital loopback mode 777 * - Leaves interrupts turned off 778 */ 779 780 ifp->if_flags |= IFF_PROMISC; 781 sc->rl_testmode = 1; 782 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 783 re_init_locked(sc); 784 sc->rl_flags |= RL_FLAG_LINK; 785 if (sc->rl_type == RL_8169) 786 phyaddr = 1; 787 else 788 phyaddr = 0; 789 790 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_RESET); 791 for (i = 0; i < RL_TIMEOUT; i++) { 792 status = re_miibus_readreg(sc->rl_dev, phyaddr, MII_BMCR); 793 if (!(status & BMCR_RESET)) 794 break; 795 } 796 797 re_miibus_writereg(sc->rl_dev, phyaddr, MII_BMCR, BMCR_LOOP); 798 CSR_WRITE_2(sc, RL_ISR, RL_INTRS); 799 800 DELAY(100000); 801 802 /* Put some data in the mbuf */ 803 804 eh = mtod(m0, struct ether_header *); 805 bcopy ((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 806 bcopy ((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 807 eh->ether_type = htons(ETHERTYPE_IP); 808 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 809 810 /* 811 * Queue the packet, start transmission. 812 * Note: IF_HANDOFF() ultimately calls re_start() for us. 813 */ 814 815 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 816 RL_UNLOCK(sc); 817 /* XXX: re_diag must not be called when in ALTQ mode */ 818 IF_HANDOFF(&ifp->if_snd, m0, ifp); 819 RL_LOCK(sc); 820 m0 = NULL; 821 822 /* Wait for it to propagate through the chip */ 823 824 DELAY(100000); 825 for (i = 0; i < RL_TIMEOUT; i++) { 826 status = CSR_READ_2(sc, RL_ISR); 827 CSR_WRITE_2(sc, RL_ISR, status); 828 if ((status & (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) == 829 (RL_ISR_TIMEOUT_EXPIRED|RL_ISR_RX_OK)) 830 break; 831 DELAY(10); 832 } 833 834 if (i == RL_TIMEOUT) { 835 device_printf(sc->rl_dev, 836 "diagnostic failed, failed to receive packet in" 837 " loopback mode\n"); 838 error = EIO; 839 goto done; 840 } 841 842 /* 843 * The packet should have been dumped into the first 844 * entry in the RX DMA ring. Grab it from there. 845 */ 846 847 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 848 sc->rl_ldata.rl_rx_list_map, 849 BUS_DMASYNC_POSTREAD); 850 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 851 sc->rl_ldata.rl_rx_desc[0].rx_dmamap, 852 BUS_DMASYNC_POSTREAD); 853 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 854 sc->rl_ldata.rl_rx_desc[0].rx_dmamap); 855 856 m0 = sc->rl_ldata.rl_rx_desc[0].rx_m; 857 sc->rl_ldata.rl_rx_desc[0].rx_m = NULL; 858 eh = mtod(m0, struct ether_header *); 859 860 cur_rx = &sc->rl_ldata.rl_rx_list[0]; 861 total_len = RL_RXBYTES(cur_rx); 862 rxstat = le32toh(cur_rx->rl_cmdstat); 863 864 if (total_len != ETHER_MIN_LEN) { 865 device_printf(sc->rl_dev, 866 "diagnostic failed, received short packet\n"); 867 error = EIO; 868 goto done; 869 } 870 871 /* Test that the received packet data matches what we sent. */ 872 873 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 874 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 875 ntohs(eh->ether_type) != ETHERTYPE_IP) { 876 device_printf(sc->rl_dev, "WARNING, DMA FAILURE!\n"); 877 device_printf(sc->rl_dev, "expected TX data: %6D/%6D/0x%x\n", 878 dst, ":", src, ":", ETHERTYPE_IP); 879 device_printf(sc->rl_dev, "received RX data: %6D/%6D/0x%x\n", 880 eh->ether_dhost, ":", eh->ether_shost, ":", 881 ntohs(eh->ether_type)); 882 device_printf(sc->rl_dev, "You may have a defective 32-bit " 883 "NIC plugged into a 64-bit PCI slot.\n"); 884 device_printf(sc->rl_dev, "Please re-install the NIC in a " 885 "32-bit slot for proper operation.\n"); 886 device_printf(sc->rl_dev, "Read the re(4) man page for more " 887 "details.\n"); 888 error = EIO; 889 } 890 891done: 892 /* Turn interface off, release resources */ 893 894 sc->rl_testmode = 0; 895 sc->rl_flags &= ~RL_FLAG_LINK; 896 ifp->if_flags &= ~IFF_PROMISC; 897 re_stop(sc); 898 if (m0 != NULL) 899 m_freem(m0); 900 901 RL_UNLOCK(sc); 902 903 return (error); 904} 905 906#endif 907 908/* 909 * Probe for a RealTek 8139C+/8169/8110 chip. Check the PCI vendor and device 910 * IDs against our list and return a device name if we find a match. 911 */ 912static int 913re_probe(device_t dev) 914{ 915 const struct rl_type *t; 916 uint16_t devid, vendor; 917 uint16_t revid, sdevid; 918 int i; 919 920 vendor = pci_get_vendor(dev); 921 devid = pci_get_device(dev); 922 revid = pci_get_revid(dev); 923 sdevid = pci_get_subdevice(dev); 924 925 if (vendor == LINKSYS_VENDORID && devid == LINKSYS_DEVICEID_EG1032) { 926 if (sdevid != LINKSYS_SUBDEVICE_EG1032_REV3) { 927 /* 928 * Only attach to rev. 3 of the Linksys EG1032 adapter. 929 * Rev. 2 is supported by sk(4). 930 */ 931 return (ENXIO); 932 } 933 } 934 935 if (vendor == RT_VENDORID && devid == RT_DEVICEID_8139) { 936 if (revid != 0x20) { 937 /* 8139, let rl(4) take care of this device. */ 938 return (ENXIO); 939 } 940 } 941 942 t = re_devs; 943 for (i = 0; i < sizeof(re_devs) / sizeof(re_devs[0]); i++, t++) { 944 if (vendor == t->rl_vid && devid == t->rl_did) { 945 device_set_desc(dev, t->rl_name); 946 return (BUS_PROBE_DEFAULT); 947 } 948 } 949 950 return (ENXIO); 951} 952 953/* 954 * Map a single buffer address. 955 */ 956 957static void 958re_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) 959{ 960 bus_addr_t *addr; 961 962 if (error) 963 return; 964 965 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 966 addr = arg; 967 *addr = segs->ds_addr; 968} 969 970static int 971re_allocmem(device_t dev, struct rl_softc *sc) 972{ 973 bus_addr_t lowaddr; 974 bus_size_t rx_list_size, tx_list_size; 975 int error; 976 int i; 977 978 rx_list_size = sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc); 979 tx_list_size = sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc); 980 981 /* 982 * Allocate the parent bus DMA tag appropriate for PCI. 983 * In order to use DAC, RL_CPLUSCMD_PCI_DAC bit of RL_CPLUS_CMD 984 * register should be set. However some RealTek chips are known 985 * to be buggy on DAC handling, therefore disable DAC by limiting 986 * DMA address space to 32bit. PCIe variants of RealTek chips 987 * may not have the limitation. 988 */ 989 lowaddr = BUS_SPACE_MAXADDR; 990 if ((sc->rl_flags & RL_FLAG_PCIE) == 0) 991 lowaddr = BUS_SPACE_MAXADDR_32BIT; 992 error = bus_dma_tag_create(bus_get_dma_tag(dev), 1, 0, 993 lowaddr, BUS_SPACE_MAXADDR, NULL, NULL, 994 BUS_SPACE_MAXSIZE_32BIT, 0, BUS_SPACE_MAXSIZE_32BIT, 0, 995 NULL, NULL, &sc->rl_parent_tag); 996 if (error) { 997 device_printf(dev, "could not allocate parent DMA tag\n"); 998 return (error); 999 } 1000 1001 /* 1002 * Allocate map for TX mbufs. 1003 */ 1004 error = bus_dma_tag_create(sc->rl_parent_tag, 1, 0, 1005 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, 1006 NULL, MCLBYTES * RL_NTXSEGS, RL_NTXSEGS, 4096, 0, 1007 NULL, NULL, &sc->rl_ldata.rl_tx_mtag); 1008 if (error) { 1009 device_printf(dev, "could not allocate TX DMA tag\n"); 1010 return (error); 1011 } 1012 1013 /* 1014 * Allocate map for RX mbufs. 1015 */ 1016 1017 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1018 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 1019 0, BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1020 MJUM9BYTES, 1, MJUM9BYTES, 0, NULL, NULL, 1021 &sc->rl_ldata.rl_jrx_mtag); 1022 if (error) { 1023 device_printf(dev, 1024 "could not allocate jumbo RX DMA tag\n"); 1025 return (error); 1026 } 1027 } 1028 error = bus_dma_tag_create(sc->rl_parent_tag, sizeof(uint64_t), 0, 1029 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1030 MCLBYTES, 1, MCLBYTES, 0, NULL, NULL, &sc->rl_ldata.rl_rx_mtag); 1031 if (error) { 1032 device_printf(dev, "could not allocate RX DMA tag\n"); 1033 return (error); 1034 } 1035 1036 /* 1037 * Allocate map for TX descriptor list. 1038 */ 1039 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1040 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1041 NULL, tx_list_size, 1, tx_list_size, 0, 1042 NULL, NULL, &sc->rl_ldata.rl_tx_list_tag); 1043 if (error) { 1044 device_printf(dev, "could not allocate TX DMA ring tag\n"); 1045 return (error); 1046 } 1047 1048 /* Allocate DMA'able memory for the TX ring */ 1049 1050 error = bus_dmamem_alloc(sc->rl_ldata.rl_tx_list_tag, 1051 (void **)&sc->rl_ldata.rl_tx_list, 1052 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1053 &sc->rl_ldata.rl_tx_list_map); 1054 if (error) { 1055 device_printf(dev, "could not allocate TX DMA ring\n"); 1056 return (error); 1057 } 1058 1059 /* Load the map for the TX ring. */ 1060 1061 sc->rl_ldata.rl_tx_list_addr = 0; 1062 error = bus_dmamap_load(sc->rl_ldata.rl_tx_list_tag, 1063 sc->rl_ldata.rl_tx_list_map, sc->rl_ldata.rl_tx_list, 1064 tx_list_size, re_dma_map_addr, 1065 &sc->rl_ldata.rl_tx_list_addr, BUS_DMA_NOWAIT); 1066 if (error != 0 || sc->rl_ldata.rl_tx_list_addr == 0) { 1067 device_printf(dev, "could not load TX DMA ring\n"); 1068 return (ENOMEM); 1069 } 1070 1071 /* Create DMA maps for TX buffers */ 1072 1073 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1074 error = bus_dmamap_create(sc->rl_ldata.rl_tx_mtag, 0, 1075 &sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1076 if (error) { 1077 device_printf(dev, "could not create DMA map for TX\n"); 1078 return (error); 1079 } 1080 } 1081 1082 /* 1083 * Allocate map for RX descriptor list. 1084 */ 1085 error = bus_dma_tag_create(sc->rl_parent_tag, RL_RING_ALIGN, 1086 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 1087 NULL, rx_list_size, 1, rx_list_size, 0, 1088 NULL, NULL, &sc->rl_ldata.rl_rx_list_tag); 1089 if (error) { 1090 device_printf(dev, "could not create RX DMA ring tag\n"); 1091 return (error); 1092 } 1093 1094 /* Allocate DMA'able memory for the RX ring */ 1095 1096 error = bus_dmamem_alloc(sc->rl_ldata.rl_rx_list_tag, 1097 (void **)&sc->rl_ldata.rl_rx_list, 1098 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1099 &sc->rl_ldata.rl_rx_list_map); 1100 if (error) { 1101 device_printf(dev, "could not allocate RX DMA ring\n"); 1102 return (error); 1103 } 1104 1105 /* Load the map for the RX ring. */ 1106 1107 sc->rl_ldata.rl_rx_list_addr = 0; 1108 error = bus_dmamap_load(sc->rl_ldata.rl_rx_list_tag, 1109 sc->rl_ldata.rl_rx_list_map, sc->rl_ldata.rl_rx_list, 1110 rx_list_size, re_dma_map_addr, 1111 &sc->rl_ldata.rl_rx_list_addr, BUS_DMA_NOWAIT); 1112 if (error != 0 || sc->rl_ldata.rl_rx_list_addr == 0) { 1113 device_printf(dev, "could not load RX DMA ring\n"); 1114 return (ENOMEM); 1115 } 1116 1117 /* Create DMA maps for RX buffers */ 1118 1119 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 1120 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1121 &sc->rl_ldata.rl_jrx_sparemap); 1122 if (error) { 1123 device_printf(dev, 1124 "could not create spare DMA map for jumbo RX\n"); 1125 return (error); 1126 } 1127 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1128 error = bus_dmamap_create(sc->rl_ldata.rl_jrx_mtag, 0, 1129 &sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1130 if (error) { 1131 device_printf(dev, 1132 "could not create DMA map for jumbo RX\n"); 1133 return (error); 1134 } 1135 } 1136 } 1137 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1138 &sc->rl_ldata.rl_rx_sparemap); 1139 if (error) { 1140 device_printf(dev, "could not create spare DMA map for RX\n"); 1141 return (error); 1142 } 1143 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1144 error = bus_dmamap_create(sc->rl_ldata.rl_rx_mtag, 0, 1145 &sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1146 if (error) { 1147 device_printf(dev, "could not create DMA map for RX\n"); 1148 return (error); 1149 } 1150 } 1151 1152 /* Create DMA map for statistics. */ 1153 error = bus_dma_tag_create(sc->rl_parent_tag, RL_DUMP_ALIGN, 0, 1154 BUS_SPACE_MAXADDR, BUS_SPACE_MAXADDR, NULL, NULL, 1155 sizeof(struct rl_stats), 1, sizeof(struct rl_stats), 0, NULL, NULL, 1156 &sc->rl_ldata.rl_stag); 1157 if (error) { 1158 device_printf(dev, "could not create statistics DMA tag\n"); 1159 return (error); 1160 } 1161 /* Allocate DMA'able memory for statistics. */ 1162 error = bus_dmamem_alloc(sc->rl_ldata.rl_stag, 1163 (void **)&sc->rl_ldata.rl_stats, 1164 BUS_DMA_WAITOK | BUS_DMA_COHERENT | BUS_DMA_ZERO, 1165 &sc->rl_ldata.rl_smap); 1166 if (error) { 1167 device_printf(dev, 1168 "could not allocate statistics DMA memory\n"); 1169 return (error); 1170 } 1171 /* Load the map for statistics. */ 1172 sc->rl_ldata.rl_stats_addr = 0; 1173 error = bus_dmamap_load(sc->rl_ldata.rl_stag, sc->rl_ldata.rl_smap, 1174 sc->rl_ldata.rl_stats, sizeof(struct rl_stats), re_dma_map_addr, 1175 &sc->rl_ldata.rl_stats_addr, BUS_DMA_NOWAIT); 1176 if (error != 0 || sc->rl_ldata.rl_stats_addr == 0) { 1177 device_printf(dev, "could not load statistics DMA memory\n"); 1178 return (ENOMEM); 1179 } 1180 1181 return (0); 1182} 1183 1184/* 1185 * Attach the interface. Allocate softc structures, do ifmedia 1186 * setup and ethernet/BPF attach. 1187 */ 1188static int 1189re_attach(device_t dev) 1190{ 1191 u_char eaddr[ETHER_ADDR_LEN]; 1192 u_int16_t as[ETHER_ADDR_LEN / 2]; 1193 struct rl_softc *sc; 1194 struct ifnet *ifp; 1195 const struct rl_hwrev *hw_rev; 1196 u_int32_t cap, ctl; 1197 int hwrev; 1198 u_int16_t devid, re_did = 0; 1199 int error = 0, i, phy, rid; 1200 int msic, msixc, reg; 1201 uint8_t cfg; 1202 1203 sc = device_get_softc(dev); 1204 sc->rl_dev = dev; 1205 1206 mtx_init(&sc->rl_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 1207 MTX_DEF); 1208 callout_init_mtx(&sc->rl_stat_callout, &sc->rl_mtx, 0); 1209 1210 /* 1211 * Map control/status registers. 1212 */ 1213 pci_enable_busmaster(dev); 1214 1215 devid = pci_get_device(dev); 1216 /* 1217 * Prefer memory space register mapping over IO space. 1218 * Because RTL8169SC does not seem to work when memory mapping 1219 * is used always activate io mapping. 1220 */ 1221 if (devid == RT_DEVICEID_8169SC) 1222 prefer_iomap = 1; 1223 if (prefer_iomap == 0) { 1224 sc->rl_res_id = PCIR_BAR(1); 1225 sc->rl_res_type = SYS_RES_MEMORY; 1226 /* RTL8168/8101E seems to use different BARs. */ 1227 if (devid == RT_DEVICEID_8168 || devid == RT_DEVICEID_8101E) 1228 sc->rl_res_id = PCIR_BAR(2); 1229 } else { 1230 sc->rl_res_id = PCIR_BAR(0); 1231 sc->rl_res_type = SYS_RES_IOPORT; 1232 } 1233 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1234 &sc->rl_res_id, RF_ACTIVE); 1235 if (sc->rl_res == NULL && prefer_iomap == 0) { 1236 sc->rl_res_id = PCIR_BAR(0); 1237 sc->rl_res_type = SYS_RES_IOPORT; 1238 sc->rl_res = bus_alloc_resource_any(dev, sc->rl_res_type, 1239 &sc->rl_res_id, RF_ACTIVE); 1240 } 1241 if (sc->rl_res == NULL) { 1242 device_printf(dev, "couldn't map ports/memory\n"); 1243 error = ENXIO; 1244 goto fail; 1245 } 1246 1247 sc->rl_btag = rman_get_bustag(sc->rl_res); 1248 sc->rl_bhandle = rman_get_bushandle(sc->rl_res); 1249 1250 msic = pci_msi_count(dev); 1251 msixc = pci_msix_count(dev); 1252 if (pci_find_cap(dev, PCIY_EXPRESS, ®) == 0) { 1253 sc->rl_flags |= RL_FLAG_PCIE; 1254 sc->rl_expcap = reg; 1255 } 1256 if (bootverbose) { 1257 device_printf(dev, "MSI count : %d\n", msic); 1258 device_printf(dev, "MSI-X count : %d\n", msixc); 1259 } 1260 if (msix_disable > 0) 1261 msixc = 0; 1262 if (msi_disable > 0) 1263 msic = 0; 1264 /* Prefer MSI-X to MSI. */ 1265 if (msixc > 0) { 1266 msixc = 1; 1267 rid = PCIR_BAR(4); 1268 sc->rl_res_pba = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 1269 &rid, RF_ACTIVE); 1270 if (sc->rl_res_pba == NULL) { 1271 device_printf(sc->rl_dev, 1272 "could not allocate MSI-X PBA resource\n"); 1273 } 1274 if (sc->rl_res_pba != NULL && 1275 pci_alloc_msix(dev, &msixc) == 0) { 1276 if (msixc == 1) { 1277 device_printf(dev, "Using %d MSI-X message\n", 1278 msixc); 1279 sc->rl_flags |= RL_FLAG_MSIX; 1280 } else 1281 pci_release_msi(dev); 1282 } 1283 if ((sc->rl_flags & RL_FLAG_MSIX) == 0) { 1284 if (sc->rl_res_pba != NULL) 1285 bus_release_resource(dev, SYS_RES_MEMORY, rid, 1286 sc->rl_res_pba); 1287 sc->rl_res_pba = NULL; 1288 msixc = 0; 1289 } 1290 } 1291 /* Prefer MSI to INTx. */ 1292 if (msixc == 0 && msic > 0) { 1293 msic = 1; 1294 if (pci_alloc_msi(dev, &msic) == 0) { 1295 if (msic == RL_MSI_MESSAGES) { 1296 device_printf(dev, "Using %d MSI message\n", 1297 msic); 1298 sc->rl_flags |= RL_FLAG_MSI; 1299 /* Explicitly set MSI enable bit. */ 1300 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1301 cfg = CSR_READ_1(sc, RL_CFG2); 1302 cfg |= RL_CFG2_MSI; 1303 CSR_WRITE_1(sc, RL_CFG2, cfg); 1304 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1305 } else 1306 pci_release_msi(dev); 1307 } 1308 if ((sc->rl_flags & RL_FLAG_MSI) == 0) 1309 msic = 0; 1310 } 1311 1312 /* Allocate interrupt */ 1313 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) { 1314 rid = 0; 1315 sc->rl_irq[0] = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 1316 RF_SHAREABLE | RF_ACTIVE); 1317 if (sc->rl_irq[0] == NULL) { 1318 device_printf(dev, "couldn't allocate IRQ resources\n"); 1319 error = ENXIO; 1320 goto fail; 1321 } 1322 } else { 1323 for (i = 0, rid = 1; i < RL_MSI_MESSAGES; i++, rid++) { 1324 sc->rl_irq[i] = bus_alloc_resource_any(dev, 1325 SYS_RES_IRQ, &rid, RF_ACTIVE); 1326 if (sc->rl_irq[i] == NULL) { 1327 device_printf(dev, 1328 "couldn't allocate IRQ resources for " 1329 "message %d\n", rid); 1330 error = ENXIO; 1331 goto fail; 1332 } 1333 } 1334 } 1335 1336 if ((sc->rl_flags & RL_FLAG_MSI) == 0) { 1337 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1338 cfg = CSR_READ_1(sc, RL_CFG2); 1339 if ((cfg & RL_CFG2_MSI) != 0) { 1340 device_printf(dev, "turning off MSI enable bit.\n"); 1341 cfg &= ~RL_CFG2_MSI; 1342 CSR_WRITE_1(sc, RL_CFG2, cfg); 1343 } 1344 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1345 } 1346 1347 /* Disable ASPM L0S/L1. */ 1348 if (sc->rl_expcap != 0) { 1349 cap = pci_read_config(dev, sc->rl_expcap + 1350 PCIER_LINK_CAP, 2); 1351 if ((cap & PCIEM_LINK_CAP_ASPM) != 0) { 1352 ctl = pci_read_config(dev, sc->rl_expcap + 1353 PCIER_LINK_CTL, 2); 1354 if ((ctl & PCIEM_LINK_CTL_ASPMC) != 0) { 1355 ctl &= ~PCIEM_LINK_CTL_ASPMC; 1356 pci_write_config(dev, sc->rl_expcap + 1357 PCIER_LINK_CTL, ctl, 2); 1358 device_printf(dev, "ASPM disabled\n"); 1359 } 1360 } else 1361 device_printf(dev, "no ASPM capability\n"); 1362 } 1363 1364 hw_rev = re_hwrevs; 1365 hwrev = CSR_READ_4(sc, RL_TXCFG); 1366 switch (hwrev & 0x70000000) { 1367 case 0x00000000: 1368 case 0x10000000: 1369 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0xfc800000); 1370 hwrev &= (RL_TXCFG_HWREV | 0x80000000); 1371 break; 1372 default: 1373 device_printf(dev, "Chip rev. 0x%08x\n", hwrev & 0x7c800000); 1374 sc->rl_macrev = hwrev & 0x00700000; 1375 hwrev &= RL_TXCFG_HWREV; 1376 break; 1377 } 1378 device_printf(dev, "MAC rev. 0x%08x\n", sc->rl_macrev); 1379 while (hw_rev->rl_desc != NULL) { 1380 if (hw_rev->rl_rev == hwrev) { 1381 sc->rl_type = hw_rev->rl_type; 1382 sc->rl_hwrev = hw_rev; 1383 break; 1384 } 1385 hw_rev++; 1386 } 1387 if (hw_rev->rl_desc == NULL) { 1388 device_printf(dev, "Unknown H/W revision: 0x%08x\n", hwrev); 1389 error = ENXIO; 1390 goto fail; 1391 } 1392 1393 switch (hw_rev->rl_rev) { 1394 case RL_HWREV_8139CPLUS: 1395 sc->rl_flags |= RL_FLAG_FASTETHER | RL_FLAG_AUTOPAD; 1396 break; 1397 case RL_HWREV_8100E: 1398 case RL_HWREV_8101E: 1399 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_FASTETHER; 1400 break; 1401 case RL_HWREV_8102E: 1402 case RL_HWREV_8102EL: 1403 case RL_HWREV_8102EL_SPIN1: 1404 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1405 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1406 RL_FLAG_AUTOPAD; 1407 break; 1408 case RL_HWREV_8103E: 1409 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | RL_FLAG_DESCV2 | 1410 RL_FLAG_MACSTAT | RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | 1411 RL_FLAG_AUTOPAD | RL_FLAG_MACSLEEP; 1412 break; 1413 case RL_HWREV_8401E: 1414 case RL_HWREV_8105E: 1415 case RL_HWREV_8105E_SPIN1: 1416 case RL_HWREV_8106E: 1417 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1418 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1419 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD; 1420 break; 1421 case RL_HWREV_8402: 1422 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1423 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1424 RL_FLAG_FASTETHER | RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | 1425 RL_FLAG_CMDSTOP_WAIT_TXQ; 1426 break; 1427 case RL_HWREV_8168B_SPIN1: 1428 case RL_HWREV_8168B_SPIN2: 1429 sc->rl_flags |= RL_FLAG_WOLRXENB; 1430 /* FALLTHROUGH */ 1431 case RL_HWREV_8168B_SPIN3: 1432 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_MACSTAT; 1433 break; 1434 case RL_HWREV_8168C_SPIN2: 1435 sc->rl_flags |= RL_FLAG_MACSLEEP; 1436 /* FALLTHROUGH */ 1437 case RL_HWREV_8168C: 1438 if (sc->rl_macrev == 0x00200000) 1439 sc->rl_flags |= RL_FLAG_MACSLEEP; 1440 /* FALLTHROUGH */ 1441 case RL_HWREV_8168CP: 1442 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1443 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1444 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK; 1445 break; 1446 case RL_HWREV_8168D: 1447 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1448 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1449 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1450 RL_FLAG_WOL_MANLINK; 1451 break; 1452 case RL_HWREV_8168DP: 1453 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1454 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_AUTOPAD | 1455 RL_FLAG_JUMBOV2 | RL_FLAG_WAIT_TXPOLL | RL_FLAG_WOL_MANLINK; 1456 break; 1457 case RL_HWREV_8168E: 1458 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PHYWAKE_PM | 1459 RL_FLAG_PAR | RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | 1460 RL_FLAG_CMDSTOP | RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1461 RL_FLAG_WOL_MANLINK; 1462 break; 1463 case RL_HWREV_8168E_VL: 1464 case RL_HWREV_8168F: 1465 case RL_HWREV_8168G: 1466 case RL_HWREV_8411: 1467 case RL_HWREV_8411B: 1468 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1469 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1470 RL_FLAG_AUTOPAD | RL_FLAG_JUMBOV2 | 1471 RL_FLAG_CMDSTOP_WAIT_TXQ | RL_FLAG_WOL_MANLINK; 1472 break; 1473 case RL_HWREV_8168GU: 1474 if (pci_get_device(dev) == RT_DEVICEID_8101E) { 1475 /* RTL8106EUS */ 1476 sc->rl_flags |= RL_FLAG_FASTETHER; 1477 } else 1478 sc->rl_flags |= RL_FLAG_JUMBOV2 | RL_FLAG_WOL_MANLINK; 1479 1480 sc->rl_flags |= RL_FLAG_PHYWAKE | RL_FLAG_PAR | 1481 RL_FLAG_DESCV2 | RL_FLAG_MACSTAT | RL_FLAG_CMDSTOP | 1482 RL_FLAG_AUTOPAD | RL_FLAG_CMDSTOP_WAIT_TXQ; 1483 break; 1484 case RL_HWREV_8169_8110SB: 1485 case RL_HWREV_8169_8110SBL: 1486 case RL_HWREV_8169_8110SC: 1487 case RL_HWREV_8169_8110SCE: 1488 sc->rl_flags |= RL_FLAG_PHYWAKE; 1489 /* FALLTHROUGH */ 1490 case RL_HWREV_8169: 1491 case RL_HWREV_8169S: 1492 case RL_HWREV_8110S: 1493 sc->rl_flags |= RL_FLAG_MACRESET; 1494 break; 1495 default: 1496 break; 1497 } 1498 1499 if (sc->rl_hwrev->rl_rev == RL_HWREV_8139CPLUS) { 1500 sc->rl_cfg0 = RL_8139_CFG0; 1501 sc->rl_cfg1 = RL_8139_CFG1; 1502 sc->rl_cfg2 = 0; 1503 sc->rl_cfg3 = RL_8139_CFG3; 1504 sc->rl_cfg4 = RL_8139_CFG4; 1505 sc->rl_cfg5 = RL_8139_CFG5; 1506 } else { 1507 sc->rl_cfg0 = RL_CFG0; 1508 sc->rl_cfg1 = RL_CFG1; 1509 sc->rl_cfg2 = RL_CFG2; 1510 sc->rl_cfg3 = RL_CFG3; 1511 sc->rl_cfg4 = RL_CFG4; 1512 sc->rl_cfg5 = RL_CFG5; 1513 } 1514 1515 /* Reset the adapter. */ 1516 RL_LOCK(sc); 1517 re_reset(sc); 1518 RL_UNLOCK(sc); 1519 1520 /* Enable PME. */ 1521 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 1522 cfg = CSR_READ_1(sc, sc->rl_cfg1); 1523 cfg |= RL_CFG1_PME; 1524 CSR_WRITE_1(sc, sc->rl_cfg1, cfg); 1525 cfg = CSR_READ_1(sc, sc->rl_cfg5); 1526 cfg &= RL_CFG5_PME_STS; 1527 CSR_WRITE_1(sc, sc->rl_cfg5, cfg); 1528 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 1529 1530 if ((sc->rl_flags & RL_FLAG_PAR) != 0) { 1531 /* 1532 * XXX Should have a better way to extract station 1533 * address from EEPROM. 1534 */ 1535 for (i = 0; i < ETHER_ADDR_LEN; i++) 1536 eaddr[i] = CSR_READ_1(sc, RL_IDR0 + i); 1537 } else { 1538 sc->rl_eewidth = RL_9356_ADDR_LEN; 1539 re_read_eeprom(sc, (caddr_t)&re_did, 0, 1); 1540 if (re_did != 0x8129) 1541 sc->rl_eewidth = RL_9346_ADDR_LEN; 1542 1543 /* 1544 * Get station address from the EEPROM. 1545 */ 1546 re_read_eeprom(sc, (caddr_t)as, RL_EE_EADDR, 3); 1547 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) 1548 as[i] = le16toh(as[i]); 1549 bcopy(as, eaddr, ETHER_ADDR_LEN); 1550 } 1551 1552 if (sc->rl_type == RL_8169) { 1553 /* Set RX length mask and number of descriptors. */ 1554 sc->rl_rxlenmask = RL_RDESC_STAT_GFRAGLEN; 1555 sc->rl_txstart = RL_GTXSTART; 1556 sc->rl_ldata.rl_tx_desc_cnt = RL_8169_TX_DESC_CNT; 1557 sc->rl_ldata.rl_rx_desc_cnt = RL_8169_RX_DESC_CNT; 1558 } else { 1559 /* Set RX length mask and number of descriptors. */ 1560 sc->rl_rxlenmask = RL_RDESC_STAT_FRAGLEN; 1561 sc->rl_txstart = RL_TXSTART; 1562 sc->rl_ldata.rl_tx_desc_cnt = RL_8139_TX_DESC_CNT; 1563 sc->rl_ldata.rl_rx_desc_cnt = RL_8139_RX_DESC_CNT; 1564 } 1565 1566 error = re_allocmem(dev, sc); 1567 if (error) 1568 goto fail; 1569 re_add_sysctls(sc); 1570 1571 ifp = sc->rl_ifp = if_alloc(IFT_ETHER); 1572 if (ifp == NULL) { 1573 device_printf(dev, "can not if_alloc()\n"); 1574 error = ENOSPC; 1575 goto fail; 1576 } 1577 1578 /* Take controller out of deep sleep mode. */ 1579 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 1580 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 1581 CSR_WRITE_1(sc, RL_GPIO, 1582 CSR_READ_1(sc, RL_GPIO) | 0x01); 1583 else 1584 CSR_WRITE_1(sc, RL_GPIO, 1585 CSR_READ_1(sc, RL_GPIO) & ~0x01); 1586 } 1587 1588 /* Take PHY out of power down mode. */ 1589 if ((sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) { 1590 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) | 0x80); 1591 if (hw_rev->rl_rev == RL_HWREV_8401E) 1592 CSR_WRITE_1(sc, 0xD1, CSR_READ_1(sc, 0xD1) & ~0x08); 1593 } 1594 if ((sc->rl_flags & RL_FLAG_PHYWAKE) != 0) { 1595 re_gmii_writereg(dev, 1, 0x1f, 0); 1596 re_gmii_writereg(dev, 1, 0x0e, 0); 1597 } 1598 1599 ifp->if_softc = sc; 1600 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1601 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1602 ifp->if_ioctl = re_ioctl; 1603 ifp->if_start = re_start; 1604 /* 1605 * RTL8168/8111C generates wrong IP checksummed frame if the 1606 * packet has IP options so disable TX IP checksum offloading. 1607 */ 1608 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168C || 1609 sc->rl_hwrev->rl_rev == RL_HWREV_8168C_SPIN2 || 1610 sc->rl_hwrev->rl_rev == RL_HWREV_8168CP) 1611 ifp->if_hwassist = CSUM_TCP | CSUM_UDP; 1612 else 1613 ifp->if_hwassist = CSUM_IP | CSUM_TCP | CSUM_UDP; 1614 ifp->if_hwassist |= CSUM_TSO; 1615 ifp->if_capabilities = IFCAP_HWCSUM | IFCAP_TSO4; 1616 ifp->if_capenable = ifp->if_capabilities; 1617 ifp->if_init = re_init; 1618 IFQ_SET_MAXLEN(&ifp->if_snd, RL_IFQ_MAXLEN); 1619 ifp->if_snd.ifq_drv_maxlen = RL_IFQ_MAXLEN; 1620 IFQ_SET_READY(&ifp->if_snd); 1621 1622 TASK_INIT(&sc->rl_inttask, 0, re_int_task, sc); 1623 1624#define RE_PHYAD_INTERNAL 0 1625 1626 /* Do MII setup. */ 1627 phy = RE_PHYAD_INTERNAL; 1628 if (sc->rl_type == RL_8169) 1629 phy = 1; 1630 error = mii_attach(dev, &sc->rl_miibus, ifp, re_ifmedia_upd, 1631 re_ifmedia_sts, BMSR_DEFCAPMASK, phy, MII_OFFSET_ANY, MIIF_DOPAUSE); 1632 if (error != 0) { 1633 device_printf(dev, "attaching PHYs failed\n"); 1634 goto fail; 1635 } 1636 1637 /* 1638 * Call MI attach routine. 1639 */ 1640 ether_ifattach(ifp, eaddr); 1641 1642 /* VLAN capability setup */ 1643 ifp->if_capabilities |= IFCAP_VLAN_MTU | IFCAP_VLAN_HWTAGGING; 1644 if (ifp->if_capabilities & IFCAP_HWCSUM) 1645 ifp->if_capabilities |= IFCAP_VLAN_HWCSUM; 1646 /* Enable WOL if PM is supported. */ 1647 if (pci_find_cap(sc->rl_dev, PCIY_PMG, ®) == 0) 1648 ifp->if_capabilities |= IFCAP_WOL; 1649 ifp->if_capenable = ifp->if_capabilities; 1650 ifp->if_capenable &= ~(IFCAP_WOL_UCAST | IFCAP_WOL_MCAST); 1651 /* 1652 * Don't enable TSO by default. It is known to generate 1653 * corrupted TCP segments(bad TCP options) under certain 1654 * circumstances. 1655 */ 1656 ifp->if_hwassist &= ~CSUM_TSO; 1657 ifp->if_capenable &= ~(IFCAP_TSO4 | IFCAP_VLAN_HWTSO); 1658#ifdef DEVICE_POLLING 1659 ifp->if_capabilities |= IFCAP_POLLING; 1660#endif 1661 /* 1662 * Tell the upper layer(s) we support long frames. 1663 * Must appear after the call to ether_ifattach() because 1664 * ether_ifattach() sets ifi_hdrlen to the default value. 1665 */ 1666 ifp->if_data.ifi_hdrlen = sizeof(struct ether_vlan_header); 1667 1668#ifdef DEV_NETMAP 1669 re_netmap_attach(sc); 1670#endif /* DEV_NETMAP */ 1671#ifdef RE_DIAG 1672 /* 1673 * Perform hardware diagnostic on the original RTL8169. 1674 * Some 32-bit cards were incorrectly wired and would 1675 * malfunction if plugged into a 64-bit slot. 1676 */ 1677 1678 if (hwrev == RL_HWREV_8169) { 1679 error = re_diag(sc); 1680 if (error) { 1681 device_printf(dev, 1682 "attach aborted due to hardware diag failure\n"); 1683 ether_ifdetach(ifp); 1684 goto fail; 1685 } 1686 } 1687#endif 1688 1689#ifdef RE_TX_MODERATION 1690 intr_filter = 1; 1691#endif 1692 /* Hook interrupt last to avoid having to lock softc */ 1693 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 1694 intr_filter == 0) { 1695 error = bus_setup_intr(dev, sc->rl_irq[0], 1696 INTR_TYPE_NET | INTR_MPSAFE, NULL, re_intr_msi, sc, 1697 &sc->rl_intrhand[0]); 1698 } else { 1699 error = bus_setup_intr(dev, sc->rl_irq[0], 1700 INTR_TYPE_NET | INTR_MPSAFE, re_intr, NULL, sc, 1701 &sc->rl_intrhand[0]); 1702 } 1703 if (error) { 1704 device_printf(dev, "couldn't set up irq\n"); 1705 ether_ifdetach(ifp); 1706 } 1707 1708fail: 1709 1710 if (error) 1711 re_detach(dev); 1712 1713 return (error); 1714} 1715 1716/* 1717 * Shutdown hardware and free up resources. This can be called any 1718 * time after the mutex has been initialized. It is called in both 1719 * the error case in attach and the normal detach case so it needs 1720 * to be careful about only freeing resources that have actually been 1721 * allocated. 1722 */ 1723static int 1724re_detach(device_t dev) 1725{ 1726 struct rl_softc *sc; 1727 struct ifnet *ifp; 1728 int i, rid; 1729 1730 sc = device_get_softc(dev); 1731 ifp = sc->rl_ifp; 1732 KASSERT(mtx_initialized(&sc->rl_mtx), ("re mutex not initialized")); 1733 1734 /* These should only be active if attach succeeded */ 1735 if (device_is_attached(dev)) { 1736#ifdef DEVICE_POLLING 1737 if (ifp->if_capenable & IFCAP_POLLING) 1738 ether_poll_deregister(ifp); 1739#endif 1740 RL_LOCK(sc); 1741#if 0 1742 sc->suspended = 1; 1743#endif 1744 re_stop(sc); 1745 RL_UNLOCK(sc); 1746 callout_drain(&sc->rl_stat_callout); 1747 taskqueue_drain(taskqueue_fast, &sc->rl_inttask); 1748 /* 1749 * Force off the IFF_UP flag here, in case someone 1750 * still had a BPF descriptor attached to this 1751 * interface. If they do, ether_ifdetach() will cause 1752 * the BPF code to try and clear the promisc mode 1753 * flag, which will bubble down to re_ioctl(), 1754 * which will try to call re_init() again. This will 1755 * turn the NIC back on and restart the MII ticker, 1756 * which will panic the system when the kernel tries 1757 * to invoke the re_tick() function that isn't there 1758 * anymore. 1759 */ 1760 ifp->if_flags &= ~IFF_UP; 1761 ether_ifdetach(ifp); 1762 } 1763 if (sc->rl_miibus) 1764 device_delete_child(dev, sc->rl_miibus); 1765 bus_generic_detach(dev); 1766 1767 /* 1768 * The rest is resource deallocation, so we should already be 1769 * stopped here. 1770 */ 1771 1772 if (sc->rl_intrhand[0] != NULL) { 1773 bus_teardown_intr(dev, sc->rl_irq[0], sc->rl_intrhand[0]); 1774 sc->rl_intrhand[0] = NULL; 1775 } 1776 if (ifp != NULL) { 1777#ifdef DEV_NETMAP 1778 netmap_detach(ifp); 1779#endif /* DEV_NETMAP */ 1780 if_free(ifp); 1781 } 1782 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 1783 rid = 0; 1784 else 1785 rid = 1; 1786 if (sc->rl_irq[0] != NULL) { 1787 bus_release_resource(dev, SYS_RES_IRQ, rid, sc->rl_irq[0]); 1788 sc->rl_irq[0] = NULL; 1789 } 1790 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0) 1791 pci_release_msi(dev); 1792 if (sc->rl_res_pba) { 1793 rid = PCIR_BAR(4); 1794 bus_release_resource(dev, SYS_RES_MEMORY, rid, sc->rl_res_pba); 1795 } 1796 if (sc->rl_res) 1797 bus_release_resource(dev, sc->rl_res_type, sc->rl_res_id, 1798 sc->rl_res); 1799 1800 /* Unload and free the RX DMA ring memory and map */ 1801 1802 if (sc->rl_ldata.rl_rx_list_tag) { 1803 if (sc->rl_ldata.rl_rx_list_map) 1804 bus_dmamap_unload(sc->rl_ldata.rl_rx_list_tag, 1805 sc->rl_ldata.rl_rx_list_map); 1806 if (sc->rl_ldata.rl_rx_list_map && sc->rl_ldata.rl_rx_list) 1807 bus_dmamem_free(sc->rl_ldata.rl_rx_list_tag, 1808 sc->rl_ldata.rl_rx_list, 1809 sc->rl_ldata.rl_rx_list_map); 1810 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_list_tag); 1811 } 1812 1813 /* Unload and free the TX DMA ring memory and map */ 1814 1815 if (sc->rl_ldata.rl_tx_list_tag) { 1816 if (sc->rl_ldata.rl_tx_list_map) 1817 bus_dmamap_unload(sc->rl_ldata.rl_tx_list_tag, 1818 sc->rl_ldata.rl_tx_list_map); 1819 if (sc->rl_ldata.rl_tx_list_map && sc->rl_ldata.rl_tx_list) 1820 bus_dmamem_free(sc->rl_ldata.rl_tx_list_tag, 1821 sc->rl_ldata.rl_tx_list, 1822 sc->rl_ldata.rl_tx_list_map); 1823 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_list_tag); 1824 } 1825 1826 /* Destroy all the RX and TX buffer maps */ 1827 1828 if (sc->rl_ldata.rl_tx_mtag) { 1829 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 1830 if (sc->rl_ldata.rl_tx_desc[i].tx_dmamap) 1831 bus_dmamap_destroy(sc->rl_ldata.rl_tx_mtag, 1832 sc->rl_ldata.rl_tx_desc[i].tx_dmamap); 1833 } 1834 bus_dma_tag_destroy(sc->rl_ldata.rl_tx_mtag); 1835 } 1836 if (sc->rl_ldata.rl_rx_mtag) { 1837 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1838 if (sc->rl_ldata.rl_rx_desc[i].rx_dmamap) 1839 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1840 sc->rl_ldata.rl_rx_desc[i].rx_dmamap); 1841 } 1842 if (sc->rl_ldata.rl_rx_sparemap) 1843 bus_dmamap_destroy(sc->rl_ldata.rl_rx_mtag, 1844 sc->rl_ldata.rl_rx_sparemap); 1845 bus_dma_tag_destroy(sc->rl_ldata.rl_rx_mtag); 1846 } 1847 if (sc->rl_ldata.rl_jrx_mtag) { 1848 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 1849 if (sc->rl_ldata.rl_jrx_desc[i].rx_dmamap) 1850 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1851 sc->rl_ldata.rl_jrx_desc[i].rx_dmamap); 1852 } 1853 if (sc->rl_ldata.rl_jrx_sparemap) 1854 bus_dmamap_destroy(sc->rl_ldata.rl_jrx_mtag, 1855 sc->rl_ldata.rl_jrx_sparemap); 1856 bus_dma_tag_destroy(sc->rl_ldata.rl_jrx_mtag); 1857 } 1858 /* Unload and free the stats buffer and map */ 1859 1860 if (sc->rl_ldata.rl_stag) { 1861 if (sc->rl_ldata.rl_smap) 1862 bus_dmamap_unload(sc->rl_ldata.rl_stag, 1863 sc->rl_ldata.rl_smap); 1864 if (sc->rl_ldata.rl_smap && sc->rl_ldata.rl_stats) 1865 bus_dmamem_free(sc->rl_ldata.rl_stag, 1866 sc->rl_ldata.rl_stats, sc->rl_ldata.rl_smap); 1867 bus_dma_tag_destroy(sc->rl_ldata.rl_stag); 1868 } 1869 1870 if (sc->rl_parent_tag) 1871 bus_dma_tag_destroy(sc->rl_parent_tag); 1872 1873 mtx_destroy(&sc->rl_mtx); 1874 1875 return (0); 1876} 1877 1878static __inline void 1879re_discard_rxbuf(struct rl_softc *sc, int idx) 1880{ 1881 struct rl_desc *desc; 1882 struct rl_rxdesc *rxd; 1883 uint32_t cmdstat; 1884 1885 if (sc->rl_ifp->if_mtu > RL_MTU && 1886 (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 1887 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 1888 else 1889 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1890 desc = &sc->rl_ldata.rl_rx_list[idx]; 1891 desc->rl_vlanctl = 0; 1892 cmdstat = rxd->rx_size; 1893 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1894 cmdstat |= RL_RDESC_CMD_EOR; 1895 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1896} 1897 1898static int 1899re_newbuf(struct rl_softc *sc, int idx) 1900{ 1901 struct mbuf *m; 1902 struct rl_rxdesc *rxd; 1903 bus_dma_segment_t segs[1]; 1904 bus_dmamap_t map; 1905 struct rl_desc *desc; 1906 uint32_t cmdstat; 1907 int error, nsegs; 1908 1909 m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR); 1910 if (m == NULL) 1911 return (ENOBUFS); 1912 1913 m->m_len = m->m_pkthdr.len = MCLBYTES; 1914#ifdef RE_FIXUP_RX 1915 /* 1916 * This is part of an evil trick to deal with non-x86 platforms. 1917 * The RealTek chip requires RX buffers to be aligned on 64-bit 1918 * boundaries, but that will hose non-x86 machines. To get around 1919 * this, we leave some empty space at the start of each buffer 1920 * and for non-x86 hosts, we copy the buffer back six bytes 1921 * to achieve word alignment. This is slightly more efficient 1922 * than allocating a new buffer, copying the contents, and 1923 * discarding the old buffer. 1924 */ 1925 m_adj(m, RE_ETHER_ALIGN); 1926#endif 1927 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_rx_mtag, 1928 sc->rl_ldata.rl_rx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1929 if (error != 0) { 1930 m_freem(m); 1931 return (ENOBUFS); 1932 } 1933 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1934 1935 rxd = &sc->rl_ldata.rl_rx_desc[idx]; 1936 if (rxd->rx_m != NULL) { 1937 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1938 BUS_DMASYNC_POSTREAD); 1939 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap); 1940 } 1941 1942 rxd->rx_m = m; 1943 map = rxd->rx_dmamap; 1944 rxd->rx_dmamap = sc->rl_ldata.rl_rx_sparemap; 1945 rxd->rx_size = segs[0].ds_len; 1946 sc->rl_ldata.rl_rx_sparemap = map; 1947 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, rxd->rx_dmamap, 1948 BUS_DMASYNC_PREREAD); 1949 1950 desc = &sc->rl_ldata.rl_rx_list[idx]; 1951 desc->rl_vlanctl = 0; 1952 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 1953 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 1954 cmdstat = segs[0].ds_len; 1955 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 1956 cmdstat |= RL_RDESC_CMD_EOR; 1957 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 1958 1959 return (0); 1960} 1961 1962static int 1963re_jumbo_newbuf(struct rl_softc *sc, int idx) 1964{ 1965 struct mbuf *m; 1966 struct rl_rxdesc *rxd; 1967 bus_dma_segment_t segs[1]; 1968 bus_dmamap_t map; 1969 struct rl_desc *desc; 1970 uint32_t cmdstat; 1971 int error, nsegs; 1972 1973 m = m_getjcl(M_NOWAIT, MT_DATA, M_PKTHDR, MJUM9BYTES); 1974 if (m == NULL) 1975 return (ENOBUFS); 1976 m->m_len = m->m_pkthdr.len = MJUM9BYTES; 1977#ifdef RE_FIXUP_RX 1978 m_adj(m, RE_ETHER_ALIGN); 1979#endif 1980 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_jrx_mtag, 1981 sc->rl_ldata.rl_jrx_sparemap, m, segs, &nsegs, BUS_DMA_NOWAIT); 1982 if (error != 0) { 1983 m_freem(m); 1984 return (ENOBUFS); 1985 } 1986 KASSERT(nsegs == 1, ("%s: %d segment returned!", __func__, nsegs)); 1987 1988 rxd = &sc->rl_ldata.rl_jrx_desc[idx]; 1989 if (rxd->rx_m != NULL) { 1990 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 1991 BUS_DMASYNC_POSTREAD); 1992 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap); 1993 } 1994 1995 rxd->rx_m = m; 1996 map = rxd->rx_dmamap; 1997 rxd->rx_dmamap = sc->rl_ldata.rl_jrx_sparemap; 1998 rxd->rx_size = segs[0].ds_len; 1999 sc->rl_ldata.rl_jrx_sparemap = map; 2000 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, rxd->rx_dmamap, 2001 BUS_DMASYNC_PREREAD); 2002 2003 desc = &sc->rl_ldata.rl_rx_list[idx]; 2004 desc->rl_vlanctl = 0; 2005 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[0].ds_addr)); 2006 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[0].ds_addr)); 2007 cmdstat = segs[0].ds_len; 2008 if (idx == sc->rl_ldata.rl_rx_desc_cnt - 1) 2009 cmdstat |= RL_RDESC_CMD_EOR; 2010 desc->rl_cmdstat = htole32(cmdstat | RL_RDESC_CMD_OWN); 2011 2012 return (0); 2013} 2014 2015#ifdef RE_FIXUP_RX 2016static __inline void 2017re_fixup_rx(struct mbuf *m) 2018{ 2019 int i; 2020 uint16_t *src, *dst; 2021 2022 src = mtod(m, uint16_t *); 2023 dst = src - (RE_ETHER_ALIGN - ETHER_ALIGN) / sizeof *src; 2024 2025 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 2026 *dst++ = *src++; 2027 2028 m->m_data -= RE_ETHER_ALIGN - ETHER_ALIGN; 2029} 2030#endif 2031 2032static int 2033re_tx_list_init(struct rl_softc *sc) 2034{ 2035 struct rl_desc *desc; 2036 int i; 2037 2038 RL_LOCK_ASSERT(sc); 2039 2040 bzero(sc->rl_ldata.rl_tx_list, 2041 sc->rl_ldata.rl_tx_desc_cnt * sizeof(struct rl_desc)); 2042 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) 2043 sc->rl_ldata.rl_tx_desc[i].tx_m = NULL; 2044#ifdef DEV_NETMAP 2045 re_netmap_tx_init(sc); 2046#endif /* DEV_NETMAP */ 2047 /* Set EOR. */ 2048 desc = &sc->rl_ldata.rl_tx_list[sc->rl_ldata.rl_tx_desc_cnt - 1]; 2049 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOR); 2050 2051 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2052 sc->rl_ldata.rl_tx_list_map, 2053 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 2054 2055 sc->rl_ldata.rl_tx_prodidx = 0; 2056 sc->rl_ldata.rl_tx_considx = 0; 2057 sc->rl_ldata.rl_tx_free = sc->rl_ldata.rl_tx_desc_cnt; 2058 2059 return (0); 2060} 2061 2062static int 2063re_rx_list_init(struct rl_softc *sc) 2064{ 2065 int error, i; 2066 2067 bzero(sc->rl_ldata.rl_rx_list, 2068 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2069 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2070 sc->rl_ldata.rl_rx_desc[i].rx_m = NULL; 2071 if ((error = re_newbuf(sc, i)) != 0) 2072 return (error); 2073 } 2074#ifdef DEV_NETMAP 2075 re_netmap_rx_init(sc); 2076#endif /* DEV_NETMAP */ 2077 2078 /* Flush the RX descriptors */ 2079 2080 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2081 sc->rl_ldata.rl_rx_list_map, 2082 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2083 2084 sc->rl_ldata.rl_rx_prodidx = 0; 2085 sc->rl_head = sc->rl_tail = NULL; 2086 sc->rl_int_rx_act = 0; 2087 2088 return (0); 2089} 2090 2091static int 2092re_jrx_list_init(struct rl_softc *sc) 2093{ 2094 int error, i; 2095 2096 bzero(sc->rl_ldata.rl_rx_list, 2097 sc->rl_ldata.rl_rx_desc_cnt * sizeof(struct rl_desc)); 2098 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 2099 sc->rl_ldata.rl_jrx_desc[i].rx_m = NULL; 2100 if ((error = re_jumbo_newbuf(sc, i)) != 0) 2101 return (error); 2102 } 2103 2104 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2105 sc->rl_ldata.rl_rx_list_map, 2106 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 2107 2108 sc->rl_ldata.rl_rx_prodidx = 0; 2109 sc->rl_head = sc->rl_tail = NULL; 2110 sc->rl_int_rx_act = 0; 2111 2112 return (0); 2113} 2114 2115/* 2116 * RX handler for C+ and 8169. For the gigE chips, we support 2117 * the reception of jumbo frames that have been fragmented 2118 * across multiple 2K mbuf cluster buffers. 2119 */ 2120static int 2121re_rxeof(struct rl_softc *sc, int *rx_npktsp) 2122{ 2123 struct mbuf *m; 2124 struct ifnet *ifp; 2125 int i, rxerr, total_len; 2126 struct rl_desc *cur_rx; 2127 u_int32_t rxstat, rxvlan; 2128 int jumbo, maxpkt = 16, rx_npkts = 0; 2129 2130 RL_LOCK_ASSERT(sc); 2131 2132 ifp = sc->rl_ifp; 2133#ifdef DEV_NETMAP 2134 if (netmap_rx_irq(ifp, 0 | (NETMAP_LOCKED_ENTER|NETMAP_LOCKED_EXIT), 2135 &rx_npkts)) 2136 return 0; 2137#endif /* DEV_NETMAP */ 2138 if (ifp->if_mtu > RL_MTU && (sc->rl_flags & RL_FLAG_JUMBOV2) != 0) 2139 jumbo = 1; 2140 else 2141 jumbo = 0; 2142 2143 /* Invalidate the descriptor memory */ 2144 2145 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2146 sc->rl_ldata.rl_rx_list_map, 2147 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2148 2149 for (i = sc->rl_ldata.rl_rx_prodidx; maxpkt > 0; 2150 i = RL_RX_DESC_NXT(sc, i)) { 2151 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) 2152 break; 2153 cur_rx = &sc->rl_ldata.rl_rx_list[i]; 2154 rxstat = le32toh(cur_rx->rl_cmdstat); 2155 if ((rxstat & RL_RDESC_STAT_OWN) != 0) 2156 break; 2157 total_len = rxstat & sc->rl_rxlenmask; 2158 rxvlan = le32toh(cur_rx->rl_vlanctl); 2159 if (jumbo != 0) 2160 m = sc->rl_ldata.rl_jrx_desc[i].rx_m; 2161 else 2162 m = sc->rl_ldata.rl_rx_desc[i].rx_m; 2163 2164 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 2165 (rxstat & (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) != 2166 (RL_RDESC_STAT_SOF | RL_RDESC_STAT_EOF)) { 2167 /* 2168 * RTL8168C or later controllers do not 2169 * support multi-fragment packet. 2170 */ 2171 re_discard_rxbuf(sc, i); 2172 continue; 2173 } else if ((rxstat & RL_RDESC_STAT_EOF) == 0) { 2174 if (re_newbuf(sc, i) != 0) { 2175 /* 2176 * If this is part of a multi-fragment packet, 2177 * discard all the pieces. 2178 */ 2179 if (sc->rl_head != NULL) { 2180 m_freem(sc->rl_head); 2181 sc->rl_head = sc->rl_tail = NULL; 2182 } 2183 re_discard_rxbuf(sc, i); 2184 continue; 2185 } 2186 m->m_len = RE_RX_DESC_BUFLEN; 2187 if (sc->rl_head == NULL) 2188 sc->rl_head = sc->rl_tail = m; 2189 else { 2190 m->m_flags &= ~M_PKTHDR; 2191 sc->rl_tail->m_next = m; 2192 sc->rl_tail = m; 2193 } 2194 continue; 2195 } 2196 2197 /* 2198 * NOTE: for the 8139C+, the frame length field 2199 * is always 12 bits in size, but for the gigE chips, 2200 * it is 13 bits (since the max RX frame length is 16K). 2201 * Unfortunately, all 32 bits in the status word 2202 * were already used, so to make room for the extra 2203 * length bit, RealTek took out the 'frame alignment 2204 * error' bit and shifted the other status bits 2205 * over one slot. The OWN, EOR, FS and LS bits are 2206 * still in the same places. We have already extracted 2207 * the frame length and checked the OWN bit, so rather 2208 * than using an alternate bit mapping, we shift the 2209 * status bits one space to the right so we can evaluate 2210 * them using the 8169 status as though it was in the 2211 * same format as that of the 8139C+. 2212 */ 2213 if (sc->rl_type == RL_8169) 2214 rxstat >>= 1; 2215 2216 /* 2217 * if total_len > 2^13-1, both _RXERRSUM and _GIANT will be 2218 * set, but if CRC is clear, it will still be a valid frame. 2219 */ 2220 if ((rxstat & RL_RDESC_STAT_RXERRSUM) != 0) { 2221 rxerr = 1; 2222 if ((sc->rl_flags & RL_FLAG_JUMBOV2) == 0 && 2223 total_len > 8191 && 2224 (rxstat & RL_RDESC_STAT_ERRS) == RL_RDESC_STAT_GIANT) 2225 rxerr = 0; 2226 if (rxerr != 0) { 2227 ifp->if_ierrors++; 2228 /* 2229 * If this is part of a multi-fragment packet, 2230 * discard all the pieces. 2231 */ 2232 if (sc->rl_head != NULL) { 2233 m_freem(sc->rl_head); 2234 sc->rl_head = sc->rl_tail = NULL; 2235 } 2236 re_discard_rxbuf(sc, i); 2237 continue; 2238 } 2239 } 2240 2241 /* 2242 * If allocating a replacement mbuf fails, 2243 * reload the current one. 2244 */ 2245 if (jumbo != 0) 2246 rxerr = re_jumbo_newbuf(sc, i); 2247 else 2248 rxerr = re_newbuf(sc, i); 2249 if (rxerr != 0) { 2250 ifp->if_iqdrops++; 2251 if (sc->rl_head != NULL) { 2252 m_freem(sc->rl_head); 2253 sc->rl_head = sc->rl_tail = NULL; 2254 } 2255 re_discard_rxbuf(sc, i); 2256 continue; 2257 } 2258 2259 if (sc->rl_head != NULL) { 2260 if (jumbo != 0) 2261 m->m_len = total_len; 2262 else { 2263 m->m_len = total_len % RE_RX_DESC_BUFLEN; 2264 if (m->m_len == 0) 2265 m->m_len = RE_RX_DESC_BUFLEN; 2266 } 2267 /* 2268 * Special case: if there's 4 bytes or less 2269 * in this buffer, the mbuf can be discarded: 2270 * the last 4 bytes is the CRC, which we don't 2271 * care about anyway. 2272 */ 2273 if (m->m_len <= ETHER_CRC_LEN) { 2274 sc->rl_tail->m_len -= 2275 (ETHER_CRC_LEN - m->m_len); 2276 m_freem(m); 2277 } else { 2278 m->m_len -= ETHER_CRC_LEN; 2279 m->m_flags &= ~M_PKTHDR; 2280 sc->rl_tail->m_next = m; 2281 } 2282 m = sc->rl_head; 2283 sc->rl_head = sc->rl_tail = NULL; 2284 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 2285 } else 2286 m->m_pkthdr.len = m->m_len = 2287 (total_len - ETHER_CRC_LEN); 2288 2289#ifdef RE_FIXUP_RX 2290 re_fixup_rx(m); 2291#endif 2292 ifp->if_ipackets++; 2293 m->m_pkthdr.rcvif = ifp; 2294 2295 /* Do RX checksumming if enabled */ 2296 2297 if (ifp->if_capenable & IFCAP_RXCSUM) { 2298 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2299 /* Check IP header checksum */ 2300 if (rxstat & RL_RDESC_STAT_PROTOID) 2301 m->m_pkthdr.csum_flags |= 2302 CSUM_IP_CHECKED; 2303 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD)) 2304 m->m_pkthdr.csum_flags |= 2305 CSUM_IP_VALID; 2306 2307 /* Check TCP/UDP checksum */ 2308 if ((RL_TCPPKT(rxstat) && 2309 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2310 (RL_UDPPKT(rxstat) && 2311 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2312 m->m_pkthdr.csum_flags |= 2313 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2314 m->m_pkthdr.csum_data = 0xffff; 2315 } 2316 } else { 2317 /* 2318 * RTL8168C/RTL816CP/RTL8111C/RTL8111CP 2319 */ 2320 if ((rxstat & RL_RDESC_STAT_PROTOID) && 2321 (rxvlan & RL_RDESC_IPV4)) 2322 m->m_pkthdr.csum_flags |= 2323 CSUM_IP_CHECKED; 2324 if (!(rxstat & RL_RDESC_STAT_IPSUMBAD) && 2325 (rxvlan & RL_RDESC_IPV4)) 2326 m->m_pkthdr.csum_flags |= 2327 CSUM_IP_VALID; 2328 if (((rxstat & RL_RDESC_STAT_TCP) && 2329 !(rxstat & RL_RDESC_STAT_TCPSUMBAD)) || 2330 ((rxstat & RL_RDESC_STAT_UDP) && 2331 !(rxstat & RL_RDESC_STAT_UDPSUMBAD))) { 2332 m->m_pkthdr.csum_flags |= 2333 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 2334 m->m_pkthdr.csum_data = 0xffff; 2335 } 2336 } 2337 } 2338 maxpkt--; 2339 if (rxvlan & RL_RDESC_VLANCTL_TAG) { 2340 m->m_pkthdr.ether_vtag = 2341 bswap16((rxvlan & RL_RDESC_VLANCTL_DATA)); 2342 m->m_flags |= M_VLANTAG; 2343 } 2344 RL_UNLOCK(sc); 2345 (*ifp->if_input)(ifp, m); 2346 RL_LOCK(sc); 2347 rx_npkts++; 2348 } 2349 2350 /* Flush the RX DMA ring */ 2351 2352 bus_dmamap_sync(sc->rl_ldata.rl_rx_list_tag, 2353 sc->rl_ldata.rl_rx_list_map, 2354 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2355 2356 sc->rl_ldata.rl_rx_prodidx = i; 2357 2358 if (rx_npktsp != NULL) 2359 *rx_npktsp = rx_npkts; 2360 if (maxpkt) 2361 return (EAGAIN); 2362 2363 return (0); 2364} 2365 2366static void 2367re_txeof(struct rl_softc *sc) 2368{ 2369 struct ifnet *ifp; 2370 struct rl_txdesc *txd; 2371 u_int32_t txstat; 2372 int cons; 2373 2374 cons = sc->rl_ldata.rl_tx_considx; 2375 if (cons == sc->rl_ldata.rl_tx_prodidx) 2376 return; 2377 2378 ifp = sc->rl_ifp; 2379#ifdef DEV_NETMAP 2380 if (netmap_tx_irq(ifp, 0 | (NETMAP_LOCKED_ENTER|NETMAP_LOCKED_EXIT))) 2381 return; 2382#endif /* DEV_NETMAP */ 2383 /* Invalidate the TX descriptor list */ 2384 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2385 sc->rl_ldata.rl_tx_list_map, 2386 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 2387 2388 for (; cons != sc->rl_ldata.rl_tx_prodidx; 2389 cons = RL_TX_DESC_NXT(sc, cons)) { 2390 txstat = le32toh(sc->rl_ldata.rl_tx_list[cons].rl_cmdstat); 2391 if (txstat & RL_TDESC_STAT_OWN) 2392 break; 2393 /* 2394 * We only stash mbufs in the last descriptor 2395 * in a fragment chain, which also happens to 2396 * be the only place where the TX status bits 2397 * are valid. 2398 */ 2399 if (txstat & RL_TDESC_CMD_EOF) { 2400 txd = &sc->rl_ldata.rl_tx_desc[cons]; 2401 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 2402 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 2403 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 2404 txd->tx_dmamap); 2405 KASSERT(txd->tx_m != NULL, 2406 ("%s: freeing NULL mbufs!", __func__)); 2407 m_freem(txd->tx_m); 2408 txd->tx_m = NULL; 2409 if (txstat & (RL_TDESC_STAT_EXCESSCOL| 2410 RL_TDESC_STAT_COLCNT)) 2411 ifp->if_collisions++; 2412 if (txstat & RL_TDESC_STAT_TXERRSUM) 2413 ifp->if_oerrors++; 2414 else 2415 ifp->if_opackets++; 2416 } 2417 sc->rl_ldata.rl_tx_free++; 2418 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2419 } 2420 sc->rl_ldata.rl_tx_considx = cons; 2421 2422 /* No changes made to the TX ring, so no flush needed */ 2423 2424 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) { 2425#ifdef RE_TX_MODERATION 2426 /* 2427 * If not all descriptors have been reaped yet, reload 2428 * the timer so that we will eventually get another 2429 * interrupt that will cause us to re-enter this routine. 2430 * This is done in case the transmitter has gone idle. 2431 */ 2432 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2433#endif 2434 } else 2435 sc->rl_watchdog_timer = 0; 2436} 2437 2438static void 2439re_tick(void *xsc) 2440{ 2441 struct rl_softc *sc; 2442 struct mii_data *mii; 2443 2444 sc = xsc; 2445 2446 RL_LOCK_ASSERT(sc); 2447 2448 mii = device_get_softc(sc->rl_miibus); 2449 mii_tick(mii); 2450 if ((sc->rl_flags & RL_FLAG_LINK) == 0) 2451 re_miibus_statchg(sc->rl_dev); 2452 /* 2453 * Reclaim transmitted frames here. Technically it is not 2454 * necessary to do here but it ensures periodic reclamation 2455 * regardless of Tx completion interrupt which seems to be 2456 * lost on PCIe based controllers under certain situations. 2457 */ 2458 re_txeof(sc); 2459 re_watchdog(sc); 2460 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 2461} 2462 2463#ifdef DEVICE_POLLING 2464static int 2465re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 2466{ 2467 struct rl_softc *sc = ifp->if_softc; 2468 int rx_npkts = 0; 2469 2470 RL_LOCK(sc); 2471 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2472 rx_npkts = re_poll_locked(ifp, cmd, count); 2473 RL_UNLOCK(sc); 2474 return (rx_npkts); 2475} 2476 2477static int 2478re_poll_locked(struct ifnet *ifp, enum poll_cmd cmd, int count) 2479{ 2480 struct rl_softc *sc = ifp->if_softc; 2481 int rx_npkts; 2482 2483 RL_LOCK_ASSERT(sc); 2484 2485 sc->rxcycles = count; 2486 re_rxeof(sc, &rx_npkts); 2487 re_txeof(sc); 2488 2489 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2490 re_start_locked(ifp); 2491 2492 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 2493 u_int16_t status; 2494 2495 status = CSR_READ_2(sc, RL_ISR); 2496 if (status == 0xffff) 2497 return (rx_npkts); 2498 if (status) 2499 CSR_WRITE_2(sc, RL_ISR, status); 2500 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2501 (sc->rl_flags & RL_FLAG_PCIE)) 2502 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2503 2504 /* 2505 * XXX check behaviour on receiver stalls. 2506 */ 2507 2508 if (status & RL_ISR_SYSTEM_ERR) { 2509 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2510 re_init_locked(sc); 2511 } 2512 } 2513 return (rx_npkts); 2514} 2515#endif /* DEVICE_POLLING */ 2516 2517static int 2518re_intr(void *arg) 2519{ 2520 struct rl_softc *sc; 2521 uint16_t status; 2522 2523 sc = arg; 2524 2525 status = CSR_READ_2(sc, RL_ISR); 2526 if (status == 0xFFFF || (status & RL_INTRS_CPLUS) == 0) 2527 return (FILTER_STRAY); 2528 CSR_WRITE_2(sc, RL_IMR, 0); 2529 2530 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2531 2532 return (FILTER_HANDLED); 2533} 2534 2535static void 2536re_int_task(void *arg, int npending) 2537{ 2538 struct rl_softc *sc; 2539 struct ifnet *ifp; 2540 u_int16_t status; 2541 int rval = 0; 2542 2543 sc = arg; 2544 ifp = sc->rl_ifp; 2545 2546 RL_LOCK(sc); 2547 2548 status = CSR_READ_2(sc, RL_ISR); 2549 CSR_WRITE_2(sc, RL_ISR, status); 2550 2551 if (sc->suspended || 2552 (ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2553 RL_UNLOCK(sc); 2554 return; 2555 } 2556 2557#ifdef DEVICE_POLLING 2558 if (ifp->if_capenable & IFCAP_POLLING) { 2559 RL_UNLOCK(sc); 2560 return; 2561 } 2562#endif 2563 2564 if (status & (RL_ISR_RX_OK|RL_ISR_RX_ERR|RL_ISR_FIFO_OFLOW)) 2565 rval = re_rxeof(sc, NULL); 2566 2567 /* 2568 * Some chips will ignore a second TX request issued 2569 * while an existing transmission is in progress. If 2570 * the transmitter goes idle but there are still 2571 * packets waiting to be sent, we need to restart the 2572 * channel here to flush them out. This only seems to 2573 * be required with the PCIe devices. 2574 */ 2575 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2576 (sc->rl_flags & RL_FLAG_PCIE)) 2577 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2578 if (status & ( 2579#ifdef RE_TX_MODERATION 2580 RL_ISR_TIMEOUT_EXPIRED| 2581#else 2582 RL_ISR_TX_OK| 2583#endif 2584 RL_ISR_TX_ERR|RL_ISR_TX_DESC_UNAVAIL)) 2585 re_txeof(sc); 2586 2587 if (status & RL_ISR_SYSTEM_ERR) { 2588 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2589 re_init_locked(sc); 2590 } 2591 2592 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2593 re_start_locked(ifp); 2594 2595 RL_UNLOCK(sc); 2596 2597 if ((CSR_READ_2(sc, RL_ISR) & RL_INTRS_CPLUS) || rval) { 2598 taskqueue_enqueue_fast(taskqueue_fast, &sc->rl_inttask); 2599 return; 2600 } 2601 2602 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 2603} 2604 2605static void 2606re_intr_msi(void *xsc) 2607{ 2608 struct rl_softc *sc; 2609 struct ifnet *ifp; 2610 uint16_t intrs, status; 2611 2612 sc = xsc; 2613 RL_LOCK(sc); 2614 2615 ifp = sc->rl_ifp; 2616#ifdef DEVICE_POLLING 2617 if (ifp->if_capenable & IFCAP_POLLING) { 2618 RL_UNLOCK(sc); 2619 return; 2620 } 2621#endif 2622 /* Disable interrupts. */ 2623 CSR_WRITE_2(sc, RL_IMR, 0); 2624 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 2625 RL_UNLOCK(sc); 2626 return; 2627 } 2628 2629 intrs = RL_INTRS_CPLUS; 2630 status = CSR_READ_2(sc, RL_ISR); 2631 CSR_WRITE_2(sc, RL_ISR, status); 2632 if (sc->rl_int_rx_act > 0) { 2633 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2634 RL_ISR_RX_OVERRUN); 2635 status &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | RL_ISR_FIFO_OFLOW | 2636 RL_ISR_RX_OVERRUN); 2637 } 2638 2639 if (status & (RL_ISR_TIMEOUT_EXPIRED | RL_ISR_RX_OK | RL_ISR_RX_ERR | 2640 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) { 2641 re_rxeof(sc, NULL); 2642 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2643 if (sc->rl_int_rx_mod != 0 && 2644 (status & (RL_ISR_RX_OK | RL_ISR_RX_ERR | 2645 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN)) != 0) { 2646 /* Rearm one-shot timer. */ 2647 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2648 intrs &= ~(RL_ISR_RX_OK | RL_ISR_RX_ERR | 2649 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN); 2650 sc->rl_int_rx_act = 1; 2651 } else { 2652 intrs |= RL_ISR_RX_OK | RL_ISR_RX_ERR | 2653 RL_ISR_FIFO_OFLOW | RL_ISR_RX_OVERRUN; 2654 sc->rl_int_rx_act = 0; 2655 } 2656 } 2657 } 2658 2659 /* 2660 * Some chips will ignore a second TX request issued 2661 * while an existing transmission is in progress. If 2662 * the transmitter goes idle but there are still 2663 * packets waiting to be sent, we need to restart the 2664 * channel here to flush them out. This only seems to 2665 * be required with the PCIe devices. 2666 */ 2667 if ((status & (RL_ISR_TX_OK | RL_ISR_TX_DESC_UNAVAIL)) && 2668 (sc->rl_flags & RL_FLAG_PCIE)) 2669 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2670 if (status & (RL_ISR_TX_OK | RL_ISR_TX_ERR | RL_ISR_TX_DESC_UNAVAIL)) 2671 re_txeof(sc); 2672 2673 if (status & RL_ISR_SYSTEM_ERR) { 2674 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2675 re_init_locked(sc); 2676 } 2677 2678 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 2679 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 2680 re_start_locked(ifp); 2681 CSR_WRITE_2(sc, RL_IMR, intrs); 2682 } 2683 RL_UNLOCK(sc); 2684} 2685 2686static int 2687re_encap(struct rl_softc *sc, struct mbuf **m_head) 2688{ 2689 struct rl_txdesc *txd, *txd_last; 2690 bus_dma_segment_t segs[RL_NTXSEGS]; 2691 bus_dmamap_t map; 2692 struct mbuf *m_new; 2693 struct rl_desc *desc; 2694 int nsegs, prod; 2695 int i, error, ei, si; 2696 int padlen; 2697 uint32_t cmdstat, csum_flags, vlanctl; 2698 2699 RL_LOCK_ASSERT(sc); 2700 M_ASSERTPKTHDR((*m_head)); 2701 2702 /* 2703 * With some of the RealTek chips, using the checksum offload 2704 * support in conjunction with the autopadding feature results 2705 * in the transmission of corrupt frames. For example, if we 2706 * need to send a really small IP fragment that's less than 60 2707 * bytes in size, and IP header checksumming is enabled, the 2708 * resulting ethernet frame that appears on the wire will 2709 * have garbled payload. To work around this, if TX IP checksum 2710 * offload is enabled, we always manually pad short frames out 2711 * to the minimum ethernet frame size. 2712 */ 2713 if ((sc->rl_flags & RL_FLAG_AUTOPAD) == 0 && 2714 (*m_head)->m_pkthdr.len < RL_IP4CSUMTX_PADLEN && 2715 ((*m_head)->m_pkthdr.csum_flags & CSUM_IP) != 0) { 2716 padlen = RL_MIN_FRAMELEN - (*m_head)->m_pkthdr.len; 2717 if (M_WRITABLE(*m_head) == 0) { 2718 /* Get a writable copy. */ 2719 m_new = m_dup(*m_head, M_NOWAIT); 2720 m_freem(*m_head); 2721 if (m_new == NULL) { 2722 *m_head = NULL; 2723 return (ENOBUFS); 2724 } 2725 *m_head = m_new; 2726 } 2727 if ((*m_head)->m_next != NULL || 2728 M_TRAILINGSPACE(*m_head) < padlen) { 2729 m_new = m_defrag(*m_head, M_NOWAIT); 2730 if (m_new == NULL) { 2731 m_freem(*m_head); 2732 *m_head = NULL; 2733 return (ENOBUFS); 2734 } 2735 } else 2736 m_new = *m_head; 2737 2738 /* 2739 * Manually pad short frames, and zero the pad space 2740 * to avoid leaking data. 2741 */ 2742 bzero(mtod(m_new, char *) + m_new->m_pkthdr.len, padlen); 2743 m_new->m_pkthdr.len += padlen; 2744 m_new->m_len = m_new->m_pkthdr.len; 2745 *m_head = m_new; 2746 } 2747 2748 prod = sc->rl_ldata.rl_tx_prodidx; 2749 txd = &sc->rl_ldata.rl_tx_desc[prod]; 2750 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2751 *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2752 if (error == EFBIG) { 2753 m_new = m_collapse(*m_head, M_NOWAIT, RL_NTXSEGS); 2754 if (m_new == NULL) { 2755 m_freem(*m_head); 2756 *m_head = NULL; 2757 return (ENOBUFS); 2758 } 2759 *m_head = m_new; 2760 error = bus_dmamap_load_mbuf_sg(sc->rl_ldata.rl_tx_mtag, 2761 txd->tx_dmamap, *m_head, segs, &nsegs, BUS_DMA_NOWAIT); 2762 if (error != 0) { 2763 m_freem(*m_head); 2764 *m_head = NULL; 2765 return (error); 2766 } 2767 } else if (error != 0) 2768 return (error); 2769 if (nsegs == 0) { 2770 m_freem(*m_head); 2771 *m_head = NULL; 2772 return (EIO); 2773 } 2774 2775 /* Check for number of available descriptors. */ 2776 if (sc->rl_ldata.rl_tx_free - nsegs <= 1) { 2777 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap); 2778 return (ENOBUFS); 2779 } 2780 2781 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, txd->tx_dmamap, 2782 BUS_DMASYNC_PREWRITE); 2783 2784 /* 2785 * Set up checksum offload. Note: checksum offload bits must 2786 * appear in all descriptors of a multi-descriptor transmit 2787 * attempt. This is according to testing done with an 8169 2788 * chip. This is a requirement. 2789 */ 2790 vlanctl = 0; 2791 csum_flags = 0; 2792 if (((*m_head)->m_pkthdr.csum_flags & CSUM_TSO) != 0) { 2793 if ((sc->rl_flags & RL_FLAG_DESCV2) != 0) { 2794 csum_flags |= RL_TDESC_CMD_LGSEND; 2795 vlanctl |= ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2796 RL_TDESC_CMD_MSSVALV2_SHIFT); 2797 } else { 2798 csum_flags |= RL_TDESC_CMD_LGSEND | 2799 ((uint32_t)(*m_head)->m_pkthdr.tso_segsz << 2800 RL_TDESC_CMD_MSSVAL_SHIFT); 2801 } 2802 } else { 2803 /* 2804 * Unconditionally enable IP checksum if TCP or UDP 2805 * checksum is required. Otherwise, TCP/UDP checksum 2806 * doesn't make effects. 2807 */ 2808 if (((*m_head)->m_pkthdr.csum_flags & RE_CSUM_FEATURES) != 0) { 2809 if ((sc->rl_flags & RL_FLAG_DESCV2) == 0) { 2810 csum_flags |= RL_TDESC_CMD_IPCSUM; 2811 if (((*m_head)->m_pkthdr.csum_flags & 2812 CSUM_TCP) != 0) 2813 csum_flags |= RL_TDESC_CMD_TCPCSUM; 2814 if (((*m_head)->m_pkthdr.csum_flags & 2815 CSUM_UDP) != 0) 2816 csum_flags |= RL_TDESC_CMD_UDPCSUM; 2817 } else { 2818 vlanctl |= RL_TDESC_CMD_IPCSUMV2; 2819 if (((*m_head)->m_pkthdr.csum_flags & 2820 CSUM_TCP) != 0) 2821 vlanctl |= RL_TDESC_CMD_TCPCSUMV2; 2822 if (((*m_head)->m_pkthdr.csum_flags & 2823 CSUM_UDP) != 0) 2824 vlanctl |= RL_TDESC_CMD_UDPCSUMV2; 2825 } 2826 } 2827 } 2828 2829 /* 2830 * Set up hardware VLAN tagging. Note: vlan tag info must 2831 * appear in all descriptors of a multi-descriptor 2832 * transmission attempt. 2833 */ 2834 if ((*m_head)->m_flags & M_VLANTAG) 2835 vlanctl |= bswap16((*m_head)->m_pkthdr.ether_vtag) | 2836 RL_TDESC_VLANCTL_TAG; 2837 2838 si = prod; 2839 for (i = 0; i < nsegs; i++, prod = RL_TX_DESC_NXT(sc, prod)) { 2840 desc = &sc->rl_ldata.rl_tx_list[prod]; 2841 desc->rl_vlanctl = htole32(vlanctl); 2842 desc->rl_bufaddr_lo = htole32(RL_ADDR_LO(segs[i].ds_addr)); 2843 desc->rl_bufaddr_hi = htole32(RL_ADDR_HI(segs[i].ds_addr)); 2844 cmdstat = segs[i].ds_len; 2845 if (i != 0) 2846 cmdstat |= RL_TDESC_CMD_OWN; 2847 if (prod == sc->rl_ldata.rl_tx_desc_cnt - 1) 2848 cmdstat |= RL_TDESC_CMD_EOR; 2849 desc->rl_cmdstat = htole32(cmdstat | csum_flags); 2850 sc->rl_ldata.rl_tx_free--; 2851 } 2852 /* Update producer index. */ 2853 sc->rl_ldata.rl_tx_prodidx = prod; 2854 2855 /* Set EOF on the last descriptor. */ 2856 ei = RL_TX_DESC_PRV(sc, prod); 2857 desc = &sc->rl_ldata.rl_tx_list[ei]; 2858 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_EOF); 2859 2860 desc = &sc->rl_ldata.rl_tx_list[si]; 2861 /* Set SOF and transfer ownership of packet to the chip. */ 2862 desc->rl_cmdstat |= htole32(RL_TDESC_CMD_OWN | RL_TDESC_CMD_SOF); 2863 2864 /* 2865 * Insure that the map for this transmission 2866 * is placed at the array index of the last descriptor 2867 * in this chain. (Swap last and first dmamaps.) 2868 */ 2869 txd_last = &sc->rl_ldata.rl_tx_desc[ei]; 2870 map = txd->tx_dmamap; 2871 txd->tx_dmamap = txd_last->tx_dmamap; 2872 txd_last->tx_dmamap = map; 2873 txd_last->tx_m = *m_head; 2874 2875 return (0); 2876} 2877 2878static void 2879re_start(struct ifnet *ifp) 2880{ 2881 struct rl_softc *sc; 2882 2883 sc = ifp->if_softc; 2884 RL_LOCK(sc); 2885 re_start_locked(ifp); 2886 RL_UNLOCK(sc); 2887} 2888 2889/* 2890 * Main transmit routine for C+ and gigE NICs. 2891 */ 2892static void 2893re_start_locked(struct ifnet *ifp) 2894{ 2895 struct rl_softc *sc; 2896 struct mbuf *m_head; 2897 int queued; 2898 2899 sc = ifp->if_softc; 2900 2901#ifdef DEV_NETMAP 2902 /* XXX is this necessary ? */ 2903 if (ifp->if_capenable & IFCAP_NETMAP) { 2904 struct netmap_kring *kring = &NA(ifp)->tx_rings[0]; 2905 if (sc->rl_ldata.rl_tx_prodidx != kring->nr_hwcur) { 2906 /* kick the tx unit */ 2907 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2908#ifdef RE_TX_MODERATION 2909 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2910#endif 2911 sc->rl_watchdog_timer = 5; 2912 } 2913 return; 2914 } 2915#endif /* DEV_NETMAP */ 2916 if ((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 2917 IFF_DRV_RUNNING || (sc->rl_flags & RL_FLAG_LINK) == 0) 2918 return; 2919 2920 for (queued = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 2921 sc->rl_ldata.rl_tx_free > 1;) { 2922 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 2923 if (m_head == NULL) 2924 break; 2925 2926 if (re_encap(sc, &m_head) != 0) { 2927 if (m_head == NULL) 2928 break; 2929 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 2930 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 2931 break; 2932 } 2933 2934 /* 2935 * If there's a BPF listener, bounce a copy of this frame 2936 * to him. 2937 */ 2938 ETHER_BPF_MTAP(ifp, m_head); 2939 2940 queued++; 2941 } 2942 2943 if (queued == 0) { 2944#ifdef RE_TX_MODERATION 2945 if (sc->rl_ldata.rl_tx_free != sc->rl_ldata.rl_tx_desc_cnt) 2946 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2947#endif 2948 return; 2949 } 2950 2951 /* Flush the TX descriptors */ 2952 2953 bus_dmamap_sync(sc->rl_ldata.rl_tx_list_tag, 2954 sc->rl_ldata.rl_tx_list_map, 2955 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 2956 2957 CSR_WRITE_1(sc, sc->rl_txstart, RL_TXSTART_START); 2958 2959#ifdef RE_TX_MODERATION 2960 /* 2961 * Use the countdown timer for interrupt moderation. 2962 * 'TX done' interrupts are disabled. Instead, we reset the 2963 * countdown timer, which will begin counting until it hits 2964 * the value in the TIMERINT register, and then trigger an 2965 * interrupt. Each time we write to the TIMERCNT register, 2966 * the timer count is reset to 0. 2967 */ 2968 CSR_WRITE_4(sc, RL_TIMERCNT, 1); 2969#endif 2970 2971 /* 2972 * Set a timeout in case the chip goes out to lunch. 2973 */ 2974 sc->rl_watchdog_timer = 5; 2975} 2976 2977static void 2978re_set_jumbo(struct rl_softc *sc, int jumbo) 2979{ 2980 2981 if (sc->rl_hwrev->rl_rev == RL_HWREV_8168E_VL) { 2982 pci_set_max_read_req(sc->rl_dev, 4096); 2983 return; 2984 } 2985 2986 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 2987 if (jumbo != 0) { 2988 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) | 2989 RL_CFG3_JUMBO_EN0); 2990 switch (sc->rl_hwrev->rl_rev) { 2991 case RL_HWREV_8168DP: 2992 break; 2993 case RL_HWREV_8168E: 2994 CSR_WRITE_1(sc, sc->rl_cfg4, 2995 CSR_READ_1(sc, sc->rl_cfg4) | 0x01); 2996 break; 2997 default: 2998 CSR_WRITE_1(sc, sc->rl_cfg4, 2999 CSR_READ_1(sc, sc->rl_cfg4) | RL_CFG4_JUMBO_EN1); 3000 } 3001 } else { 3002 CSR_WRITE_1(sc, sc->rl_cfg3, CSR_READ_1(sc, sc->rl_cfg3) & 3003 ~RL_CFG3_JUMBO_EN0); 3004 switch (sc->rl_hwrev->rl_rev) { 3005 case RL_HWREV_8168DP: 3006 break; 3007 case RL_HWREV_8168E: 3008 CSR_WRITE_1(sc, sc->rl_cfg4, 3009 CSR_READ_1(sc, sc->rl_cfg4) & ~0x01); 3010 break; 3011 default: 3012 CSR_WRITE_1(sc, sc->rl_cfg4, 3013 CSR_READ_1(sc, sc->rl_cfg4) & ~RL_CFG4_JUMBO_EN1); 3014 } 3015 } 3016 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3017 3018 switch (sc->rl_hwrev->rl_rev) { 3019 case RL_HWREV_8168DP: 3020 pci_set_max_read_req(sc->rl_dev, 4096); 3021 break; 3022 default: 3023 if (jumbo != 0) 3024 pci_set_max_read_req(sc->rl_dev, 512); 3025 else 3026 pci_set_max_read_req(sc->rl_dev, 4096); 3027 } 3028} 3029 3030static void 3031re_init(void *xsc) 3032{ 3033 struct rl_softc *sc = xsc; 3034 3035 RL_LOCK(sc); 3036 re_init_locked(sc); 3037 RL_UNLOCK(sc); 3038} 3039 3040static void 3041re_init_locked(struct rl_softc *sc) 3042{ 3043 struct ifnet *ifp = sc->rl_ifp; 3044 struct mii_data *mii; 3045 uint32_t reg; 3046 uint16_t cfg; 3047 union { 3048 uint32_t align_dummy; 3049 u_char eaddr[ETHER_ADDR_LEN]; 3050 } eaddr; 3051 3052 RL_LOCK_ASSERT(sc); 3053 3054 mii = device_get_softc(sc->rl_miibus); 3055 3056 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3057 return; 3058 3059 /* 3060 * Cancel pending I/O and free all RX/TX buffers. 3061 */ 3062 re_stop(sc); 3063 3064 /* Put controller into known state. */ 3065 re_reset(sc); 3066 3067 /* 3068 * For C+ mode, initialize the RX descriptors and mbufs. 3069 */ 3070 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3071 if (ifp->if_mtu > RL_MTU) { 3072 if (re_jrx_list_init(sc) != 0) { 3073 device_printf(sc->rl_dev, 3074 "no memory for jumbo RX buffers\n"); 3075 re_stop(sc); 3076 return; 3077 } 3078 /* Disable checksum offloading for jumbo frames. */ 3079 ifp->if_capenable &= ~(IFCAP_HWCSUM | IFCAP_TSO4); 3080 ifp->if_hwassist &= ~(RE_CSUM_FEATURES | CSUM_TSO); 3081 } else { 3082 if (re_rx_list_init(sc) != 0) { 3083 device_printf(sc->rl_dev, 3084 "no memory for RX buffers\n"); 3085 re_stop(sc); 3086 return; 3087 } 3088 } 3089 re_set_jumbo(sc, ifp->if_mtu > RL_MTU); 3090 } else { 3091 if (re_rx_list_init(sc) != 0) { 3092 device_printf(sc->rl_dev, "no memory for RX buffers\n"); 3093 re_stop(sc); 3094 return; 3095 } 3096 if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3097 pci_get_device(sc->rl_dev) != RT_DEVICEID_8101E) { 3098 if (ifp->if_mtu > RL_MTU) 3099 pci_set_max_read_req(sc->rl_dev, 512); 3100 else 3101 pci_set_max_read_req(sc->rl_dev, 4096); 3102 } 3103 } 3104 re_tx_list_init(sc); 3105 3106 /* 3107 * Enable C+ RX and TX mode, as well as VLAN stripping and 3108 * RX checksum offload. We must configure the C+ register 3109 * before all others. 3110 */ 3111 cfg = RL_CPLUSCMD_PCI_MRW; 3112 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0) 3113 cfg |= RL_CPLUSCMD_RXCSUM_ENB; 3114 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) != 0) 3115 cfg |= RL_CPLUSCMD_VLANSTRIP; 3116 if ((sc->rl_flags & RL_FLAG_MACSTAT) != 0) { 3117 cfg |= RL_CPLUSCMD_MACSTAT_DIS; 3118 /* XXX magic. */ 3119 cfg |= 0x0001; 3120 } else 3121 cfg |= RL_CPLUSCMD_RXENB | RL_CPLUSCMD_TXENB; 3122 CSR_WRITE_2(sc, RL_CPLUS_CMD, cfg); 3123 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SC || 3124 sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) { 3125 reg = 0x000fff00; 3126 if ((CSR_READ_1(sc, sc->rl_cfg2) & RL_CFG2_PCI66MHZ) != 0) 3127 reg |= 0x000000ff; 3128 if (sc->rl_hwrev->rl_rev == RL_HWREV_8169_8110SCE) 3129 reg |= 0x00f00000; 3130 CSR_WRITE_4(sc, 0x7c, reg); 3131 /* Disable interrupt mitigation. */ 3132 CSR_WRITE_2(sc, 0xe2, 0); 3133 } 3134 /* 3135 * Disable TSO if interface MTU size is greater than MSS 3136 * allowed in controller. 3137 */ 3138 if (ifp->if_mtu > RL_TSO_MTU && (ifp->if_capenable & IFCAP_TSO4) != 0) { 3139 ifp->if_capenable &= ~IFCAP_TSO4; 3140 ifp->if_hwassist &= ~CSUM_TSO; 3141 } 3142 3143 /* 3144 * Init our MAC address. Even though the chipset 3145 * documentation doesn't mention it, we need to enter "Config 3146 * register write enable" mode to modify the ID registers. 3147 */ 3148 /* Copy MAC address on stack to align. */ 3149 bcopy(IF_LLADDR(ifp), eaddr.eaddr, ETHER_ADDR_LEN); 3150 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_WRITECFG); 3151 CSR_WRITE_4(sc, RL_IDR0, 3152 htole32(*(u_int32_t *)(&eaddr.eaddr[0]))); 3153 CSR_WRITE_4(sc, RL_IDR4, 3154 htole32(*(u_int32_t *)(&eaddr.eaddr[4]))); 3155 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3156 3157 /* 3158 * Load the addresses of the RX and TX lists into the chip. 3159 */ 3160 3161 CSR_WRITE_4(sc, RL_RXLIST_ADDR_HI, 3162 RL_ADDR_HI(sc->rl_ldata.rl_rx_list_addr)); 3163 CSR_WRITE_4(sc, RL_RXLIST_ADDR_LO, 3164 RL_ADDR_LO(sc->rl_ldata.rl_rx_list_addr)); 3165 3166 CSR_WRITE_4(sc, RL_TXLIST_ADDR_HI, 3167 RL_ADDR_HI(sc->rl_ldata.rl_tx_list_addr)); 3168 CSR_WRITE_4(sc, RL_TXLIST_ADDR_LO, 3169 RL_ADDR_LO(sc->rl_ldata.rl_tx_list_addr)); 3170 3171 /* 3172 * Enable transmit and receive. 3173 */ 3174 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 3175 3176 /* 3177 * Set the initial TX configuration. 3178 */ 3179 if (sc->rl_testmode) { 3180 if (sc->rl_type == RL_8169) 3181 CSR_WRITE_4(sc, RL_TXCFG, 3182 RL_TXCFG_CONFIG|RL_LOOPTEST_ON); 3183 else 3184 CSR_WRITE_4(sc, RL_TXCFG, 3185 RL_TXCFG_CONFIG|RL_LOOPTEST_ON_CPLUS); 3186 } else 3187 CSR_WRITE_4(sc, RL_TXCFG, RL_TXCFG_CONFIG); 3188 3189 CSR_WRITE_1(sc, RL_EARLY_TX_THRESH, 16); 3190 3191 /* 3192 * Set the initial RX configuration. 3193 */ 3194 re_set_rxmode(sc); 3195 3196 /* Configure interrupt moderation. */ 3197 if (sc->rl_type == RL_8169) { 3198 /* Magic from vendor. */ 3199 CSR_WRITE_2(sc, RL_INTRMOD, 0x5100); 3200 } 3201 3202#ifdef DEVICE_POLLING 3203 /* 3204 * Disable interrupts if we are polling. 3205 */ 3206 if (ifp->if_capenable & IFCAP_POLLING) 3207 CSR_WRITE_2(sc, RL_IMR, 0); 3208 else /* otherwise ... */ 3209#endif 3210 3211 /* 3212 * Enable interrupts. 3213 */ 3214 if (sc->rl_testmode) 3215 CSR_WRITE_2(sc, RL_IMR, 0); 3216 else 3217 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3218 CSR_WRITE_2(sc, RL_ISR, RL_INTRS_CPLUS); 3219 3220 /* Set initial TX threshold */ 3221 sc->rl_txthresh = RL_TX_THRESH_INIT; 3222 3223 /* Start RX/TX process. */ 3224 CSR_WRITE_4(sc, RL_MISSEDPKT, 0); 3225#ifdef notdef 3226 /* Enable receiver and transmitter. */ 3227 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_TX_ENB|RL_CMD_RX_ENB); 3228#endif 3229 3230 /* 3231 * Initialize the timer interrupt register so that 3232 * a timer interrupt will be generated once the timer 3233 * reaches a certain number of ticks. The timer is 3234 * reloaded on each transmit. 3235 */ 3236#ifdef RE_TX_MODERATION 3237 /* 3238 * Use timer interrupt register to moderate TX interrupt 3239 * moderation, which dramatically improves TX frame rate. 3240 */ 3241 if (sc->rl_type == RL_8169) 3242 CSR_WRITE_4(sc, RL_TIMERINT_8169, 0x800); 3243 else 3244 CSR_WRITE_4(sc, RL_TIMERINT, 0x400); 3245#else 3246 /* 3247 * Use timer interrupt register to moderate RX interrupt 3248 * moderation. 3249 */ 3250 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) != 0 && 3251 intr_filter == 0) { 3252 if (sc->rl_type == RL_8169) 3253 CSR_WRITE_4(sc, RL_TIMERINT_8169, 3254 RL_USECS(sc->rl_int_rx_mod)); 3255 } else { 3256 if (sc->rl_type == RL_8169) 3257 CSR_WRITE_4(sc, RL_TIMERINT_8169, RL_USECS(0)); 3258 } 3259#endif 3260 3261 /* 3262 * For 8169 gigE NICs, set the max allowed RX packet 3263 * size so we can receive jumbo frames. 3264 */ 3265 if (sc->rl_type == RL_8169) { 3266 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3267 /* 3268 * For controllers that use new jumbo frame scheme, 3269 * set maximum size of jumbo frame depending on 3270 * controller revisions. 3271 */ 3272 if (ifp->if_mtu > RL_MTU) 3273 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3274 sc->rl_hwrev->rl_max_mtu + 3275 ETHER_VLAN_ENCAP_LEN + ETHER_HDR_LEN + 3276 ETHER_CRC_LEN); 3277 else 3278 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 3279 RE_RX_DESC_BUFLEN); 3280 } else if ((sc->rl_flags & RL_FLAG_PCIE) != 0 && 3281 sc->rl_hwrev->rl_max_mtu == RL_MTU) { 3282 /* RTL810x has no jumbo frame support. */ 3283 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, RE_RX_DESC_BUFLEN); 3284 } else 3285 CSR_WRITE_2(sc, RL_MAXRXPKTLEN, 16383); 3286 } 3287 3288 if (sc->rl_testmode) 3289 return; 3290 3291 CSR_WRITE_1(sc, sc->rl_cfg1, CSR_READ_1(sc, sc->rl_cfg1) | 3292 RL_CFG1_DRVLOAD); 3293 3294 ifp->if_drv_flags |= IFF_DRV_RUNNING; 3295 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 3296 3297 sc->rl_flags &= ~RL_FLAG_LINK; 3298 mii_mediachg(mii); 3299 3300 sc->rl_watchdog_timer = 0; 3301 callout_reset(&sc->rl_stat_callout, hz, re_tick, sc); 3302} 3303 3304/* 3305 * Set media options. 3306 */ 3307static int 3308re_ifmedia_upd(struct ifnet *ifp) 3309{ 3310 struct rl_softc *sc; 3311 struct mii_data *mii; 3312 int error; 3313 3314 sc = ifp->if_softc; 3315 mii = device_get_softc(sc->rl_miibus); 3316 RL_LOCK(sc); 3317 error = mii_mediachg(mii); 3318 RL_UNLOCK(sc); 3319 3320 return (error); 3321} 3322 3323/* 3324 * Report current media status. 3325 */ 3326static void 3327re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 3328{ 3329 struct rl_softc *sc; 3330 struct mii_data *mii; 3331 3332 sc = ifp->if_softc; 3333 mii = device_get_softc(sc->rl_miibus); 3334 3335 RL_LOCK(sc); 3336 mii_pollstat(mii); 3337 ifmr->ifm_active = mii->mii_media_active; 3338 ifmr->ifm_status = mii->mii_media_status; 3339 RL_UNLOCK(sc); 3340} 3341 3342static int 3343re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 3344{ 3345 struct rl_softc *sc = ifp->if_softc; 3346 struct ifreq *ifr = (struct ifreq *) data; 3347 struct mii_data *mii; 3348 uint32_t rev; 3349 int error = 0; 3350 3351 switch (command) { 3352 case SIOCSIFMTU: 3353 if (ifr->ifr_mtu < ETHERMIN || 3354 ifr->ifr_mtu > sc->rl_hwrev->rl_max_mtu || 3355 ((sc->rl_flags & RL_FLAG_FASTETHER) != 0 && 3356 ifr->ifr_mtu > RL_MTU)) { 3357 error = EINVAL; 3358 break; 3359 } 3360 RL_LOCK(sc); 3361 if (ifp->if_mtu != ifr->ifr_mtu) { 3362 ifp->if_mtu = ifr->ifr_mtu; 3363 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3364 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3365 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3366 re_init_locked(sc); 3367 } 3368 if (ifp->if_mtu > RL_TSO_MTU && 3369 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3370 ifp->if_capenable &= ~(IFCAP_TSO4 | 3371 IFCAP_VLAN_HWTSO); 3372 ifp->if_hwassist &= ~CSUM_TSO; 3373 } 3374 VLAN_CAPABILITIES(ifp); 3375 } 3376 RL_UNLOCK(sc); 3377 break; 3378 case SIOCSIFFLAGS: 3379 RL_LOCK(sc); 3380 if ((ifp->if_flags & IFF_UP) != 0) { 3381 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) { 3382 if (((ifp->if_flags ^ sc->rl_if_flags) 3383 & (IFF_PROMISC | IFF_ALLMULTI)) != 0) 3384 re_set_rxmode(sc); 3385 } else 3386 re_init_locked(sc); 3387 } else { 3388 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3389 re_stop(sc); 3390 } 3391 sc->rl_if_flags = ifp->if_flags; 3392 RL_UNLOCK(sc); 3393 break; 3394 case SIOCADDMULTI: 3395 case SIOCDELMULTI: 3396 RL_LOCK(sc); 3397 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 3398 re_set_rxmode(sc); 3399 RL_UNLOCK(sc); 3400 break; 3401 case SIOCGIFMEDIA: 3402 case SIOCSIFMEDIA: 3403 mii = device_get_softc(sc->rl_miibus); 3404 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 3405 break; 3406 case SIOCSIFCAP: 3407 { 3408 int mask, reinit; 3409 3410 mask = ifr->ifr_reqcap ^ ifp->if_capenable; 3411 reinit = 0; 3412#ifdef DEVICE_POLLING 3413 if (mask & IFCAP_POLLING) { 3414 if (ifr->ifr_reqcap & IFCAP_POLLING) { 3415 error = ether_poll_register(re_poll, ifp); 3416 if (error) 3417 return (error); 3418 RL_LOCK(sc); 3419 /* Disable interrupts */ 3420 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3421 ifp->if_capenable |= IFCAP_POLLING; 3422 RL_UNLOCK(sc); 3423 } else { 3424 error = ether_poll_deregister(ifp); 3425 /* Enable interrupts. */ 3426 RL_LOCK(sc); 3427 CSR_WRITE_2(sc, RL_IMR, RL_INTRS_CPLUS); 3428 ifp->if_capenable &= ~IFCAP_POLLING; 3429 RL_UNLOCK(sc); 3430 } 3431 } 3432#endif /* DEVICE_POLLING */ 3433 RL_LOCK(sc); 3434 if ((mask & IFCAP_TXCSUM) != 0 && 3435 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 3436 ifp->if_capenable ^= IFCAP_TXCSUM; 3437 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) { 3438 rev = sc->rl_hwrev->rl_rev; 3439 if (rev == RL_HWREV_8168C || 3440 rev == RL_HWREV_8168C_SPIN2 || 3441 rev == RL_HWREV_8168CP) 3442 ifp->if_hwassist |= CSUM_TCP | CSUM_UDP; 3443 else 3444 ifp->if_hwassist |= RE_CSUM_FEATURES; 3445 } else 3446 ifp->if_hwassist &= ~RE_CSUM_FEATURES; 3447 reinit = 1; 3448 } 3449 if ((mask & IFCAP_RXCSUM) != 0 && 3450 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) { 3451 ifp->if_capenable ^= IFCAP_RXCSUM; 3452 reinit = 1; 3453 } 3454 if ((mask & IFCAP_TSO4) != 0 && 3455 (ifp->if_capabilities & IFCAP_TSO4) != 0) { 3456 ifp->if_capenable ^= IFCAP_TSO4; 3457 if ((IFCAP_TSO4 & ifp->if_capenable) != 0) 3458 ifp->if_hwassist |= CSUM_TSO; 3459 else 3460 ifp->if_hwassist &= ~CSUM_TSO; 3461 if (ifp->if_mtu > RL_TSO_MTU && 3462 (ifp->if_capenable & IFCAP_TSO4) != 0) { 3463 ifp->if_capenable &= ~IFCAP_TSO4; 3464 ifp->if_hwassist &= ~CSUM_TSO; 3465 } 3466 } 3467 if ((mask & IFCAP_VLAN_HWTSO) != 0 && 3468 (ifp->if_capabilities & IFCAP_VLAN_HWTSO) != 0) 3469 ifp->if_capenable ^= IFCAP_VLAN_HWTSO; 3470 if ((mask & IFCAP_VLAN_HWTAGGING) != 0 && 3471 (ifp->if_capabilities & IFCAP_VLAN_HWTAGGING) != 0) { 3472 ifp->if_capenable ^= IFCAP_VLAN_HWTAGGING; 3473 /* TSO over VLAN requires VLAN hardware tagging. */ 3474 if ((ifp->if_capenable & IFCAP_VLAN_HWTAGGING) == 0) 3475 ifp->if_capenable &= ~IFCAP_VLAN_HWTSO; 3476 reinit = 1; 3477 } 3478 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0 && 3479 (mask & (IFCAP_HWCSUM | IFCAP_TSO4 | 3480 IFCAP_VLAN_HWTSO)) != 0) 3481 reinit = 1; 3482 if ((mask & IFCAP_WOL) != 0 && 3483 (ifp->if_capabilities & IFCAP_WOL) != 0) { 3484 if ((mask & IFCAP_WOL_UCAST) != 0) 3485 ifp->if_capenable ^= IFCAP_WOL_UCAST; 3486 if ((mask & IFCAP_WOL_MCAST) != 0) 3487 ifp->if_capenable ^= IFCAP_WOL_MCAST; 3488 if ((mask & IFCAP_WOL_MAGIC) != 0) 3489 ifp->if_capenable ^= IFCAP_WOL_MAGIC; 3490 } 3491 if (reinit && ifp->if_drv_flags & IFF_DRV_RUNNING) { 3492 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3493 re_init_locked(sc); 3494 } 3495 RL_UNLOCK(sc); 3496 VLAN_CAPABILITIES(ifp); 3497 } 3498 break; 3499 default: 3500 error = ether_ioctl(ifp, command, data); 3501 break; 3502 } 3503 3504 return (error); 3505} 3506 3507static void 3508re_watchdog(struct rl_softc *sc) 3509{ 3510 struct ifnet *ifp; 3511 3512 RL_LOCK_ASSERT(sc); 3513 3514 if (sc->rl_watchdog_timer == 0 || --sc->rl_watchdog_timer != 0) 3515 return; 3516 3517 ifp = sc->rl_ifp; 3518 re_txeof(sc); 3519 if (sc->rl_ldata.rl_tx_free == sc->rl_ldata.rl_tx_desc_cnt) { 3520 if_printf(ifp, "watchdog timeout (missed Tx interrupts) " 3521 "-- recovering\n"); 3522 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3523 re_start_locked(ifp); 3524 return; 3525 } 3526 3527 if_printf(ifp, "watchdog timeout\n"); 3528 ifp->if_oerrors++; 3529 3530 re_rxeof(sc, NULL); 3531 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 3532 re_init_locked(sc); 3533 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 3534 re_start_locked(ifp); 3535} 3536 3537/* 3538 * Stop the adapter and free any mbufs allocated to the 3539 * RX and TX lists. 3540 */ 3541static void 3542re_stop(struct rl_softc *sc) 3543{ 3544 int i; 3545 struct ifnet *ifp; 3546 struct rl_txdesc *txd; 3547 struct rl_rxdesc *rxd; 3548 3549 RL_LOCK_ASSERT(sc); 3550 3551 ifp = sc->rl_ifp; 3552 3553 sc->rl_watchdog_timer = 0; 3554 callout_stop(&sc->rl_stat_callout); 3555 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 3556 3557 /* 3558 * Disable accepting frames to put RX MAC into idle state. 3559 * Otherwise it's possible to get frames while stop command 3560 * execution is in progress and controller can DMA the frame 3561 * to already freed RX buffer during that period. 3562 */ 3563 CSR_WRITE_4(sc, RL_RXCFG, CSR_READ_4(sc, RL_RXCFG) & 3564 ~(RL_RXCFG_RX_ALLPHYS | RL_RXCFG_RX_INDIV | RL_RXCFG_RX_MULTI | 3565 RL_RXCFG_RX_BROAD)); 3566 3567 if ((sc->rl_flags & RL_FLAG_WAIT_TXPOLL) != 0) { 3568 for (i = RL_TIMEOUT; i > 0; i--) { 3569 if ((CSR_READ_1(sc, sc->rl_txstart) & 3570 RL_TXSTART_START) == 0) 3571 break; 3572 DELAY(20); 3573 } 3574 if (i == 0) 3575 device_printf(sc->rl_dev, 3576 "stopping TX poll timed out!\n"); 3577 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3578 } else if ((sc->rl_flags & RL_FLAG_CMDSTOP) != 0) { 3579 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_STOPREQ | RL_CMD_TX_ENB | 3580 RL_CMD_RX_ENB); 3581 if ((sc->rl_flags & RL_FLAG_CMDSTOP_WAIT_TXQ) != 0) { 3582 for (i = RL_TIMEOUT; i > 0; i--) { 3583 if ((CSR_READ_4(sc, RL_TXCFG) & 3584 RL_TXCFG_QUEUE_EMPTY) != 0) 3585 break; 3586 DELAY(100); 3587 } 3588 if (i == 0) 3589 device_printf(sc->rl_dev, 3590 "stopping TXQ timed out!\n"); 3591 } 3592 } else 3593 CSR_WRITE_1(sc, RL_COMMAND, 0x00); 3594 DELAY(1000); 3595 CSR_WRITE_2(sc, RL_IMR, 0x0000); 3596 CSR_WRITE_2(sc, RL_ISR, 0xFFFF); 3597 3598 if (sc->rl_head != NULL) { 3599 m_freem(sc->rl_head); 3600 sc->rl_head = sc->rl_tail = NULL; 3601 } 3602 3603 /* Free the TX list buffers. */ 3604 for (i = 0; i < sc->rl_ldata.rl_tx_desc_cnt; i++) { 3605 txd = &sc->rl_ldata.rl_tx_desc[i]; 3606 if (txd->tx_m != NULL) { 3607 bus_dmamap_sync(sc->rl_ldata.rl_tx_mtag, 3608 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 3609 bus_dmamap_unload(sc->rl_ldata.rl_tx_mtag, 3610 txd->tx_dmamap); 3611 m_freem(txd->tx_m); 3612 txd->tx_m = NULL; 3613 } 3614 } 3615 3616 /* Free the RX list buffers. */ 3617 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3618 rxd = &sc->rl_ldata.rl_rx_desc[i]; 3619 if (rxd->rx_m != NULL) { 3620 bus_dmamap_sync(sc->rl_ldata.rl_rx_mtag, 3621 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3622 bus_dmamap_unload(sc->rl_ldata.rl_rx_mtag, 3623 rxd->rx_dmamap); 3624 m_freem(rxd->rx_m); 3625 rxd->rx_m = NULL; 3626 } 3627 } 3628 3629 if ((sc->rl_flags & RL_FLAG_JUMBOV2) != 0) { 3630 for (i = 0; i < sc->rl_ldata.rl_rx_desc_cnt; i++) { 3631 rxd = &sc->rl_ldata.rl_jrx_desc[i]; 3632 if (rxd->rx_m != NULL) { 3633 bus_dmamap_sync(sc->rl_ldata.rl_jrx_mtag, 3634 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 3635 bus_dmamap_unload(sc->rl_ldata.rl_jrx_mtag, 3636 rxd->rx_dmamap); 3637 m_freem(rxd->rx_m); 3638 rxd->rx_m = NULL; 3639 } 3640 } 3641 } 3642} 3643 3644/* 3645 * Device suspend routine. Stop the interface and save some PCI 3646 * settings in case the BIOS doesn't restore them properly on 3647 * resume. 3648 */ 3649static int 3650re_suspend(device_t dev) 3651{ 3652 struct rl_softc *sc; 3653 3654 sc = device_get_softc(dev); 3655 3656 RL_LOCK(sc); 3657 re_stop(sc); 3658 re_setwol(sc); 3659 sc->suspended = 1; 3660 RL_UNLOCK(sc); 3661 3662 return (0); 3663} 3664 3665/* 3666 * Device resume routine. Restore some PCI settings in case the BIOS 3667 * doesn't, re-enable busmastering, and restart the interface if 3668 * appropriate. 3669 */ 3670static int 3671re_resume(device_t dev) 3672{ 3673 struct rl_softc *sc; 3674 struct ifnet *ifp; 3675 3676 sc = device_get_softc(dev); 3677 3678 RL_LOCK(sc); 3679 3680 ifp = sc->rl_ifp; 3681 /* Take controller out of sleep mode. */ 3682 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3683 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3684 CSR_WRITE_1(sc, RL_GPIO, 3685 CSR_READ_1(sc, RL_GPIO) | 0x01); 3686 } 3687 3688 /* 3689 * Clear WOL matching such that normal Rx filtering 3690 * wouldn't interfere with WOL patterns. 3691 */ 3692 re_clrwol(sc); 3693 3694 /* reinitialize interface if necessary */ 3695 if (ifp->if_flags & IFF_UP) 3696 re_init_locked(sc); 3697 3698 sc->suspended = 0; 3699 RL_UNLOCK(sc); 3700 3701 return (0); 3702} 3703 3704/* 3705 * Stop all chip I/O so that the kernel's probe routines don't 3706 * get confused by errant DMAs when rebooting. 3707 */ 3708static int 3709re_shutdown(device_t dev) 3710{ 3711 struct rl_softc *sc; 3712 3713 sc = device_get_softc(dev); 3714 3715 RL_LOCK(sc); 3716 re_stop(sc); 3717 /* 3718 * Mark interface as down since otherwise we will panic if 3719 * interrupt comes in later on, which can happen in some 3720 * cases. 3721 */ 3722 sc->rl_ifp->if_flags &= ~IFF_UP; 3723 re_setwol(sc); 3724 RL_UNLOCK(sc); 3725 3726 return (0); 3727} 3728 3729static void 3730re_set_linkspeed(struct rl_softc *sc) 3731{ 3732 struct mii_softc *miisc; 3733 struct mii_data *mii; 3734 int aneg, i, phyno; 3735 3736 RL_LOCK_ASSERT(sc); 3737 3738 mii = device_get_softc(sc->rl_miibus); 3739 mii_pollstat(mii); 3740 aneg = 0; 3741 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) == 3742 (IFM_ACTIVE | IFM_AVALID)) { 3743 switch IFM_SUBTYPE(mii->mii_media_active) { 3744 case IFM_10_T: 3745 case IFM_100_TX: 3746 return; 3747 case IFM_1000_T: 3748 aneg++; 3749 break; 3750 default: 3751 break; 3752 } 3753 } 3754 miisc = LIST_FIRST(&mii->mii_phys); 3755 phyno = miisc->mii_phy; 3756 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 3757 PHY_RESET(miisc); 3758 re_miibus_writereg(sc->rl_dev, phyno, MII_100T2CR, 0); 3759 re_miibus_writereg(sc->rl_dev, phyno, 3760 MII_ANAR, ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10 | ANAR_CSMA); 3761 re_miibus_writereg(sc->rl_dev, phyno, 3762 MII_BMCR, BMCR_AUTOEN | BMCR_STARTNEG); 3763 DELAY(1000); 3764 if (aneg != 0) { 3765 /* 3766 * Poll link state until re(4) get a 10/100Mbps link. 3767 */ 3768 for (i = 0; i < MII_ANEGTICKS_GIGE; i++) { 3769 mii_pollstat(mii); 3770 if ((mii->mii_media_status & (IFM_ACTIVE | IFM_AVALID)) 3771 == (IFM_ACTIVE | IFM_AVALID)) { 3772 switch (IFM_SUBTYPE(mii->mii_media_active)) { 3773 case IFM_10_T: 3774 case IFM_100_TX: 3775 return; 3776 default: 3777 break; 3778 } 3779 } 3780 RL_UNLOCK(sc); 3781 pause("relnk", hz); 3782 RL_LOCK(sc); 3783 } 3784 if (i == MII_ANEGTICKS_GIGE) 3785 device_printf(sc->rl_dev, 3786 "establishing a link failed, WOL may not work!"); 3787 } 3788 /* 3789 * No link, force MAC to have 100Mbps, full-duplex link. 3790 * MAC does not require reprogramming on resolved speed/duplex, 3791 * so this is just for completeness. 3792 */ 3793 mii->mii_media_status = IFM_AVALID | IFM_ACTIVE; 3794 mii->mii_media_active = IFM_ETHER | IFM_100_TX | IFM_FDX; 3795} 3796 3797static void 3798re_setwol(struct rl_softc *sc) 3799{ 3800 struct ifnet *ifp; 3801 int pmc; 3802 uint16_t pmstat; 3803 uint8_t v; 3804 3805 RL_LOCK_ASSERT(sc); 3806 3807 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3808 return; 3809 3810 ifp = sc->rl_ifp; 3811 /* Put controller into sleep mode. */ 3812 if ((sc->rl_flags & RL_FLAG_MACSLEEP) != 0) { 3813 if ((CSR_READ_1(sc, RL_MACDBG) & 0x80) == 0x80) 3814 CSR_WRITE_1(sc, RL_GPIO, 3815 CSR_READ_1(sc, RL_GPIO) & ~0x01); 3816 } 3817 if ((ifp->if_capenable & IFCAP_WOL) != 0) { 3818 re_set_rxmode(sc); 3819 if ((sc->rl_flags & RL_FLAG_WOL_MANLINK) != 0) 3820 re_set_linkspeed(sc); 3821 if ((sc->rl_flags & RL_FLAG_WOLRXENB) != 0) 3822 CSR_WRITE_1(sc, RL_COMMAND, RL_CMD_RX_ENB); 3823 } 3824 /* Enable config register write. */ 3825 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3826 3827 /* Enable PME. */ 3828 v = CSR_READ_1(sc, sc->rl_cfg1); 3829 v &= ~RL_CFG1_PME; 3830 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3831 v |= RL_CFG1_PME; 3832 CSR_WRITE_1(sc, sc->rl_cfg1, v); 3833 3834 v = CSR_READ_1(sc, sc->rl_cfg3); 3835 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3836 if ((ifp->if_capenable & IFCAP_WOL_MAGIC) != 0) 3837 v |= RL_CFG3_WOL_MAGIC; 3838 CSR_WRITE_1(sc, sc->rl_cfg3, v); 3839 3840 v = CSR_READ_1(sc, sc->rl_cfg5); 3841 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST | 3842 RL_CFG5_WOL_LANWAKE); 3843 if ((ifp->if_capenable & IFCAP_WOL_UCAST) != 0) 3844 v |= RL_CFG5_WOL_UCAST; 3845 if ((ifp->if_capenable & IFCAP_WOL_MCAST) != 0) 3846 v |= RL_CFG5_WOL_MCAST | RL_CFG5_WOL_BCAST; 3847 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3848 v |= RL_CFG5_WOL_LANWAKE; 3849 CSR_WRITE_1(sc, sc->rl_cfg5, v); 3850 3851 /* Config register write done. */ 3852 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3853 3854 if ((ifp->if_capenable & IFCAP_WOL) == 0 && 3855 (sc->rl_flags & RL_FLAG_PHYWAKE_PM) != 0) 3856 CSR_WRITE_1(sc, RL_PMCH, CSR_READ_1(sc, RL_PMCH) & ~0x80); 3857 /* 3858 * It seems that hardware resets its link speed to 100Mbps in 3859 * power down mode so switching to 100Mbps in driver is not 3860 * needed. 3861 */ 3862 3863 /* Request PME if WOL is requested. */ 3864 pmstat = pci_read_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, 2); 3865 pmstat &= ~(PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE); 3866 if ((ifp->if_capenable & IFCAP_WOL) != 0) 3867 pmstat |= PCIM_PSTAT_PME | PCIM_PSTAT_PMEENABLE; 3868 pci_write_config(sc->rl_dev, pmc + PCIR_POWER_STATUS, pmstat, 2); 3869} 3870 3871static void 3872re_clrwol(struct rl_softc *sc) 3873{ 3874 int pmc; 3875 uint8_t v; 3876 3877 RL_LOCK_ASSERT(sc); 3878 3879 if (pci_find_cap(sc->rl_dev, PCIY_PMG, &pmc) != 0) 3880 return; 3881 3882 /* Enable config register write. */ 3883 CSR_WRITE_1(sc, RL_EECMD, RL_EE_MODE); 3884 3885 v = CSR_READ_1(sc, sc->rl_cfg3); 3886 v &= ~(RL_CFG3_WOL_LINK | RL_CFG3_WOL_MAGIC); 3887 CSR_WRITE_1(sc, sc->rl_cfg3, v); 3888 3889 /* Config register write done. */ 3890 CSR_WRITE_1(sc, RL_EECMD, RL_EEMODE_OFF); 3891 3892 v = CSR_READ_1(sc, sc->rl_cfg5); 3893 v &= ~(RL_CFG5_WOL_BCAST | RL_CFG5_WOL_MCAST | RL_CFG5_WOL_UCAST); 3894 v &= ~RL_CFG5_WOL_LANWAKE; 3895 CSR_WRITE_1(sc, sc->rl_cfg5, v); 3896} 3897 3898static void 3899re_add_sysctls(struct rl_softc *sc) 3900{ 3901 struct sysctl_ctx_list *ctx; 3902 struct sysctl_oid_list *children; 3903 int error; 3904 3905 ctx = device_get_sysctl_ctx(sc->rl_dev); 3906 children = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->rl_dev)); 3907 3908 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "stats", 3909 CTLTYPE_INT | CTLFLAG_RW, sc, 0, re_sysctl_stats, "I", 3910 "Statistics Information"); 3911 if ((sc->rl_flags & (RL_FLAG_MSI | RL_FLAG_MSIX)) == 0) 3912 return; 3913 3914 SYSCTL_ADD_PROC(ctx, children, OID_AUTO, "int_rx_mod", 3915 CTLTYPE_INT | CTLFLAG_RW, &sc->rl_int_rx_mod, 0, 3916 sysctl_hw_re_int_mod, "I", "re RX interrupt moderation"); 3917 /* Pull in device tunables. */ 3918 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3919 error = resource_int_value(device_get_name(sc->rl_dev), 3920 device_get_unit(sc->rl_dev), "int_rx_mod", &sc->rl_int_rx_mod); 3921 if (error == 0) { 3922 if (sc->rl_int_rx_mod < RL_TIMER_MIN || 3923 sc->rl_int_rx_mod > RL_TIMER_MAX) { 3924 device_printf(sc->rl_dev, "int_rx_mod value out of " 3925 "range; using default: %d\n", 3926 RL_TIMER_DEFAULT); 3927 sc->rl_int_rx_mod = RL_TIMER_DEFAULT; 3928 } 3929 } 3930 3931} 3932 3933static int 3934re_sysctl_stats(SYSCTL_HANDLER_ARGS) 3935{ 3936 struct rl_softc *sc; 3937 struct rl_stats *stats; 3938 int error, i, result; 3939 3940 result = -1; 3941 error = sysctl_handle_int(oidp, &result, 0, req); 3942 if (error || req->newptr == NULL) 3943 return (error); 3944 3945 if (result == 1) { 3946 sc = (struct rl_softc *)arg1; 3947 RL_LOCK(sc); 3948 if ((sc->rl_ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { 3949 RL_UNLOCK(sc); 3950 goto done; 3951 } 3952 bus_dmamap_sync(sc->rl_ldata.rl_stag, 3953 sc->rl_ldata.rl_smap, BUS_DMASYNC_PREREAD); 3954 CSR_WRITE_4(sc, RL_DUMPSTATS_HI, 3955 RL_ADDR_HI(sc->rl_ldata.rl_stats_addr)); 3956 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 3957 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr)); 3958 CSR_WRITE_4(sc, RL_DUMPSTATS_LO, 3959 RL_ADDR_LO(sc->rl_ldata.rl_stats_addr | 3960 RL_DUMPSTATS_START)); 3961 for (i = RL_TIMEOUT; i > 0; i--) { 3962 if ((CSR_READ_4(sc, RL_DUMPSTATS_LO) & 3963 RL_DUMPSTATS_START) == 0) 3964 break; 3965 DELAY(1000); 3966 } 3967 bus_dmamap_sync(sc->rl_ldata.rl_stag, 3968 sc->rl_ldata.rl_smap, BUS_DMASYNC_POSTREAD); 3969 RL_UNLOCK(sc); 3970 if (i == 0) { 3971 device_printf(sc->rl_dev, 3972 "DUMP statistics request timed out\n"); 3973 return (ETIMEDOUT); 3974 } 3975done: 3976 stats = sc->rl_ldata.rl_stats; 3977 printf("%s statistics:\n", device_get_nameunit(sc->rl_dev)); 3978 printf("Tx frames : %ju\n", 3979 (uintmax_t)le64toh(stats->rl_tx_pkts)); 3980 printf("Rx frames : %ju\n", 3981 (uintmax_t)le64toh(stats->rl_rx_pkts)); 3982 printf("Tx errors : %ju\n", 3983 (uintmax_t)le64toh(stats->rl_tx_errs)); 3984 printf("Rx errors : %u\n", 3985 le32toh(stats->rl_rx_errs)); 3986 printf("Rx missed frames : %u\n", 3987 (uint32_t)le16toh(stats->rl_missed_pkts)); 3988 printf("Rx frame alignment errs : %u\n", 3989 (uint32_t)le16toh(stats->rl_rx_framealign_errs)); 3990 printf("Tx single collisions : %u\n", 3991 le32toh(stats->rl_tx_onecoll)); 3992 printf("Tx multiple collisions : %u\n", 3993 le32toh(stats->rl_tx_multicolls)); 3994 printf("Rx unicast frames : %ju\n", 3995 (uintmax_t)le64toh(stats->rl_rx_ucasts)); 3996 printf("Rx broadcast frames : %ju\n", 3997 (uintmax_t)le64toh(stats->rl_rx_bcasts)); 3998 printf("Rx multicast frames : %u\n", 3999 le32toh(stats->rl_rx_mcasts)); 4000 printf("Tx aborts : %u\n", 4001 (uint32_t)le16toh(stats->rl_tx_aborts)); 4002 printf("Tx underruns : %u\n", 4003 (uint32_t)le16toh(stats->rl_rx_underruns)); 4004 } 4005 4006 return (error); 4007} 4008 4009static int 4010sysctl_int_range(SYSCTL_HANDLER_ARGS, int low, int high) 4011{ 4012 int error, value; 4013 4014 if (arg1 == NULL) 4015 return (EINVAL); 4016 value = *(int *)arg1; 4017 error = sysctl_handle_int(oidp, &value, 0, req); 4018 if (error || req->newptr == NULL) 4019 return (error); 4020 if (value < low || value > high) 4021 return (EINVAL); 4022 *(int *)arg1 = value; 4023 4024 return (0); 4025} 4026 4027static int 4028sysctl_hw_re_int_mod(SYSCTL_HANDLER_ARGS) 4029{ 4030 4031 return (sysctl_int_range(oidp, arg1, arg2, req, RL_TIMER_MIN, 4032 RL_TIMER_MAX)); 4033} 4034