1316485Sdavidcs/* 2316485Sdavidcs * Copyright (c) 2017-2018 Cavium, Inc. 3316485Sdavidcs * All rights reserved. 4316485Sdavidcs * 5316485Sdavidcs * Redistribution and use in source and binary forms, with or without 6316485Sdavidcs * modification, are permitted provided that the following conditions 7316485Sdavidcs * are met: 8316485Sdavidcs * 9316485Sdavidcs * 1. Redistributions of source code must retain the above copyright 10316485Sdavidcs * notice, this list of conditions and the following disclaimer. 11316485Sdavidcs * 2. Redistributions in binary form must reproduce the above copyright 12316485Sdavidcs * notice, this list of conditions and the following disclaimer in the 13316485Sdavidcs * documentation and/or other materials provided with the distribution. 14316485Sdavidcs * 15316485Sdavidcs * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16316485Sdavidcs * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17316485Sdavidcs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18316485Sdavidcs * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19316485Sdavidcs * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20316485Sdavidcs * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21316485Sdavidcs * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22316485Sdavidcs * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23316485Sdavidcs * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24316485Sdavidcs * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25316485Sdavidcs * POSSIBILITY OF SUCH DAMAGE. 26316485Sdavidcs * 27316485Sdavidcs * $FreeBSD: stable/10/sys/dev/qlnx/qlnxe/nvm_map.h 337519 2018-08-09 01:39:47Z davidcs $ 28316485Sdavidcs * 29316485Sdavidcs */ 30316485Sdavidcs 31320162Sdavidcs 32316485Sdavidcs/**************************************************************************** 33316485Sdavidcs * Name: nvm_map.h 34316485Sdavidcs * 35316485Sdavidcs * Description: Everest NVRAM map 36316485Sdavidcs * 37316485Sdavidcs ****************************************************************************/ 38316485Sdavidcs 39316485Sdavidcs#ifndef NVM_MAP_H 40316485Sdavidcs#define NVM_MAP_H 41316485Sdavidcs 42316485Sdavidcs#define CRC_MAGIC_VALUE 0xDEBB20E3 43316485Sdavidcs#define CRC32_POLYNOMIAL 0xEDB88320 44337519Sdavidcs#define _KB(x) (x*1024) 45337519Sdavidcs#define _MB(x) (_KB(x)*1024) 46316485Sdavidcs#define NVM_CRC_SIZE (sizeof(u32)) 47316485Sdavidcsenum nvm_sw_arbitrator { 48316485Sdavidcs NVM_SW_ARB_HOST, 49316485Sdavidcs NVM_SW_ARB_MCP, 50316485Sdavidcs NVM_SW_ARB_UART, 51316485Sdavidcs NVM_SW_ARB_RESERVED 52316485Sdavidcs}; 53316485Sdavidcs 54316485Sdavidcs/**************************************************************************** 55316485Sdavidcs * Boot Strap Region * 56316485Sdavidcs ****************************************************************************/ 57316485Sdavidcsstruct legacy_bootstrap_region { 58316485Sdavidcs u32 magic_value; /* a pattern not likely to occur randomly */ 59316485Sdavidcs#define NVM_MAGIC_VALUE 0x669955aa 60316485Sdavidcs u32 sram_start_addr; /* where to locate LIM code (byte addr) */ 61316485Sdavidcs u32 code_len; /* boot code length (in dwords) */ 62316485Sdavidcs u32 code_start_addr; /* location of code on media (media byte addr) */ 63316485Sdavidcs u32 crc; /* 32-bit CRC */ 64316485Sdavidcs}; 65316485Sdavidcs 66316485Sdavidcs/**************************************************************************** 67316485Sdavidcs * Directories Region * 68316485Sdavidcs ****************************************************************************/ 69316485Sdavidcsstruct nvm_code_entry { 70316485Sdavidcs u32 image_type; /* Image type */ 71316485Sdavidcs u32 nvm_start_addr; /* NVM address of the image */ 72316485Sdavidcs u32 len; /* Include CRC */ 73316485Sdavidcs u32 sram_start_addr; /* Where to load the image on the scratchpad */ 74316485Sdavidcs u32 sram_run_addr; /* Relevant in case of MIM only */ 75316485Sdavidcs}; 76316485Sdavidcs 77316485Sdavidcsenum nvm_image_type { 78316485Sdavidcs NVM_TYPE_TIM1 = 0x01, 79316485Sdavidcs NVM_TYPE_TIM2 = 0x02, 80316485Sdavidcs NVM_TYPE_MIM1 = 0x03, 81316485Sdavidcs NVM_TYPE_MIM2 = 0x04, 82316485Sdavidcs NVM_TYPE_MBA = 0x05, 83316485Sdavidcs NVM_TYPE_MODULES_PN = 0x06, 84316485Sdavidcs NVM_TYPE_VPD = 0x07, 85316485Sdavidcs NVM_TYPE_MFW_TRACE1 = 0x08, 86316485Sdavidcs NVM_TYPE_MFW_TRACE2 = 0x09, 87316485Sdavidcs NVM_TYPE_NVM_CFG1 = 0x0a, 88316485Sdavidcs NVM_TYPE_L2B = 0x0b, 89316485Sdavidcs NVM_TYPE_DIR1 = 0x0c, 90316485Sdavidcs NVM_TYPE_EAGLE_FW1 = 0x0d, 91316485Sdavidcs NVM_TYPE_FALCON_FW1 = 0x0e, 92316485Sdavidcs NVM_TYPE_PCIE_FW1 = 0x0f, 93316485Sdavidcs NVM_TYPE_HW_SET = 0x10, 94316485Sdavidcs NVM_TYPE_LIM = 0x11, 95316485Sdavidcs NVM_TYPE_AVS_FW1 = 0x12, 96316485Sdavidcs NVM_TYPE_DIR2 = 0x13, 97316485Sdavidcs NVM_TYPE_CCM = 0x14, 98316485Sdavidcs NVM_TYPE_EAGLE_FW2 = 0x15, 99316485Sdavidcs NVM_TYPE_FALCON_FW2 = 0x16, 100316485Sdavidcs NVM_TYPE_PCIE_FW2 = 0x17, 101316485Sdavidcs NVM_TYPE_AVS_FW2 = 0x18, 102316485Sdavidcs NVM_TYPE_INIT_HW = 0x19, 103316485Sdavidcs NVM_TYPE_DEFAULT_CFG= 0x1a, 104316485Sdavidcs NVM_TYPE_MDUMP = 0x1b, 105316485Sdavidcs NVM_TYPE_NVM_META = 0x1c, 106316485Sdavidcs NVM_TYPE_ISCSI_CFG = 0x1d, 107316485Sdavidcs NVM_TYPE_FCOE_CFG = 0x1f, 108316485Sdavidcs NVM_TYPE_ETH_PHY_FW1 = 0x20, 109316485Sdavidcs NVM_TYPE_ETH_PHY_FW2 = 0x21, 110316485Sdavidcs NVM_TYPE_BDN = 0x22, 111316485Sdavidcs NVM_TYPE_8485X_PHY_FW = 0x23, 112316485Sdavidcs NVM_TYPE_PUB_KEY = 0x24, 113316485Sdavidcs NVM_TYPE_RECOVERY = 0x25, 114337519Sdavidcs NVM_TYPE_PLDM = 0x26, 115337519Sdavidcs NVM_TYPE_UPK1 = 0x27, 116337519Sdavidcs NVM_TYPE_UPK2 = 0x28, 117337519Sdavidcs NVM_TYPE_MASTER_KC = 0x29, 118337519Sdavidcs NVM_TYPE_BACKUP_KC = 0x2a, 119337519Sdavidcs NVM_TYPE_ROM_TEST = 0xf0, 120316485Sdavidcs NVM_TYPE_MAX, 121316485Sdavidcs}; 122316485Sdavidcs 123316485Sdavidcs#ifdef DEFINE_IMAGE_TABLE 124316485Sdavidcsstruct image_map { 125316485Sdavidcs char name[32]; 126316485Sdavidcs char option[32]; 127316485Sdavidcs u32 image_type; 128316485Sdavidcs}; 129316485Sdavidcs 130316485Sdavidcsstruct image_map g_image_table[] = { 131316485Sdavidcs {"TIM1", "-tim1", NVM_TYPE_TIM1}, 132316485Sdavidcs {"TIM2", "-tim2", NVM_TYPE_TIM2}, 133316485Sdavidcs {"MIM1", "-mim1", NVM_TYPE_MIM1}, 134316485Sdavidcs {"MIM2", "-mim2", NVM_TYPE_MIM2}, 135316485Sdavidcs {"MBA", "-mba", NVM_TYPE_MBA}, 136316485Sdavidcs {"OPT_MODULES", "-optm", NVM_TYPE_MODULES_PN}, 137316485Sdavidcs {"VPD", "-vpd", NVM_TYPE_VPD}, 138316485Sdavidcs {"MFW_TRACE1", "-mfwt1", NVM_TYPE_MFW_TRACE1}, 139316485Sdavidcs {"MFW_TRACE2", "-mfwt2", NVM_TYPE_MFW_TRACE2}, 140316485Sdavidcs {"NVM_CFG1", "-cfg", NVM_TYPE_NVM_CFG1}, 141316485Sdavidcs {"L2B", "-l2b", NVM_TYPE_L2B}, 142316485Sdavidcs {"DIR1", "-dir1", NVM_TYPE_DIR1}, 143316485Sdavidcs {"EAGLE_FW1", "-eagle1", NVM_TYPE_EAGLE_FW1}, 144316485Sdavidcs {"FALCON_FW1", "-falcon1", NVM_TYPE_FALCON_FW1}, 145316485Sdavidcs {"PCIE_FW1", "-pcie1", NVM_TYPE_PCIE_FW1}, 146316485Sdavidcs {"HW_SET", "-hw_set", NVM_TYPE_HW_SET}, 147316485Sdavidcs {"LIM", "-lim", NVM_TYPE_LIM}, 148316485Sdavidcs {"AVS_FW1", "-avs1", NVM_TYPE_AVS_FW1}, 149316485Sdavidcs {"DIR2", "-dir2", NVM_TYPE_DIR2}, 150316485Sdavidcs {"CCM", "-ccm", NVM_TYPE_CCM}, 151316485Sdavidcs {"EAGLE_FW2", "-eagle2", NVM_TYPE_EAGLE_FW2}, 152316485Sdavidcs {"FALCON_FW2", "-falcon2", NVM_TYPE_FALCON_FW2}, 153316485Sdavidcs {"PCIE_FW2", "-pcie2", NVM_TYPE_PCIE_FW2}, 154316485Sdavidcs {"AVS_FW2", "-avs2", NVM_TYPE_AVS_FW2}, 155316485Sdavidcs {"INIT_HW", "-init_hw", NVM_TYPE_INIT_HW}, 156316485Sdavidcs {"DEFAULT_CFG", "-def_cfg", NVM_TYPE_DEFAULT_CFG}, 157316485Sdavidcs {"CRASH_DUMP", "-mdump", NVM_TYPE_MDUMP}, 158316485Sdavidcs {"META", "-meta", NVM_TYPE_NVM_META}, 159316485Sdavidcs {"ISCSI_CFG", "-iscsi_cfg", NVM_TYPE_ISCSI_CFG}, 160316485Sdavidcs {"FCOE_CFG", "-fcoe_cfg",NVM_TYPE_FCOE_CFG}, 161316485Sdavidcs {"ETH_PHY_FW1", "-ethphy1", NVM_TYPE_ETH_PHY_FW1}, 162316485Sdavidcs {"ETH_PHY_FW2", "-ethphy2", NVM_TYPE_ETH_PHY_FW2}, 163316485Sdavidcs {"BDN", "-bdn", NVM_TYPE_BDN}, 164316485Sdavidcs {"PK", "-pk", NVM_TYPE_PUB_KEY}, 165337519Sdavidcs {"RECOVERY", "-recovery",NVM_TYPE_RECOVERY}, 166337519Sdavidcs {"PLDM", "-pldm", NVM_TYPE_PLDM}, 167337519Sdavidcs {"UPK1", "-upk1", NVM_TYPE_UPK1}, 168337519Sdavidcs {"UPK2", "-upk2", NVM_TYPE_UPK2}, 169337519Sdavidcs {"ROMTEST", "-romtest" ,NVM_TYPE_ROM_TEST}, 170337519Sdavidcs {"MASTER_KC", "-kc" ,NVM_TYPE_MASTER_KC}, 171337519Sdavidcs {"BACKUP_KC", "" ,NVM_TYPE_BACKUP_KC} 172316485Sdavidcs}; 173316485Sdavidcs 174316485Sdavidcs#define IMAGE_TABLE_SIZE (sizeof(g_image_table) / sizeof(struct image_map)) 175316485Sdavidcs 176316485Sdavidcs#endif /* #ifdef DEFINE_IMAGE_TABLE */ 177316485Sdavidcs#define MAX_NVM_DIR_ENTRIES 150 178316485Sdavidcs/* Note: The has given 150 possible entries since anyway each file captures at least one page. */ 179316485Sdavidcs 180337519Sdavidcsstruct nvm_dir_meta { 181337519Sdavidcs u32 dir_id; 182337519Sdavidcs u32 nvm_dir_addr; 183337519Sdavidcs u32 num_images; 184337519Sdavidcs u32 next_mfw_to_run; 185337519Sdavidcs}; 186337519Sdavidcs 187337519Sdavidcsstruct nvm_dir { 188316485Sdavidcs s32 seq; /* This dword is used to indicate whether this dir is valid, and whether it is more updated than the other dir */ 189316485Sdavidcs#define NVM_DIR_NEXT_MFW_MASK 0x00000001 190316485Sdavidcs#define NVM_DIR_SEQ_MASK 0xfffffffe 191316485Sdavidcs#define NVM_DIR_NEXT_MFW(seq) ((seq) & NVM_DIR_NEXT_MFW_MASK) 192316485Sdavidcs#define NVM_DIR_UPDATE_SEQ(_seq, swap_mfw) \ 193316485Sdavidcs do { \ 194316485Sdavidcs _seq = (((_seq + 2) & NVM_DIR_SEQ_MASK) | (NVM_DIR_NEXT_MFW(_seq ^ swap_mfw))); \ 195316485Sdavidcs } while (0) 196316485Sdavidcs#define IS_DIR_SEQ_VALID(seq) ((seq & NVM_DIR_SEQ_MASK) != NVM_DIR_SEQ_MASK) 197316485Sdavidcs 198316485Sdavidcs u32 num_images; 199316485Sdavidcs u32 rsrv; 200316485Sdavidcs struct nvm_code_entry code[1]; /* Up to MAX_NVM_DIR_ENTRIES */ 201316485Sdavidcs}; 202316485Sdavidcs#define NVM_DIR_SIZE(_num_images) (sizeof(struct nvm_dir) + (_num_images - 1) * sizeof(struct nvm_code_entry) + NVM_CRC_SIZE) 203316485Sdavidcs 204316485Sdavidcsstruct nvm_vpd_image { 205316485Sdavidcs u32 format_revision; 206316485Sdavidcs#define VPD_IMAGE_VERSION 1 207316485Sdavidcs 208316485Sdavidcs /* This array length depends on the number of VPD fields */ 209316485Sdavidcs u8 vpd_data[1]; 210316485Sdavidcs}; 211316485Sdavidcs 212316485Sdavidcs/**************************************************************************** 213316485Sdavidcs * NVRAM FULL MAP * 214316485Sdavidcs ****************************************************************************/ 215316485Sdavidcs#define DIR_ID_1 (0) 216316485Sdavidcs#define DIR_ID_2 (1) 217316485Sdavidcs#define MAX_DIR_IDS (2) 218316485Sdavidcs 219316485Sdavidcs#define MFW_BUNDLE_1 (0) 220316485Sdavidcs#define MFW_BUNDLE_2 (1) 221316485Sdavidcs#define MAX_MFW_BUNDLES (2) 222316485Sdavidcs 223316485Sdavidcs#define FLASH_PAGE_SIZE 0x1000 224316485Sdavidcs#define NVM_DIR_MAX_SIZE (FLASH_PAGE_SIZE) /* 4Kb */ 225337519Sdavidcs#define LEGACY_ASIC_MIM_MAX_SIZE (_KB(1200)) /* 1.2Mb - E4*/ 226337519Sdavidcs#define NG_ASIC_MIM_MAX_SIZE (_MB(2)) /* 2Mb - E5 */ 227316485Sdavidcs 228337519Sdavidcs#define FPGA_MIM_MAX_SIZE (0x3E000) /* 250Kb */ 229337519Sdavidcs 230316485Sdavidcs/* Each image must start on its own page. Bootstrap and LIM are bound together, so they can share the same page. 231316485Sdavidcs * The LIM itself should be very small, so limit it to 8Kb, but in order to open a new page, we decrement the bootstrap size out of it. 232316485Sdavidcs */ 233316485Sdavidcs#define LIM_MAX_SIZE ((2*FLASH_PAGE_SIZE) - sizeof(struct legacy_bootstrap_region) - NVM_RSV_SIZE) 234316485Sdavidcs#define LIM_OFFSET (NVM_OFFSET(lim_image)) 235316485Sdavidcs#define NVM_RSV_SIZE (44) 236337519Sdavidcs#define GET_MIM_MAX_SIZE(is_asic, is_e4) ((!is_asic) ? FPGA_MIM_MAX_SIZE : ((is_e4) ? LEGACY_ASIC_MIM_MAX_SIZE : NG_ASIC_MIM_MAX_SIZE)) 237337519Sdavidcs#define GET_MIM_OFFSET(idx, is_asic, is_e4) (NVM_OFFSET(dir[MAX_MFW_BUNDLES]) + ((idx == NVM_TYPE_MIM2) ?GET_MIM_MAX_SIZE(is_asic, is_e4) : 0)) 238337519Sdavidcs#define GET_NVM_FIXED_AREA_SIZE(is_asic, is_e4) (sizeof(struct nvm_image) + GET_MIM_MAX_SIZE(is_asic, is_e4)*2) 239316485Sdavidcs 240337519Sdavidcs#define EMUL_NVM_FIXED_AREA_SIZE() (sizeof(struct nvm_image) + GET_MIM_MAX_SIZE(0, 0)) 241337519Sdavidcs 242337519Sdavidcs#define E5_MASTER_KEY_CHAIN_ADDR 0x1000 243337519Sdavidcs#define E5_BACKUP_KEY_CHAIN_ADDR ((0x20000 << (REG_READ(0, MCP_REG_NVM_CFG4) & 0x7)) - 0x1000) 244337519Sdavidcs 245316485Sdavidcsunion nvm_dir_union { 246316485Sdavidcs struct nvm_dir dir; 247316485Sdavidcs u8 page[FLASH_PAGE_SIZE]; 248316485Sdavidcs}; 249316485Sdavidcs 250337519Sdavidcs/* E4 Address E5 Address 251337519Sdavidcs * +-------------------+ 0x000000 * +-------------------+ 0x000000 252337519Sdavidcs * | Bootstrap: | * | | 253337519Sdavidcs * | magic_number | * | | 254337519Sdavidcs * | sram_start_addr | * | | 255337519Sdavidcs * | code_len | * | | 256337519Sdavidcs * | code_start_addr | * | | 257337519Sdavidcs * | crc | * | | 258337519Sdavidcs * +-------------------+ 0x000014 * | | 259337519Sdavidcs * | rsrv | * | rsrv | 260337519Sdavidcs * +-------------------+ 0x000040 * +-------------------+ 0x001000 261337519Sdavidcs * | LIM | * | Master Key Chain | 262337519Sdavidcs * +-------------------+ 0x002000 * +-------------------+ 0x002000 263337519Sdavidcs * | Dir1 | * | Dir1 | 264337519Sdavidcs * +-------------------+ 0x003000 * +-------------------+ 0x003000 265337519Sdavidcs * | Dir2 | * | Dir2 | 266337519Sdavidcs * +-------------------+ 0x004000 * +-------------------+ 0x004000 267337519Sdavidcs * | MIM1 | * | MIM1 | 268337519Sdavidcs * +-------------------+ 0x130000 * +-------------------+ 0x130000 269337519Sdavidcs * | MIM2 | * | MIM2 | 270337519Sdavidcs * +-------------------+ 0x25C000 * +-------------------+ 0x25C000 271337519Sdavidcs * | Rest Images: | * | Rest Images: | 272337519Sdavidcs * | TIM1/2 | * | TIM1/2 | 273337519Sdavidcs * | MFW_TRACE1/2 | * | MFW_TRACE1/2 | 274337519Sdavidcs * | Eagle/Falcon FW | * | Eagle/Falcon FW | 275337519Sdavidcs * | PCIE/AVS FW | * | PCIE/AVS FW | 276337519Sdavidcs * | MBA/CCM/L2B | * | MBA/CCM/L2B | 277337519Sdavidcs * | VPD | * | VPD | 278337519Sdavidcs * | optic_modules | * +-------------------+ Flash end - 0x1000 279337519Sdavidcs * | ... | * | Backup Key Chain | 280337519Sdavidcs * +-------------------+ 0x400000 * +-------------------+ Flash end 281337519Sdavidcs*/ 282337519Sdavidcsstruct nvm_image { 283316485Sdavidcs/*********** !!! FIXED SECTIONS !!! DO NOT MODIFY !!! **********************/ 284316485Sdavidcs /* NVM Offset (size) */ 285316485Sdavidcs struct legacy_bootstrap_region bootstrap; /* 0x000000 (0x000014) */ 286316485Sdavidcs u8 rsrv[NVM_RSV_SIZE]; /* 0x000014 (0x00002c) */ 287316485Sdavidcs u8 lim_image[LIM_MAX_SIZE]; /* 0x000040 (0x001fc0) */ 288316485Sdavidcs union nvm_dir_union dir[MAX_MFW_BUNDLES]; /* 0x002000 (0x001000)x2 */ 289316485Sdavidcs /* MIM1_IMAGE 0x004000 (0x12c000) */ 290316485Sdavidcs /* MIM2_IMAGE 0x130000 (0x12c000) */ 291316485Sdavidcs/*********** !!! FIXED SECTIONS !!! DO NOT MODIFY !!! **********************/ 292316485Sdavidcs}; /* 0x134 */ 293316485Sdavidcs 294316485Sdavidcs#define NVM_OFFSET(f) ((u32_t)((int_ptr_t)(&(((struct nvm_image*)0)->f)))) 295316485Sdavidcs 296337519Sdavidcs 297316485Sdavidcsstruct hw_set_info { 298316485Sdavidcs u32 reg_type; 299316485Sdavidcs#define GRC_REG_TYPE 1 300316485Sdavidcs#define PHY_REG_TYPE 2 301316485Sdavidcs#define PCI_REG_TYPE 4 302316485Sdavidcs 303316485Sdavidcs u32 bank_num; 304316485Sdavidcs u32 pf_num; 305316485Sdavidcs u32 operation; 306316485Sdavidcs#define READ_OP 1 307316485Sdavidcs#define WRITE_OP 2 308316485Sdavidcs#define RMW_SET_OP 3 309316485Sdavidcs#define RMW_CLR_OP 4 310316485Sdavidcs 311316485Sdavidcs u32 reg_addr; 312316485Sdavidcs u32 reg_data; 313316485Sdavidcs 314316485Sdavidcs u32 reset_type; 315316485Sdavidcs#define POR_RESET_TYPE (1 << 0) 316316485Sdavidcs#define HARD_RESET_TYPE (1 << 1) 317316485Sdavidcs#define CORE_RESET_TYPE (1 << 2) 318316485Sdavidcs#define MCP_RESET_TYPE (1 << 3) 319316485Sdavidcs#define PERSET_ASSERT (1 << 4) 320316485Sdavidcs#define PERSET_DEASSERT (1 << 5) 321316485Sdavidcs 322316485Sdavidcs}; 323316485Sdavidcs 324316485Sdavidcsstruct hw_set_image { 325316485Sdavidcs u32 format_version; 326316485Sdavidcs#define HW_SET_IMAGE_VERSION 1 327316485Sdavidcs u32 no_hw_sets; 328316485Sdavidcs /* This array length depends on the no_hw_sets */ 329316485Sdavidcs struct hw_set_info hw_sets[1]; 330316485Sdavidcs}; 331316485Sdavidcs 332316485Sdavidcs#endif //NVM_MAP_H 333