128221Smsmith/*- 271622Snsouch * Copyright (c) 2001 Alcove - Nicolas Souchu 328221Smsmith * All rights reserved. 428221Smsmith * 528221Smsmith * Redistribution and use in source and binary forms, with or without 628221Smsmith * modification, are permitted provided that the following conditions 728221Smsmith * are met: 828221Smsmith * 1. Redistributions of source code must retain the above copyright 928221Smsmith * notice, this list of conditions and the following disclaimer. 1028221Smsmith * 2. Redistributions in binary form must reproduce the above copyright 1128221Smsmith * notice, this list of conditions and the following disclaimer in the 1228221Smsmith * documentation and/or other materials provided with the distribution. 1328221Smsmith * 1428221Smsmith * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1528221Smsmith * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1628221Smsmith * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1728221Smsmith * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1828221Smsmith * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1928221Smsmith * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2028221Smsmith * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2128221Smsmith * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2228221Smsmith * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2328221Smsmith * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2428221Smsmith * SUCH DAMAGE. 2528221Smsmith * 2650477Speter * $FreeBSD$ 2728221Smsmith * 2828221Smsmith */ 2938061Smsmith#ifndef __PPCREG_H 3038061Smsmith#define __PPCREG_H 3128221Smsmith 32187576Sjhb#include <sys/_lock.h> 33187576Sjhb#include <sys/_mutex.h> 34187576Sjhb 3528221Smsmith/* 3628221Smsmith * Parallel Port Chipset type. 3728221Smsmith */ 3840784Snsouch#define SMC_LIKE 0 3940784Snsouch#define SMC_37C665GT 1 4040784Snsouch#define SMC_37C666GT 2 4140784Snsouch#define NS_PC87332 3 4240784Snsouch#define NS_PC87306 4 4340784Snsouch#define INTEL_820191AA 5 /* XXX not implemented */ 4440784Snsouch#define GENERIC 6 4540784Snsouch#define WINB_W83877F 7 4640784Snsouch#define WINB_W83877AF 8 4740784Snsouch#define WINB_UNKNOWN 9 4840784Snsouch#define NS_PC87334 10 4963403Sdfr#define SMC_37C935 11 5063624Sdfr#define NS_PC87303 12 5128221Smsmith 5228221Smsmith/* 5355939Snsouch * Parallel Port Chipset Type. SMC versus GENERIC (others) 5455939Snsouch */ 5555939Snsouch#define PPC_TYPE_SMCLIKE 0 5655939Snsouch#define PPC_TYPE_GENERIC 1 5755939Snsouch 5855939Snsouch/* 5928221Smsmith * Generic structure to hold parallel port chipset info. 6028221Smsmith */ 6128221Smsmithstruct ppc_data { 62184130Sjhb device_t ppc_dev; 6355939Snsouch int ppc_model; /* chipset model if detected */ 6455939Snsouch int ppc_type; /* generic or smclike chipset type */ 6528221Smsmith 6638061Smsmith int ppc_mode; /* chipset current mode */ 6738061Smsmith int ppc_avm; /* chipset available modes */ 6871622Snsouch int ppc_dtm; /* chipset detected modes */ 6938061Smsmith 7042475Snsouch#define PPC_IRQ_NONE 0x0 7142475Snsouch#define PPC_IRQ_nACK 0x1 7242475Snsouch#define PPC_IRQ_DMA 0x2 7342475Snsouch#define PPC_IRQ_FIFO 0x4 7442475Snsouch#define PPC_IRQ_nFAULT 0x8 7542475Snsouch int ppc_irqstat; /* remind irq settings */ 7642475Snsouch 7742475Snsouch#define PPC_DMA_INIT 0x01 7842475Snsouch#define PPC_DMA_STARTED 0x02 7942475Snsouch#define PPC_DMA_COMPLETE 0x03 8042475Snsouch#define PPC_DMA_INTERRUPTED 0x04 8142475Snsouch#define PPC_DMA_ERROR 0x05 8242475Snsouch int ppc_dmastat; /* dma state */ 8342475Snsouch int ppc_dmachan; /* dma channel */ 8442475Snsouch int ppc_dmaflags; /* dma transfer flags */ 8542475Snsouch caddr_t ppc_dmaddr; /* buffer address */ 8642475Snsouch u_int ppc_dmacnt; /* count of bytes sent with dma */ 87158005Smarcel void (*ppc_dmadone)(struct ppc_data*); 8842475Snsouch 8942475Snsouch#define PPC_PWORD_MASK 0x30 9042475Snsouch#define PPC_PWORD_16 0x00 9142475Snsouch#define PPC_PWORD_8 0x10 9242475Snsouch#define PPC_PWORD_32 0x20 9342475Snsouch char ppc_pword; /* PWord size */ 9442475Snsouch short ppc_fifo; /* FIFO threshold */ 9542475Snsouch 9642475Snsouch short ppc_wthr; /* writeIntrThresold */ 9742475Snsouch short ppc_rthr; /* readIntrThresold */ 9842475Snsouch 9955939Snsouch char *ppc_ptr; /* microseq current pointer */ 10055939Snsouch int ppc_accum; /* microseq accumulator */ 10155939Snsouch int ppc_base; /* parallel port base address */ 10255939Snsouch int ppc_epp; /* EPP mode (1.7 or 1.9) */ 10355939Snsouch int ppc_irq; 10428221Smsmith 10528221Smsmith unsigned char ppc_flags; 10628221Smsmith 10755939Snsouch device_t ppbus; /* parallel port chipset corresponding ppbus */ 10855939Snsouch 10963403Sdfr int rid_irq, rid_drq, rid_ioport; 11063403Sdfr struct resource *res_irq, *res_drq, *res_ioport; 11155939Snsouch 11255939Snsouch void *intr_cookie; 11355939Snsouch 114187576Sjhb ppc_intr_handler ppc_intr_hook; 115187576Sjhb void *ppc_intr_arg; 116187576Sjhb 117187576Sjhb struct mtx ppc_lock; 11828221Smsmith}; 11928221Smsmith 120187576Sjhb#define PPC_LOCK(data) mtx_lock(&(data)->ppc_lock) 121187576Sjhb#define PPC_UNLOCK(data) mtx_unlock(&(data)->ppc_lock) 122187576Sjhb#define PPC_ASSERT_LOCKED(data) mtx_assert(&(data)->ppc_lock, MA_OWNED) 123187576Sjhb 12428221Smsmith/* 12528221Smsmith * Parallel Port Chipset registers. 12628221Smsmith */ 12728221Smsmith#define PPC_SPP_DTR 0 /* SPP data register */ 12842475Snsouch#define PPC_ECP_A_FIFO 0 /* ECP Address fifo register */ 12928221Smsmith#define PPC_SPP_STR 1 /* SPP status register */ 13028221Smsmith#define PPC_SPP_CTR 2 /* SPP control register */ 13143433Snsouch#define PPC_EPP_ADDR 3 /* EPP address register (8 bit) */ 13228221Smsmith#define PPC_EPP_DATA 4 /* EPP data register (8, 16 or 32 bit) */ 133158005Smarcel#if defined(__i386__) && defined(PC98) 134158005Smarcel#define PPC_1284_ENABLE 0x09 /* IEEE STD 1284 Enable register */ 135158005Smarcel#define PPC_ECP_D_FIFO 0x0c /* ECP Data fifo register */ 136158005Smarcel#define PPC_ECP_CNFGA 0x0c /* Configuration register A */ 137158005Smarcel#define PPC_ECP_CNFGB 0x0d /* Configuration register B */ 138158005Smarcel#define PPC_ECP_ECR 0x0e /* ECP extended control register */ 139158005Smarcel#else 14042475Snsouch#define PPC_ECP_D_FIFO 0x400 /* ECP Data fifo register */ 14142475Snsouch#define PPC_ECP_CNFGA 0x400 /* Configuration register A */ 14242475Snsouch#define PPC_ECP_CNFGB 0x401 /* Configuration register B */ 14328221Smsmith#define PPC_ECP_ECR 0x402 /* ECP extended control register */ 144158005Smarcel#endif 14528221Smsmith 14642475Snsouch#define PPC_FIFO_EMPTY 0x1 /* ecr register - bit 0 */ 14742475Snsouch#define PPC_FIFO_FULL 0x2 /* ecr register - bit 1 */ 14842475Snsouch#define PPC_SERVICE_INTR 0x4 /* ecr register - bit 2 */ 14942475Snsouch#define PPC_ENABLE_DMA 0x8 /* ecr register - bit 3 */ 15042475Snsouch#define PPC_nFAULT_INTR 0x10 /* ecr register - bit 4 */ 15142475Snsouch#define PPC_ECR_STD 0x0 15242475Snsouch#define PPC_ECR_PS2 0x20 15342475Snsouch#define PPC_ECR_FIFO 0x40 15442475Snsouch#define PPC_ECR_ECP 0x60 15542475Snsouch#define PPC_ECR_EPP 0x80 15642475Snsouch 15742475Snsouch#define PPC_DISABLE_INTR (PPC_SERVICE_INTR | PPC_nFAULT_INTR) 15842475Snsouch#define PPC_ECR_RESET (PPC_ECR_PS2 | PPC_DISABLE_INTR) 15942475Snsouch 160182016Sjhb#define r_dtr(ppc) (bus_read_1((ppc)->res_ioport, PPC_SPP_DTR)) 161182016Sjhb#define r_str(ppc) (bus_read_1((ppc)->res_ioport, PPC_SPP_STR)) 162182016Sjhb#define r_ctr(ppc) (bus_read_1((ppc)->res_ioport, PPC_SPP_CTR)) 16328221Smsmith 164182016Sjhb#define r_epp_A(ppc) (bus_read_1((ppc)->res_ioport, PPC_EPP_ADDR)) 165182016Sjhb#define r_epp_D(ppc) (bus_read_1((ppc)->res_ioport, PPC_EPP_DATA)) 166182016Sjhb#define r_cnfgA(ppc) (bus_read_1((ppc)->res_ioport, PPC_ECP_CNFGA)) 167182016Sjhb#define r_cnfgB(ppc) (bus_read_1((ppc)->res_ioport, PPC_ECP_CNFGB)) 168182016Sjhb#define r_ecr(ppc) (bus_read_1((ppc)->res_ioport, PPC_ECP_ECR)) 169182016Sjhb#define r_fifo(ppc) (bus_read_1((ppc)->res_ioport, PPC_ECP_D_FIFO)) 17028221Smsmith 171182016Sjhb#define w_dtr(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_SPP_DTR, byte)) 172182016Sjhb#define w_str(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_SPP_STR, byte)) 173182016Sjhb#define w_ctr(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_SPP_CTR, byte)) 17478646Snsouch 175182016Sjhb#define w_epp_A(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_EPP_ADDR, byte)) 176182016Sjhb#define w_epp_D(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_EPP_DATA, byte)) 177182016Sjhb#define w_ecr(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_ECP_ECR, byte)) 178182016Sjhb#define w_fifo(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_ECP_D_FIFO, byte)) 17978646Snsouch 18028221Smsmith/* 18128221Smsmith * Register defines for the PC873xx parts 18228221Smsmith */ 18328221Smsmith 18428221Smsmith#define PC873_FER 0x00 18528221Smsmith#define PC873_PPENABLE (1<<0) 18628221Smsmith#define PC873_FAR 0x01 18728221Smsmith#define PC873_PTR 0x02 18828221Smsmith#define PC873_CFGLOCK (1<<6) 18928221Smsmith#define PC873_EPPRDIR (1<<7) 19040784Snsouch#define PC873_EXTENDED (1<<7) 19140784Snsouch#define PC873_LPTBIRQ7 (1<<3) 19228221Smsmith#define PC873_FCR 0x03 19328221Smsmith#define PC873_ZWS (1<<5) 19428221Smsmith#define PC873_ZWSPWDN (1<<6) 19528221Smsmith#define PC873_PCR 0x04 19628221Smsmith#define PC873_EPPEN (1<<0) 19728221Smsmith#define PC873_EPP19 (1<<1) 19828221Smsmith#define PC873_ECPEN (1<<2) 19928221Smsmith#define PC873_ECPCLK (1<<3) 20028221Smsmith#define PC873_PMC 0x06 20128221Smsmith#define PC873_TUP 0x07 20228221Smsmith#define PC873_SID 0x08 20340784Snsouch#define PC873_PNP0 0x1b 20440784Snsouch#define PC873_PNP1 0x1c 20540784Snsouch#define PC873_LPTBA 0x19 20628221Smsmith 20728221Smsmith/* 20838061Smsmith * Register defines for the SMC FDC37C66xGT parts 20928221Smsmith */ 21028221Smsmith 21128221Smsmith/* Init codes */ 21228221Smsmith#define SMC665_iCODE 0x55 21328221Smsmith#define SMC666_iCODE 0x44 21428221Smsmith 21528221Smsmith/* Base configuration ports */ 21628221Smsmith#define SMC66x_CSR 0x3F0 21728221Smsmith#define SMC666_CSR 0x370 /* hard-configured value for 666 */ 21828221Smsmith 21928221Smsmith/* Bits */ 22028221Smsmith#define SMC_CR1_ADDR 0x3 /* bit 0 and 1 */ 22138061Smsmith#define SMC_CR1_MODE (1<<3) /* bit 3 */ 22228221Smsmith#define SMC_CR4_EMODE 0x3 /* bits 0 and 1 */ 22338061Smsmith#define SMC_CR4_EPPTYPE (1<<6) /* bit 6 */ 22428221Smsmith 22528221Smsmith/* Extended modes */ 22628221Smsmith#define SMC_SPP 0x0 /* SPP */ 22728221Smsmith#define SMC_EPPSPP 0x1 /* EPP and SPP */ 22828221Smsmith#define SMC_ECP 0x2 /* ECP */ 22928221Smsmith#define SMC_ECPEPP 0x3 /* ECP and EPP */ 23028221Smsmith 23138061Smsmith/* 23263403Sdfr * Register defines for the SMC FDC37C935 parts 23363403Sdfr */ 23463403Sdfr 23563403Sdfr/* Configuration ports */ 23663403Sdfr#define SMC935_CFG 0x370 23763403Sdfr#define SMC935_IND 0x370 23863403Sdfr#define SMC935_DAT 0x371 23963403Sdfr 24063403Sdfr/* Registers */ 24163403Sdfr#define SMC935_LOGDEV 0x7 24263403Sdfr#define SMC935_ID 0x20 24363403Sdfr#define SMC935_PORTHI 0x60 24463403Sdfr#define SMC935_PORTLO 0x61 24563403Sdfr#define SMC935_PPMODE 0xf0 24663403Sdfr 24763403Sdfr/* Parallel port modes */ 24863403Sdfr#define SMC935_SPP 0x38 + 0 24963403Sdfr#define SMC935_EPP19SPP 0x38 + 1 25063403Sdfr#define SMC935_ECP 0x38 + 2 25163403Sdfr#define SMC935_ECPEPP19 0x38 + 3 25263403Sdfr#define SMC935_CENT 0x38 + 4 25363403Sdfr#define SMC935_EPP17SPP 0x38 + 5 25463403Sdfr#define SMC935_UNUSED 0x38 + 6 25563403Sdfr#define SMC935_ECPEPP17 0x38 + 7 25663403Sdfr 25763403Sdfr/* 25838061Smsmith * Register defines for the Winbond W83877F parts 25938061Smsmith */ 26038061Smsmith 26138061Smsmith#define WINB_W83877F_ID 0xa 26238061Smsmith#define WINB_W83877AF_ID 0xb 26338061Smsmith 26438061Smsmith/* Configuration bits */ 26538061Smsmith#define WINB_HEFERE (1<<5) /* CROC bit 5 */ 26638061Smsmith#define WINB_HEFRAS (1<<0) /* CR16 bit 0 */ 26738061Smsmith 26838061Smsmith#define WINB_PNPCVS (1<<2) /* CR16 bit 2 */ 26938061Smsmith#define WINB_CHIPID 0xf /* CR9 bits 0-3 */ 27038061Smsmith 27138061Smsmith#define WINB_PRTMODS0 (1<<2) /* CR0 bit 2 */ 27238061Smsmith#define WINB_PRTMODS1 (1<<3) /* CR0 bit 3 */ 27338061Smsmith#define WINB_PRTMODS2 (1<<7) /* CR9 bit 7 */ 27438061Smsmith 27538061Smsmith/* W83877F modes: CR9/bit7 | CR0/bit3 | CR0/bit2 */ 27638061Smsmith#define WINB_W83757 0x0 27738061Smsmith#define WINB_EXTFDC 0x4 27838061Smsmith#define WINB_EXTADP 0x8 27938061Smsmith#define WINB_EXT2FDD 0xc 28038061Smsmith#define WINB_JOYSTICK 0x80 28138061Smsmith 28238061Smsmith#define WINB_PARALLEL 0x80 28338061Smsmith#define WINB_EPP_SPP 0x4 28438061Smsmith#define WINB_ECP 0x8 28538061Smsmith#define WINB_ECP_EPP 0xc 28638061Smsmith 28728221Smsmith#endif 288