sadefs.h revision 285809
1/******************************************************************************* 2*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. 3* 4*Redistribution and use in source and binary forms, with or without modification, are permitted provided 5*that the following conditions are met: 6*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the 7*following disclaimer. 8*2. Redistributions in binary form must reproduce the above copyright notice, 9*this list of conditions and the following disclaimer in the documentation and/or other materials provided 10*with the distribution. 11* 12*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 13*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 14*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 15*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 16*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 17*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 18*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 19*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE 20* 21* $FreeBSD$ 22* 23********************************************************************************/ 24/*******************************************************************************/ 25/*! \file sadefs.h 26 * \brief The file defines the constants used by LL layer 27 */ 28 29/*******************************************************************************/ 30 31#ifndef __SADEFS_H__ 32 33#define __SADEFS_H__ 34 35#define SA_LL_IBQ_PROTECT 36 37#define AGSA_MAX_VALID_PORTS AGSA_MAX_VALID_PHYS /**< defines the maximum number of ports */ 38 39#define NUM_TIMERS 2 /**< defines the maximum number of timers */ 40#define SA_USECS_PER_TICK 1000000 /**< defines the heart beat of the LL layer 1us */ 41#define MAX_ACTIVE_IO_REQUESTS 4096 /**< Maximum Active IO Requests */ 42#define SMP_RESPONSE_FRAMES AGSA_MAX_VALID_PHYS /**< SMP Response Frame Buffer */ 43#define MAX_NUM_VECTOR 64 /**< Maximum Number of Interrupt Vectors */ 44#define REGISTER_DUMP_BUFF_SIZE 0x4000 /**< Maximum Fatal Error Register Dump Buffer Size */ 45#define KBYTES 1024 46 47/* number of IQ/OQ */ 48#define IQ_NUM_32 32 49#define OQ_NUM_32 32 50 51/* default value of Inbound/Outbound element size */ 52#define INBOUND_DEPTH_SIZE 512 53#define OUTBOUND_DEPTH_SIZE 512 54 55/* Priority of Queue */ 56#define MPI_QUEUE_NORMAL 0 57#define MPI_QUEUE_PRIORITY 1 58 59/* size of IOMB - multiple with 32 bytes */ 60#define IOMB_SIZE64 64 61#define IOMB_SIZE96 96 62#define IOMB_SIZE128 128 63#define IOMB_SIZE256 256 64 65/* DIR bit of IOMB for SSP read/write command */ 66#define DIR_NODATA 0x000 67#define DIR_READ 0x100 68#define DIR_WRITE 0x200 69 70/* TLR bits mask */ 71#define TLR_MASK 0x00000003 72/* port and phy Id bits Mask */ 73 74 75#define PORTID_MASK 0x0000000F 76#define PORTID_V_MASK 0x000000FF 77#define PHYID_MASK 0x0000000F 78#define PHYID_V_MASK 0x000000FF 79#define PORT_STATE_MASK 0x0000000F 80#define PHY_IN_PORT_MASK 0x000000F0 81 82#define SM_PHYID_MASK (smIS_SPC(agRoot) ? PHYID_MASK : PHYID_V_MASK ) 83#define SM_PORTID_MASK (smIS_SPC(agRoot) ? PORTID_MASK : PORTID_V_MASK ) 84 85/* the index for memory requirement, must be continious */ 86#define LLROOT_MEM_INDEX 0 /**< the index of root memory */ 87#define DEVICELINK_MEM_INDEX (LLROOT_MEM_INDEX + 1) /**< the index of device descriptors memory */ 88#define IOREQLINK_MEM_INDEX (DEVICELINK_MEM_INDEX+1) /**< the index of IO requests memory */ 89 90#ifdef SA_ENABLE_HDA_FUNCTIONS 91#define HDA_DMA_BUFFER (IOREQLINK_MEM_INDEX+1) /** HDA Buffer */ 92#else /* SA_ENABLE_HDA_FUNCTIONS */ 93#define HDA_DMA_BUFFER (IOREQLINK_MEM_INDEX) /** HDA Buffer */ 94#endif /* SA_ENABLE_HDA_FUNCTIONS */ 95 96#ifdef SA_ENABLE_TRACE_FUNCTIONS 97#define LL_FUNCTION_TRACE (HDA_DMA_BUFFER+1) /**TraceLog */ 98#else /* SA_ENABLE_TRACE_FUNCTIONS */ 99#define LL_FUNCTION_TRACE HDA_DMA_BUFFER /**TraceLog */ 100#endif /* END SA_ENABLE_TRACE_FUNCTIONS */ 101 102#define TIMERLINK_MEM_INDEX (LL_FUNCTION_TRACE+1) /**< the index of timers memory */ 103 104#ifdef FAST_IO_TEST 105#define LL_FAST_IO (TIMERLINK_MEM_INDEX+1) 106#define MPI_IBQ_OBQ_INDEX (LL_FAST_IO + 1) 107 108#else /* FAST_IO_TEST */ 109 110#define LL_FAST_IO TIMERLINK_MEM_INDEX 111#define MPI_IBQ_OBQ_INDEX (LL_FAST_IO + 1) 112#endif /* FAST_IO_TEST */ 113 114#define MPI_MEM_INDEX (MPI_IBQ_OBQ_INDEX - LLROOT_MEM_INDEX) 115 116#define MPI_EVENTLOG_INDEX 0 117#define MPI_IOP_EVENTLOG_INDEX 1 118#define MPI_CI_INDEX 2 119/* The following is a reference index */ 120#define MPI_PI_INDEX (MPI_CI_INDEX + 1) 121#define MPI_IBQ_INDEX (MPI_PI_INDEX + 1) 122#define MPI_OBQ_INDEX (MPI_IBQ_INDEX + MPI_MAX_INBOUND_QUEUES) 123 124#define TOTAL_MPI_MEM_CHUNKS (MPI_MAX_INBOUND_QUEUES * 2) + MPI_IBQ_INDEX 125 126 127#define LL_DEVICE_LOCK 0 128#define LL_PORT_LOCK (LL_DEVICE_LOCK+1) 129#define LL_TIMER_LOCK (LL_PORT_LOCK+1) 130#define LL_IOREQ_LOCKEQ_LOCK (LL_TIMER_LOCK+1) 131 132#ifdef FAST_IO_TEST 133#define LL_FAST_IO_LOCK (LL_IOREQ_LOCKEQ_LOCK+1) 134#else /* FAST_IO_TEST */ 135#define LL_FAST_IO_LOCK (LL_IOREQ_LOCKEQ_LOCK) 136#endif /* FAST_IO_TEST */ 137 138#ifdef SA_ENABLE_TRACE_FUNCTIONS 139#define LL_TRACE_LOCK (LL_FAST_IO_LOCK+1) 140#else /* SA_ENABLE_TRACE_FUNCTIONS */ 141#define LL_TRACE_LOCK (LL_FAST_IO_LOCK) 142#endif /* SA_ENABLE_TRACE_FUNCTIONS */ 143 144#ifdef MPI_DEBUG_TRACE_ENABLE 145#define LL_IOMB_TRACE_LOCK (LL_TRACE_LOCK+1) 146#else /* MPI_DEBUG_TRACE_ENABLE */ 147#define LL_IOMB_TRACE_LOCK (LL_TRACE_LOCK) 148#endif /* MPI_DEBUG_TRACE_ENABLE */ 149 150#define LL_IOREQ_OBQ_LOCK (LL_IOMB_TRACE_LOCK+1) 151 152#define LL_IOREQ_IBQ_LOCK (LL_IOREQ_OBQ_LOCK +1) 153#define LL_IOREQ_IBQ_LOCK_PARM (LL_IOREQ_OBQ_LOCK + queueConfig->numOutboundQueues +1) 154#define LL_IOREQ_IBQ0_LOCK (LL_IOREQ_OBQ_LOCK + saRoot->QueueConfig.numOutboundQueues +1) 155 156 157 158/* define phy states */ 159#define PHY_STOPPED 0x00000000 /**< flag indicates phy stopped */ 160#define PHY_UP 0x00000001 /**< flag indicates phy up */ 161#define PHY_DOWN 0x00000002 /**< flag indicates phy down */ 162 163/* define port states */ 164#define PORT_NORMAL 0x0000 165#define PORT_INVALIDATING 0x0002 166 167/* define chip status */ 168#define CHIP_NORMAL 0x0000 169#define CHIP_SHUTDOWN 0x0001 170#define CHIP_RESETTING 0x0002 171#define CHIP_RESET_FW 0x0004 172#define CHIP_FATAL_ERROR 0x0008 173 174/* define device types */ 175#define SAS_SATA_UNKNOWN_DEVICE 0xFF /**< SAS SATA unknown device type */ 176 177#define STP_DEVICE 0x00 /**< SATA device behind an expander */ 178#define SSP_SMP_DEVICE 0x01 /**< SSP or SMP device type */ 179#define DIRECT_SATA_DEVICE 0x02 /**< SATA direct device type */ 180 181/* SATA */ 182#define SATA_FIS_MASK 0x00000001 183#define MAX_SATARESP_SUPPORT_BYTES 44 184 185#define MARK_OFF 0xFFFFFFFF 186#define PORT_MARK_OFF 0xFFFFFFFF 187#define NO_FATAL_ERROR_VECTOR 0xFFFFFFFF 188 189#define SATA_PROTOCOL_RSRT_ASSERT 0x01 190#define SATA_PROTOCOL_RSRT_DEASSERT 0x02 191#define SATA_NON_DATA_PROTOCOL 0x0d 192#define SATA_PIO_READ_PROTOCOL 0x0e 193#define SATA_DMA_READ_PROTOCOL 0x0f 194#define SATA_FPDMA_READ_PROTOCOL 0x10 195#define SATA_PIO_WRITE_PROTOCOL 0x11 196#define SATA_DMA_WRITE_PROTOCOL 0x12 197#define SATA_FPDMA_WRITE_PROTOCOL 0x13 198#define SATA_DEVICE_RESET_PROTOCOL 0x14 199 200/* Definition for bit shift */ 201#define SHIFT0 0 202#define SHIFT1 1 203#define SHIFT2 2 204#define SHIFT3 3 205#define SHIFT4 4 206#define SHIFT5 5 207#define SHIFT6 6 208#define SHIFT7 7 209#define SHIFT8 8 210#define SHIFT9 9 211#define SHIFT10 10 212#define SHIFT11 11 213#define SHIFT12 12 214#define SHIFT13 13 215#define SHIFT14 14 216#define SHIFT15 15 217#define SHIFT16 16 218#define SHIFT17 17 219#define SHIFT18 18 220#define SHIFT19 19 221#define SHIFT20 20 222#define SHIFT21 21 223#define SHIFT22 22 224#define SHIFT23 23 225#define SHIFT24 24 226#define SHIFT25 25 227#define SHIFT26 26 228#define SHIFT27 27 229#define SHIFT28 28 230#define SHIFT29 29 231#define SHIFT30 30 232#define SHIFT31 31 233 234/* These flags used for saSSPAbort(), saSATAAbort() */ 235#define ABORT_MASK 0x3 236#define ABORT_SINGLE 0x0 237#define ABORT_SCOPE 0x3 /* bits 0-1*/ 238#define ABORT_ALL 0x1 239#define ABORT_TSDK_QUARANTINE 0x4 240#define ABORT_QUARANTINE_SPC 0x4 241#define ABORT_QUARANTINE_SPCV 0x8 242 243/* These flags used for saGetRegDump() */ 244#define REG_DUMP_NUM0 0x0 245#define REG_DUMP_NUM1 0x1 246#define REG_DUMP_NONFLASH 0x0 247#define REG_DUMP_FLASH 0x1 248 249/* MSIX Interupts */ 250#define MSIX_TABLE_OFFSET 0x2000 251#define MSIX_TABLE_ELEMENT_SIZE 0x10 252#define MSIX_INTERRUPT_CONTROL_OFFSET 0xC 253#define MSIX_TABLE_BASE (MSIX_TABLE_OFFSET+MSIX_INTERRUPT_CONTROL_OFFSET) 254#define MSIX_INTERRUPT_DISABLE 0x1 255#define MSIX_INTERRUPT_ENABLE 0x0 256 257#define MAX_QUEUE_EACH_MEM 8 258 259#define NUM_MEM_CHUNKS(Q, rem) ((((bit32)Q % rem) > 0) ? (bit32)(Q/rem+1) : (bit32)(Q/rem)) 260#define NUM_QUEUES_IN_MEM(Q, rem) ((((bit32)Q % rem) > 0) ? (bit32)(Q%rem) : (bit32)(MAX_QUEUE_EACH_MEM)) 261 262#define MAX_DEV_BITS 0xFFFF0000 263#define PHY_COUNT_BITS 0x01f80000 264#define Q_SUPPORT_BITS 0x0007ffff 265#define SAS_SPEC_BITS 0xfe000000 266#define HP_SUPPORT_BIT 0x00010000 267#define INT_COL_BIT 0x00040000 268#define INT_DELAY_BITS 0xFFFF 269#define INT_THR_BITS 0xFF 270#define INT_VEC_BITS 0xFF 271 272#define AUTO_HARD_RESET_DEREG_FLAG 0x00000001 273#define AUTO_FW_CLEANUP_DEREG_FLAG 0x00000002 274 275#define BYTE_MASK 0xff 276 277#define INT_OPTION 0x7FFF 278#define SMP_TO_DEFAULT 100 279#define ITL_TO_DEFAULT 0xFFFF 280 281 282/* 283agsaHwConfig_s hwOption 284*/ 285#define HW_CFG_PICI_EFFECTIVE_ADDRESS 0x1 286 287/* SPC or SPCv ven dev Id */ 288 289#define SUBID_SPC 0x00000000 290#define SUBID_SPCV 0x56781234 291 292#define VEN_DEV_SPC 0x80010000 293#define VEN_DEV_HIL 0x80810000 294 295#define VEN_DEV_SPCV 0x80080000 296#define VEN_DEV_SPCVE 0x80090000 297#define VEN_DEV_SPCVP 0x80180000 298#define VEN_DEV_SPCVEP 0x80190000 299 300#define VEN_DEV_SPC12V 0x80700000 301#define VEN_DEV_SPC12VE 0x80710000 302#define VEN_DEV_SPC12VP 0x80720000 303#define VEN_DEV_SPC12VEP 0x80730000 304#define VEN_DEV_9015 0x90150000 305#define VEN_DEV_9060 0x90600000 306 307#define VEN_DEV_ADAPVEP 0x80890000 308#define VEN_DEV_ADAPVP 0x80880000 309 310 311#define VEN_DEV_SFC 0x80250000 312 313/*DelRay PCIid */ 314#define VEN_DEV_SPC12ADP 0x80740000 /* 8 ports */ 315#define VEN_DEV_SPC12ADPE 0x80750000 /* 8 ports encrypt */ 316#define VEN_DEV_SPC12ADPP 0x80760000 /* 16 ports */ 317#define VEN_DEV_SPC12ADPEP 0x80770000 /* 16 ports encrypt */ 318#define VEN_DEV_SPC12SATA 0x80060000 /* SATA HBA */ 319 320#endif /*__SADEFS_H__ */ 321