1285809Sscottl/******************************************************************************* 2285809Sscottl*Copyright (c) 2014 PMC-Sierra, Inc. All rights reserved. 3285809Sscottl* 4285809Sscottl*Redistribution and use in source and binary forms, with or without modification, are permitted provided 5285809Sscottl*that the following conditions are met: 6285809Sscottl*1. Redistributions of source code must retain the above copyright notice, this list of conditions and the 7285809Sscottl*following disclaimer. 8285809Sscottl*2. Redistributions in binary form must reproduce the above copyright notice, 9285809Sscottl*this list of conditions and the following disclaimer in the documentation and/or other materials provided 10285809Sscottl*with the distribution. 11285809Sscottl* 12285809Sscottl*THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND ANY EXPRESS OR IMPLIED 13285809Sscottl*WARRANTIES,INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS 14285809Sscottl*FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 15285809Sscottl*FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 16285809Sscottl*NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR 17285809Sscottl*BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 18285809Sscottl*LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 19285809Sscottl*SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE 20285809Sscottl* 21285809Sscottl* $FreeBSD$ 22285809Sscottl* 23285809Sscottl********************************************************************************/ 24285809Sscottl/*******************************************************************************/ 25285809Sscottl/*! \file sa.h 26285809Sscottl * \brief The file defines the constants, data structure, and functions defined by LL API 27285809Sscottl */ 28285809Sscottl/******************************************************************************/ 29285809Sscottl 30285809Sscottl#ifndef __SA_H__ 31285809Sscottl#define __SA_H__ 32285809Sscottl 33285809Sscottl#include <dev/pms/RefTisa/sallsdk/api/sa_spec.h> 34285809Sscottl#include <dev/pms/RefTisa/sallsdk/api/sa_err.h> 35285809Sscottl 36285809Sscottl/* TestBase needed to have the 'Multi-Data fetch disable' feature */ 37285809Sscottl#define SA_CONFIG_MDFD_REGISTRY 38285809Sscottl 39285809Sscottl#define OSSA_OFFSET_OF(STRUCT_TYPE, FEILD) \ 40285809Sscottl (bitptr)&(((STRUCT_TYPE *)0)->FEILD) 41285809Sscottl 42285809Sscottl#if defined(SA_CPU_LITTLE_ENDIAN) 43285809Sscottl 44285809Sscottl#define OSSA_WRITE_LE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \ 45285809Sscottl (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit16)(VALUE16); 46285809Sscottl 47285809Sscottl#define OSSA_WRITE_LE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \ 48285809Sscottl (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit32)(VALUE32); 49285809Sscottl 50285809Sscottl#define OSSA_READ_LE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \ 51285809Sscottl (*((bit16 *)ADDR16)) = (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) 52285809Sscottl 53285809Sscottl#define OSSA_READ_LE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \ 54285809Sscottl (*((bit32 *)ADDR32)) = (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) 55285809Sscottl 56285809Sscottl#define OSSA_WRITE_BE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \ 57285809Sscottl (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)((((bit16)VALUE16)>>8)&0xFF); \ 58285809Sscottl (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)(((bit16)VALUE16)&0xFF); 59285809Sscottl 60285809Sscottl#define OSSA_WRITE_BE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \ 61285809Sscottl (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)((((bit32)VALUE32)>>24)&0xFF); \ 62285809Sscottl (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit32)VALUE32)>>16)&0xFF); \ 63285809Sscottl (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))) = (bit8)((((bit32)VALUE32)>>8)&0xFF); \ 64285809Sscottl (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))) = (bit8)(((bit32)VALUE32)&0xFF); 65285809Sscottl 66285809Sscottl#define OSSA_READ_BE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \ 67285809Sscottl (*(bit8 *)(((bit8 *)ADDR16)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \ 68285809Sscottl (*(bit8 *)(((bit8 *)ADDR16))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); 69285809Sscottl 70285809Sscottl#define OSSA_READ_BE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \ 71285809Sscottl (*(bit8 *)(((bit8 *)ADDR32)+3)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \ 72285809Sscottl (*(bit8 *)(((bit8 *)ADDR32)+2)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); \ 73285809Sscottl (*(bit8 *)(((bit8 *)ADDR32)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))); \ 74285809Sscottl (*(bit8 *)(((bit8 *)ADDR32))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))); 75285809Sscottl 76285809Sscottl#define OSSA_WRITE_BYTE_STRING(AGROOT, DEST_ADDR, SRC_ADDR, LEN) \ 77285809Sscottl si_memcpy(DEST_ADDR, SRC_ADDR, LEN); 78285809Sscottl 79285809Sscottl 80285809Sscottl#elif defined(SA_CPU_BIG_ENDIAN) 81285809Sscottl 82285809Sscottl#define OSSA_WRITE_LE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \ 83285809Sscottl (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit16)VALUE16)>>8)&0xFF); \ 84285809Sscottl (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)(((bit16)VALUE16)&0xFF); 85285809Sscottl 86285809Sscottl#define OSSA_WRITE_LE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \ 87285809Sscottl (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))) = (bit8)((((bit32)VALUE32)>>24)&0xFF); \ 88285809Sscottl (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))) = (bit8)((((bit32)VALUE32)>>16)&0xFF); \ 89285809Sscottl (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))) = (bit8)((((bit32)VALUE32)>>8)&0xFF); \ 90285809Sscottl (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit8)(((bit32)VALUE32)&0xFF); 91285809Sscottl 92285809Sscottl#define OSSA_READ_LE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \ 93285809Sscottl (*(bit8 *)(((bit8 *)ADDR16)+1)) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \ 94285809Sscottl (*(bit8 *)(((bit8 *)ADDR16))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); 95285809Sscottl 96285809Sscottl#define OSSA_READ_LE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \ 97285809Sscottl (*((bit8 *)(((bit8 *)ADDR32)+3))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); \ 98285809Sscottl (*((bit8 *)(((bit8 *)ADDR32)+2))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+1))); \ 99285809Sscottl (*((bit8 *)(((bit8 *)ADDR32)+1))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+2))); \ 100285809Sscottl (*((bit8 *)(((bit8 *)ADDR32)))) = (*((bit8 *)(((bit8 *)DMA_ADDR)+(OFFSET)+3))); 101285809Sscottl 102285809Sscottl#define OSSA_WRITE_BE_16(AGROOT, DMA_ADDR, OFFSET, VALUE16) \ 103285809Sscottl (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit16)(VALUE16); 104285809Sscottl 105285809Sscottl#define OSSA_WRITE_BE_32(AGROOT, DMA_ADDR, OFFSET, VALUE32) \ 106285809Sscottl (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))) = (bit32)(VALUE32); 107285809Sscottl 108285809Sscottl#define OSSA_READ_BE_16(AGROOT, ADDR16, DMA_ADDR, OFFSET) \ 109285809Sscottl (*((bit16 *)ADDR16)) = (*((bit16 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); 110285809Sscottl 111285809Sscottl#define OSSA_READ_BE_32(AGROOT, ADDR32, DMA_ADDR, OFFSET) \ 112285809Sscottl (*((bit32 *)ADDR32)) = (*((bit32 *)(((bit8 *)DMA_ADDR)+(OFFSET)))); 113285809Sscottl 114285809Sscottl#define OSSA_WRITE_BYTE_STRING(AGROOT, DEST_ADDR, SRC_ADDR, LEN) \ 115285809Sscottl si_memcpy(DEST_ADDR, SRC_ADDR, LEN); 116285809Sscottl 117285809Sscottl#else 118285809Sscottl 119285809Sscottl#error (Host CPU endianess undefined!!) 120285809Sscottl 121285809Sscottl#endif 122285809Sscottl 123285809Sscottl#define AGSA_WRITE_SGL(sglDest, sgLower, sgUpper, len, extReserved) \ 124285809Sscottl OSSA_WRITE_LE_32(agRoot, sglDest, 0, sgLower); \ 125285809Sscottl OSSA_WRITE_LE_32(agRoot, sglDest, 4, sgUpper); \ 126285809Sscottl OSSA_WRITE_LE_32(agRoot, sglDest, 8, len); \ 127285809Sscottl OSSA_WRITE_LE_32(agRoot, sglDest, 12, extReserved); 128285809Sscottl 129285809Sscottl 130285809Sscottl/************************************************************************** 131285809Sscottl * define byte swap macro * 132285809Sscottl **************************************************************************/ 133285809Sscottl/*! \def AGSA_FLIP_2_BYTES(_x) 134285809Sscottl* \brief AGSA_FLIP_2_BYTES macro 135285809Sscottl* 136285809Sscottl* use to flip two bytes 137285809Sscottl*/ 138285809Sscottl#define AGSA_FLIP_2_BYTES(_x) ((bit16)(((((bit16)(_x))&0x00FF)<<8)| \ 139285809Sscottl ((((bit16)(_x))&0xFF00)>>8))) 140285809Sscottl 141285809Sscottl/*! \def AGSA_FLIP_4_BYTES(_x) 142285809Sscottl* \brief AGSA_FLIP_4_BYTES macro 143285809Sscottl* 144285809Sscottl* use to flip four bytes 145285809Sscottl*/ 146285809Sscottl#define AGSA_FLIP_4_BYTES(_x) ((bit32)(((((bit32)(_x))&0x000000FF)<<24)| \ 147285809Sscottl ((((bit32)(_x))&0x0000FF00)<<8)| \ 148285809Sscottl ((((bit32)(_x))&0x00FF0000)>>8)| \ 149285809Sscottl ((((bit32)(_x))&0xFF000000)>>24))) 150285809Sscottl 151285809Sscottl 152285809Sscottl#if defined(SA_CPU_LITTLE_ENDIAN) 153285809Sscottl 154285809Sscottl/*! \def LEBIT16_TO_BIT16(_x) 155285809Sscottl* \brief LEBIT16_TO_BIT16 macro 156285809Sscottl* 157285809Sscottl* use to convert little endian bit16 to host bit16 158285809Sscottl*/ 159285809Sscottl#ifndef LEBIT16_TO_BIT16 160285809Sscottl#define LEBIT16_TO_BIT16(_x) (_x) 161285809Sscottl#endif 162285809Sscottl 163285809Sscottl/*! \def BIT16_TO_LEBIT16(_x) 164285809Sscottl* \brief BIT16_TO_LEBIT16 macro 165285809Sscottl* 166285809Sscottl* use to convert host bit16 to little endian bit16 167285809Sscottl*/ 168285809Sscottl#ifndef BIT16_TO_LEBIT16 169285809Sscottl#define BIT16_TO_LEBIT16(_x) (_x) 170285809Sscottl#endif 171285809Sscottl 172285809Sscottl/*! \def BEBIT16_TO_BIT16(_x) 173285809Sscottl* \brief BEBIT16_TO_BIT16 macro 174285809Sscottl* 175285809Sscottl* use to convert big endian bit16 to host bit16 176285809Sscottl*/ 177285809Sscottl#ifndef BEBIT16_TO_BIT16 178285809Sscottl#define BEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x) 179285809Sscottl#endif 180285809Sscottl 181285809Sscottl/*! \def BIT16_TO_BEBIT16(_x) 182285809Sscottl* \brief BIT16_TO_BEBIT16 macro 183285809Sscottl* 184285809Sscottl* use to convert host bit16 to big endian bit16 185285809Sscottl*/ 186285809Sscottl#ifndef BIT16_TO_BEBIT16 187285809Sscottl#define BIT16_TO_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 188285809Sscottl#endif 189285809Sscottl 190285809Sscottl/*! \def LEBIT32_TO_BIT32(_x) 191285809Sscottl* \brief LEBIT32_TO_BIT32 macro 192285809Sscottl* 193285809Sscottl* use to convert little endian bit32 to host bit32 194285809Sscottl*/ 195285809Sscottl#ifndef LEBIT32_TO_BIT32 196285809Sscottl#define LEBIT32_TO_BIT32(_x) (_x) 197285809Sscottl#endif 198285809Sscottl 199285809Sscottl/*! \def BIT32_TO_LEBIT32(_x) 200285809Sscottl* \brief BIT32_TO_LEBIT32 macro 201285809Sscottl* 202285809Sscottl* use to convert host bit32 to little endian bit32 203285809Sscottl*/ 204285809Sscottl#ifndef BIT32_TO_LEBIT32 205285809Sscottl#define BIT32_TO_LEBIT32(_x) (_x) 206285809Sscottl#endif 207285809Sscottl 208285809Sscottl/*! \def BEBIT32_TO_BIT32(_x) 209285809Sscottl* \brief BEBIT32_TO_BIT32 macro 210285809Sscottl* 211285809Sscottl* use to convert big endian bit32 to host bit32 212285809Sscottl*/ 213285809Sscottl#ifndef BEBIT32_TO_BIT32 214285809Sscottl#define BEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x) 215285809Sscottl#endif 216285809Sscottl 217285809Sscottl/*! \def BIT32_TO_BEBIT32(_x) 218285809Sscottl* \brief BIT32_TO_BEBIT32 macro 219285809Sscottl* 220285809Sscottl* use to convert host bit32 to big endian bit32 221285809Sscottl*/ 222285809Sscottl#ifndef BIT32_TO_BEBIT32 223285809Sscottl#define BIT32_TO_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 224285809Sscottl#endif 225285809Sscottl 226285809Sscottl 227285809Sscottl/* 228285809Sscottl * bit8 to Byte[x] of bit32 229285809Sscottl */ 230285809Sscottl#ifndef BIT8_TO_BIT32_B0 231285809Sscottl#define BIT8_TO_BIT32_B0(_x) ((bit32)(_x)) 232285809Sscottl#endif 233285809Sscottl 234285809Sscottl#ifndef BIT8_TO_BIT32_B1 235285809Sscottl#define BIT8_TO_BIT32_B1(_x) (((bit32)(_x)) << 8) 236285809Sscottl#endif 237285809Sscottl 238285809Sscottl#ifndef BIT8_TO_BIT32_B2 239285809Sscottl#define BIT8_TO_BIT32_B2(_x) (((bit32)(_x)) << 16) 240285809Sscottl#endif 241285809Sscottl 242285809Sscottl#ifndef BIT8_TO_BIT32_B3 243285809Sscottl#define BIT8_TO_BIT32_B3(_x) (((bit32)(_x)) << 24) 244285809Sscottl#endif 245285809Sscottl 246285809Sscottl/* 247285809Sscottl * Byte[x] of bit32 to bit8 248285809Sscottl */ 249285809Sscottl#ifndef BIT32_B0_TO_BIT8 250285809Sscottl#define BIT32_B0_TO_BIT8(_x) ((bit8)(((bit32)(_x)) & 0x000000FF)) 251285809Sscottl#endif 252285809Sscottl 253285809Sscottl#ifndef BIT32_B1_TO_BIT8 254285809Sscottl#define BIT32_B1_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x0000FF00) >> 8)) 255285809Sscottl#endif 256285809Sscottl 257285809Sscottl#ifndef BIT32_B2_TO_BIT8 258285809Sscottl#define BIT32_B2_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x00FF0000) >> 16)) 259285809Sscottl#endif 260285809Sscottl 261285809Sscottl#ifndef BIT32_B3_TO_BIT8 262285809Sscottl#define BIT32_B3_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0xFF000000) >> 24)) 263285809Sscottl#endif 264285809Sscottl 265285809Sscottl#elif defined(SA_CPU_BIG_ENDIAN) 266285809Sscottl 267285809Sscottl/*! \def LEBIT16_TO_BIT16(_x) 268285809Sscottl* \brief LEBIT16_TO_BIT16 macro 269285809Sscottl* 270285809Sscottl* use to convert little endian bit16 to host bit16 271285809Sscottl*/ 272285809Sscottl#ifndef LEBIT16_TO_BIT16 273285809Sscottl#define LEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x) 274285809Sscottl#endif 275285809Sscottl 276285809Sscottl/*! \def BIT16_TO_LEBIT16(_x) 277285809Sscottl* \brief BIT16_TO_LEBIT16 macro 278285809Sscottl* 279285809Sscottl* use to convert host bit16 to little endian bit16 280285809Sscottl*/ 281285809Sscottl#ifndef BIT16_TO_LEBIT16 282285809Sscottl#define BIT16_TO_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 283285809Sscottl#endif 284285809Sscottl 285285809Sscottl/*! \def BEBIT16_TO_BIT16(_x) 286285809Sscottl* \brief BEBIT16_TO_BIT16 macro 287285809Sscottl* 288285809Sscottl* use to convert big endian bit16 to host bit16 289285809Sscottl*/ 290285809Sscottl#ifndef BEBIT16_TO_BIT16 291285809Sscottl#define BEBIT16_TO_BIT16(_x) (_x) 292285809Sscottl#endif 293285809Sscottl 294285809Sscottl/*! \def BIT16_TO_BEBIT16(_x) 295285809Sscottl* \brief BIT16_TO_BEBIT16 macro 296285809Sscottl* 297285809Sscottl* use to convert host bit16 to big endian bit16 298285809Sscottl*/ 299285809Sscottl#ifndef BIT16_TO_BEBIT16 300285809Sscottl#define BIT16_TO_BEBIT16(_x) (_x) 301285809Sscottl#endif 302285809Sscottl 303285809Sscottl/*! \def LEBIT32_TO_BIT32(_x) 304285809Sscottl* \brief LEBIT32_TO_BIT32 macro 305285809Sscottl* 306285809Sscottl* use to convert little endian bit32 to host bit32 307285809Sscottl*/ 308285809Sscottl#ifndef LEBIT32_TO_BIT32 309285809Sscottl#define LEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x) 310285809Sscottl#endif 311285809Sscottl 312285809Sscottl/*! \def BIT32_TO_LEBIT32(_x) 313285809Sscottl* \brief BIT32_TO_LEBIT32 macro 314285809Sscottl* 315285809Sscottl* use to convert host bit32 to little endian bit32 316285809Sscottl*/ 317285809Sscottl#ifndef BIT32_TO_LEBIT32 318285809Sscottl#define BIT32_TO_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 319285809Sscottl#endif 320285809Sscottl 321285809Sscottl/*! \def BEBIT32_TO_BIT32(_x) 322285809Sscottl* \brief BEBIT32_TO_BIT32 macro 323285809Sscottl* 324285809Sscottl* use to convert big endian bit32 to host bit32 325285809Sscottl*/ 326285809Sscottl#ifndef BEBIT32_TO_BIT32 327285809Sscottl#define BEBIT32_TO_BIT32(_x) (_x) 328285809Sscottl#endif 329285809Sscottl 330285809Sscottl/*! \def BIT32_TO_BEBIT32(_x) 331285809Sscottl* \brief BIT32_TO_BEBIT32 macro 332285809Sscottl* 333285809Sscottl* use to convert host bit32 to big endian bit32 334285809Sscottl*/ 335285809Sscottl#ifndef BIT32_TO_BEBIT32 336285809Sscottl#define BIT32_TO_BEBIT32(_x) (_x) 337285809Sscottl#endif 338285809Sscottl 339285809Sscottl 340285809Sscottl/* 341285809Sscottl * bit8 to Byte[x] of bit32 342285809Sscottl */ 343285809Sscottl#ifndef BIT8_TO_BIT32_B0 344285809Sscottl#define BIT8_TO_BIT32_B0(_x) (((bit32)(_x)) << 24) 345285809Sscottl#endif 346285809Sscottl 347285809Sscottl#ifndef BIT8_TO_BIT32_B1 348285809Sscottl#define BIT8_TO_BIT32_B1(_x) (((bit32)(_x)) << 16) 349285809Sscottl#endif 350285809Sscottl 351285809Sscottl#ifndef BIT8_TO_BIT32_B2 352285809Sscottl#define BIT8_TO_BIT32_B2(_x) (((bit32)(_x)) << 8) 353285809Sscottl#endif 354285809Sscottl 355285809Sscottl#ifndef BIT8_TO_BIT32_B3 356285809Sscottl#define BIT8_TO_BIT32_B3(_x) ((bit32)(_x)) 357285809Sscottl#endif 358285809Sscottl 359285809Sscottl/* 360285809Sscottl * Byte[x] of bit32 to bit8 361285809Sscottl */ 362285809Sscottl#ifndef BIT32_B0_TO_BIT8 363285809Sscottl#define BIT32_B0_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0xFF000000) >> 24)) 364285809Sscottl#endif 365285809Sscottl 366285809Sscottl#ifndef BIT32_B1_TO_BIT8 367285809Sscottl#define BIT32_B1_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x00FF0000) >> 16)) 368285809Sscottl#endif 369285809Sscottl 370285809Sscottl#ifndef BIT32_B2_TO_BIT8 371285809Sscottl#define BIT32_B2_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x0000FF00) >> 8)) 372285809Sscottl#endif 373285809Sscottl 374285809Sscottl#ifndef BIT32_B3_TO_BIT8 375285809Sscottl#define BIT32_B3_TO_BIT8(_x) ((bit8)(((bit32)(_x)) & 0x000000FF)) 376285809Sscottl#endif 377285809Sscottl 378285809Sscottl#else 379285809Sscottl 380285809Sscottl#error No definition of SA_CPU_BIG_ENDIAN or SA_CPU_LITTLE_ENDIAN 381285809Sscottl 382285809Sscottl#endif 383285809Sscottl 384285809Sscottl 385285809Sscottl#if defined(SA_DMA_LITTLE_ENDIAN) 386285809Sscottl 387285809Sscottl/* 388285809Sscottl * ** bit32 to bit32 389285809Sscottl * */ 390285809Sscottl#ifndef DMA_BIT32_TO_BIT32 391285809Sscottl#define DMA_BIT32_TO_BIT32(_x) (_x) 392285809Sscottl#endif 393285809Sscottl 394285809Sscottl#ifndef DMA_LEBIT32_TO_BIT32 395285809Sscottl#define DMA_LEBIT32_TO_BIT32(_x) (_x) 396285809Sscottl#endif 397285809Sscottl 398285809Sscottl#ifndef DMA_BEBIT32_TO_BIT32 399285809Sscottl#define DMA_BEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x) 400285809Sscottl#endif 401285809Sscottl 402285809Sscottl#ifndef BIT32_TO_DMA_BIT32 403285809Sscottl#define BIT32_TO_DMA_BIT32(_x) (_x) 404285809Sscottl#endif 405285809Sscottl 406285809Sscottl#ifndef BIT32_TO_DMA_LEBIT32 407285809Sscottl#define BIT32_TO_DMA_LEBIT32(_x) (_x) 408285809Sscottl#endif 409285809Sscottl 410285809Sscottl#ifndef BIT32_TO_DMA_BEBIT32 411285809Sscottl#define BIT32_TO_DMA_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 412285809Sscottl#endif 413285809Sscottl 414285809Sscottl 415285809Sscottl/* 416285809Sscottl * ** bit16 to bit16 417285809Sscottl * */ 418285809Sscottl#ifndef DMA_BIT16_TO_BIT16 419285809Sscottl#define DMA_BIT16_TO_BIT16(_x) (_x) 420285809Sscottl#endif 421285809Sscottl 422285809Sscottl#ifndef DMA_LEBIT16_TO_BIT16 423285809Sscottl#define DMA_LEBIT16_TO_BIT16(_x) (_x) 424285809Sscottl#endif 425285809Sscottl 426285809Sscottl#ifndef DMA_BEBIT16_TO_BIT16 427285809Sscottl#define DMA_BEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x) 428285809Sscottl#endif 429285809Sscottl 430285809Sscottl#ifndef BIT16_TO_DMA_BIT16 431285809Sscottl#define BIT16_TO_DMA_BIT16(_x) (_x) 432285809Sscottl#endif 433285809Sscottl 434285809Sscottl#ifndef BIT16_TO_DMA_LEBIT16 435285809Sscottl#define BIT16_TO_DMA_LEBIT16(_x) (_x) 436285809Sscottl#endif 437285809Sscottl 438285809Sscottl#ifndef BIT16_TO_DMA_BEBIT16 439285809Sscottl#define BIT16_TO_DMA_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 440285809Sscottl#endif 441285809Sscottl 442285809Sscottl#if defined(SA_CPU_LITTLE_ENDIAN) 443285809Sscottl 444285809Sscottl#ifndef BEBIT32_TO_DMA_BEBIT32 445285809Sscottl#define BEBIT32_TO_DMA_BEBIT32(_x) (_x) 446285809Sscottl#endif 447285809Sscottl 448285809Sscottl#ifndef LEBIT32_TO_DMA_LEBIT32 449285809Sscottl#define LEBIT32_TO_DMA_LEBIT32(_x) (_x) 450285809Sscottl#endif 451285809Sscottl 452285809Sscottl#ifndef DMA_LEBIT32_TO_LEBIT32 453285809Sscottl#define DMA_LEBIT32_TO_LEBIT32(_x) (_x) 454285809Sscottl#endif 455285809Sscottl 456285809Sscottl#ifndef DMA_BEBIT32_TO_BEBIT32 457285809Sscottl#define DMA_BEBIT32_TO_BEBIT32(_x) (_x) 458285809Sscottl#endif 459285809Sscottl 460285809Sscottl/* 461285809Sscottl * ** bit16 to bit16 462285809Sscottl * */ 463285809Sscottl#ifndef BEBIT16_TO_DMA_BEBIT16 464285809Sscottl#define BEBIT16_TO_DMA_BEBIT16(_x) (_x) 465285809Sscottl#endif 466285809Sscottl 467285809Sscottl#ifndef LEBIT16_TO_DMA_LEBIT16 468285809Sscottl#define LEBIT16_TO_DMA_LEBIT16(_x) (_x) 469285809Sscottl#endif 470285809Sscottl 471285809Sscottl#ifndef DMA_LEBIT16_TO_LEBIT16 472285809Sscottl#define DMA_LEBIT16_TO_LEBIT16(_x) (_x) 473285809Sscottl#endif 474285809Sscottl 475285809Sscottl#ifndef DMA_BEBIT16_TO_BEBIT16 476285809Sscottl#define DMA_BEBIT16_TO_BEBIT16(_x) (_x) 477285809Sscottl#endif 478285809Sscottl 479285809Sscottl#else /* defined(SA_CPU_BIG_ENDIAN) */ 480285809Sscottl 481285809Sscottl 482285809Sscottl/* 483285809Sscottl * ** bit32 to bit32 484285809Sscottl * */ 485285809Sscottl#ifndef BEBIT32_TO_DMA_BEBIT32 486285809Sscottl#define BEBIT32_TO_DMA_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 487285809Sscottl#endif 488285809Sscottl 489285809Sscottl#ifndef LEBIT32_TO_DMA_LEBIT32 490285809Sscottl#define LEBIT32_TO_DMA_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 491285809Sscottl#endif 492285809Sscottl 493285809Sscottl#ifndef DMA_LEBIT32_TO_LEBIT32 494285809Sscottl#define DMA_LEBIT32_TO_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 495285809Sscottl#endif 496285809Sscottl 497285809Sscottl#ifndef DMA_BEBIT32_TO_BEBIT32 498285809Sscottl#define DMA_BEBIT32_TO_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 499285809Sscottl#endif 500285809Sscottl 501285809Sscottl/* 502285809Sscottl * ** bit16 to bit16 503285809Sscottl * */ 504285809Sscottl#ifndef BEBIT16_TO_DMA_BEBIT16 505285809Sscottl#define BEBIT16_TO_DMA_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 506285809Sscottl#endif 507285809Sscottl 508285809Sscottl#ifndef LEBIT16_TO_DMA_LEBIT16 509285809Sscottl#define LEBIT16_TO_DMA_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 510285809Sscottl#endif 511285809Sscottl 512285809Sscottl#ifndef DMA_LEBIT16_TO_LEBIT16 513285809Sscottl#define DMA_LEBIT16_TO_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 514285809Sscottl#endif 515285809Sscottl 516285809Sscottl#ifndef DMA_BEBIT16_TO_BEBIT16 517285809Sscottl#define DMA_BEBIT16_TO_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 518285809Sscottl#endif 519285809Sscottl 520285809Sscottl#endif 521285809Sscottl 522285809Sscottl/* 523285809Sscottl * bit8 to Byte[x] of bit32 524285809Sscottl */ 525285809Sscottl#ifndef BIT8_TO_DMA_BIT32_B0 526285809Sscottl#define BIT8_TO_DMA_BIT32_B0(_x) ((bit32)(_x)) 527285809Sscottl#endif 528285809Sscottl 529285809Sscottl#ifndef BIT8_TO_DMA_BIT32_B1 530285809Sscottl#define BIT8_TO_DMA_BIT32_B1(_x) (((bit32)(_x)) << 8) 531285809Sscottl#endif 532285809Sscottl 533285809Sscottl#ifndef BIT8_TO_DMA_BIT32_B2 534285809Sscottl#define BIT8_TO_DMA_BIT32_B2(_x) (((bit32)(_x)) << 16) 535285809Sscottl#endif 536285809Sscottl 537285809Sscottl#ifndef BIT8_TO_DMA_BIT32_B3 538285809Sscottl#define BIT8_TO_DMA_BIT32_B3(_x) (((bit32)(_x)) << 24) 539285809Sscottl#endif 540285809Sscottl 541285809Sscottl/* 542285809Sscottl * Byte[x] of bit32 to bit8 543285809Sscottl */ 544285809Sscottl#ifndef DMA_BIT32_B0_TO_BIT8 545285809Sscottl#define DMA_BIT32_B0_TO_BIT8(_x) ((bit8)(((bit32)(_x)) & 0x000000FF)) 546285809Sscottl#endif 547285809Sscottl 548285809Sscottl#ifndef DMA_BIT32_B1_TO_BIT8 549285809Sscottl#define DMA_BIT32_B1_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x0000FF00) >> 8)) 550285809Sscottl#endif 551285809Sscottl 552285809Sscottl#ifndef DMA_BIT32_B2_TO_BIT8 553285809Sscottl#define DMA_BIT32_B2_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x00FF0000) >> 16)) 554285809Sscottl#endif 555285809Sscottl 556285809Sscottl#ifndef DMA_BIT32_B3_TO_BIT8 557285809Sscottl#define DMA_BIT32_B3_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0xFF000000) >> 24)) 558285809Sscottl#endif 559285809Sscottl 560285809Sscottl/*| | 561285809Sscottl | end of DMA access macros for LITTLE ENDIAN | 562285809Sscottl --------------------------------------------------------------------- 563285809Sscottl */ 564285809Sscottl 565285809Sscottl#elif defined(SA_DMA_BIG_ENDIAN) /* DMA big endian */ 566285809Sscottl 567285809Sscottl/*-------------------------------------------------------------------- 568285809Sscottl | DMA buffer access macros for BIG ENDIAN | 569285809Sscottl | | 570285809Sscottl */ 571285809Sscottl 572285809Sscottl/* bit32 to bit32 */ 573285809Sscottl#ifndef DMA_BEBIT32_TO_BIT32 574285809Sscottl#define DMA_BEBIT32_TO_BIT32(_x) (_x) 575285809Sscottl#endif 576285809Sscottl 577285809Sscottl#ifndef DMA_LEBIT32_TO_BIT32 578285809Sscottl#define DMA_LEBIT32_TO_BIT32(_x) AGSA_FLIP_4_BYTES(_x) 579285809Sscottl#endif 580285809Sscottl 581285809Sscottl#ifndef BIT32_TO_DMA_BIT32 582285809Sscottl#define BIT32_TO_DMA_BIT32(_x) (_x) 583285809Sscottl#endif 584285809Sscottl 585285809Sscottl#ifndef BIT32_TO_DMA_LEBIT32 586285809Sscottl#define BIT32_TO_DMA_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 587285809Sscottl#endif 588285809Sscottl 589285809Sscottl#ifndef BIT32_TO_DMA_BEBIT32 590285809Sscottl#define BIT32_TO_DMA_BEBIT32(_x) (_x) 591285809Sscottl#endif 592285809Sscottl 593285809Sscottl/* bit16 to bit16 */ 594285809Sscottl#ifndef DMA_BEBIT16_TO_BIT16 595285809Sscottl#define DMA_BEBIT16_TO_BIT16(_x) (_x) 596285809Sscottl#endif 597285809Sscottl 598285809Sscottl#ifndef DMA_LEBIT16_TO_BIT16 599285809Sscottl#define DMA_LEBIT16_TO_BIT16(_x) AGSA_FLIP_2_BYTES(_x) 600285809Sscottl#endif 601285809Sscottl 602285809Sscottl#ifndef BIT16_TO_DMA_BIT16 603285809Sscottl#define BIT16_TO_DMA_BIT16(_x) (_x) 604285809Sscottl#endif 605285809Sscottl 606285809Sscottl#ifndef BIT16_TO_DMA_LEBIT16 607285809Sscottl#define BIT16_TO_DMA_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 608285809Sscottl#endif 609285809Sscottl 610285809Sscottl#ifndef BIT16_TO_DMA_BEBIT16 611285809Sscottl#define BIT16_TO_DMA_BEBIT16(_x) (_x) 612285809Sscottl#endif 613285809Sscottl 614285809Sscottl 615285809Sscottl#if defined(SA_CPU_LITTLE_ENDIAN) /* CPU little endain */ 616285809Sscottl 617285809Sscottl/* bit32 to bit32 */ 618285809Sscottl#ifndef BEBIT32_TO_DMA_BEBIT32 619285809Sscottl#define BEBIT32_TO_DMA_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 620285809Sscottl#endif 621285809Sscottl 622285809Sscottl#ifndef LEBIT32_TO_DMA_LEBIT32 623285809Sscottl#define LEBIT32_TO_DMA_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 624285809Sscottl#endif 625285809Sscottl 626285809Sscottl#ifndef DMA_LEBIT32_TO_LEBIT32 627285809Sscottl#define DMA_LEBIT32_TO_LEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 628285809Sscottl#endif 629285809Sscottl 630285809Sscottl#ifndef DMA_BEBIT32_TO_BEBIT32 631285809Sscottl#define DMA_BEBIT32_TO_BEBIT32(_x) AGSA_FLIP_4_BYTES(_x) 632285809Sscottl#endif 633285809Sscottl 634285809Sscottl/* bit16 to bit16 */ 635285809Sscottl#ifndef BEBIT16_TO_DMA_BEBIT16 636285809Sscottl#define BEBIT16_TO_DMA_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 637285809Sscottl#endif 638285809Sscottl 639285809Sscottl#ifndef LEBIT16_TO_DMA_LEBIT16 640285809Sscottl#define LEBIT16_TO_DMA_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 641285809Sscottl#endif 642285809Sscottl 643285809Sscottl#ifndef DMA_LEBIT16_TO_LEBIT16 644285809Sscottl#define DMA_LEBIT16_TO_LEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 645285809Sscottl#endif 646285809Sscottl 647285809Sscottl#ifndef DMA_BEBIT16_TO_BEBIT16 648285809Sscottl#define DMA_BEBIT16_TO_BEBIT16(_x) AGSA_FLIP_2_BYTES(_x) 649285809Sscottl#endif 650285809Sscottl 651285809Sscottl 652285809Sscottl#else /* defined(SA_CPU_BIG_ENDIAN) */ 653285809Sscottl 654285809Sscottl/* bit32 to bit32 */ 655285809Sscottl#ifndef BEBIT32_TO_DMA_BEBIT32 656285809Sscottl#define BEBIT32_TO_DMA_BEBIT32(_x) (_x) 657285809Sscottl#endif 658285809Sscottl 659285809Sscottl#ifndef LEBIT32_TO_DMA_LEBIT32 660285809Sscottl#define LEBIT32_TO_DMA_LEBIT32(_x) (_x) 661285809Sscottl#endif 662285809Sscottl 663285809Sscottl#ifndef DMA_LEBIT32_TO_LEBIT32 664285809Sscottl#define DMA_LEBIT32_TO_LEBIT32(_x) (_x) 665285809Sscottl#endif 666285809Sscottl 667285809Sscottl#ifndef DMA_BEBIT32_TO_BEBIT32 668285809Sscottl#define DMA_BEBIT32_TO_BEBIT32(_x) (_x) 669285809Sscottl#endif 670285809Sscottl 671285809Sscottl/* bit16 to bit16 */ 672285809Sscottl#ifndef BEBIT16_TO_DMA_BEBIT16 673285809Sscottl#define BEBIT16_TO_DMA_BEBIT16(_x) (_x) 674285809Sscottl#endif 675285809Sscottl 676285809Sscottl#ifndef LEBIT16_TO_DMA_LEBIT16 677285809Sscottl#define LEBIT16_TO_DMA_LEBIT16(_x) (_x) 678285809Sscottl#endif 679285809Sscottl 680285809Sscottl#ifndef DMA_LEBIT16_TO_LEBIT16 681285809Sscottl#define DMA_LEBIT16_TO_LEBIT16(_x) (_x) 682285809Sscottl#endif 683285809Sscottl 684285809Sscottl#ifndef DMA_BEBIT16_TO_BEBIT16 685285809Sscottl#define DMA_BEBIT16_TO_BEBIT16(_x) (_x) 686285809Sscottl#endif 687285809Sscottl 688285809Sscottl#endif 689285809Sscottl 690285809Sscottl/* 691285809Sscottl * bit8 to Byte[x] of bit32 692285809Sscottl */ 693285809Sscottl#ifndef BIT8_TO_DMA_BIT32_B0 694285809Sscottl#define BIT8_TO_DMA_BIT32_B0(_x) (((bit32)(_x)) << 24) 695285809Sscottl#endif 696285809Sscottl 697285809Sscottl#ifndef BIT8_TO_DMA_BIT32_B1 698285809Sscottl#define BIT8_TO_DMA_BIT32_B1(_x) (((bit32)(_x)) << 16) 699285809Sscottl#endif 700285809Sscottl 701285809Sscottl#ifndef BIT8_TO_DMA_BIT32_B2 702285809Sscottl#define BIT8_TO_DMA_BIT32_B2(_x) (((bit32)(_x)) << 8) 703285809Sscottl#endif 704285809Sscottl 705285809Sscottl#ifndef BIT8_TO_DMA_BIT32_B3 706285809Sscottl#define BIT8_TO_DMA_BIT32_B3(_x) ((bit32)(_x)) 707285809Sscottl#endif 708285809Sscottl 709285809Sscottl/* 710285809Sscottl * ** Byte[x] of bit32 to bit8 711285809Sscottl * */ 712285809Sscottl#ifndef DMA_BIT32_B0_TO_BIT8 713285809Sscottl#define DMA_BIT32_B0_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0xFF000000) >> 24)) 714285809Sscottl#endif 715285809Sscottl 716285809Sscottl#ifndef DMA_BIT32_B1_TO_BIT8 717285809Sscottl#define DMA_BIT32_B1_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x00FF0000) >> 16)) 718285809Sscottl#endif 719285809Sscottl 720285809Sscottl#ifndef DMA_BIT32_B2_TO_BIT8 721285809Sscottl#define DMA_BIT32_B2_TO_BIT8(_x) ((bit8)((((bit32)(_x)) & 0x0000FF00) >> 8)) 722285809Sscottl#endif 723285809Sscottl 724285809Sscottl#ifndef DMA_BIT32_B3_TO_BIT8 725285809Sscottl#define DMA_BIT32_B3_TO_BIT8(_x) ((bit8)(((bit32)(_x)) & 0x000000FF)) 726285809Sscottl#endif 727285809Sscottl 728285809Sscottl/*| | 729285809Sscottl | end of DMA access macros for BIG ENDIAN | 730285809Sscottl --------------------------------------------------------------------- 731285809Sscottl*/ 732285809Sscottl#else 733285809Sscottl 734285809Sscottl#error No definition of SA_DMA_BIG_ENDIAN or SA_DMA_LITTLE_ENDIAN 735285809Sscottl 736285809Sscottl#endif /* DMA endian */ 737285809Sscottl/* 738285809Sscottl * End of DMA buffer access macros * 739285809Sscottl * * 740285809Sscottl ********************************************************************** 741285809Sscottl */ 742285809Sscottl 743285809Sscottl/************************************************************************************ 744285809Sscottl * * 745285809Sscottl * Constants defined for LL Layer starts * 746285809Sscottl * * 747285809Sscottl ************************************************************************************/ 748285809Sscottl 749285809Sscottl/********************************************************* 750285809Sscottl * sTSDK LL revision and Interface revision, FW version 751285809Sscottl *********************************************************/ 752285809Sscottl 753285809Sscottl#define FW_THIS_VERSION_SPC12G 0x03060005 754285809Sscottl 755285809Sscottl#define FW_THIS_VERSION_SPC6G 0x02092400 756285809Sscottl#define FW_THIS_VERSION_SPC 0x01110000 757285809Sscottl 758285809Sscottl 759285809Sscottl#define STSDK_LL_INTERFACE_VERSION 0x20A 760285809Sscottl#define STSDK_LL_OLD_INTERFACE_VERSION 0x1 /* SPC and SPCv before 02030401 */ 761285809Sscottl#define STSDK_LL_VERSION FW_THIS_VERSION_SPC6G /**< current sTSDK version */ 762285809Sscottl#define MAX_FW_VERSION_SUPPORTED FW_THIS_VERSION_SPC6G /**< FW */ 763285809Sscottl#define MATCHING_V_FW_VERSION FW_THIS_VERSION_SPC6G /**< current V matching FW version */ 764285809Sscottl#define MIN_FW_SPCVE_VERSION_SUPPORTED 0x02000000 /**< 2.00 FW */ 765285809Sscottl 766285809Sscottl#define STSDK_LL_12G_INTERFACE_VERSION 0x302 767285809Sscottl#define STSDK_LL_12G_VERSION FW_THIS_VERSION_SPC12G /**< current sTSDK version */ 768285809Sscottl#define MAX_FW_12G_VERSION_SUPPORTED FW_THIS_VERSION_SPC12G /**< FW */ 769285809Sscottl#define MATCHING_12G_V_FW_VERSION FW_THIS_VERSION_SPC12G /**< current V matching FW version */ 770285809Sscottl#define MIN_FW_12G_SPCVE_VERSION_SUPPORTED 0x03000000 /**< 3.00 FW */ 771285809Sscottl 772285809Sscottl#define STSDK_LL_SPC_VERSION 0x01100000 /**< current SPC FW version supported */ 773285809Sscottl#define MATCHING_SPC_FW_VERSION FW_THIS_VERSION_SPC /**< current SPC matching FW version */ 774285809Sscottl#define MIN_FW_SPC_VERSION_SUPPORTED 0x01062502 /**< 1.06d FW */ 775285809Sscottl 776285809Sscottl#define STSDK_LL_INTERFACE_VERSION_IGNORE_MASK 0xF00 777285809Sscottl/************************************************* 778285809Sscottl * constants for API return values 779285809Sscottl *************************************************/ 780285809Sscottl#define AGSA_RC_SUCCESS 0x00 /**< Successful function return value */ 781285809Sscottl#define AGSA_RC_FAILURE 0x01 /**< Failed function return value */ 782285809Sscottl#define AGSA_RC_BUSY 0x02 /**< Busy function return value */ 783285809Sscottl/* current only return from saGetControllerInfo() and saGetControllerStatus() */ 784285809Sscottl#define AGSA_RC_HDA_NO_FW_RUNNING 0x03 /**< HDA mode and no FW running */ 785285809Sscottl#define AGSA_RC_FW_NOT_IN_READY_STATE 0x04 /**< FW not in ready state */ 786285809Sscottl/* current only return from saInitialize() for version checking */ 787285809Sscottl#define AGSA_RC_VERSION_INCOMPATIBLE 0x05 /**< Version mismatch */ 788285809Sscottl#define AGSA_RC_VERSION_UNTESTED 0x06 /**< Version not tested */ 789285809Sscottl#define AGSA_RC_NOT_SUPPORTED 0x07 /**< Operation not supported on the current hardware */ 790285809Sscottl#define AGSA_RC_COMPLETE 0x08 791285809Sscottl 792285809Sscottl/************************************************* 793285809Sscottl * constants for type field in agsaMem_t 794285809Sscottl *************************************************/ 795285809Sscottl#define AGSA_CACHED_MEM 0x00 /**< CACHED memory type */ 796285809Sscottl#define AGSA_DMA_MEM 0x01 /**< DMA memory type */ 797285809Sscottl#define AGSA_CACHED_DMA_MEM 0x02 /**< CACHED DMA memory type */ 798285809Sscottl 799285809Sscottl#ifdef SA_ENABLE_TRACE_FUNCTIONS 800285809Sscottl#ifdef FAST_IO_TEST 801285809Sscottl#define AGSA_NUM_MEM_CHUNKS (12 + AGSA_MAX_INBOUND_Q + AGSA_MAX_OUTBOUND_Q) /**< max # of memory chunks supported */ 802285809Sscottl#else 803285809Sscottl#define AGSA_NUM_MEM_CHUNKS (11 + AGSA_MAX_INBOUND_Q + AGSA_MAX_OUTBOUND_Q) /**< max # of memory chunks supported */ 804285809Sscottl#endif 805285809Sscottl#else 806285809Sscottl#ifdef FAST_IO_TEST 807285809Sscottl#define AGSA_NUM_MEM_CHUNKS (11 + AGSA_MAX_INBOUND_Q + AGSA_MAX_OUTBOUND_Q) /**< max # of memory chunks supported */ 808285809Sscottl#else 809285809Sscottl#define AGSA_NUM_MEM_CHUNKS (10 + AGSA_MAX_INBOUND_Q + AGSA_MAX_OUTBOUND_Q) /**< max # of memory chunks supported */ 810285809Sscottl#endif 811285809Sscottl#endif /* END SA_ENABLE_TRACE_FUNCTIONS */ 812285809Sscottl 813285809Sscottl 814285809Sscottl/********************************** 815285809Sscottl * default constant for phy count 816285809Sscottl **********************************/ 817285809Sscottl#define AGSA_MAX_VALID_PHYS 16 /* was 8 for SPC */ /**< max # of phys supported by the hardware */ 818285809Sscottl 819285809Sscottl/************************************ 820285809Sscottl * default constant for Esgl entries 821285809Sscottl ************************************/ 822285809Sscottl#define MAX_ESGL_ENTRIES 10 /**< max # of extended SG list entry */ 823285809Sscottl 824285809Sscottl/******************************************* 825285809Sscottl * constant for max inbound/outbound queues 826285809Sscottl *******************************************/ 827285809Sscottl#define AGSA_MAX_INBOUND_Q 64 /**< max # of inbound queue */ 828285809Sscottl#define AGSA_MAX_OUTBOUND_Q 64 /**< max # of outbound queue */ 829285809Sscottl#define AGSA_MAX_BEST_INBOUND_Q 16 /* Max inbound Q number with good IO performance */ 830285809Sscottl 831285809Sscottl/**************************** 832285809Sscottl * Phy Control constants 833285809Sscottl ****************************/ 834285809Sscottl#define AGSA_PHY_LINK_RESET 0x01 835285809Sscottl#define AGSA_PHY_HARD_RESET 0x02 836285809Sscottl#define AGSA_PHY_GET_ERROR_COUNTS 0x03 /* SPC only used in original saLocalPhyControl */ 837285809Sscottl#define AGSA_PHY_CLEAR_ERROR_COUNTS 0x04 /* SPC only */ 838285809Sscottl#define AGSA_PHY_GET_BW_COUNTS 0x05 /* SPC only */ 839285809Sscottl#define AGSA_PHY_NOTIFY_ENABLE_SPINUP 0x10 840285809Sscottl#define AGSA_PHY_BROADCAST_ASYNCH_EVENT 0x12 841285809Sscottl#define AGSA_PHY_COMINIT_OOB 0x20 842285809Sscottl 843285809Sscottl#define AGSA_SAS_PHY_ERR_COUNTERS_PAGE 0x01 /* retrieve the SAS PHY error counters */ 844285809Sscottl#define AGSA_SAS_PHY_ERR_COUNTERS_CLR_PAGE 0x02 /* retrieve the SAS PHY error counters After capturing the errors, the hardware error counters are cleared and restarted. */ 845285809Sscottl#define AGSA_SAS_PHY_BW_COUNTERS_PAGE 0x03 /* retrieve the SAS PHY transmit and receive bandwidth counters. */ 846285809Sscottl#define AGSA_SAS_PHY_ANALOG_SETTINGS_PAGE 0x04 /* retrieve the SAS PHY analog settings */ 847285809Sscottl#define AGSA_SAS_PHY_GENERAL_STATUS_PAGE 0x05 /* retrieve the SAS PHY general status for the PHY specified in the phyID parameter */ 848285809Sscottl#define AGSA_PHY_SNW3_PAGE 0x06 849285809Sscottl#define AGSA_PHY_RATE_CONTROL_PAGE 0x07 /* Used to set several rate control parameters. */ 850285809Sscottl#define AGSA_SAS_PHY_MISC_PAGE 0x08 851285809Sscottl#define AGSA_SAS_PHY_OPEN_REJECT_RETRY_BACKOFF_THRESHOLD_PAGE 0x08 /* Used to set retry and backoff threshold parameters. */ 852285809Sscottl 853285809Sscottl/***************** 854285809Sscottl * HW Reset 855285809Sscottl *****************/ 856285809Sscottl#define AGSA_CHIP_RESET 0x00 /**< flag to reset hard reset */ 857285809Sscottl#define AGSA_SOFT_RESET 0x01 /**< flag to reset the controller chip */ 858285809Sscottl 859285809Sscottl/*************************************** 860285809Sscottl * Discovery Types 861285809Sscottl ***************************************/ 862285809Sscottl#define AG_SA_DISCOVERY_TYPE_SAS 0x00 /**< flag to discover SAS devices */ 863285809Sscottl#define AG_SA_DISCOVERY_TYPE_SATA 0x01 /**< flag to discover SATA devices */ 864285809Sscottl 865285809Sscottl/*************************************** 866285809Sscottl * Discovery Options 867285809Sscottl ***************************************/ 868285809Sscottl#define AG_SA_DISCOVERY_OPTION_FULL_START 0x00 /**< flag to start full discovery */ 869285809Sscottl#define AG_SA_DISCOVERY_OPTION_INCREMENTAL_START 0x01 /**< flag to start incremental discovery */ 870285809Sscottl#define AG_SA_DISCOVERY_OPTION_ABORT 0x02 /**< flag to abort a discovery */ 871285809Sscottl 872285809Sscottl/**************************************************************** 873285809Sscottl * SSP/SMP/SATA Request type 874285809Sscottl ****************************************************************/ 875285809Sscottl/* bit31-28 - request type 876285809Sscottl bit27-16 - reserved 877285809Sscottl bit15-10 - SATA ATAP 878285809Sscottl bit9-8 - direction 879285809Sscottl bit7 - AUTO 880285809Sscottl bit6 - reserved 881285809Sscottl bit5 - EXT 882285809Sscottl bit4 - MSG 883285809Sscottl bit3-0 - Initiator, target or task mode (1 to 8) 884285809Sscottl */ 885285809Sscottl#define AGSA_REQTYPE_MASK 0xF0000000 /**< request type mask */ 886285809Sscottl#define AGSA_REQ_TYPE_UNKNOWN 0x00000000 /**< unknown request type */ 887285809Sscottl#define AGSA_SSP_REQTYPE 0x80000000 888285809Sscottl#define AGSA_SMP_REQTYPE 0x40000000 889285809Sscottl#define AGSA_SATA_REQTYPE 0x20000000 890285809Sscottl 891285809Sscottl#define AGSA_DIR_MASK 0x00000300 892285809Sscottl#define AGSA_AUTO_MASK 0x00000080 893285809Sscottl#define AGSA_SATA_ATAP_MASK 0x0000FC00 894285809Sscottl 895285809Sscottl#define AGSA_DIR_NONE 0x00000000 896285809Sscottl#define AGSA_DIR_CONTROLLER_TO_HOST 0x00000100 /**< used to be called AGSA_DIR_READ */ 897285809Sscottl#define AGSA_DIR_HOST_TO_CONTROLLER 0x00000200 /**< used to be called AGSA_DIR_WRITE */ 898285809Sscottl 899285809Sscottl/* bit definition - AUTO mode */ 900285809Sscottl#define AGSA_AUTO_GOOD_RESPONSE 0x00000080 901285809Sscottl 902285809Sscottl/* request type - not bit difination */ 903285809Sscottl#define AGSA_SSP_INIT 0x00000001 904285809Sscottl#define AGSA_SSP_TGT_MODE 0x00000003 905285809Sscottl#define AGSA_SSP_TASK_MGNT 0x00000005 906285809Sscottl#define AGSA_SSP_TGT_RSP 0x00000006 907285809Sscottl#define AGSA_SMP_INIT 0x00000007 908285809Sscottl#define AGSA_SMP_TGT 0x00000008 909285809Sscottl 910285809Sscottl/* request type for SSP Initiator and extend */ 911285809Sscottl#define AGSA_SSP_INIT_EXT (AGSA_SSP_INIT | AGSA_SSP_EXT_BIT) 912285809Sscottl 913285809Sscottl/* request type for SSP Initiator and indirect */ 914285809Sscottl#define AGSA_SSP_INIT_INDIRECT (AGSA_SSP_INIT | AGSA_SSP_INDIRECT_BIT) 915285809Sscottl 916285809Sscottl/* bit definition */ 917285809Sscottl#define AGSA_MSG 0x00000010 918285809Sscottl#define AGSA_SSP_EXT_BIT 0x00000020 919285809Sscottl#define AGSA_SSP_INDIRECT_BIT 0x00000040 920285809Sscottl#define AGSA_MSG_BIT AGSA_MSG >> 2 921285809Sscottl 922285809Sscottl/* agsaSSPIniEncryptIOStartCmd_t dirMTlr bits*/ 923285809Sscottl#define AGSA_INDIRECT_CDB_BIT 0x00000008 924285809Sscottl#define AGSA_SKIP_MASK_BIT 0x00000010 925285809Sscottl#define AGSA_ENCRYPT_BIT 0x00000020 926285809Sscottl#define AGSA_DIF_BIT 0x00000040 927285809Sscottl#define AGSA_DIF_LA_BIT 0x00000080 928285809Sscottl#define AGSA_DIRECTION_BITS 0x00000300 929285809Sscottl#define AGSA_SKIP_MASK_OFFSET_BITS 0x0F000000 930285809Sscottl#define AGSA_SSP_INFO_LENGTH_BITS 0xF0000000 931285809Sscottl 932285809Sscottl/* agsaSSPTgtIOStartCmd_t INITagAgrDir bits */ 933285809Sscottl#define AGSA_SSP_TGT_BITS_INI_TAG 0xFFFF0000 /* 16 31 */ 934285809Sscottl#define AGSA_SSP_TGT_BITS_ODS 0x00008000 /* 15 */ 935285809Sscottl#define AGSA_SSP_TGT_BITS_DEE_DIF 0x00004000 /* 14 */ 936285809Sscottl#define AGSA_SSP_TGT_BITS_DEE 0x00002000 /* 13 14 */ 937285809Sscottl#define AGSA_SSP_TGT_BITS_R 0x00001000 /* 12 */ 938285809Sscottl#define AGSA_SSP_TGT_BITS_DAD 0x00000600 /* 11 10 */ 939285809Sscottl#define AGSA_SSP_TGT_BITS_DIR 0x00000300 /* 8 9 */ 940285809Sscottl#define AGSA_SSP_TGT_BITS_DIR_IN 0x00000100 /* 8 9 */ 941285809Sscottl#define AGSA_SSP_TGT_BITS_DIR_OUT 0x00000200 /* 8 9 */ 942285809Sscottl#define AGSA_SSP_TGT_BITS_AGR 0x00000080 /* 7 */ 943285809Sscottl#define AGSA_SSP_TGT_BITS_RDF 0x00000040 /* 6 */ 944285809Sscottl#define AGSA_SSP_TGT_BITS_RTE 0x00000030 /* 4 5 */ 945285809Sscottl#define AGSA_SSP_TGT_BITS_AN 0x00000006 /* 2 3 */ 946285809Sscottl 947285809Sscottl 948285809Sscottl/* agsaSSPIniEncryptIOStartCmd_t DIF_flags bit definitions */ 949285809Sscottl#define AGSA_DIF_UPDATE_BITS 0xFC000000 950285809Sscottl#define AGSA_DIF_VERIFY_BITS 0x03F00000 951285809Sscottl#define AGSA_DIF_BLOCK_SIZE_BITS 0x000F0000 952285809Sscottl#define AGSA_DIF_ENABLE_BLOCK_COUNT_BIT 0x00000040 953285809Sscottl#define AGSA_DIF_CRC_SEED_BIT 0x00000020 954285809Sscottl#define AGSA_DIF_CRC_INVERT_BIT 0x00000010 955285809Sscottl#define AGSA_DIF_CRC_VERIFY_BIT 0x00000008 956285809Sscottl#define AGSA_DIF_OP_BITS 0x00000007 957285809Sscottl 958285809Sscottl#define AGSA_DIF_OP_INSERT 0x00000000 959285809Sscottl#define AGSA_DIF_OP_VERIFY_AND_FORWARD 0x00000001 960285809Sscottl#define AGSA_DIF_OP_VERIFY_AND_DELETE 0x00000002 961285809Sscottl#define AGSA_DIF_OP_VERIFY_AND_REPLACE 0x00000003 962285809Sscottl#define AGSA_DIF_OP_RESERVED2 0x00000004 963285809Sscottl#define AGSA_DIF_OP_VERIFY_UDT_REPLACE_CRC 0x00000005 964285809Sscottl#define AGSA_DIF_OP_RESERVED3 0x00000006 965285809Sscottl#define AGSA_DIF_OP_REPLACE_UDT_REPLACE_CRC 0x00000007 966285809Sscottl 967285809Sscottl 968285809Sscottl/* agsaSSPIniEncryptIOStartCmd_t EncryptFlagsLo bit definitions */ 969285809Sscottl#define AGSA_ENCRYPT_DEK_BITS 0xFFFFFF000 970285809Sscottl#define AGSA_ENCRYPT_SKIP_DIF_BIT 0x000000010 971285809Sscottl#define AGSA_ENCRYPT_KEY_TABLE_BITS 0x00000000C 972285809Sscottl#define AGSA_ENCRYPT_KEY_TAG_BIT 0x000000002 973285809Sscottl 974285809Sscottl/* Cipher mode to be used for this I/O. */ 975285809Sscottl#define AGSA_ENCRYPT_ECB_Mode 0 976285809Sscottl#define AGSA_ENCRYPT_XTS_Mode 0x6 977285809Sscottl 978285809Sscottl/* agsaSSPIniEncryptIOStartCmd_t EncryptFlagsHi bit definitions */ 979285809Sscottl#define AGSA_ENCRYPT_KEK_SELECT_BITS 0x0000000E0 980285809Sscottl#define AGSA_ENCRYPT_SECTOR_SIZE_BITS 0x00000001F 981285809Sscottl 982285809Sscottl/* defined in the sTSDK spec. */ 983285809Sscottl#define AGSA_SSP_INIT_NONDATA (AGSA_SSP_REQTYPE | AGSA_DIR_NONE | AGSA_SSP_INIT) /**< SSP initiator non data request type */ 984285809Sscottl#define AGSA_SSP_INIT_READ (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT) /**< SSP initiator read request type */ 985285809Sscottl#define AGSA_SSP_INIT_WRITE (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT) /**< SSP initiator write request type */ 986285809Sscottl#define AGSA_SSP_TGT_READ_DATA (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_TGT_MODE) /**< SSP target read data request type */ 987285809Sscottl#define AGSA_SSP_TGT_READ (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_TGT_MODE) /**< SSP target read data request type */ 988285809Sscottl#define AGSA_SSP_TGT_READ_GOOD_RESP (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_TGT_MODE | AGSA_AUTO_GOOD_RESPONSE) /**< SSP target read data with automatic good response request type */ 989285809Sscottl#define AGSA_SSP_TGT_WRITE_DATA (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_TGT_MODE) /**< SSP target write data request type */ 990285809Sscottl#define AGSA_SSP_TGT_WRITE (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_TGT_MODE) /**< SSP target write data request type */ 991285809Sscottl#define AGSA_SSP_TGT_WRITE_GOOD_RESP (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_TGT_MODE | AGSA_AUTO_GOOD_RESPONSE) /**< SSP target write data request type with automatic good response request type*/ 992285809Sscottl#define AGSA_SSP_TASK_MGNT_REQ (AGSA_SSP_REQTYPE | AGSA_SSP_TASK_MGNT) /**< SSP task management request type */ 993285809Sscottl#define AGSA_SSP_TGT_CMD_OR_TASK_RSP (AGSA_SSP_REQTYPE | AGSA_SSP_TGT_RSP) /**< SSP command or task management response request type */ 994285809Sscottl#define AGSA_SMP_INIT_REQ (AGSA_SMP_REQTYPE | AGSA_SMP_INIT) /**< SMP initiator request type */ 995285809Sscottl#define AGSA_SMP_TGT_RESPONSE (AGSA_SMP_REQTYPE | AGSA_SMP_TGT) /**< SMP target response request type */ 996285809Sscottl#define AGSA_SSP_INIT_READ_M (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT | AGSA_MSG) 997285809Sscottl#define AGSA_SSP_INIT_WRITE_M (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT | AGSA_MSG) 998285809Sscottl#define AGSA_SSP_TASK_MGNT_REQ_M (AGSA_SSP_REQTYPE | AGSA_SSP_TASK_MGNT | AGSA_MSG) 999285809Sscottl#define AGSA_SSP_INIT_READ_EXT (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT_EXT) /**< SSP initiator read request Ext type */ 1000285809Sscottl#define AGSA_SSP_INIT_WRITE_EXT (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT_EXT) /**< SSP initiator write request Ext type */ 1001285809Sscottl 1002285809Sscottl#define AGSA_SSP_INIT_READ_INDIRECT (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT_INDIRECT) /**< SSP initiator read request indirect type */ 1003285809Sscottl#define AGSA_SSP_INIT_WRITE_INDIRECT (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT_INDIRECT) /**< SSP initiator write request indirect type */ 1004285809Sscottl 1005285809Sscottl#define AGSA_SSP_INIT_READ_INDIRECT_M (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT_INDIRECT | AGSA_MSG) /**< SSP initiator read request indirect type */ 1006285809Sscottl#define AGSA_SSP_INIT_WRITE_INDIRECT_M (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT_INDIRECT | AGSA_MSG) /**< SSP initiator write request indirect type */ 1007285809Sscottl#define AGSA_SSP_INIT_READ_EXT_M (AGSA_SSP_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SSP_INIT_EXT | AGSA_MSG) 1008285809Sscottl#define AGSA_SSP_INIT_WRITE_EXT_M (AGSA_SSP_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SSP_INIT_EXT | AGSA_MSG) 1009285809Sscottl 1010285809Sscottl#define AGSA_SMP_IOCTL_REQUEST 0xFFFFFFFF 1011285809Sscottl 1012285809Sscottl#define AGSA_SATA_ATAP_SRST_ASSERT 0x00000400 1013285809Sscottl#define AGSA_SATA_ATAP_SRST_DEASSERT 0x00000800 1014285809Sscottl#define AGSA_SATA_ATAP_EXECDEVDIAG 0x00000C00 1015285809Sscottl#define AGSA_SATA_ATAP_NON_DATA 0x00001000 1016285809Sscottl#define AGSA_SATA_ATAP_PIO 0x00001400 1017285809Sscottl#define AGSA_SATA_ATAP_DMA 0x00001800 1018285809Sscottl#define AGSA_SATA_ATAP_NCQ 0x00001C00 1019285809Sscottl#define AGSA_SATA_ATAP_PKT_DEVRESET 0x00002000 1020285809Sscottl#define AGSA_SATA_ATAP_PKT 0x00002400 1021285809Sscottl 1022285809Sscottl#define AGSA_SATA_PROTOCOL_NON_DATA (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_NON_DATA) 1023285809Sscottl#define AGSA_SATA_PROTOCOL_PIO_READ (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_PIO) /**< SATA PIO read request type */ 1024285809Sscottl#define AGSA_SATA_PROTOCOL_DMA_READ (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_DMA) /**< SATA DMA read request type */ 1025285809Sscottl#define AGSA_SATA_PROTOCOL_FPDMA_READ (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_NCQ) /**< SATA FDMA read request type */ 1026285809Sscottl#define AGSA_SATA_PROTOCOL_PIO_WRITE (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_PIO) /**< SATA PIO read request type */ 1027285809Sscottl#define AGSA_SATA_PROTOCOL_DMA_WRITE (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_DMA) /**< SATA DMA read request type */ 1028285809Sscottl#define AGSA_SATA_PROTOCOL_FPDMA_WRITE (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_NCQ) /**< SATA FDMA read request type */ 1029285809Sscottl#define AGSA_SATA_PROTOCOL_DEV_RESET (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_PKT_DEVRESET) /**< SATA device reset request type */ 1030285809Sscottl#define AGSA_SATA_PROTOCOL_SRST_ASSERT (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_SRST_ASSERT) /**< SATA device reset assert */ 1031285809Sscottl#define AGSA_SATA_PROTOCOL_SRST_DEASSERT (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_SRST_DEASSERT) /**< SATA device reset deassert */ 1032285809Sscottl#define AGSA_SATA_PROTOCOL_D2H_PKT (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_PKT) 1033285809Sscottl#define AGSA_SATA_PROTOCOL_H2D_PKT (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_PKT) 1034285809Sscottl#define AGSA_SATA_PROTOCOL_NON_PKT (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_PKT) 1035285809Sscottl 1036285809Sscottl 1037285809Sscottl#define AGSA_SATA_PROTOCOL_NON_DATA_M (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_NON_DATA | AGSA_MSG) 1038285809Sscottl#define AGSA_SATA_PROTOCOL_PIO_READ_M (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_PIO | AGSA_MSG) /**< SATA PIO read request type */ 1039285809Sscottl#define AGSA_SATA_PROTOCOL_DMA_READ_M (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_DMA | AGSA_MSG) /**< SATA DMA read request type */ 1040285809Sscottl#define AGSA_SATA_PROTOCOL_FPDMA_READ_M (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_NCQ | AGSA_MSG) /**< SATA FDMA read request type */ 1041285809Sscottl#define AGSA_SATA_PROTOCOL_PIO_WRITE_M (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_PIO | AGSA_MSG) /**< SATA PIO read request type */ 1042285809Sscottl#define AGSA_SATA_PROTOCOL_DMA_WRITE_M (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_DMA | AGSA_MSG) /**< SATA DMA read request type */ 1043285809Sscottl#define AGSA_SATA_PROTOCOL_FPDMA_WRITE_M (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_NCQ | AGSA_MSG) /**< SATA FDMA read request type */ 1044285809Sscottl#define AGSA_SATA_PROTOCOL_D2H_PKT_M (AGSA_SATA_REQTYPE | AGSA_DIR_CONTROLLER_TO_HOST | AGSA_SATA_ATAP_PKT | AGSA_MSG) 1045285809Sscottl#define AGSA_SATA_PROTOCOL_H2D_PKT_M (AGSA_SATA_REQTYPE | AGSA_DIR_HOST_TO_CONTROLLER | AGSA_SATA_ATAP_PKT | AGSA_MSG) 1046285809Sscottl#define AGSA_SATA_PROTOCOL_NON_PKT_M (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_PKT | AGSA_MSG) 1047285809Sscottl/* TestBase */ 1048285809Sscottl#define AGSA_SATA_PROTOCOL_DEV_RESET_M (AGSA_SATA_REQTYPE | AGSA_DIR_NONE | AGSA_SATA_ATAP_PKT_DEVRESET | AGSA_MSG) /**< SATA device reset request type */ 1049285809Sscottl 1050285809Sscottl 1051285809Sscottl 1052285809Sscottl#define AGSA_INTERRUPT_HANDLE_ALL_CHANNELS 0xFFFFFFFF /**< flag indicates handles interrupts for all channles */ 1053285809Sscottl 1054285809Sscottl/**************************************************************************** 1055285809Sscottl** INBOUND Queue related macros 1056285809Sscottl****************************************************************************/ 1057285809Sscottl#define AGSA_IBQ_PRIORITY_NORMAL 0x0 1058285809Sscottl#define AGSA_IBQ_PRIORITY_HIGH 0x1 1059285809Sscottl 1060285809Sscottl/**************************************************************************** 1061285809Sscottl** Phy properties related macros 1062285809Sscottl****************************************************************************/ 1063285809Sscottl/* link rate */ 1064285809Sscottl#define AGSA_PHY_MAX_LINK_RATE_MASK 0x0000000F /* bits 0-3 */ 1065285809Sscottl#define AGSA_PHY_MAX_LINK_RATE_1_5G 0x00000001 /* 0001b */ 1066285809Sscottl#define AGSA_PHY_MAX_LINK_RATE_3_0G 0x00000002 /* 0010b */ 1067285809Sscottl#define AGSA_PHY_MAX_LINK_RATE_6_0G 0x00000004 /* 0100b */ 1068285809Sscottl#define AGSA_PHY_MAX_LINK_RATE_12_0G 0x00000008 /* 1000b */ 1069285809Sscottl 1070285809Sscottl/* SAS/SATA mode */ 1071285809Sscottl#define AGSA_PHY_MODE_MASK 0x00000030 /* bits 4-5 */ 1072285809Sscottl#define AGSA_PHY_MODE_SAS 0x00000010 /* 01b */ 1073285809Sscottl#define AGSA_PHY_MODE_SATA 0x00000020 /* 10b */ 1074285809Sscottl 1075285809Sscottl/* control spin-up hold */ 1076285809Sscottl#define AGSA_PHY_SPIN_UP_HOLD_MASK 0x00000040 /* bit6 */ 1077285809Sscottl#define AGSA_PHY_SPIN_UP_HOLD_ON 0x00000040 /* 1b */ 1078285809Sscottl#define AGSA_PHY_SPIN_UP_HOLD_OFF 0x00000000 /* 0b */ 1079285809Sscottl 1080285809Sscottl/**************************************************************************** 1081285809Sscottl** Device Info related macros 1082285809Sscottl****************************************************************************/ 1083285809Sscottl/* S (SAS/SATA) */ 1084285809Sscottl#define AGSA_DEV_INFO_SASSATA_MASK 0x00000010 /* bit 4 */ 1085285809Sscottl#define AGSA_DEV_INFO_SASSATA_SAS 0x00000010 /* 1b */ 1086285809Sscottl#define AGSA_DEV_INFO_SASSATA_SATA 0x00000000 /* 0b */ 1087285809Sscottl 1088285809Sscottl/* Rate (link-rate) */ 1089285809Sscottl#define AGSA_DEV_INFO_RATE_MASK 0x0000000F /* bits 0-3 */ 1090285809Sscottl#define AGSA_DEV_INFO_RATE_1_5G 0x00000008 /* 8h */ 1091285809Sscottl#define AGSA_DEV_INFO_RATE_3_0G 0x00000009 /* 9h */ 1092285809Sscottl#define AGSA_DEV_INFO_RATE_6_0G 0x0000000A /* Ah */ 1093285809Sscottl#define AGSA_DEV_INFO_RATE_12_0G 0x0000000B /* Bh */ 1094285809Sscottl 1095285809Sscottl/* devType */ 1096285809Sscottl#define AGSA_DEV_INFO_DEV_TYPE_MASK 0x000000E0 /* bits 5-7 */ 1097285809Sscottl#define AGSA_DEV_INFO_DEV_TYPE_END_DEVICE 0x00000020 /* 001b */ 1098285809Sscottl#define AGSA_DEV_INFO_DEV_TYPE_EDGE_EXP_DEVICE 0x00000040 /* 010b */ 1099285809Sscottl#define AGSA_DEV_INFO_DEV_TYPE_FANOUT_EXP_DEVICE 0x00000060 /* 011b */ 1100285809Sscottl 1101285809Sscottl/***************************************************************************** 1102285809Sscottl** SAS TM Function definitions see SAS spec p308 Table 105 (Revision 7) 1103285809Sscottl*****************************************************************************/ 1104285809Sscottl#define AGSA_ABORT_TASK 0x01 1105285809Sscottl#define AGSA_ABORT_TASK_SET 0x02 1106285809Sscottl#define AGSA_CLEAR_TASK_SET 0x04 1107285809Sscottl#define AGSA_LOGICAL_UNIT_RESET 0x08 1108285809Sscottl#define AGSA_IT_NEXUS_RESET 0x10 1109285809Sscottl#define AGSA_CLEAR_ACA 0x40 1110285809Sscottl#define AGSA_QUERY_TASK 0x80 1111285809Sscottl#define AGSA_QUERY_TASK_SET 0x81 1112285809Sscottl#define AGSA_QUERY_UNIT_ATTENTION 0x82 1113285809Sscottl 1114285809Sscottl/***************************************************************************** 1115285809Sscottl** SAS TM Function Response Code see SAS spec p312 Table 111 (Revision 7) 1116285809Sscottl*****************************************************************************/ 1117285809Sscottl#define AGSA_TASK_MANAGEMENT_FUNCTION_COMPLETE 0x0 1118285809Sscottl#define AGSA_INVALID_FRAME 0x2 1119285809Sscottl#define AGSA_TASK_MANAGEMENT_FUNCTION_NOT_SUPPORTED 0x4 1120285809Sscottl#define AGSA_TASK_MANAGEMENT_FUNCTION_FAILED 0x5 1121285809Sscottl#define AGSA_TASK_MANAGEMENT_FUNCTION_SUCCEEDED 0x8 1122285809Sscottl#define AGSA_INCORRECT_LOGICAL_UNIT_NUMBER 0x9 1123285809Sscottl/* SAS spec 9.2.2.5.3 p356 Table 128 (Revision 9e) */ 1124285809Sscottl#define AGSA_OVERLAPPED_TAG_ATTEMPTED 0xA 1125285809Sscottl 1126285809Sscottl#define AGSA_SATA_BSY_OVERRIDE 0x00080000 1127285809Sscottl#define AGSA_SATA_CLOSE_CLEAR_AFFILIATION 0x00400000 1128285809Sscottl 1129285809Sscottl#define AGSA_MAX_SMPPAYLOAD_VIA_SFO 40 1130285809Sscottl#define AGSA_MAX_SSPPAYLOAD_VIA_SFO 36 1131285809Sscottl 1132285809Sscottl/* SATA Initiator Request option field defintion */ 1133285809Sscottl#define AGSA_RETURN_D2H_FIS_GOOD_COMPLETION 0x000001 1134285809Sscottl#define AGSA_SATA_ENABLE_ENCRYPTION 0x000004 1135285809Sscottl#define AGSA_SATA_ENABLE_DIF 0x000008 1136285809Sscottl#define AGSA_SATA_SKIP_QWORD 0xFFFF00 1137285809Sscottl 1138285809Sscottl/* SAS Initiator Request flag definitions */ 1139285809Sscottl/* Bits 0,1 use TLR_MASK */ 1140285809Sscottl 1141285809Sscottl#define AGSA_SAS_ENABLE_ENCRYPTION 0x0004 1142285809Sscottl#define AGSA_SAS_ENABLE_DIF 0x0008 1143285809Sscottl 1144285809Sscottl#ifdef SAFLAG_USE_DIF_ENC_IOMB 1145285809Sscottl#define AGSA_SAS_USE_DIF_ENC_OPSTART 0x0010 1146285809Sscottl#endif /* SAFLAG_USE_DIF_ENC_IOMB */ 1147285809Sscottl 1148285809Sscottl#define AGSA_SAS_ENABLE_SKIP_MASK 0x0010 1149285809Sscottl#define AGSA_SAS_SKIP_MASK_OFFSET 0xFFE0 1150285809Sscottl 1151285809Sscottl/**************************************************************************** 1152285809Sscottl** SMP Phy control Phy Operation field 1153285809Sscottl****************************************************************************/ 1154285809Sscottl#define AGSA_PHY_CONTROL_LINK_RESET_OP 0x1 1155285809Sscottl#define AGSA_PHY_CONTROL_HARD_RESET_OP 0x2 1156285809Sscottl#define AGSA_PHY_CONTROL_DISABLE 0x3 1157285809Sscottl#define AGSA_PHY_CONTROL_CLEAR_ERROR_LOG_OP 0x5 1158285809Sscottl#define AGSA_PHY_CONTROL_CLEAR_AFFILIATION 0x6 1159285809Sscottl#define AGSA_PHY_CONTROL_XMIT_SATA_PS_SIGNAL 0x7 1160285809Sscottl 1161285809Sscottl/**************************************************************************** 1162285809Sscottl** SAS Diagnostic Operation code 1163285809Sscottl****************************************************************************/ 1164285809Sscottl#define AGSA_SAS_DIAG_START 0x1 1165285809Sscottl#define AGSA_SAS_DIAG_END 0x0 1166285809Sscottl 1167285809Sscottl/**************************************************************************** 1168285809Sscottl** Port Control constants 1169285809Sscottl****************************************************************************/ 1170285809Sscottl#define AGSA_PORT_SET_SMP_PHY_WIDTH 0x1 1171285809Sscottl#define AGSA_PORT_SET_PORT_RECOVERY_TIME 0x2 1172285809Sscottl#define AGSA_PORT_IO_ABORT 0x3 1173285809Sscottl#define AGSA_PORT_SET_PORT_RESET_TIME 0x4 1174285809Sscottl#define AGSA_PORT_HARD_RESET 0x5 1175285809Sscottl#define AGSA_PORT_CLEAN_UP 0x6 1176285809Sscottl#define AGSA_STOP_PORT_RECOVERY_TIMER 0x7 1177285809Sscottl 1178285809Sscottl/* Device State */ 1179285809Sscottl#define SA_DS_OPERATIONAL 0x1 1180285809Sscottl#define SA_DS_PORT_IN_RESET 0x2 1181285809Sscottl#define SA_DS_IN_RECOVERY 0x3 1182285809Sscottl#define SA_DS_IN_ERROR 0x4 1183285809Sscottl#define SA_DS_NON_OPERATIONAL 0x7 1184285809Sscottl 1185285809Sscottl/************************************************************************************ 1186285809Sscottl * * 1187285809Sscottl * Constants defined for LL Layer ends * 1188285809Sscottl * * 1189285809Sscottl ************************************************************************************/ 1190285809Sscottl 1191285809Sscottl/************************************************************************************ 1192285809Sscottl * * 1193285809Sscottl * Constants defined for OS Layer starts * 1194285809Sscottl * * 1195285809Sscottl ************************************************************************************/ 1196285809Sscottl/***************************************** 1197285809Sscottl * ossaXXX return values 1198285809Sscottl ******************************************/ 1199285809Sscottl/* common for all ossaXXX CB */ 1200285809Sscottl#define OSSA_SUCCESS 0x00 /**< flag indicates successful callback status */ 1201285809Sscottl#define OSSA_FAILURE 0x01 /**< flag indicates failed callback status */ 1202285809Sscottl 1203285809Sscottl/* ossaHwCB() */ 1204285809Sscottl#define OSSA_RESET_PENDING 0x03 /**< flag indicates reset pending callback status */ 1205285809Sscottl#define OSSA_CHIP_FAILED 0x04 /**< flag indicates chip failed callback status */ 1206285809Sscottl#define OSSA_FREEZE_FAILED 0x05 /**< flag indicates freeze failed callback status */ 1207285809Sscottl 1208285809Sscottl/* ossaLocalPhyControl() */ 1209285809Sscottl#define OSSA_PHY_CONTROL_FAILURE 0x03 /**< flag indicates phy Control operation failure */ 1210285809Sscottl 1211285809Sscottl/* ossaDeviceRegisterCB() */ 1212285809Sscottl#define OSSA_FAILURE_OUT_OF_RESOURCE 0x01 /**< flag indicates failed callback status */ 1213285809Sscottl#define OSSA_FAILURE_DEVICE_ALREADY_REGISTERED 0x02 /**< flag indicates failed callback status */ 1214285809Sscottl#define OSSA_FAILURE_INVALID_PHY_ID 0x03 /**< flag indicates failed callback status */ 1215285809Sscottl#define OSSA_FAILURE_PHY_ID_ALREADY_REGISTERED 0x04 /**< flag indicates failed callback status */ 1216285809Sscottl#define OSSA_FAILURE_PORT_ID_OUT_OF_RANGE 0x05 /**< flag indicates failed callback status */ 1217285809Sscottl#define OSSA_FAILURE_PORT_NOT_VALID_STATE 0x06 /**< flag indicates failed callback status */ 1218285809Sscottl#define OSSA_FAILURE_DEVICE_TYPE_NOT_VALID 0x07 /**< flag indicates failed callback status */ 1219285809Sscottl#define OSSA_ERR_DEVICE_HANDLE_UNAVAILABLE 0x1020 1220285809Sscottl#define OSSA_ERR_DEVICE_ALREADY_REGISTERED 0x1021 1221285809Sscottl#define OSSA_ERR_DEVICE_TYPE_NOT_VALID 0x1022 1222285809Sscottl 1223285809Sscottl#define OSSA_MPI_ERR_DEVICE_ACCEPT_PENDING 0x1027 /**/ 1224285809Sscottl 1225285809Sscottl#define OSSA_ERR_PORT_INVALID 0x1041 1226285809Sscottl#define OSSA_ERR_PORT_STATE_NOT_VALID 0x1042 1227285809Sscottl 1228285809Sscottl#define OSSA_ERR_PORT_SMP_PHY_WIDTH_EXCEED 0x1045 1229285809Sscottl 1230285809Sscottl#define OSSA_ERR_PHY_ID_INVALID 0x1061 1231285809Sscottl#define OSSA_ERR_PHY_ID_ALREADY_REGISTERED 0x1062 1232285809Sscottl 1233285809Sscottl 1234285809Sscottl 1235285809Sscottl/* ossaDeregisterDeviceCB() */ 1236285809Sscottl#define OSSA_INVALID_HANDLE 0x02 /**< flag indicates failed callback status */ 1237285809Sscottl#define OSSA_ERR_DEVICE_HANDLE_INVALID 0x1023 /* MPI_ERR_DEVICE_HANDLE_INVALID The device handle associated with DEVICE_ID does not exist. */ 1238285809Sscottl#define OSSA_ERR_DEVICE_BUSY 0x1024 /* MPI_ERR_DEVICE_BUSY Device has outstanding I/Os. */ 1239285809Sscottl 1240285809Sscottl 1241285809Sscottl#define OSSA_RC_ACCEPT 0x00 /**< flag indicates the result of the callback function */ 1242285809Sscottl#define OSSA_RC_REJECT 0x01 /**< flag indicates the result of the callback function */ 1243285809Sscottl 1244285809Sscottl/* ossaSetDeviceStateCB() */ 1245285809Sscottl#define OSSA_INVALID_STATE 0x0001 1246285809Sscottl#define OSSA_ERR_DEVICE_NEW_STATE_INVALID 0x1025 1247285809Sscottl#define OSSA_ERR_DEVICE_STATE_CHANGE_NOT_ALLOWED 0x1026 1248285809Sscottl#define OSSA_ERR_DEVICE_STATE_INVALID 0x0049 1249285809Sscottl 1250285809Sscottl/* status of ossaSASDiagExecuteCB() */ 1251285809Sscottl#define OSSA_DIAG_SUCCESS 0x00 /* Successful SAS diagnostic command. */ 1252285809Sscottl#define OSSA_DIAG_INVALID_COMMAND 0x01 /* Invalid SAS diagnostic command. */ 1253285809Sscottl#define OSSA_REGISTER_ACCESS_TIMEOUT 0x02 /* Register access has been timed-out. This is applicable only to the SPCv controller. */ 1254285809Sscottl#define OSSA_DIAG_FAIL 0x02 /* SAS diagnostic command failed. This is applicable only to the SPC controller. */ 1255285809Sscottl#define OSSA_DIAG_NOT_IN_DIAGNOSTIC_MODE 0x03 /* Attempted to execute SAS diagnostic command but PHY is not in diagnostic mode */ 1256285809Sscottl#define OSSA_DIAG_INVALID_PHY 0x04 /* Attempted to execute SAS diagnostic command on an invalid/out-of-range PHY. */ 1257285809Sscottl#define OSSA_MEMORY_ALLOC_FAILURE 0x05 /* Memory allocation failed in diagnostic. This is applicable only to the SPCv controller. */ 1258285809Sscottl 1259285809Sscottl 1260285809Sscottl/* status of ossaSASDiagStartEndCB() */ 1261285809Sscottl#define OSSA_DIAG_SE_SUCCESS 0x00 1262285809Sscottl#define OSSA_DIAG_SE_INVALID_PHY_ID 0x01 1263285809Sscottl#define OSSA_DIAG_PHY_NOT_DISABLED 0x02 1264285809Sscottl#define OSSA_DIAG_OTHER_FAILURE 0x03 /* SPC */ 1265285809Sscottl#define OSSA_DIAG_OPCODE_INVALID 0x03 1266285809Sscottl 1267285809Sscottl/* status of ossaPortControlCB() */ 1268285809Sscottl#define OSSA_PORT_CONTROL_FAILURE 0x03 1269285809Sscottl 1270285809Sscottl#define OSSA_MPI_ERR_PORT_IO_RESOURCE_UNAVAILABLE 0x1004 1271285809Sscottl#define OSSA_MPI_ERR_PORT_INVALID 0x1041 /**/ 1272285809Sscottl#define OSSA_MPI_ERR_PORT_OP_NOT_IN_USE 0x1043 /**/ 1273285809Sscottl#define OSSA_MPI_ERR_PORT_OP_NOT_SUPPORTED 0x1044 /**/ 1274285809Sscottl#define OSSA_MPI_ERR_PORT_SMP_WIDTH_EXCEEDED 0x1045 /**/ 1275285809Sscottl#define OSSA_MPI_ERR_PORT_NOT_IN_CORRECT_STATE 0x1047 /**/ 1276285809Sscottl 1277285809Sscottl/*regDumpNum of agsaRegDumpInfo_t */ 1278285809Sscottl#define GET_GSM_SM_INFO 0x02 1279285809Sscottl#define GET_IOST_RB_INFO 0x03 1280285809Sscottl 1281285809Sscottl/************************************************************************************ 1282285809Sscottl * HW Events 1283285809Sscottl ************************************************************************************/ 1284285809Sscottl#define OSSA_HW_EVENT_RESET_START 0x01 /**< flag indicates reset started event */ 1285285809Sscottl#define OSSA_HW_EVENT_RESET_COMPLETE 0x02 /**< flag indicates chip reset completed event */ 1286285809Sscottl#define OSSA_HW_EVENT_PHY_STOP_STATUS 0x03 /**< flag indicates phy stop event status */ 1287285809Sscottl#define OSSA_HW_EVENT_SAS_PHY_UP 0x04 /**< flag indicates SAS link up event */ 1288285809Sscottl#define OSSA_HW_EVENT_SATA_PHY_UP 0x05 /**< flag indicates SATA link up event */ 1289285809Sscottl#define OSSA_HW_EVENT_SATA_SPINUP_HOLD 0x06 /**< flag indicates SATA spinup hold event */ 1290285809Sscottl#define OSSA_HW_EVENT_PHY_DOWN 0x07 /**< flag indicates link down event */ 1291285809Sscottl 1292285809Sscottl#define OSSA_HW_EVENT_BROADCAST_CHANGE 0x09 /**< flag indicates broadcast change event */ 1293285809Sscottl/* not used spcv 0x0A*/ 1294285809Sscottl#define OSSA_HW_EVENT_PHY_ERROR 0x0A /**< flag indicates link error event */ 1295285809Sscottl#define OSSA_HW_EVENT_BROADCAST_SES 0x0B /**< flag indicates broadcast change (SES) event */ 1296285809Sscottl#define OSSA_HW_EVENT_PHY_ERR_INBOUND_CRC 0x0C 1297285809Sscottl#define OSSA_HW_EVENT_HARD_RESET_RECEIVED 0x0D /**< flag indicates hardware reset received event */ 1298285809Sscottl/* not used spcv 0x0E*/ 1299285809Sscottl#define OSSA_HW_EVENT_MALFUNCTION 0x0E /**< flag indicates unrecoverable Error */ 1300285809Sscottl#define OSSA_HW_EVENT_ID_FRAME_TIMEOUT 0x0F /**< flag indicates ID Frame Timeout event */ 1301285809Sscottl#define OSSA_HW_EVENT_BROADCAST_EXP 0x10 /**< flag indicates broadcast (EXPANDER) event */ 1302285809Sscottl/* not used spcv 0x11*/ 1303285809Sscottl#define OSSA_HW_EVENT_PHY_START_STATUS 0x11 /**< flag indicates phy start event status */ 1304285809Sscottl#define OSSA_HW_EVENT_PHY_ERR_INVALID_DWORD 0x12 /**< flag indicates Link error invalid DWORD */ 1305285809Sscottl#define OSSA_HW_EVENT_PHY_ERR_DISPARITY_ERROR 0x13 /**< flag indicates Phy error disparity */ 1306285809Sscottl#define OSSA_HW_EVENT_PHY_ERR_CODE_VIOLATION 0x14 /**< flag indicates Phy error code violation */ 1307285809Sscottl#define OSSA_HW_EVENT_PHY_ERR_LOSS_OF_DWORD_SYNCH 0x15 /**< flag indicates Link error loss of DWORD synch */ 1308285809Sscottl#define OSSA_HW_EVENT_PHY_ERR_PHY_RESET_FAILED 0x16 /**< flag indicates Link error phy reset failed */ 1309285809Sscottl#define OSSA_HW_EVENT_PORT_RECOVERY_TIMER_TMO 0x17 /**< flag indicates Port Recovery timeout */ 1310285809Sscottl#define OSSA_HW_EVENT_PORT_RECOVER 0x18 /**< flag indicates Port Recovery */ 1311285809Sscottl#define OSSA_HW_EVENT_PORT_RESET_TIMER_TMO 0x19 /**< flag indicates Port Reset Timer out */ 1312285809Sscottl#define OSSA_HW_EVENT_PORT_RESET_COMPLETE 0x20 /**< flag indicates Port Reset Complete */ 1313285809Sscottl#define OSSA_HW_EVENT_BROADCAST_ASYNCH_EVENT 0x21 /**< flag indicates Broadcast Asynch Event */ 1314285809Sscottl#define OSSA_HW_EVENT_IT_NEXUS_LOSS 0x22 /**< Custom: H/W event for IT Nexus Loss */ 1315285809Sscottl 1316285809Sscottl#define OSSA_HW_EVENT_OPEN_RETRY_BACKOFF_THR_ADJUSTED 0x25 1317285809Sscottl 1318285809Sscottl#define OSSA_HW_EVENT_ENCRYPTION 0x83 /**< TSDK internal flag indicating that an encryption event occurred */ 1319285809Sscottl#define OSSA_HW_EVENT_MODE 0x84 /**< TSDK internal flag indicating that a controller mode page operation completed */ 1320285809Sscottl#define OSSA_HW_EVENT_SECURITY_MODE 0x85 /**< TSDK internal flag indicating that saEncryptSetMode() completed */ 1321285809Sscottl 1322285809Sscottl 1323285809Sscottl/* port state */ 1324285809Sscottl#define OSSA_PORT_NOT_ESTABLISHED 0x00 /**< flag indicates port is not established */ 1325285809Sscottl#define OSSA_PORT_VALID 0x01 /**< flag indicates port valid */ 1326285809Sscottl#define OSSA_PORT_LOSTCOMM 0x02 /**< flag indicates port lost communication */ 1327285809Sscottl#define OSSA_PORT_IN_RESET 0x04 /**< flag indicates port in reset state */ 1328285809Sscottl#define OSSA_PORT_3RDPARTY_RESET 0x07 /**< flag indicates port in 3rd party reset state */ 1329285809Sscottl#define OSSA_PORT_INVALID 0x08 /**< flag indicates port invalid */ 1330285809Sscottl 1331285809Sscottl/* status for agsaHWEventMode_t */ 1332285809Sscottl#define OSSA_CTL_SUCCESS 0x0000 1333285809Sscottl#define OSSA_CTL_INVALID_CONFIG_PAGE 0x1001 1334285809Sscottl#define OSSA_CTL_INVALID_PARAM_IN_CONFIG_PAGE 0x1002 1335285809Sscottl#define OSSA_CTL_INVALID_ENCRYPTION_SECURITY_MODE 0x1003 1336285809Sscottl#define OSSA_CTL_RESOURCE_NOT_AVAILABLE 0x1004 1337285809Sscottl#define OSSA_CTL_CONTROLLER_NOT_IDLE 0x1005 1338285809Sscottl// #define OSSA_CTL_NVM_MEMORY_ACCESS_ERR 0x100B 1339285809Sscottl#define OSSA_CTL_OPERATOR_AUTHENTICATION_FAILURE 0x100XX 1340285809Sscottl 1341285809Sscottl 1342285809Sscottl 1343285809Sscottl/************************************************************************************ 1344285809Sscottl * General Events value 1345285809Sscottl ************************************************************************************/ 1346285809Sscottl#define OSSA_INBOUND_V_BIT_NOT_SET 0x01 1347285809Sscottl#define OSSA_INBOUND_OPC_NOT_SUPPORTED 0x02 1348285809Sscottl#define OSSA_INBOUND_IOMB_INVALID_OBID 0x03 1349285809Sscottl 1350285809Sscottl/************************************************************************************ 1351285809Sscottl * FW Flash Update status values 1352285809Sscottl ************************************************************************************/ 1353285809Sscottl#define OSSA_FLASH_UPDATE_COMPLETE_PENDING_REBOOT 0x00 /**< flag indicates fw flash update completed */ 1354285809Sscottl#define OSSA_FLASH_UPDATE_IN_PROGRESS 0x01 /**< flag indicates fw flash update in progress */ 1355285809Sscottl#define OSSA_FLASH_UPDATE_HDR_ERR 0x02 /**< flag indicates fw flash header error */ 1356285809Sscottl#define OSSA_FLASH_UPDATE_OFFSET_ERR 0x03 /**< flag indicates fw flash offset error */ 1357285809Sscottl#define OSSA_FLASH_UPDATE_CRC_ERR 0x04 /**< flag indicates fw flash CRC error */ 1358285809Sscottl#define OSSA_FLASH_UPDATE_LENGTH_ERR 0x05 /**< flag indicates fw flash length error */ 1359285809Sscottl#define OSSA_FLASH_UPDATE_HW_ERR 0x06 /**< flag indicates fw flash HW error */ 1360285809Sscottl#define OSSA_FLASH_UPDATE_HMAC_ERR 0x0E /**< flag indicates fw flash Firmware image HMAC authentication failure.*/ 1361285809Sscottl 1362285809Sscottl#define OSSA_FLASH_UPDATE_DNLD_NOT_SUPPORTED 0x10 /**< flag indicates fw flash down load not supported */ 1363285809Sscottl#define OSSA_FLASH_UPDATE_DISABLED 0x11 /**< flag indicates fw flash Update disabled */ 1364285809Sscottl#define OSSA_FLASH_FWDNLD_DEVICE_UNSUPPORT 0x12 /**< flag indicates fw flash Update disabled */ 1365285809Sscottl 1366285809Sscottl/************************************************************************************ 1367285809Sscottl* Discovery status values 1368285809Sscottl************************************************************************************/ 1369285809Sscottl#define OSSA_DISCOVER_STARTED 0x00 /**< flag indicates discover started */ 1370285809Sscottl#define OSSA_DISCOVER_FOUND_DEVICE 0x01 /**< flag indicates discovery found a new device */ 1371285809Sscottl#define OSSA_DISCOVER_REMOVED_DEVICE 0x02 /**< flag indicates discovery found a device removed */ 1372285809Sscottl#define OSSA_DISCOVER_COMPLETE 0x03 /**< flag indicates discover completed */ 1373285809Sscottl#define OSSA_DISCOVER_ABORT 0x04 /**< flag indicates discover error12 */ 1374285809Sscottl#define OSSA_DISCOVER_ABORT_ERROR_1 0x05 /**< flag indicates discover error1 */ 1375285809Sscottl#define OSSA_DISCOVER_ABORT_ERROR_2 0x06 /**< flag indicates discover error2 */ 1376285809Sscottl#define OSSA_DISCOVER_ABORT_ERROR_3 0x07 /**< flag indicates discover error3 */ 1377285809Sscottl#define OSSA_DISCOVER_ABORT_ERROR_4 0x08 /**< flag indicates discover error4 */ 1378285809Sscottl#define OSSA_DISCOVER_ABORT_ERROR_5 0x09 /**< flag indicates discover error5 */ 1379285809Sscottl#define OSSA_DISCOVER_ABORT_ERROR_6 0x0A /**< flag indicates discover error6 */ 1380285809Sscottl#define OSSA_DISCOVER_ABORT_ERROR_7 0x0B /**< flag indicates discover error7 */ 1381285809Sscottl#define OSSA_DISCOVER_ABORT_ERROR_8 0x0C /**< flag indicates discover error8 */ 1382285809Sscottl#define OSSA_DISCOVER_ABORT_ERROR_9 0x0D /**< flag indicates discover error9 */ 1383285809Sscottl 1384285809Sscottl/*********************************************************************************** 1385285809Sscottl * Log Debug Levels 1386285809Sscottl ***********************************************************************************/ 1387285809Sscottl#define OSSA_DEBUG_LEVEL_0 0x00 /**< debug level 0 */ 1388285809Sscottl#define OSSA_DEBUG_LEVEL_1 0x01 /**< debug level 1 */ 1389285809Sscottl#define OSSA_DEBUG_LEVEL_2 0x02 /**< debug level 2 */ 1390285809Sscottl#define OSSA_DEBUG_LEVEL_3 0x03 /**< debug level 3 */ 1391285809Sscottl#define OSSA_DEBUG_LEVEL_4 0x04 /**< debug level 4 */ 1392285809Sscottl 1393285809Sscottl#define OSSA_DEBUG_PRINT_INVALID_NUMBER 0xFFFFFFFF /**< the number won't be printed by OS layer */ 1394285809Sscottl 1395285809Sscottl#define OSSA_FRAME_TYPE_SSP_CMD 0x06 /**< flag indicates received frame is SSP command */ 1396285809Sscottl#define OSSA_FRAME_TYPE_SSP_TASK 0x16 /**< flag indicates received frame is SSP task management */ 1397285809Sscottl 1398285809Sscottl/* Event Source Type of saRegisterEventCallback() */ 1399285809Sscottl#define OSSA_EVENT_SOURCE_DEVICE_HANDLE_ADDED 0x00 1400285809Sscottl#define OSSA_EVENT_SOURCE_DEVICE_HANDLE_REMOVED 0x01 1401285809Sscottl 1402285809Sscottl/* Status of Get Device Info CB */ 1403285809Sscottl#define OSSA_DEV_INFO_INVALID_HANDLE 0x01 1404285809Sscottl#define OSSA_DEV_INFO_NO_EXTENDED_INFO 0x02 1405285809Sscottl#define OSSA_DEV_INFO_SAS_EXTENDED_INFO 0x03 1406285809Sscottl#define OSSA_DEV_INFO_SATA_EXTENDED_INFO 0x04 1407285809Sscottl 1408285809Sscottl/* Diagnostic Command Type */ 1409285809Sscottl#define AGSA_CMD_TYPE_DIAG_OPRN_PERFORM 0x00 1410285809Sscottl#define AGSA_CMD_TYPE_DIAG_OPRN_STOP 0x01 1411285809Sscottl#define AGSA_CMD_TYPE_DIAG_THRESHOLD_SPECIFY 0x02 1412285809Sscottl#define AGSA_CMD_TYPE_DIAG_RECEIVE_ENABLE 0x03 1413285809Sscottl#define AGSA_CMD_TYPE_DIAG_REPORT_GET 0x04 1414285809Sscottl#define AGSA_CMD_TYPE_DIAG_ERR_CNT_RESET 0x05 1415285809Sscottl 1416285809Sscottl/* Command Description for CMD_TYPE DIAG_OPRN_PERFORM, DIAG_OPRN_STOP, THRESHOLD_SPECIFY */ 1417285809Sscottl#define AGSA_CMD_DESC_PRBS 0x00 1418285809Sscottl#define AGSA_CMD_DESC_CJTPAT 0x01 1419285809Sscottl#define AGSA_CMD_DESC_USR_PATTERNS 0x02 1420285809Sscottl#define AGSA_CMD_DESC_PRBS_ERR_INSERT 0x08 1421285809Sscottl#define AGSA_CMD_DESC_PRBS_INVERT 0x09 1422285809Sscottl#define AGSA_CMD_DESC_CJTPAT_INVERT 0x0A 1423285809Sscottl#define AGSA_CMD_DESC_CODE_VIOL_INSERT 0x0B 1424285809Sscottl#define AGSA_CMD_DESC_DISP_ERR_INSERT 0x0C 1425285809Sscottl#define AGSA_CMD_DESC_SSPA_PERF_EVENT_1 0x0E 1426285809Sscottl#define AGSA_CMD_DESC_LINE_SIDE_ANA_LPBK 0x10 1427285809Sscottl#define AGSA_CMD_DESC_LINE_SIDE_DIG_LPBK 0x11 1428285809Sscottl#define AGSA_CMD_DESC_SYS_SIDE_ANA_LPBK 0x12 1429285809Sscottl 1430285809Sscottl/* Command Description for CMD_TYPE DIAG_REPORT_GET and ERR_CNT_RESET */ 1431285809Sscottl#define AGSA_CMD_DESC_PRBS_ERR_CNT 0x00 1432285809Sscottl#define AGSA_CMD_DESC_CODE_VIOL_ERR_CNT 0x01 1433285809Sscottl#define AGSA_CMD_DESC_DISP_ERR_CNT 0x02 1434285809Sscottl#define AGSA_CMD_DESC_LOST_DWD_SYNC_CNT 0x05 1435285809Sscottl#define AGSA_CMD_DESC_INVALID_DWD_CNT 0x06 1436285809Sscottl#define AGSA_CMD_DESC_CODE_VIOL_ERR_CNT_THHD 0x09 1437285809Sscottl#define AGSA_CMD_DESC_DISP_ERR_CNT_THHD 0x0A 1438285809Sscottl#define AGSA_CMD_DESC_SSPA_PERF_CNT 0x0B 1439285809Sscottl#define AGSA_CMD_DESC_PHY_RST_CNT 0x0C 1440285809Sscottl#define AGSA_CMD_DESC_SSPA_PERF_1_THRESHOLD 0x0E 1441285809Sscottl 1442285809Sscottl#define AGSA_CMD_DESC_CODE_VIOL_ERR_THHD 0x19 1443285809Sscottl#define AGSA_CMD_DESC_DISP_ERR_THHD 0x1A 1444285809Sscottl#define AGSA_CMD_DESC_RX_LINK_BANDWIDTH 0x1B 1445285809Sscottl#define AGSA_CMD_DESC_TX_LINK_BANDWIDTH 0x1C 1446285809Sscottl#define AGSA_CMD_DESC_ALL 0x1F 1447285809Sscottl 1448285809Sscottl/* NVMDevice type */ 1449285809Sscottl#define AGSA_NVMD_TWI_DEVICES 0x00 1450285809Sscottl#define AGSA_NVMD_CONFIG_SEEPROM 0x01 1451285809Sscottl#define AGSA_NVMD_VPD_FLASH 0x04 1452285809Sscottl#define AGSA_NVMD_AAP1_REG_FLASH 0x05 1453285809Sscottl#define AGSA_NVMD_IOP_REG_FLASH 0x06 1454285809Sscottl#define AGSA_NVMD_EXPANSION_ROM 0x07 1455285809Sscottl#define AGSA_NVMD_REG_FLASH 0x05 1456285809Sscottl 1457285809Sscottl 1458285809Sscottl/* GET/SET NVMD Data Response errors */ 1459285809Sscottl#define OSSA_NVMD_SUCCESS 0x0000 1460285809Sscottl#define OSSA_NVMD_MODE_ERROR 0x0001 1461285809Sscottl#define OSSA_NVMD_LENGTH_ERROR 0x0002 1462285809Sscottl#define OSSA_NVMD_TWI_ADDRESS_SIZE_ERROR 0x0005 1463285809Sscottl#define OSSA_NVMD_TWI_NACK_ERROR 0x2001 1464285809Sscottl#define OSSA_NVMD_TWI_LOST_ARB_ERROR 0x2002 1465285809Sscottl#define OSSA_NVMD_TWI_TIMEOUT_ERROR 0x2021 1466285809Sscottl#define OSSA_NVMD_TWI_BUS_NACK_ERROR 0x2081 1467285809Sscottl#define OSSA_NVMD_TWI_ARB_FAILED_ERROR 0x2082 1468285809Sscottl#define OSSA_NVMD_TWI_BUS_TIMEOUT_ERROR 0x20FF 1469285809Sscottl#define OSSA_NVMD_FLASH_PARTITION_NUM_ERROR 0x9001 1470285809Sscottl#define OSSA_NVMD_FLASH_LENGTH_TOOBIG_ERROR 0x9002 1471285809Sscottl#define OSSA_NVMD_FLASH_PROGRAM_ERROR 0x9003 1472285809Sscottl#define OSSA_NVMD_FLASH_DEVICEID_ERROR 0x9004 1473285809Sscottl#define OSSA_NVMD_FLASH_VENDORID_ERROR 0x9005 1474285809Sscottl#define OSSA_NVMD_FLASH_ERASE_TIMEOUT_ERROR 0x9006 1475285809Sscottl#define OSSA_NVMD_FLASH_ERASE_ERROR 0x9007 1476285809Sscottl#define OSSA_NVMD_FLASH_BUSY_ERROR 0x9008 1477285809Sscottl#define OSSA_NVMD_FLASH_NOT_SUPPORT_DEVICE_ERROR 0x9009 1478285809Sscottl#define OSSA_NVMD_FLASH_CFI_INF_ERROR 0x900A 1479285809Sscottl#define OSSA_NVMD_FLASH_MORE_ERASE_BLOCK_ERROR 0x900B 1480285809Sscottl#define OSSA_NVMD_FLASH_READ_ONLY_ERROR 0x900C 1481285809Sscottl#define OSSA_NVMD_FLASH_MAP_TYPE_ERROR 0x900D 1482285809Sscottl#define OSSA_NVMD_FLASH_MAP_DISABLE_ERROR 0x900E 1483285809Sscottl 1484285809Sscottl/************************************************************ 1485285809Sscottl* ossaHwCB Encryption encryptOperation of agsaHWEventEncrypt_t 1486285809Sscottl************************************************************/ 1487285809Sscottl#define OSSA_HW_ENCRYPT_KEK_UPDATE 0x0000 1488285809Sscottl#define OSSA_HW_ENCRYPT_KEK_UPDATE_AND_STORE 0x0001 1489285809Sscottl#define OSSA_HW_ENCRYPT_KEK_INVALIDTE 0x0002 1490285809Sscottl#define OSSA_HW_ENCRYPT_DEK_UPDATE 0x0003 1491285809Sscottl#define OSSA_HW_ENCRYPT_DEK_INVALIDTE 0x0004 1492285809Sscottl#define OSSA_HW_ENCRYPT_OPERATOR_MANAGEMENT 0x0005 1493285809Sscottl#define OSSA_HW_ENCRYPT_TEST_EXECUTE 0x0006 1494285809Sscottl#define OSSA_HW_ENCRYPT_SET_OPERATOR 0x0007 1495285809Sscottl#define OSSA_HW_ENCRYPT_GET_OPERATOR 0x0008 1496285809Sscottl 1497285809Sscottl 1498285809Sscottl/************************************************************ 1499285809Sscottl* ossaHwCB Encryption status of agsaHWEventEncrypt_t 1500285809Sscottl************************************************************/ 1501285809Sscottl/* KEK and DEK managment status from PM */ 1502285809Sscottl#define OSSA_INVALID_ENCRYPTION_SECURITY_MODE 0x1003 1503285809Sscottl#define OSSA_KEK_MGMT_SUBOP_NOT_SUPPORTED_ 0x2000 /*not in PM 101222*/ 1504285809Sscottl#define OSSA_DEK_MGMT_SUBOP_NOT_SUPPORTED 0x2000 1505285809Sscottl#define OSSA_MPI_ENC_ERR_ILLEGAL_DEK_PARAM 0x2001 1506285809Sscottl#define OSSA_MPI_ERR_DEK_MANAGEMENT_DEK_UNWRAP_FAIL 0x2002 1507285809Sscottl#define OSSA_MPI_ENC_ERR_ILLEGAL_KEK_PARAM 0x2021 1508285809Sscottl#define OSSA_MPI_ERR_KEK_MANAGEMENT_KEK_UNWRAP_FAIL 0x2022 1509285809Sscottl#define OSSA_MPI_ERR_KEK_MANAGEMENT_NVRAM_OPERATION_FAIL 0x2023 1510285809Sscottl 1511285809Sscottl/*encrypt operator management response status */ 1512285809Sscottl#define OSSA_OPR_MGMT_OP_NOT_SUPPORTED 0x2060 1513285809Sscottl#define OSSA_MPI_ENC_ERR_OPR_PARAM_ILLEGAL 0x2061 1514285809Sscottl#define OSSA_MPI_ENC_ERR_OPR_ID_NOT_FOUND 0x2062 1515285809Sscottl#define OSSA_MPI_ENC_ERR_OPR_ROLE_NOT_MATCH 0x2063 1516285809Sscottl#define OSSA_MPI_ENC_ERR_OPR_MAX_NUM_EXCEEDED 0x2064 1517285809Sscottl 1518285809Sscottl/*encrypt saSetOperator() response status */ 1519285809Sscottl#define OSSA_MPI_ENC_ERR_CONTROLLER_NOT_IDLE 0x1005 1520285809Sscottl#define OSSA_MPI_ENC_NVM_MEM_ACCESS_ERR 0x100B 1521285809Sscottl 1522285809Sscottl/* agsaEncryptSMX | agsaEncryptCipherMode == cipherMode for saEncryptSetMode()*/ 1523285809Sscottl/* Make sure all definitions are unique bits */ 1524285809Sscottl#define agsaEncryptSMF 0x00000000 1525285809Sscottl#define agsaEncryptSMA 0x00000100 1526285809Sscottl#define agsaEncryptSMB 0x00000200 1527285809Sscottl#define agsaEncryptReturnSMF (1 << 12) 1528285809Sscottl#define agsaEncryptAuthorize (1 << 13) 1529285809Sscottl 1530285809Sscottl/* 1531285809SscottlBits 16-23: Allowable Cipher Mode(ACM) 1532285809SscottlBit 16: Enable AES ECB. If set to 1, AES ECB is enable. If set to 0, AES ECB is disabled. 1533285809SscottlBit 22: Enable AES XTS. If set to 1, AES XTS is enable. If set to 0, AES XTS is disabled. 1534285809Sscottl*/ 1535285809Sscottl#define agsaEncryptAcmMask 0x00ff0000 1536285809Sscottl#define agsaEncryptEnableAES_ECB (1 << 16) 1537285809Sscottl#define agsaEncryptEnableAES_XTS (1 << 22) 1538285809Sscottl 1539285809Sscottl 1540285809Sscottl 1541285809Sscottl#define agsaEncryptCipherModeECB 0x00000001 1542285809Sscottl#define agsaEncryptCipherModeXTS 0x00000002 1543285809Sscottl 1544285809Sscottl 1545285809Sscottl 1546285809Sscottl#define agsaEncryptStatusNoNVRAM 0x00000001 1547285809Sscottl#define agsaEncryptStatusNVRAMErr 0x00000002 1548285809Sscottl 1549285809Sscottl/* 1550285809Sscottl 1551285809SscottlBin Hex Sector Total 1552285809Sscottl00000 :0x0 512B 512 1553285809Sscottl11000 :0x1 520B 520 1554285809Sscottl00010 :0x2 4K 4096 1555285809Sscottl00011 :0x3 4K+64B 4160 1556285809Sscottl00100 :0x4 4K+128B 4224 1557285809Sscottl 1558285809Sscottl11000 :0x18 512+8B 520 1559285809Sscottl11001 :0x19 520+8B 528 1560285809Sscottl11010 :0x1A 4K+8B 4104 1561285809Sscottl11011 :0x1B 4K+64B+8B 4168 1562285809Sscottl11100 :0x1C 4K+128B+8B 4232 1563285809Sscottl 1564285809Sscottl*/ 1565285809Sscottl 1566285809Sscottl#define agsaEncryptSectorSize512 0 1567285809Sscottl/* define agsaEncryptSectorSize520 1 Not supported */ 1568285809Sscottl#define agsaEncryptSectorSize4096 2 1569285809Sscottl#define agsaEncryptSectorSize4160 3 1570285809Sscottl#define agsaEncryptSectorSize4224 4 1571285809Sscottl 1572285809Sscottl#define agsaEncryptDIFSectorSize520 (agsaEncryptSectorSize512 | 0x18) 1573285809Sscottl#define agsaEncryptDIFSectorSize528 ( 0x19) 1574285809Sscottl#define agsaEncryptDIFSectorSize4104 (agsaEncryptSectorSize4096 | 0x18) 1575285809Sscottl#define agsaEncryptDIFSectorSize4168 (agsaEncryptSectorSize4160 | 0x18) 1576285809Sscottl#define agsaEncryptDIFSectorSize4232 (agsaEncryptSectorSize4224 | 0x18) 1577285809Sscottl 1578285809Sscottl 1579285809Sscottl#define AGSA_ENCRYPT_STORE_NVRAM 1 1580285809Sscottl 1581285809Sscottl/************************************************************ 1582285809Sscottl* ossaHwCB Mode page event definitions 1583285809Sscottl************************************************************/ 1584285809Sscottl#define agsaModePageGet 1 1585285809Sscottl#define agsaModePageSet 2 1586285809Sscottl 1587285809Sscottl/************************************************************ 1588285809Sscottl* saSgpio() SGPIO Function and Register type 1589285809Sscottl************************************************************/ 1590285809Sscottl#define AGSA_READ_SGPIO_REGISTER 0x02 1591285809Sscottl#define AGSA_WRITE_SGPIO_REGISTER 0x82 1592285809Sscottl 1593285809Sscottl#define AGSA_SGPIO_CONFIG_REG 0x0 1594285809Sscottl#define AGSA_SGPIO_DRIVE_BY_DRIVE_RECEIVE_REG 0x1 1595285809Sscottl#define AGSA_SGPIO_GENERAL_PURPOSE_RECEIVE_REG 0x2 1596285809Sscottl#define AGSA_SGPIO_DRIVE_BY_DRIVE_TRANSMIT_REG 0x3 1597285809Sscottl#define AGSA_SGPIO_GENERAL_PURPOSE_TRANSMIT_REG 0x4 1598285809Sscottl 1599285809Sscottl/************************************************************ 1600285809Sscottl* ossaSGpioCB() Function result 1601285809Sscottl************************************************************/ 1602285809Sscottl#define OSSA_SGPIO_COMMAND_SUCCESS 0x00 1603285809Sscottl#define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_TYPE 0x01 1604285809Sscottl#define OSSA_SGPIO_CMD_ERROR_WRONG_REG_TYPE 0x02 1605285809Sscottl#define OSSA_SGPIO_CMD_ERROR_WRONG_REG_INDEX 0x03 1606285809Sscottl#define OSSA_SGPIO_CMD_ERROR_WRONG_REG_COUNT 0x04 1607285809Sscottl#define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_REG_TYPE 0x05 1608285809Sscottl#define OSSA_SGPIO_CMD_ERROR_WRONG_FUNCTION 0x06 1609285809Sscottl#define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_TYPE_REG_INDEX 0x19 1610285809Sscottl#define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_TYPE_REG_CNT 0x81 1611285809Sscottl#define OSSA_SGPIO_CMD_ERROR_WRONG_REG_TYPE_REG_INDEX 0x1A 1612285809Sscottl#define OSSA_SGPIO_CMD_ERROR_WRONG_REG_TYPE_REG_COUNT 0x82 1613285809Sscottl#define OSSA_SGPIO_CMD_ERROR_WRONG_REG_INDEX_REG_COUNT 0x83 1614285809Sscottl#define OSSA_SGPIO_CMD_ERROR_WRONG_FRAME_REG_TYPE_REG_INDEX 0x1D 1615285809Sscottl#define OSSA_SGPIO_CMD_ERROR_WRONG_ALL_HEADER_PARAMS 0x9D 1616285809Sscottl 1617285809Sscottl#define OSSA_SGPIO_MAX_READ_DATA_COUNT 0x0D 1618285809Sscottl#define OSSA_SGPIO_MAX_WRITE_DATA_COUNT 0x0C 1619285809Sscottl 1620285809Sscottl/************************************************************ 1621285809Sscottl* ossaGetDFEDataCB() status 1622285809Sscottl************************************************************/ 1623285809Sscottl#define OSSA_DFE_MPI_IO_SUCCESS 0x0000 1624285809Sscottl#define OSSA_DFE_DATA_OVERFLOW 0x0002 1625285809Sscottl#define OSSA_DFE_MPI_ERR_RESOURCE_UNAVAILABLE 0x1004 1626285809Sscottl#define OSSA_DFE_CHANNEL_DOWN 0x100E 1627285809Sscottl#define OSSA_DFE_MEASUREMENT_IN_PROGRESS 0x100F 1628285809Sscottl#define OSSA_DFE_CHANNEL_INVALID 0x1010 1629285809Sscottl#define OSSA_DFE_DMA_FAILURE 0x1011 1630285809Sscottl 1631285809Sscottl/************************************************************************************ 1632285809Sscottl * * 1633285809Sscottl * Constants defined for OS Layer ends * 1634285809Sscottl * * 1635285809Sscottl ************************************************************************************/ 1636285809Sscottl 1637285809Sscottl/************************************************************************************ 1638285809Sscottl * * 1639285809Sscottl * Data Structures Defined for LL API start * 1640285809Sscottl * * 1641285809Sscottl ************************************************************************************/ 1642285809Sscottl/** \brief data structure stores OS specific and LL specific context 1643285809Sscottl * 1644285809Sscottl * The agsaContext_t data structure contains two generic pointers, 1645285809Sscottl * also known as handles, which are used to store OS Layer-specific and 1646285809Sscottl * LL Layer-specific contexts. Only the handle specific to a layer can 1647285809Sscottl * be modified by the layer. The other layer's handle must be returned 1648285809Sscottl * unmodified when communicating between the layers. 1649285809Sscottl 1650285809Sscottl * A layer's handle is typically typecast to an instance of a layer-specific 1651285809Sscottl * data structure. The layer can use its handle to point to any data type 1652285809Sscottl * that is to be associated with a function call. A handle provides a way 1653285809Sscottl * to uniquely identify responses when multiple calls to the same function 1654285809Sscottl * are necessary. 1655285809Sscottl * 1656285809Sscottl */ 1657285809Sscottltypedef struct agsaContext_s 1658285809Sscottl{ 1659285809Sscottl void *osData; /**< Pointer-sized value used internally by the OS Layer */ 1660285809Sscottl void *sdkData; /**< Pointer-sized value used internally by the LL Layer */ 1661285809Sscottl} agsaContext_t; 1662285809Sscottl 1663285809Sscottl/** \brief hold points to global data strutures used by the LL and OS Layers 1664285809Sscottl * 1665285809Sscottl * The agsaRoot_t data structure is used to hold pointer-sized values for 1666285809Sscottl * internal use by the LL and OS Layers. It is intended that the 1667285809Sscottl * sdkData element of the agsaRoot_t data structure be used to 1668285809Sscottl * identify an instance of the hardware context. The sdkData 1669285809Sscottl * element is set by the LL Layer in the saHwInitialize() 1670285809Sscottl * function and returned to the OS Layer in the agsaRoot_t data 1671285809Sscottl * structure 1672285809Sscottl */ 1673285809Sscottltypedef agsaContext_t agsaRoot_t; 1674285809Sscottl 1675285809Sscottl/** \brief holds the pointers to the device data structure used by the LL and OS Layers 1676285809Sscottl * 1677285809Sscottl * The agsaDevHandle_t data structure is the device instance handle. 1678285809Sscottl * It holds pointer-sized values used internally by each of the LL and 1679285809Sscottl * OS Layers. It is intended that the agsaDevHandle_t data 1680285809Sscottl * structure be used to identify a specific device instance. A 1681285809Sscottl * device instance is uniquely identified by its device handle. 1682285809Sscottl */ 1683285809Sscottltypedef agsaContext_t agsaDevHandle_t; 1684285809Sscottl 1685285809Sscottl/** \brief holds the pointers to the port data structure used by the LL and 1686285809Sscottl * OS Layers 1687285809Sscottl * 1688285809Sscottl * The agsaPortContext_t data structure is used to describe an instance of 1689285809Sscottl * SAS port or SATA port. It holds pointer-sized values used 1690285809Sscottl * internally by each of the LL and OS Layers. 1691285809Sscottl * 1692285809Sscottl * When connected to other SAS end-devices or expanders, each instance of 1693285809Sscottl * agsaPortContext_t represents a SAS local narrow-port or 1694285809Sscottl * wide-port. 1695285809Sscottl * 1696285809Sscottl * When connected to SATA device, each instance of agsaPortContext_t 1697285809Sscottl * represents a local SATA port. 1698285809Sscottl * 1699285809Sscottl */ 1700285809Sscottltypedef agsaContext_t agsaPortContext_t; 1701285809Sscottl 1702285809Sscottl/** \brief data structure pointer to IO request structure 1703285809Sscottl * 1704285809Sscottl * It is intended that the agsaIORequest_t structure be used to 1705285809Sscottl * uniquely identify each I/O Request for either target or 1706285809Sscottl * initiator. The OS Layer is responsible for allocating and 1707285809Sscottl * managing agsaIORequest_t structures. The LL Layer uses each 1708285809Sscottl * structure only between calls to: saSSPStart() and 1709285809Sscottl * ossaSSPCompleted(), saSATAStart() and ossaSATACompleted(), 1710285809Sscottl * saSMPStart() and ossaSMPCompleted() 1711285809Sscottl * 1712285809Sscottl */ 1713285809Sscottltypedef agsaContext_t agsaIORequest_t; 1714285809Sscottl 1715285809Sscottl/** \brief handle to access frame 1716285809Sscottl * 1717285809Sscottl * This data structure is the handle to access frame 1718285809Sscottl */ 1719285809Sscottltypedef void *agsaFrameHandle_t; 1720285809Sscottl 1721285809Sscottl/** \brief describe a SAS ReCofiguration structure in the SAS/SATA hardware 1722285809Sscottl * 1723285809Sscottl * Describe a SAS ReConfiguration in the SAS/SATA hardware 1724285809Sscottl * 1725285809Sscottl */ 1726285809Sscottltypedef struct agsaSASReconfig_s { 1727285809Sscottl bit32 flags; /* flag to indicate a change to the default parameter 1728285809Sscottl bit31-30:reserved 1729285809Sscottl bit29: a change to the default SAS/SATA ports is requested 1730285809Sscottl bit28: the OPEN REJECT (RETRY) in command phase is requested 1731285809Sscottl bit27: the OPEN REJECT (RETRY) in data phase is requested 1732285809Sscottl bit26: REJECT will be mapped into OPEN REJECT 1733285809Sscottl bit25: delay for SATA Head-of-Line blocking detection timeout 1734285809Sscottl bit24-00:reserved */ 1735285809Sscottl bit16 reserved0; /* reserved */ 1736285809Sscottl bit8 reserved1; /* reserved */ 1737285809Sscottl bit8 maxPorts; /* This field is valid if bit 29 of the flags field is set to 1 */ 1738285809Sscottl bit16 openRejectRetriesCmd; /* This field is valid if bit 28 of the flags field is set to 1 */ 1739285809Sscottl bit16 openRejectRetriesData; /* This field is valid if bit 27 of the flags field is set to 1.*/ 1740285809Sscottl bit16 reserved2; /* reserved */ 1741285809Sscottl bit16 sataHolTmo; /* This field is valid if bit 25 of the flags field is set to 1 */ 1742285809Sscottl} agsaSASReconfig_t; 1743285809Sscottl 1744285809Sscottl/** \brief describe a Phy Analog Setup registers for a Controller in the SAS/SATA hardware 1745285809Sscottl * 1746285809Sscottl * Describe a Phy Analog Setup registers for a controller in the SAS/SATA hardware 1747285809Sscottl * 1748285809Sscottl */ 1749285809Sscottltypedef struct agsaPhyAnalogSetupRegisters_s 1750285809Sscottl{ 1751285809Sscottl bit32 spaRegister0; 1752285809Sscottl bit32 spaRegister1; 1753285809Sscottl bit32 spaRegister2; 1754285809Sscottl bit32 spaRegister3; 1755285809Sscottl bit32 spaRegister4; 1756285809Sscottl bit32 spaRegister5; 1757285809Sscottl bit32 spaRegister6; 1758285809Sscottl bit32 spaRegister7; 1759285809Sscottl bit32 spaRegister8; 1760285809Sscottl bit32 spaRegister9; 1761285809Sscottl} agsaPhyAnalogSetupRegisters_t; 1762285809Sscottl 1763285809Sscottl#define MAX_INDEX 10 1764285809Sscottl 1765285809Sscottl/** \brief 1766285809Sscottl * 1767285809Sscottl */ 1768285809Sscottltypedef struct agsaPhyAnalogSetupTable_s 1769285809Sscottl{ 1770285809Sscottl agsaPhyAnalogSetupRegisters_t phyAnalogSetupRegisters[MAX_INDEX]; 1771285809Sscottl} agsaPhyAnalogSetupTable_t; 1772285809Sscottl 1773285809Sscottl/** \brief describe a Phy Analog Setting 1774285809Sscottl * 1775285809Sscottl * Describe a Phy Analog Setup registers for a controller in the SAS/SATA hardware 1776285809Sscottl * 1777285809Sscottl */ 1778285809Sscottltypedef struct agsaPhyAnalogSettingsPage_s 1779285809Sscottl{ 1780285809Sscottl bit32 Dword0; 1781285809Sscottl bit32 Dword1; 1782285809Sscottl bit32 Dword2; 1783285809Sscottl bit32 Dword3; 1784285809Sscottl bit32 Dword4; 1785285809Sscottl bit32 Dword5; 1786285809Sscottl bit32 Dword6; 1787285809Sscottl bit32 Dword7; 1788285809Sscottl bit32 Dword8; 1789285809Sscottl bit32 Dword9; 1790285809Sscottl} agsaPhyAnalogSettingsPage_t; 1791285809Sscottl 1792285809Sscottl 1793285809Sscottl/** \brief describe a Open reject retry backoff threshold page 1794285809Sscottl * 1795285809Sscottl * Describe a Open reject retry backoff threshold registers in the SAS/SATA hardware 1796285809Sscottl * 1797285809Sscottl */ 1798285809Sscottltypedef struct agsaSASPhyOpenRejectRetryBackOffThresholdPage_s 1799285809Sscottl{ 1800285809Sscottl bit32 Dword0; 1801285809Sscottl bit32 Dword1; 1802285809Sscottl bit32 Dword2; 1803285809Sscottl bit32 Dword3; 1804285809Sscottl} agsaSASPhyOpenRejectRetryBackOffThresholdPage_t; 1805285809Sscottl 1806285809Sscottl/** \brief describe a Phy Rate Control 1807285809Sscottl * 4.56 agsaPhyRateControlPage_t 1808285809Sscottl * Description 1809285809Sscottl * This profile page is used to read or set several rate control 1810285809Sscottl * parameters. The page code for this profile page is 0x07. This page can 1811285809Sscottl * be READ by issuing saGetPhyProfile(). It can be read anytime and there 1812285809Sscottl * is no need to quiesce the I/O to the controller. 1813285809Sscottl * Related parameters can be modified by issuing saSetPhyProfile() before 1814285809Sscottl * calling saPhyStart() to the PHY. 1815285809Sscottl * Note: This page is applicable only to the SPCv controller. 1816285809Sscottl * Usage 1817285809Sscottl * Initiator and target. 1818285809Sscottl */ 1819285809Sscottltypedef struct agsaPhyRateControlPage_s 1820285809Sscottl{ 1821285809Sscottl bit32 Dword0; 1822285809Sscottl bit32 Dword1; 1823285809Sscottl bit32 Dword2; 1824285809Sscottl} agsaPhyRateControlPage_t; 1825285809Sscottl 1826285809Sscottl/** 1827285809Sscottl * Dword0 Bits 0-11: ALIGN_RATE(ALNR). Align Insertion rate is 2 in every 1828285809Sscottl * ALIGN_RATE+1 DWord. The default value results in the standard compliant 1829285809Sscottl * value of 2/256. This rate applies to out of connection, SMP and SSP 1830285809Sscottl * connections. The default value is 0x0ff. Other bits are reserved. 1831285809Sscottl * Dword1 Bits 0 -11: STP_ALIGN_RATE(STPALNR) Align Insertion rate is 2 in 1832285809Sscottl * every ALIGN_RATE+1 DWords. Default value results in standard compliant 1833285809Sscottl * value of 2/256. This rate applies to out of STP connections. The default 1834285809Sscottl * value is 0x0ff. Other bits are reserved. 1835285809Sscottl * Dword2 Bits 0-7: SSP_FRAME_RATE(SSPFRMR) The number of idle DWords 1836285809Sscottl * between each SSP frame. 0 means no idle cycles. The default value is 1837285809Sscottl * 0x0. Other bits are reserved. 1838285809Sscottl**/ 1839285809Sscottl 1840285809Sscottl/** \brief describe a Register Dump information for a Controller in the SAS/SATA hardware 1841285809Sscottl * 1842285809Sscottl * Describe a register dump information for a controller in the SAS/SATA hardware 1843285809Sscottl * 1844285809Sscottl */ 1845285809Sscottltypedef struct agsaRegDumpInfo_s 1846285809Sscottl{ 1847285809Sscottl bit8 regDumpSrc; 1848285809Sscottl bit8 regDumpNum; 1849285809Sscottl bit8 reserved[2]; 1850285809Sscottl bit32 regDumpOffset; 1851285809Sscottl bit32 directLen; 1852285809Sscottl void *directData; 1853285809Sscottl bit32 indirectAddrUpper32; 1854285809Sscottl bit32 indirectAddrLower32; 1855285809Sscottl bit32 indirectLen; 1856285809Sscottl} agsaRegDumpInfo_t; 1857285809Sscottl 1858285809Sscottl/* 1859285809Sscottl7 : SPC GSM register at [MEMBASE-III SHIFT = 0x00_0000] 1860285809Sscottl8 : SPC GSM register at [MEMBASE-III SHIFT = 0x05_0000] 1861285809Sscottl9 : BDMA GSM register at [MEMBASE-III SHIFT = 0x01_0000] 1862285809Sscottl10: PCIe APP GSM register at [MEMBASE-III SHIFT = 0x01_0000] 1863285809Sscottl11: PCIe PHY GSM register at [MEMBASE-III SHIFT = 0x01_0000] 1864285809Sscottl12: PCIe CORE GSM register at [MEMBASE-III SHIFT = 0x01_0000] 1865285809Sscottl13: OSSP GSM register at [MEMBASE-III SHIFT = 0x02_0000] 1866285809Sscottl14: SSPA GSM register at [MEMBASE-III SHIFT = 0x03_0000] 1867285809Sscottl15: SSPA GSM register at [MEMBASE-III SHIFT = 0x04_0000] 1868285809Sscottl16: HSST GSM register at [MEMBASE-III SHIFT = 0x02_0000] 1869285809Sscottl17: LMS_DSS(A) GSM register at [MEMBASE-III SHIFT = 0x03_0000] 1870285809Sscottl18: SSPL_6G GSM register at [MEMBASE-III SHIFT = 0x03_0000] 1871285809Sscottl19: HSST(A) GSM register at [MEMBASE-III SHIFT = 0x03_0000] 1872285809Sscottl20: LMS_DSS(A) GSM register at [MEMBASE-III SHIFT = 0x04_0000] 1873285809Sscottl21: SSPL_6G GSM register at [MEMBASE-III SHIFT = 0x04_0000] 1874285809Sscottl22: HSST(A) GSM register at [MEMBASE-III SHIFT = 0x04_0000] 1875285809Sscottl23: MBIC IOP GSM register at [MEMBASE-III SHIFT = 0x06_0000] 1876285809Sscottl24: MBIC AAP1 GSM register at [MEMBASE-III SHIFT = 0x07_0000] 1877285809Sscottl25: SPBC GSM register at [MEMBASE-III SHIFT = 0x09_0000] 1878285809Sscottl26: GSM GSM register at [MEMBASE-III SHIFT = 0x70_0000] 1879285809Sscottl*/ 1880285809Sscottl 1881285809Sscottl#define TYPE_GSM_SPACE 1 1882285809Sscottl#define TYPE_QUEUE 2 1883285809Sscottl#define TYPE_FATAL 3 1884285809Sscottl#define TYPE_NON_FATAL 4 1885285809Sscottl#define TYPE_INBOUND_QUEUE 5 1886285809Sscottl#define TYPE_OUTBOUND_QUEUE 6 1887285809Sscottl 1888285809Sscottl 1889285809Sscottl#define BAR_SHIFT_GSM_OFFSET 0x400000 1890285809Sscottl 1891285809Sscottl#define ONE_MEGABYTE 0x100000 1892285809Sscottl#define SIXTYFOURKBYTE (1024 * 64) 1893285809Sscottl 1894285809Sscottl 1895285809Sscottl 1896285809Sscottl#define TYPE_INBOUND 1 1897285809Sscottl#define TYPE_OUTBOUND 2 1898285809Sscottl 1899285809Sscottltypedef struct 1900285809Sscottl{ 1901285809Sscottl bit32 DataType; 1902285809Sscottl union 1903285809Sscottl { 1904285809Sscottl struct 1905285809Sscottl { 1906285809Sscottl bit32 directLen; 1907285809Sscottl bit32 directOffset; 1908285809Sscottl bit32 readLen; 1909285809Sscottl void *directData; 1910285809Sscottl }gsmBuf; 1911285809Sscottl 1912285809Sscottl struct 1913285809Sscottl { 1914285809Sscottl bit16 queueType; 1915285809Sscottl bit16 queueIndex; 1916285809Sscottl bit32 directLen; 1917285809Sscottl void *directData; 1918285809Sscottl }queueBuf; 1919285809Sscottl 1920285809Sscottl struct 1921285809Sscottl { 1922285809Sscottl bit32 directLen; 1923285809Sscottl bit32 directOffset; 1924285809Sscottl bit32 readLen; 1925285809Sscottl void *directData; 1926285809Sscottl }dataBuf; 1927285809Sscottl } BufferType; 1928285809Sscottl} agsaForensicData_t; 1929285809Sscottl 1930285809Sscottl/** \brief describe a NVMData for a Controller in the SAS/SATA hardware 1931285809Sscottl * 1932285809Sscottl * Describe a NVMData for a controller in the SAS/SATA hardware 1933285809Sscottl * 1934285809Sscottl */ 1935285809Sscottltypedef struct agsaNVMDData_s 1936285809Sscottl{ 1937285809Sscottl bit32 indirectPayload :1; 1938285809Sscottl bit32 reserved :7; 1939285809Sscottl bit32 TWIDeviceAddress :8; 1940285809Sscottl bit32 TWIBusNumber :4; 1941285809Sscottl bit32 TWIDevicePageSize :4; 1942285809Sscottl bit32 TWIDeviceAddressSize :4; 1943285809Sscottl bit32 NVMDevice :4; 1944285809Sscottl bit32 directLen :8; 1945285809Sscottl bit32 dataOffsetAddress :24; 1946285809Sscottl void *directData; 1947285809Sscottl bit32 indirectAddrUpper32; 1948285809Sscottl bit32 indirectAddrLower32; 1949285809Sscottl bit32 indirectLen; 1950285809Sscottl bit32 signature; 1951285809Sscottl} agsaNVMDData_t; 1952285809Sscottl 1953285809Sscottl 1954285809Sscottl/* status of ossaPCIeDiagExecuteCB() is shared with ossaSASDiagExecuteCB() */ 1955285809Sscottl#define OSSA_PCIE_DIAG_SUCCESS 0x0000 1956285809Sscottl#define OSSA_PCIE_DIAG_INVALID_COMMAND 0x0001 1957285809Sscottl#define OSSA_PCIE_DIAG_INTERNAL_FAILURE 0x0002 1958285809Sscottl#define OSSA_PCIE_DIAG_INVALID_CMD_TYPE 0x1006 1959285809Sscottl#define OSSA_PCIE_DIAG_INVALID_CMD_DESC 0x1007 1960285809Sscottl#define OSSA_PCIE_DIAG_INVALID_PCIE_ADDR 0x1008 1961285809Sscottl#define OSSA_PCIE_DIAG_INVALID_BLOCK_SIZE 0x1009 1962285809Sscottl#define OSSA_PCIE_DIAG_LENGTH_NOT_BLOCK_SIZE_ALIGNED 0x100A 1963285809Sscottl#define OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_MISMATCH 0x3000 1964285809Sscottl#define OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH 0x3001 1965285809Sscottl#define OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH 0x3002 1966285809Sscottl#define OSSA_PCIE_DIAG_IO_XFR_ERROR_DIF_CRC_MISMATCH 0x3003 1967285809Sscottl#define OSSA_PCIE_DIAG_MPI_ERR_INVALID_LENGTH 0x0042 1968285809Sscottl#define OSSA_PCIE_DIAG_MPI_ERR_IO_RESOURCE_UNAVAILABLE 0x1004 1969285809Sscottl#define OSSA_PCIE_DIAG_MPI_ERR_CONTROLLER_NOT_IDLE 0x1005 1970285809Sscottl 1971285809Sscottl 1972285809Sscottltypedef struct agsaPCIeDiagExecute_s 1973285809Sscottl{ 1974285809Sscottl bit32 command; 1975285809Sscottl bit32 flags; 1976285809Sscottl bit16 initialIOSeed; 1977285809Sscottl bit16 reserved; 1978285809Sscottl bit32 rdAddrLower; 1979285809Sscottl bit32 rdAddrUpper; 1980285809Sscottl bit32 wrAddrLower; 1981285809Sscottl bit32 wrAddrUpper; 1982285809Sscottl bit32 len; 1983285809Sscottl bit32 pattern; 1984285809Sscottl bit8 udtArray[6]; 1985285809Sscottl bit8 udrtArray[6]; 1986285809Sscottl} agsaPCIeDiagExecute_t; 1987285809Sscottl 1988285809Sscottl 1989285809Sscottl/** \brief agsaPCIeDiagResponse_t 1990285809Sscottl * 1991285809Sscottl * status of ossaPCIeDiagExecuteCB() 1992285809Sscottl * The agsaPCIeDiagResponse_t structure is a parameter passed to 1993285809Sscottl * ossaPCIeDiagExecuteCB() 1994285809Sscottl * to contain a PCIe Diagnostic command response. 1995285809Sscottl */ 1996285809Sscottl 1997285809Sscottltypedef struct agsaPCIeDiagResponse_s { 1998285809Sscottl bit32 ERR_BLKH; 1999285809Sscottl bit32 ERR_BLKL; 2000285809Sscottl bit32 DWord8; 2001285809Sscottl bit32 DWord9; 2002285809Sscottl bit32 DWord10; 2003285809Sscottl bit32 DWord11; 2004285809Sscottl bit32 DIF_ERR; 2005285809Sscottl} agsaPCIeDiagResponse_t; 2006285809Sscottl 2007285809Sscottl 2008285809Sscottl/** \brief describe a fatal error information for a Controller in the SAS/SATA hardware 2009285809Sscottl * 2010285809Sscottl * Describe a fatal error information for a controller in the SAS/SATA hardware 2011285809Sscottl * 2012285809Sscottl */ 2013285809Sscottltypedef struct agsaFatalErrorInfo_s 2014285809Sscottl{ 2015285809Sscottl bit32 errorInfo0; 2016285809Sscottl bit32 errorInfo1; 2017285809Sscottl bit32 errorInfo2; 2018285809Sscottl bit32 errorInfo3; 2019285809Sscottl bit32 regDumpBusBaseNum0; 2020285809Sscottl bit32 regDumpOffset0; 2021285809Sscottl bit32 regDumpLen0; 2022285809Sscottl bit32 regDumpBusBaseNum1; 2023285809Sscottl bit32 regDumpOffset1; 2024285809Sscottl bit32 regDumpLen1; 2025285809Sscottl} agsaFatalErrorInfo_t; 2026285809Sscottl 2027285809Sscottl/** \brief describe a information for a Event in the SAS/SATA hardware 2028285809Sscottl * 2029285809Sscottl * Describe a general information for a Event in the SAS/SATA hardware 2030285809Sscottl * 2031285809Sscottl */ 2032285809Sscottltypedef struct agsaEventSource_s 2033285809Sscottl{ 2034285809Sscottl agsaPortContext_t *agPortContext; 2035285809Sscottl bit32 event; 2036285809Sscottl bit32 param; 2037285809Sscottl} agsaEventSource_t; 2038285809Sscottl 2039285809Sscottl/** \brief describe a information for a Controller in the SAS/SATA hardware 2040285809Sscottl * 2041285809Sscottl * Describe a general information for a controller in the SAS/SATA hardware 2042285809Sscottl * 2043285809Sscottl */ 2044285809Sscottltypedef struct agsaControllerInfo_s 2045285809Sscottl{ 2046285809Sscottl bit32 signature; /* coherent controller information */ 2047285809Sscottl bit32 fwInterfaceRev; /* host and controller interface version */ 2048285809Sscottl bit32 hwRevision; /* controller HW Revision number */ 2049285809Sscottl bit32 fwRevision; /* controller FW Revision number */ 2050285809Sscottl bit32 ilaRevision; /* controller ILA Revision number */ 2051285809Sscottl bit32 maxPendingIO; /* maximum number of outstanding I/Os supported */ 2052285809Sscottl bit32 maxDevices; /* Maximum Device Supported by controller */ 2053285809Sscottl bit32 maxSgElements; /* maximum number of SG elements supported */ 2054285809Sscottl bit32 queueSupport; /* maximum number of IQ and OQ supported 2055285809Sscottl bit31-19 reserved 2056285809Sscottl bit18 interrupt coalescing 2057285809Sscottl bit17 reserved 2058285809Sscottl bit16 high priority IQ supported 2059285809Sscottl bit15-08 maximum number of OQ 2060285809Sscottl bit07-00 maximum number of IQ */ 2061285809Sscottl bit8 phyCount; /* number of phy available in the controller */ 2062285809Sscottl bit8 controllerSetting;/* Controller setting 2063285809Sscottl bit07-04 reserved 2064285809Sscottl bit03-00 HDA setting */ 2065285809Sscottl bit8 PCILinkRate; /* PCI generation 1/2/3 2.5g/5g/8g */ 2066285809Sscottl bit8 PCIWidth; /* PCI number of lanes */ 2067285809Sscottl bit32 sasSpecsSupport; /* the supported SAS spec. */ 2068285809Sscottl bit32 sdkInterfaceRev; /* sdk interface reversion */ 2069285809Sscottl bit32 sdkRevision; /* sdk reversion */ 2070285809Sscottl} agsaControllerInfo_t; 2071285809Sscottl 2072285809Sscottl/** \brief describe a status for a Controller in the SAS/SATA hardware 2073285809Sscottl * 2074285809Sscottl * Describe a general status for a controller in the SAS/SATA hardware 2075285809Sscottl * 2076285809Sscottl */ 2077285809Sscottltypedef struct agsaControllerStatus_s 2078285809Sscottl{ 2079285809Sscottl agsaFatalErrorInfo_t fatalErrorInfo; /* fatal error information */ 2080285809Sscottl bit32 interfaceState; /* host and controller interface state 2081285809Sscottl bit02-00 state of host and controller 2082285809Sscottl bit16-03 reserved 2083285809Sscottl bit31-16 detail of error based on error state */ 2084285809Sscottl bit32 iqFreezeState0; /* freeze state of 1st set of IQ */ 2085285809Sscottl bit32 iqFreezeState1; /* freeze state of 2nd set of IQ */ 2086285809Sscottl bit32 tickCount0; /* tick count in second for internal CPU-0 */ 2087285809Sscottl bit32 tickCount1; /* tick count in second for internal CPU-1 */ 2088285809Sscottl bit32 tickCount2; /* tick count in second for internal CPU-2 */ 2089285809Sscottl bit32 phyStatus[8]; /* status of phy 0 to phy 15 */ 2090285809Sscottl bit32 recoverableErrorInfo[8]; /* controller specific recoverable error information */ 2091285809Sscottl bit32 bootStatus; 2092285809Sscottl bit16 bootComponentState[8]; 2093285809Sscottl 2094285809Sscottl} agsaControllerStatus_t; 2095285809Sscottl 2096285809Sscottl/** \brief describe a GPIO Event Setup Infomation in the SAS/SATA hardware 2097285809Sscottl * 2098285809Sscottl * Describe a configuration for a GPIO Event Setup Infomation in the SAS/SATA hardware 2099285809Sscottl * 2100285809Sscottl */ 2101285809Sscottltypedef struct agsaGpioEventSetupInfo_s 2102285809Sscottl{ 2103285809Sscottl bit32 gpioPinMask; 2104285809Sscottl bit32 gpioEventLevel; 2105285809Sscottl bit32 gpioEventRisingEdge; 2106285809Sscottl bit32 gpioEventFallingEdge; 2107285809Sscottl} agsaGpioEventSetupInfo_t; 2108285809Sscottl 2109285809Sscottl/** \brief describe a GPIO Pin Setup Infomation in the SAS/SATA hardware 2110285809Sscottl * 2111285809Sscottl * Describe a configuration for a GPIO Pin Setup Infomation in the SAS/SATA hardware 2112285809Sscottl * 2113285809Sscottl */ 2114285809Sscottltypedef struct agsaGpioPinSetupInfo_t 2115285809Sscottl{ 2116285809Sscottl bit32 gpioPinMask; 2117285809Sscottl bit32 gpioInputEnabled; 2118285809Sscottl bit32 gpioTypePart1; 2119285809Sscottl bit32 gpioTypePart2; 2120285809Sscottl} agsaGpioPinSetupInfo_t; 2121285809Sscottl 2122285809Sscottl/** \brief describe a serial GPIO operation in the SAS/SATA hardware 2123285809Sscottl * 2124285809Sscottl * Describe a configuration for a GPIO write Setup Infomation in the SAS/SATA hardware 2125285809Sscottl * 2126285809Sscottl */ 2127285809Sscottltypedef struct agsaGpioWriteSetupInfo_s 2128285809Sscottl{ 2129285809Sscottl bit32 gpioWritemask; 2130285809Sscottl bit32 gpioWriteVal; 2131285809Sscottl}agsaGpioWriteSetupInfo_t; 2132285809Sscottl 2133285809Sscottl/** \brief describe a GPIO Read Infomation in the SAS/SATA hardware 2134285809Sscottl * 2135285809Sscottl * Describe a configuration for a GPIO read Infomation in the SAS/SATA hardware 2136285809Sscottl * 2137285809Sscottl */ 2138285809Sscottltypedef struct agsaGpioReadInfo_s 2139285809Sscottl{ 2140285809Sscottl bit32 gpioReadValue; 2141285809Sscottl bit32 gpioInputEnabled; /* GPIOIE */ 2142285809Sscottl bit32 gpioEventLevelChangePart1; /* GPIEVCHANGE (pins 11-0) */ 2143285809Sscottl bit32 gpioEventLevelChangePart2; /* GPIEVCHANGE (pins 23-20) */ 2144285809Sscottl bit32 gpioEventRisingEdgePart1; /* GPIEVRISE (pins 11-0) */ 2145285809Sscottl bit32 gpioEventRisingEdgePart2; /* GPIEVRISE (pins 23-20) */ 2146285809Sscottl bit32 gpioEventFallingEdgePart1; /* GPIEVALL (pins 11-0) */ 2147285809Sscottl bit32 gpioEventFallingEdgePart2; /* GPIEVALL (pins 23-20) */ 2148285809Sscottl}agsaGpioReadInfo_t; 2149285809Sscottl 2150285809Sscottl/** \brief describe a serial GPIO request and response in the SAS/SATA hardware 2151285809Sscottl * 2152285809Sscottl * Describe the fields required for serial GPIO request and response in the SAS/SATA hardware 2153285809Sscottl * 2154285809Sscottl */ 2155285809Sscottltypedef struct agsaSGpioReqResponse_s 2156285809Sscottl{ 2157285809Sscottl bit8 smpFrameType; /* 0x40 for request, 0x41 for response*/ 2158285809Sscottl bit8 function; /* 0x02 for read, 0x82 for write */ 2159285809Sscottl bit8 registerType; /* used only in request */ 2160285809Sscottl bit8 registerIndex; /* used only in request */ 2161285809Sscottl bit8 registerCount; /* used only in request */ 2162285809Sscottl bit8 functionResult; /* used only in response */ 2163285809Sscottl bit32 readWriteData[OSSA_SGPIO_MAX_READ_DATA_COUNT]; /* write data for request; read data for response */ 2164285809Sscottl} agsaSGpioReqResponse_t; 2165285809Sscottl 2166285809Sscottl 2167285809Sscottl/** \brief describe a serial GPIO operation response in the SAS/SATA hardware 2168285809Sscottl * 2169285809Sscottl * Describe the fields required for serial GPIO operations response in the SAS/SATA hardware 2170285809Sscottl * 2171285809Sscottl */ 2172285809Sscottltypedef struct agsaSGpioCfg0 2173285809Sscottl{ 2174285809Sscottl bit8 reserved1; 2175285809Sscottl bit8 version:4; 2176285809Sscottl bit8 reserved2:4; 2177285809Sscottl bit8 gpRegisterCount:4; 2178285809Sscottl bit8 cfgRegisterCount:3; 2179285809Sscottl bit8 gpioEnable:1; 2180285809Sscottl bit8 supportedDriveCount; 2181285809Sscottl} agsaSGpioCfg0_t; 2182285809Sscottl 2183285809Sscottl/** \brief SGPIO configuration register 1 2184285809Sscottl * 2185285809Sscottl * These fields constitute SGPIO configuration register 1, as defined by SFF-8485 spec 2186285809Sscottl * 2187285809Sscottl */ 2188285809Sscottltypedef struct agsaSGpioCfg1{ 2189285809Sscottl bit8 reserved; 2190285809Sscottl bit8 blinkGenA:4; 2191285809Sscottl bit8 blinkGenB:4; 2192285809Sscottl bit8 maxActOn:4; 2193285809Sscottl bit8 forceActOff:4; 2194285809Sscottl bit8 stretchActOn:4; 2195285809Sscottl bit8 stretchActOff:4; 2196285809Sscottl} agsaSGpioCfg1_t; 2197285809Sscottl 2198285809Sscottl/** \brief describe a configuration for a PHY in the SAS/SATA hardware 2199285809Sscottl * 2200285809Sscottl * Describe a configuration for a PHY in the SAS/SATA hardware 2201285809Sscottl * 2202285809Sscottl */ 2203285809Sscottltypedef struct agsaPhyConfig_s 2204285809Sscottl{ 2205285809Sscottl bit32 phyProperties; 2206285809Sscottl /**< b31-b8 reserved */ 2207285809Sscottl /**< b16-b19 SSC Disable */ 2208285809Sscottl /**< b15-b8 phy analog setup index */ 2209285809Sscottl /**< b7 phy analog setup enable */ 2210285809Sscottl /**< b6 Control spin up hold */ 2211285809Sscottl /**< b5-b4 SAS/SATA mode, bit4 - SAS, bit5 - SATA, 11b - Auto mode */ 2212285809Sscottl /**< b3-b0 Max. Link Rate, bit0 - 1.5Gb/s, bit1 - 3.0Gb/s, 2213285809Sscottl bit2 - 6.0Gb/s, bit3 - reserved */ 2214285809Sscottl} agsaPhyConfig_t; 2215285809Sscottl 2216285809Sscottl 2217285809Sscottl/** \brief Structure is used as a parameter passed in saLocalPhyControlCB() to describe the error counter 2218285809Sscottl * 2219285809Sscottl * Description 2220285809Sscottl * This profile page is used to read or set the SNW-3 PHY capabilities of a 2221285809Sscottl * SAS PHY. This page can be read by calling saGetPhyProfile(). It can be 2222285809Sscottl * read anytime and there is no need to quiesce he I/O to the controller. 2223285809Sscottl * The format of the 32-bit SNW3 is the same as defined in the SAS 2 2224285809Sscottl * specification. 2225285809Sscottl * Local SNW3 can be modified by calling saSetPhyProfile() before 2226285809Sscottl * saPhyStart() to the PHY. REQUESTED LOGICAL LINK RATE is reserved. 2227285809Sscottl * The SPCv will calculate the PARITY field. 2228285809Sscottl 2229285809Sscottl * Note: This page is applicable only to the SPCv controller. 2230285809Sscottl * Usage 2231285809Sscottl * Initiator and target. 2232285809Sscottl */ 2233285809Sscottl 2234285809Sscottltypedef struct agsaPhySNW3Page_s 2235285809Sscottl{ 2236285809Sscottl bit32 LSNW3; 2237285809Sscottl bit32 RSNW3; 2238285809Sscottl} agsaPhySNW3Page_t; 2239285809Sscottl 2240285809Sscottl/** \brief structure describe error counters of a PHY in the SAS/SATA 2241285809Sscottl * 2242285809Sscottl * Structure is used as a parameter passed in saLocalPhyControlCB() 2243285809Sscottl * to describe the error counter 2244285809Sscottl * 2245285809Sscottl */ 2246285809Sscottltypedef struct agsaPhyErrCounters_s 2247285809Sscottl{ 2248285809Sscottl bit32 invalidDword; /* Number of invalid dwords that have been 2249285809Sscottl received outside of phy reset sequences.*/ 2250285809Sscottl bit32 runningDisparityError; /* Number of dwords containing running disparity 2251285809Sscottl errors that have been received outside of phy 2252285809Sscottl reset sequences.*/ 2253285809Sscottl bit32 lossOfDwordSynch; /* Number of times the phy has restarted the link 2254285809Sscottl reset sequence because it lost dword synchronization.*/ 2255285809Sscottl bit32 phyResetProblem; /* Number of times the phy did not obtain dword 2256285809Sscottl synchronization during the final SAS speed 2257285809Sscottl negotiation window.*/ 2258285809Sscottl bit32 elasticityBufferOverflow; /* Number of times the phys receive elasticity 2259285809Sscottl buffer has overflowed.*/ 2260285809Sscottl bit32 receivedErrorPrimitive; /* Number of times the phy received an ERROR primitive */ 2261285809Sscottl bit32 inboundCRCError; /* Number of inbound CRC Error */ 2262285809Sscottl bit32 codeViolation; /* Number of code violation */ 2263285809Sscottl} agsaPhyErrCounters_t; 2264285809Sscottl 2265285809Sscottl 2266285809Sscottl/** \brief 2267285809Sscottl * used in saGetPhyProfile 2268285809Sscottl */ 2269285809Sscottltypedef struct agsaPhyErrCountersPage_s 2270285809Sscottl{ 2271285809Sscottl bit32 invalidDword; 2272285809Sscottl bit32 runningDisparityError; 2273285809Sscottl bit32 codeViolation; 2274285809Sscottl bit32 lossOfDwordSynch; 2275285809Sscottl bit32 phyResetProblem; 2276285809Sscottl bit32 inboundCRCError; 2277285809Sscottl} agsaPhyErrCountersPage_t; 2278285809Sscottl 2279285809Sscottl/** \brief structure describes bandwidth counters of a PHY in the SAS/SATA 2280285809Sscottl * 2281285809Sscottl * Structure is used as a parameter passed in saGetPhyProfile() 2282285809Sscottl * to describe the error counter 2283285809Sscottl * 2284285809Sscottl */ 2285285809Sscottl 2286285809Sscottltypedef struct agsaPhyBWCountersPage_s 2287285809Sscottl{ 2288285809Sscottl bit32 TXBWCounter; 2289285809Sscottl bit32 RXBWCounter; 2290285809Sscottl} agsaPhyBWCountersPage_t; 2291285809Sscottl 2292285809Sscottl 2293285809Sscottl 2294285809Sscottl/** \brief structure describe hardware configuration 2295285809Sscottl * 2296285809Sscottl * Structure is used as a parameter passed in saInitialize() to describe the 2297285809Sscottl * configuration used during hardware initialization 2298285809Sscottl * 2299285809Sscottl */ 2300285809Sscottltypedef struct agsaHwConfig_s 2301285809Sscottl{ 2302285809Sscottl bit32 phyCount; /**< Number of PHYs that are to be configured 2303285809Sscottl and initialized. */ 2304285809Sscottl bit32 hwInterruptCoalescingTimer; /**< Host Interrupt CoalescingTimer */ 2305285809Sscottl bit32 hwInterruptCoalescingControl; /**< Host Interrupt CoalescingControl */ 2306285809Sscottl bit32 intReassertionOption; /**< Interrupt Ressertion Option */ 2307285809Sscottl bit32 hwOption; /** PCAD64 on 64 bit addressing */ 2308285809Sscottl 2309285809Sscottl agsaPhyAnalogSetupTable_t phyAnalogConfig; /**< Phy Analog Setting Table */ 2310285809Sscottl} agsaHwConfig_t; 2311285809Sscottl 2312285809Sscottl/** \brief structure describe software configuration 2313285809Sscottl * 2314285809Sscottl * Structure is used as a parameter passed in saInitialize() to describe the 2315285809Sscottl * configuration used during software initialization 2316285809Sscottl * 2317285809Sscottl */ 2318285809Sscottltypedef struct agsaSwConfig_s 2319285809Sscottl{ 2320285809Sscottl bit32 maxActiveIOs; /**< Maximum active I/O requests supported */ 2321285809Sscottl bit32 numDevHandles; /**< Number of SAS/SATA device handles allocated 2322285809Sscottl in the pool */ 2323285809Sscottl bit32 smpReqTimeout; /**< SMP request time out in millisecond */ 2324285809Sscottl bit32 numberOfEventRegClients; /**< Maximum number of OS Layer clients for the event 2325285809Sscottl registration defined by saRegisterEventCallback() */ 2326285809Sscottl bit32 sizefEventLog1; /**< Size of Event Log 1 */ 2327285809Sscottl bit32 sizefEventLog2; /**< Size of Event Log 2 */ 2328285809Sscottl bit32 eventLog1Option; /**< Option of Event Log 1 */ 2329285809Sscottl bit32 eventLog2Option; /**< Option of Event Log 2 */ 2330285809Sscottl 2331285809Sscottl bit32 fatalErrorInterruptEnable:1; /**< 0 Fatal Error Iterrupt Enable */ 2332285809Sscottl bit32 sgpioSupportEnable:1; /**< 1 SGPIO Support Enable */ 2333285809Sscottl bit32 fatalErrorInterruptVector:8; /**< 2-9 Fatal Error Interrupt Vector */ 2334285809Sscottl bit32 max_MSI_InterruptVectors:8; /**< 10-18 Maximum MSI Interrupt Vectors */ 2335285809Sscottl bit32 max_MSIX_InterruptVectors:8; /**< 18-25 Maximum MSIX Interrupt Vectors */ 2336285809Sscottl bit32 legacyInt_X:1; /**< 26 Support Legacy Interrupt */ 2337285809Sscottl bit32 hostDirectAccessSupport:1; /**< 27 Support HDA mode */ 2338285809Sscottl bit32 hostDirectAccessMode:2; /**< 28-29 HDA mode: 00b - HDA SoftReset, 01b - HDA Normal */ 2339285809Sscottl bit32 enableDIF:1; /**< 30 */ 2340285809Sscottl bit32 enableEncryption:1; /**< 31 */ 2341285809Sscottl#ifdef SA_CONFIG_MDFD_REGISTRY 2342285809Sscottl bit32 disableMDF; /*disable MDF*/ 2343285809Sscottl#endif 2344285809Sscottl bit32 param1; /**< parameter1 */ 2345285809Sscottl bit32 param2; /**< parameter2 */ 2346285809Sscottl void *param3; /**< parameter3 */ 2347285809Sscottl void *param4; /**< paramater4 */ 2348285809Sscottl bit32 stallUsec; 2349285809Sscottl bit32 FWConfig; 2350285809Sscottl bit32 PortRecoveryResetTimer; 2351285809Sscottl void *mpiContextTable; /** Pointer to a table that contains agsaMPIContext_t 2352285809Sscottl entries. This table is used to fill in MPI table 2353285809Sscottl fields. Values in this table are written to MPI table last. 2354285809Sscottl Any previous values in MPI table are overwritten by values 2355285809Sscottl in this table. */ 2356285809Sscottl 2357285809Sscottl bit32 mpiContextTablelen; /** Number of agsaMPIContext_t entries in mpiContextTable */ 2358285809Sscottl 2359285809Sscottl#if defined(SALLSDK_DEBUG) 2360285809Sscottl bit32 sallDebugLevel; /**< Low Layer debug level */ 2361285809Sscottl#endif 2362285809Sscottl 2363285809Sscottl#ifdef SA_ENABLE_PCI_TRIGGER 2364285809Sscottl bit32 PCI_trigger; 2365285809Sscottl#endif /* SA_ENABLE_PCI_TRIGGER */ 2366285809Sscottl 2367285809Sscottl#ifdef SA_ENABLE_TRACE_FUNCTIONS 2368285809Sscottl bit32 TraceDestination; 2369285809Sscottl bit32 TraceBufferSize; 2370285809Sscottl bit32 TraceMask; 2371285809Sscottl#endif /* SA_ENABLE_TRACE_FUNCTIONS */ 2372285809Sscottl} agsaSwConfig_t; 2373285809Sscottl 2374285809Sscottl 2375285809Sscottltypedef struct agsaQueueInbound_s 2376285809Sscottl{ 2377285809Sscottl bit32 elementCount:16; /* Maximum number of elements in the queue (queue depth). 2378285809Sscottl A value of zero indicates that the host disabled this queue.*/ 2379285809Sscottl bit32 elementSize:16; /* Size of each element in the queue in bytes.*/ 2380285809Sscottl bit32 priority:2; /* Queue priority: 2381285809Sscottl 00: normal priority 2382285809Sscottl 01: high priority 2383285809Sscottl 10: reserved 2384285809Sscottl 11: reserved */ 2385285809Sscottl bit32 reserved:30; 2386285809Sscottl} agsaQueueInbound_t; 2387285809Sscottl 2388285809Sscottltypedef struct agsaQueueOutbound_s 2389285809Sscottl{ 2390285809Sscottl bit32 elementCount:16; /* Maximum number of elements in the queue (queue depth). 2391285809Sscottl A value of zero indicates that the host disabled 2392285809Sscottl this queue.*/ 2393285809Sscottl bit32 elementSize:16; /* Size of each element in the queue in bytes.*/ 2394285809Sscottl bit32 interruptDelay:16; /* Time, in usec, to delay interrupts to the host. 2395285809Sscottl Zero means not to delay based on time. An 2396285809Sscottl interrupt is passed to the host when either of 2397285809Sscottl the interruptDelay or interruptCount parameters 2398285809Sscottl is satisfied. Default value is 0.*/ 2399285809Sscottl bit32 interruptCount:16; /* Number of interrupts required before passing to 2400285809Sscottl the host. Zero means not to coalesce based on count. */ 2401285809Sscottl bit32 interruptVectorIndex:8; /* MSI/MSI-X interrupt vector index. For MSI, when 2402285809Sscottl Multiple Messages is enabled, this field is the 2403285809Sscottl index to the MSI vectors derived from a single 2404285809Sscottl Message Address and multiple Message Data. 2405285809Sscottl For MSI-X, this field is the index to the 2406285809Sscottl MSI-X Table Structure. */ 2407285809Sscottl bit32 interruptEnable:1; /* 0b: No interrupt to host (host polling) 2408285809Sscottl 1b: Interrupt enabled */ 2409285809Sscottl bit32 reserved:23; 2410285809Sscottl 2411285809Sscottl} agsaQueueOutbound_t; 2412285809Sscottl 2413285809Sscottltypedef struct agsaPhyCalibrationTbl_s 2414285809Sscottl{ 2415285809Sscottl bit32 txPortConfig1; /* transmitter per port configuration 1 SAS_SATA G1 */ 2416285809Sscottl bit32 txPortConfig2; /* transmitter per port configuration 2 SAS_SATA G1*/ 2417285809Sscottl bit32 txPortConfig3; /* transmitter per port configuration 3 SAS_SATA G1*/ 2418285809Sscottl bit32 txConfig1; /* transmitter configuration 1 */ 2419285809Sscottl bit32 rvPortConfig1; /* reveiver per port configuration 1 SAS_SATA G1G2 */ 2420285809Sscottl bit32 rvPortConfig2; /* reveiver per port configuration 2 SAS_SATA G3 */ 2421285809Sscottl bit32 rvConfig1; /* reveiver per configuration 1 */ 2422285809Sscottl bit32 rvConfig2; /* reveiver per configuration 2 */ 2423285809Sscottl bit32 reserved[2]; /* reserved */ 2424285809Sscottl} agsaPhyCalibrationTbl_t; 2425285809Sscottl 2426285809Sscottltypedef struct agsaQueueConfig_s 2427285809Sscottl{ 2428285809Sscottl bit16 numInboundQueues; 2429285809Sscottl bit16 numOutboundQueues; 2430285809Sscottl bit8 sasHwEventQueue[AGSA_MAX_VALID_PHYS]; 2431285809Sscottl bit8 sataNCQErrorEventQueue[AGSA_MAX_VALID_PHYS]; 2432285809Sscottl bit8 tgtITNexusEventQueue[AGSA_MAX_VALID_PHYS]; 2433285809Sscottl bit8 tgtSSPEventQueue[AGSA_MAX_VALID_PHYS]; 2434285809Sscottl bit8 tgtSMPEventQueue[AGSA_MAX_VALID_PHYS]; 2435285809Sscottl bit8 iqNormalPriorityProcessingDepth; 2436285809Sscottl bit8 iqHighPriorityProcessingDepth; 2437285809Sscottl bit8 generalEventQueue; 2438285809Sscottl bit8 tgtDeviceRemovedEventQueue; 2439285809Sscottl bit32 queueOption; 2440285809Sscottl agsaQueueInbound_t inboundQueues[AGSA_MAX_INBOUND_Q]; 2441285809Sscottl agsaQueueOutbound_t outboundQueues[AGSA_MAX_OUTBOUND_Q]; 2442285809Sscottl} agsaQueueConfig_t; 2443285809Sscottl 2444285809Sscottl#define OQ_SHARE_PATH_BIT 0x00000001 2445285809Sscottl 2446285809Sscottltypedef struct agsaFwImg_s 2447285809Sscottl{ 2448285809Sscottl bit8 *aap1Img; /**< AAP1 Image */ 2449285809Sscottl bit32 aap1Len; /**< AAP1 Image Length */ 2450285809Sscottl bit8 *ilaImg; /**< ILA Image */ 2451285809Sscottl bit32 ilaLen; /**< ILA Image Length */ 2452285809Sscottl bit8 *iopImg; /**< IOP Image */ 2453285809Sscottl bit32 iopLen; /**< IOP Image Length */ 2454285809Sscottl bit8 *istrImg; /**< Init String */ 2455285809Sscottl bit32 istrLen; /**< Init String Length */ 2456285809Sscottl} agsaFwImg_t; 2457285809Sscottl 2458285809Sscottl/** \brief generic memory descriptor 2459285809Sscottl * 2460285809Sscottl * a generic memory descriptor used for describing a memory requirement in a structure 2461285809Sscottl * 2462285809Sscottl */ 2463285809Sscottltypedef struct agsaMem_s 2464285809Sscottl{ 2465285809Sscottl void *virtPtr; /**< Virtual pointer to the memory chunk */ 2466285809Sscottl void *osHandle; /**< Handle used for OS to free memory */ 2467285809Sscottl bit32 phyAddrUpper; /**< Upper 32 bits of physical address */ 2468285809Sscottl bit32 phyAddrLower; /**< Lower 32 bits of physical address */ 2469285809Sscottl bit32 totalLength; /**< Total length in bytes allocated */ 2470285809Sscottl bit32 numElements; /**< Number of elements */ 2471285809Sscottl bit32 singleElementLength; /**< Size in bytes of an element */ 2472285809Sscottl bit32 alignment; /**< Alignment in bytes needed. A value of one indicates 2473285809Sscottl no specific alignment requirement */ 2474285809Sscottl bit32 type; /**< DMA or Cache */ 2475285809Sscottl bit32 reserved; /**< reserved */ 2476285809Sscottl} agsaMem_t; 2477285809Sscottl 2478285809Sscottl/** \brief specify the controller Event Log for the SAS/SATA LL Layer 2479285809Sscottl * 2480285809Sscottl * data structure used in the saGetControllerEventLogInfo() function calls 2481285809Sscottl * 2482285809Sscottl */ 2483285809Sscottltypedef struct agsaControllerEventLog_s 2484285809Sscottl{ 2485285809Sscottl agsaMem_t eventLog1; 2486285809Sscottl agsaMem_t eventLog2; 2487285809Sscottl bit32 eventLog1Option; 2488285809Sscottl bit32 eventLog2Option; 2489285809Sscottl} agsaControllerEventLog_t; 2490285809Sscottl 2491285809Sscottl/* Log Option - bit3-0 */ 2492285809Sscottl#define DISABLE_LOGGING 0x0 2493285809Sscottl#define CRITICAL_ERROR 0x1 2494285809Sscottl#define WARNING 0x2 2495285809Sscottl#define NOTICE 0x3 2496285809Sscottl#define INFORMATION 0x4 2497285809Sscottl#define DEBUGGING 0x5 2498285809Sscottl 2499285809Sscottl/** \brief specify the SAS Diagnostic Parameters for the SAS/SATA LL Layer 2500285809Sscottl * 2501285809Sscottl * data structure used in the saGetRequirements() and the saInitialize() function calls 2502285809Sscottl * 2503285809Sscottl */ 2504285809Sscottltypedef struct agsaSASDiagExecute_s 2505285809Sscottl{ 2506285809Sscottl bit32 command; 2507285809Sscottl bit32 param0; 2508285809Sscottl bit32 param1; 2509285809Sscottl bit32 param2; 2510285809Sscottl bit32 param3; 2511285809Sscottl bit32 param4; 2512285809Sscottl bit32 param5; 2513285809Sscottl} agsaSASDiagExecute_t; 2514285809Sscottl 2515285809Sscottl 2516285809Sscottl/** \brief for the SAS/SATA LL Layer 2517285809Sscottl * 2518285809Sscottl * This data structure contains the general status of a SAS Phy. 2519285809Sscottl * Section 4.60 2520285809Sscottl */ 2521285809Sscottltypedef struct agsaSASPhyGeneralStatusPage_s 2522285809Sscottl{ 2523285809Sscottl bit32 Dword0; 2524285809Sscottl bit32 Dword1; 2525285809Sscottl} agsaSASPhyGeneralStatusPage_t; 2526285809Sscottl 2527285809Sscottl 2528285809Sscottl/** \brief specify the memory allocation requirement for the SAS/SATA LL Layer 2529285809Sscottl * 2530285809Sscottl * data structure used in the saGetRequirements() and the saInitialize() function calls 2531285809Sscottl * 2532285809Sscottl */ 2533285809Sscottltypedef struct agsaMemoryRequirement_s 2534285809Sscottl{ 2535285809Sscottl bit32 count; /**< The number of memory chunks used 2536285809Sscottl in the agMemory table */ 2537285809Sscottl agsaMem_t agMemory[AGSA_NUM_MEM_CHUNKS]; /**< The structure that defines the memory 2538285809Sscottl requirement structure */ 2539285809Sscottl} agsaMemoryRequirement_t; 2540285809Sscottl 2541285809Sscottl 2542285809Sscottl/** \brief describe a SAS address and PHY Identifier 2543285809Sscottl * 2544285809Sscottl * This structure is used 2545285809Sscottl * 2546285809Sscottl */ 2547285809Sscottltypedef struct agsaSASAddressID_s 2548285809Sscottl{ 2549285809Sscottl bit8 sasAddressLo[4]; /**< HOST SAS address lower part */ 2550285809Sscottl bit8 sasAddressHi[4]; /**< HOST SAS address higher part */ 2551285809Sscottl bit8 phyIdentifier; /**< PHY IDENTIFIER of the PHY */ 2552285809Sscottl} agsaSASAddressID_t; 2553285809Sscottl 2554285809Sscottl/** \brief data structure provides some information about a SATA device 2555285809Sscottl * 2556285809Sscottl * data structure provides some information about a SATA device discovered 2557285809Sscottl * following the SATA discovery. 2558285809Sscottl * 2559285809Sscottl */ 2560285809Sscottltypedef struct agsaDeviceInfo_s 2561285809Sscottl{ 2562285809Sscottl bit16 smpTimeout; 2563285809Sscottl bit16 it_NexusTimeout; 2564285809Sscottl bit16 firstBurstSize; 2565285809Sscottl bit8 reserved; 2566285809Sscottl /* Not Used */ 2567285809Sscottl bit8 devType_S_Rate; 2568285809Sscottl /* Bit 6-7: reserved 2569285809Sscottl Bit 4-5: Two-bit flag to specify a SSP/SMP, or directly attached SATA or STP device 2570285809Sscottl 00: STP device 2571285809Sscottl 01: SSP or SMP device 2572285809Sscottl 10: Direct SATA device 2573285809Sscottl Bit 0-3: Connection Rate field when opening the device. 2574285809Sscottl Code Description: 2575285809Sscottl 08h: 1.5 Gbps 2576285809Sscottl 09h: 3.0 Gbps 2577285809Sscottl 0ah: 6.0 Gbps 2578285809Sscottl All others Reserved 2579285809Sscottl */ 2580285809Sscottl bit8 sasAddressHi[4]; 2581285809Sscottl bit8 sasAddressLo[4]; 2582285809Sscottl bit32 flag; 2583285809Sscottl/* 2584285809Sscottlflag 2585285809SscottlBit 0: Retry flag. 2586285809Sscottl 1b: enable SAS TLR (Transport Layer Retry). 2587285809Sscottl 0b: disable SAS TLR (Transport Layer Retry). 2588285809Sscottl When used during device registration, it is recommended that TLR is 2589285809Sscottl enabled, i.e. set the bit to 1. 2590285809SscottlBit 1: Priority setting for AWT (Arbitration Wait Time) for this device. 2591285809Sscottl 0b: Default setting (recommended). Actual AWT value TBD. 2592285809Sscottl 1b: Increase priority. Actual AWT value TBD. 2593285809SscottlBit 2-3: Reserved 2594285809SscottlBit 4-11: Zero-based PHY identifier. This field is used only if bits 4-5 in devType_S_Rate are set to 10b 2595285809Sscottl which indicates a directly-attached SATA drive. 2596285809SscottlBit 12-15: Reserved 2597285809SscottlBit 16-19 : Maximum Connection Number. This field specifies the maximum number of connections that 2598285809Sscottl can be established with the device concurrently. This field is set to the lowest port width along the pathway 2599285809Sscottl from the controller to the device. This is applicable only to the SPCv controller. 2600285809Sscottl However, for backward compatibility reasons, if this field is set to zero, it is treated as 1 so that the controller 2601285809Sscottl can establish at least one connection. 2602285809SscottlBit 20: Initiator Role 2603285809Sscottl This bit indicates whether the device has SSP initiator role capability. This is applicable only to the SPCv controller. 2604285809Sscottl 0b : The device has no SSP initiator capability. 2605285809Sscottl 1b : The device has SSP initiator capability. 2606285809SscottlBit 21: ATAPI Device Flag. (Only applies to the SPCv) Flag to indicate ATAPI protocol support 2607285809Sscottl 0b : Device does not support ATAPI protocol. 2608285809Sscottl 1b : Device supports ATAPI protocol. 2609285809SscottlBit 22-31: Reserved 2610285809Sscottl*/ 2611285809Sscottl} agsaDeviceInfo_t; 2612285809Sscottl 2613285809Sscottl 2614285809Sscottl#define DEV_INFO_MASK 0xFF 2615285809Sscottl#define DEV_INFO_MCN_SHIFT 16 2616285809Sscottl#define DEV_INFO_IR_SHIFT 20 2617285809Sscottl 2618285809Sscottl#define RETRY_DEVICE_FLAG (1 << SHIFT0) 2619285809Sscottl#define AWT_DEVICE_FLAG (1 << SHIFT1) 2620285809Sscottl#define SSP_DEVICE_FLAG (1 << SHIFT20) 2621285809Sscottl#define ATAPI_DEVICE_FLAG 0x200000 /* bit21 */ 2622285809Sscottl#define XFER_RDY_PRIORTY_DEVICE_FLAG (1 << SHIFT22) 2623285809Sscottl 2624285809Sscottl 2625285809Sscottl#define DEV_LINK_RATE 0x3F 2626285809Sscottl 2627285809Sscottl#define SA_DEVINFO_GET_SAS_ADDRESSLO(devInfo) \ 2628285809Sscottl DMA_BEBIT32_TO_BIT32(*(bit32 *)(devInfo)->sasAddressLo) 2629285809Sscottl 2630285809Sscottl#define SA_DEVINFO_GET_SAS_ADDRESSHI(devInfo) \ 2631285809Sscottl DMA_BEBIT32_TO_BIT32(*(bit32 *)(devInfo)->sasAddressHi) 2632285809Sscottl 2633285809Sscottl#define SA_DEVINFO_GET_DEVICETTYPE(devInfo) \ 2634285809Sscottl (((devInfo)->devType_S_Rate & 0xC0) >> 5) 2635285809Sscottl 2636285809Sscottl#define SA_DEVINFO_PUT_SAS_ADDRESSLO(devInfo, src32) \ 2637285809Sscottl *(bit32 *)((devInfo)->sasAddressLo) = BIT32_TO_DMA_BEBIT32(src32) 2638285809Sscottl 2639285809Sscottl#define SA_DEVINFO_PUT_SAS_ADDRESSHI(devInfo, src32) \ 2640285809Sscottl *(bit32 *)((devInfo)->sasAddressHi) = BIT32_TO_DMA_BEBIT32(src32) 2641285809Sscottl 2642285809Sscottl/** \brief data structure provides some information about a SATA device 2643285809Sscottl * 2644285809Sscottl * data structure provides some information about a SATA device discovered 2645285809Sscottl * following the SATA discovery. 2646285809Sscottl * 2647285809Sscottl */ 2648285809Sscottltypedef struct agsaSATADeviceInfo_s 2649285809Sscottl{ 2650285809Sscottl agsaDeviceInfo_t commonDevInfo; /**< The general/common part of the 2651285809Sscottl SAS/SATA device information */ 2652285809Sscottl bit8 connection; /**< How device is connected: 2653285809Sscottl 0: Direct attached. 2654285809Sscottl 1: Behind Port Multiplier, 2655285809Sscottl portMultiplierField is valid. 2656285809Sscottl 2: STP, stpPhyIdentifier is valid */ 2657285809Sscottl 2658285809Sscottl bit8 portMultiplierField; /**< The first 4 bits indicate that 2659285809Sscottl the Port Multiplier field is defined 2660285809Sscottl by SATA-II. This field is valid only 2661285809Sscottl if the connection field above is 2662285809Sscottl set to 1 */ 2663285809Sscottl 2664285809Sscottl bit8 stpPhyIdentifier; /**< PHY ID of the STP PHY. Valid only if 2665285809Sscottl connection field is set to 2 (STP). */ 2666285809Sscottl 2667285809Sscottl bit8 reserved; 2668285809Sscottl bit8 signature[8]; /**< The signature of SATA in Task 2669285809Sscottl File registers following power up. 2670285809Sscottl Only five bytes are defined by ATA. 2671285809Sscottl The added three bytes are for 2672285809Sscottl alignment purposes */ 2673285809Sscottl} agsaSATADeviceInfo_t; 2674285809Sscottl 2675285809Sscottl/** \brief data structure provides some information about a SAS device 2676285809Sscottl * 2677285809Sscottl * data structure provides some information about a SAS device discovered 2678285809Sscottl * following the SAS discovery 2679285809Sscottl * 2680285809Sscottl */ 2681285809Sscottltypedef struct agsaSASDeviceInfo_s 2682285809Sscottl{ 2683285809Sscottl agsaDeviceInfo_t commonDevInfo; /**< The general/common part of the SAS/SATA 2684285809Sscottl device information */ 2685285809Sscottl bit8 initiator_ssp_stp_smp; /**< SAS initiator capabilities */ 2686285809Sscottl /* b4-7: reserved */ 2687285809Sscottl /* b3: SSP initiator port */ 2688285809Sscottl /* b2: STP initiator port */ 2689285809Sscottl /* b1: SMP initiator port */ 2690285809Sscottl /* b0: reserved */ 2691285809Sscottl bit8 target_ssp_stp_smp; /**< SAS target capabilities */ 2692285809Sscottl /* b4-7: reserved */ 2693285809Sscottl /* b3: SSP target port */ 2694285809Sscottl /* b2: STP target port */ 2695285809Sscottl /* b1: SMP target port */ 2696285809Sscottl /* b0: reserved */ 2697285809Sscottl bit32 numOfPhys; /**< Number of PHYs in the device */ 2698285809Sscottl bit8 phyIdentifier; /**< PHY IDENTIFIER in IDENTIFY address 2699285809Sscottl frame as defined by the SAS 2700285809Sscottl specification. */ 2701285809Sscottl} agsaSASDeviceInfo_t; 2702285809Sscottl 2703285809Sscottl#define SA_SASDEV_SSP_BIT SA_IDFRM_SSP_BIT /* SSP Initiator port */ 2704285809Sscottl#define SA_SASDEV_STP_BIT SA_IDFRM_STP_BIT /* STP Initiator port */ 2705285809Sscottl#define SA_SASDEV_SMP_BIT SA_IDFRM_SMP_BIT /* SMP Initiator port */ 2706285809Sscottl#define SA_SASDEV_SATA_BIT SA_IDFRM_SATA_BIT /* SATA device, valid in the discovery response only */ 2707285809Sscottl 2708285809Sscottl#define SA_SASDEV_IS_SSP_INITIATOR(sasDev) \ 2709285809Sscottl (((sasDev)->initiator_ssp_stp_smp & SA_SASDEV_SSP_BIT) == SA_SASDEV_SSP_BIT) 2710285809Sscottl 2711285809Sscottl#define SA_SASDEV_IS_STP_INITIATOR(sasDev) \ 2712285809Sscottl (((sasDev)->initiator_ssp_stp_smp & SA_SASDEV_STP_BIT) == SA_SASDEV_STP_BIT) 2713285809Sscottl 2714285809Sscottl#define SA_SASDEV_IS_SMP_INITIATOR(sasDev) \ 2715285809Sscottl (((sasDev)->initiator_ssp_stp_smp & SA_SASDEV_SMP_BIT) == SA_SASDEV_SMP_BIT) 2716285809Sscottl 2717285809Sscottl#define SA_SASDEV_IS_SSP_TARGET(sasDev) \ 2718285809Sscottl (((sasDev)->target_ssp_stp_smp & SA_SASDEV_SSP_BIT) == SA_SASDEV_SSP_BIT) 2719285809Sscottl 2720285809Sscottl#define SA_SASDEV_IS_STP_TARGET(sasDev) \ 2721285809Sscottl (((sasDev)->target_ssp_stp_smp & SA_SASDEV_STP_BIT) == SA_SASDEV_STP_BIT) 2722285809Sscottl 2723285809Sscottl#define SA_SASDEV_IS_SMP_TARGET(sasDev) \ 2724285809Sscottl (((sasDev)->target_ssp_stp_smp & SA_SASDEV_SMP_BIT) == SA_SASDEV_SMP_BIT) 2725285809Sscottl 2726285809Sscottl#define SA_SASDEV_IS_SATA_DEVICE(sasDev) \ 2727285809Sscottl (((sasDev)->target_ssp_stp_smp & SA_SASDEV_SATA_BIT) == SA_SASDEV_SATA_BIT) 2728285809Sscottl 2729285809Sscottl 2730285809Sscottl 2731285809Sscottl 2732285809Sscottl/** \brief the data structure describe SG list 2733285809Sscottl * 2734285809Sscottl * the data structure describe SG list 2735285809Sscottl * 2736285809Sscottl */ 2737285809Sscottltypedef struct _SASG_DESCRIPTOR 2738285809Sscottl{ 2739285809Sscottl bit32 sgLower; /**< Lower 32 bits of data area physical address */ 2740285809Sscottl bit32 sgUpper; /**< Upper 32 bits of data area physical address */ 2741285809Sscottl bit32 len; /**< Total data length in bytes */ 2742285809Sscottl} SASG_DESCRIPTOR, * PSASG_DESCRIPTOR; 2743285809Sscottl 2744285809Sscottl/** \brief data structure used to pass information about the scatter-gather list to the LL Layer 2745285809Sscottl * 2746285809Sscottl * The ESGL pages are uncached, have a configurable number of SGL 2747285809Sscottl * of (min, max) = (1, 10), and are 16-byte aligned. Although 2748285809Sscottl * the application can configure the page size, the size must be 2749285809Sscottl * incremented in TBD-byte increments. Refer the hardware 2750285809Sscottl * documentation for more detail on the format of ESGL 2751285809Sscottl * structure. 2752285809Sscottl * 2753285809Sscottl */ 2754285809Sscottltypedef struct agsaSgl_s 2755285809Sscottl{ 2756285809Sscottl bit32 sgLower; /**< Lower 32 bits of data area physical address */ 2757285809Sscottl bit32 sgUpper; /**< Upper 32 bits of data area physical address */ 2758285809Sscottl bit32 len; /**< Total data length in bytes */ 2759285809Sscottl bit32 extReserved; /**< bit31 is for extended sgl list */ 2760285809Sscottl} agsaSgl_t; 2761285809Sscottl 2762285809Sscottl/** \brief data structure is used to pass information about the extended 2763285809Sscottl * scatter-gather list (ESGL) to the LL Layer 2764285809Sscottl * 2765285809Sscottl * The agsaEsgl_t data structure is used to pass information about the 2766285809Sscottl * extended scatter-gather list (ESGL) to the LL Layer. 2767285809Sscottl * 2768285809Sscottl * When ESGL is used, its starting address is specified the first descriptor 2769285809Sscottl * entry (i.e. descriptor[0]) in agsaSgl_t structure. 2770285809Sscottl * 2771285809Sscottl * The ESGL pages are uncached, have a fixed number of SGL of 10, and are 2772285809Sscottl * 16-byte aligned. Refer the hardware documentation for more 2773285809Sscottl * detail on ESGL. 2774285809Sscottl * 2775285809Sscottl */ 2776285809Sscottltypedef struct agsaEsgl_s 2777285809Sscottl{ 2778285809Sscottl agsaSgl_t descriptor[MAX_ESGL_ENTRIES]; 2779285809Sscottl} agsaEsgl_t; 2780285809Sscottl 2781285809Sscottl/** \brief data structure describes an SSP Command INFORMATION UNIT 2782285809Sscottl * 2783285809Sscottl * data structure describes an SSP Command INFORMATION UNIT used for SSP command and is part of 2784285809Sscottl * the SSP frame. 2785285809Sscottl * 2786285809Sscottl * Currently, Additional CDB length is supported to 16 bytes 2787285809Sscottl * 2788285809Sscottl */ 2789285809Sscottl#define MAX_CDB_LEN 32 2790285809Sscottltypedef struct agsaSSPCmdInfoUnitExt_s 2791285809Sscottl{ 2792285809Sscottl bit8 lun[8]; 2793285809Sscottl bit8 reserved1; 2794285809Sscottl bit8 efb_tp_taskAttribute; 2795285809Sscottl bit8 reserved2; 2796285809Sscottl bit8 additionalCdbLen; 2797285809Sscottl bit8 cdb[MAX_CDB_LEN]; 2798285809Sscottl} agsaSSPCmdInfoUnitExt_t ; 2799285809Sscottl 2800285809Sscottl#define DIF_UDT_SIZE 6 2801285809Sscottl 2802285809Sscottl/* difAction in agsaDif_t */ 2803285809Sscottl#define AGSA_DIF_INSERT 0 2804285809Sscottl#define AGSA_DIF_VERIFY_FORWARD 1 2805285809Sscottl#define AGSA_DIF_VERIFY_DELETE 2 2806285809Sscottl#define AGSA_DIF_VERIFY_REPLACE 3 2807285809Sscottl#define AGSA_DIF_VERIFY_UDT_REPLACE_CRC 5 2808285809Sscottl#define AGSA_DIF_REPLACE_UDT_REPLACE_CRC 7 2809285809Sscottl 2810285809Sscottl#define agsaDIFSectorSize512 0 2811285809Sscottl#define agsaDIFSectorSize520 1 2812285809Sscottl#define agsaDIFSectorSize4096 2 2813285809Sscottl#define agsaDIFSectorSize4160 3 2814285809Sscottl 2815285809Sscottl 2816285809Sscottl 2817285809Sscottltypedef struct agsaDif_s 2818285809Sscottl{ 2819285809Sscottl agBOOLEAN enableDIFPerLA; 2820285809Sscottl bit32 flags; 2821285809Sscottl bit16 initialIOSeed; 2822285809Sscottl bit16 reserved; 2823285809Sscottl bit32 DIFPerLAAddrLo; 2824285809Sscottl bit32 DIFPerLAAddrHi; 2825285809Sscottl bit16 DIFPerLARegion0SecCount; 2826285809Sscottl bit16 Reserved2; 2827285809Sscottl bit8 udtArray[DIF_UDT_SIZE]; 2828285809Sscottl bit8 udrtArray[DIF_UDT_SIZE]; 2829285809Sscottl} agsaDif_t; 2830285809Sscottl 2831285809Sscottl 2832285809Sscottl/* From LL SDK2 */ 2833285809Sscottl#define DIF_FLAG_BITS_ACTION 0x00000007 /* 0-2*/ 2834285809Sscottl#define DIF_FLAG_BITS_CRC_VER 0x00000008 /* 3 */ 2835285809Sscottl#define DIF_FLAG_BITS_CRC_INV 0x00000010 /* 4 */ 2836285809Sscottl#define DIF_FLAG_BITS_CRC_SEED 0x00000020 /* 5 */ 2837285809Sscottl#define DIF_FLAG_BITS_UDT_REF_TAG 0x00000040 /* 6 */ 2838285809Sscottl#define DIF_FLAG_BITS_UDT_APP_TAG 0x00000080 /* 7 */ 2839285809Sscottl#define DIF_FLAG_BITS_UDTR_REF_BLKCOUNT 0x00000100 /* 8 */ 2840285809Sscottl#define DIF_FLAG_BITS_UDTR_APP_BLKCOUNT 0x00000200 /* 9 */ 2841285809Sscottl#define DIF_FLAG_BITS_CUST_APP_TAG 0x00000C00 /* 10 11*/ 2842285809Sscottl#define DIF_FLAG_BITS_EPRC 0x00001000 /* 12 */ 2843285809Sscottl#define DIF_FLAG_BITS_Reserved 0x0000E000 /* 13 14 15*/ 2844285809Sscottl#define DIF_FLAG_BITS_BLOCKSIZE_MASK 0x00070000 /* 16 17 18 */ 2845285809Sscottl#define DIF_FLAG_BITS_BLOCKSIZE_SHIFT 16 2846285809Sscottl#define DIF_FLAG_BITS_BLOCKSIZE_512 0x00000000 /* */ 2847285809Sscottl#define DIF_FLAG_BITS_BLOCKSIZE_520 0x00010000 /* 16 */ 2848285809Sscottl#define DIF_FLAG_BITS_BLOCKSIZE_4096 0x00020000 /* 17 */ 2849285809Sscottl#define DIF_FLAG_BITS_BLOCKSIZE_4160 0x00030000 /* 16 17 */ 2850285809Sscottl#define DIF_FLAG_BITS_UDTVMASK 0x03F00000 /* 20 21 22 23 24 25 */ 2851285809Sscottl#define DIF_FLAG_BITS_UDTV_SHIFT 20 2852285809Sscottl#define DIF_FLAG_BITS_UDTUPMASK 0xF6000000 /* 26 27 28 29 30 31 */ 2853285809Sscottl#define DIF_FLAG_BITS_UDTUPSHIFT 26 2854285809Sscottl 2855285809Sscottltypedef struct agsaEncryptDek_s 2856285809Sscottl{ 2857285809Sscottl bit32 dekTable; 2858285809Sscottl bit32 dekIndex; 2859285809Sscottl} agsaEncryptDek_t; 2860285809Sscottl 2861285809Sscottltypedef struct agsaEncrypt_s 2862285809Sscottl{ 2863285809Sscottl agsaEncryptDek_t dekInfo; 2864285809Sscottl bit32 kekIndex; 2865285809Sscottl agBOOLEAN keyTagCheck; 2866285809Sscottl agBOOLEAN enableEncryptionPerLA; /* new */ 2867285809Sscottl bit32 sectorSizeIndex; 2868285809Sscottl bit32 cipherMode; 2869285809Sscottl bit32 keyTag_W0; 2870285809Sscottl bit32 keyTag_W1; 2871285809Sscottl bit32 tweakVal_W0; 2872285809Sscottl bit32 tweakVal_W1; 2873285809Sscottl bit32 tweakVal_W2; 2874285809Sscottl bit32 tweakVal_W3; 2875285809Sscottl bit32 EncryptionPerLAAddrLo; /* new */ 2876285809Sscottl bit32 EncryptionPerLAAddrHi; /* new */ 2877285809Sscottl bit16 EncryptionPerLRegion0SecCount; /* new */ 2878285809Sscottl bit16 reserved; 2879285809Sscottl} agsaEncrypt_t; 2880285809Sscottl 2881285809Sscottl/** \brief data structure describes a SAS SSP command request to be sent to the target device 2882285809Sscottl * 2883285809Sscottl * data structure describes a SAS SSP command request to be sent to the 2884285809Sscottl * target device. This structure limits the CDB length in SSP 2885285809Sscottl * command up to 16 bytes long. 2886285809Sscottl * 2887285809Sscottl * This data structure is one instance of the generic request issued to 2888285809Sscottl * saSSPStart() and is passed as an agsaSASRequestBody_t . 2889285809Sscottl * 2890285809Sscottl */ 2891285809Sscottltypedef struct agsaSSPInitiatorRequest_s 2892285809Sscottl{ 2893285809Sscottl agsaSgl_t agSgl; /**< This structure is used to define either 2894285809Sscottl an ESGL list or a single SGL for the SSP 2895285809Sscottl command operation */ 2896285809Sscottl bit32 dataLength; /**< Total data length in bytes */ 2897285809Sscottl bit16 firstBurstSize; /**< First Burst Size field as defined by 2898285809Sscottl SAS specification */ 2899285809Sscottl bit16 flag; /**< bit1-0 TLR as SAS specification 2900285809Sscottl bit31-2 reserved */ 2901285809Sscottl agsaSSPCmdInfoUnit_t sspCmdIU; /**< Structure containing SSP Command 2902285809Sscottl INFORMATION UNIT */ 2903285809Sscottl agsaDif_t dif; 2904285809Sscottl agsaEncrypt_t encrypt; 2905285809Sscottl#ifdef SA_TESTBASE_EXTRA 2906285809Sscottl /* Added by TestBase */ 2907285809Sscottl bit16 bstIndex; 2908285809Sscottl#endif /* SA_TESTBASE_EXTRA */ 2909285809Sscottl} agsaSSPInitiatorRequest_t; 2910285809Sscottl 2911285809Sscottl/** \brief data structure describes a SAS SSP command request Ext to be sent to the target device 2912285809Sscottl * 2913285809Sscottl * data structure describes a SAS SSP command request to be sent to the 2914285809Sscottl * target device. This structure support the CDB length in SSP 2915285809Sscottl * command more than 16 bytes long. 2916285809Sscottl * 2917285809Sscottl * This data structure is one instance of the generic request issued to 2918285809Sscottl * saSSPStart() and is passed as an agsaSASRequestBody_t . 2919285809Sscottl * 2920285809Sscottl */ 2921285809Sscottltypedef struct agsaSSPInitiatorRequestExt_s 2922285809Sscottl{ 2923285809Sscottl agsaSgl_t agSgl; /**< This structure is used to define either 2924285809Sscottl an ESGL list or a single SGL for the SSP 2925285809Sscottl command operation */ 2926285809Sscottl bit32 dataLength; 2927285809Sscottl bit16 firstBurstSize; 2928285809Sscottl bit16 flag; 2929285809Sscottl agsaSSPCmdInfoUnitExt_t sspCmdIUExt; 2930285809Sscottl agsaDif_t dif; 2931285809Sscottl agsaEncrypt_t encrypt; 2932285809Sscottl} agsaSSPInitiatorRequestExt_t; 2933285809Sscottl 2934285809Sscottl 2935285809Sscottltypedef struct agsaSSPInitiatorRequestIndirect_s 2936285809Sscottl{ 2937285809Sscottl agsaSgl_t agSgl; /**< This structure is used to define either 2938285809Sscottl an ESGL list or a single SGL for the SSP 2939285809Sscottl command operation */ 2940285809Sscottl bit32 dataLength; 2941285809Sscottl bit16 firstBurstSize; 2942285809Sscottl bit16 flag; 2943285809Sscottl bit32 sspInitiatorReqAddrUpper32; /**< The upper 32 bits of the 64-bit physical DMA address of the SSP initiator request buffer */ 2944285809Sscottl bit32 sspInitiatorReqAddrLower32; /**< The lower 32 bits of the 64-bit physical DMA address of the SSP initiator request buffer */ 2945285809Sscottl bit32 sspInitiatorReqLen; /**< Specifies the length of the SSP initiator request in bytes */ 2946285809Sscottl agsaDif_t dif; 2947285809Sscottl agsaEncrypt_t encrypt; 2948285809Sscottl 2949285809Sscottl}agsaSSPInitiatorRequestIndirect_t; 2950285809Sscottl 2951285809Sscottl 2952285809Sscottl 2953285809Sscottl 2954285809Sscottl/** \brief data structure describes a SAS SSP target read and write request 2955285809Sscottl * 2956285809Sscottl * The agsaSSPTargetRequest_t data structure describes a SAS SSP target read 2957285809Sscottl * and write request to be issued on the port. It includes the 2958285809Sscottl * length of the data to be received or sent, an offset into the 2959285809Sscottl * data block where the transfer is to start, and a list of 2960285809Sscottl * scatter-gather buffers. 2961285809Sscottl * 2962285809Sscottl * This data structure is one instance of the generic request issued 2963285809Sscottl * to saSSPStart() and is passed as an agsaSASRequestBody_t . 2964285809Sscottl * 2965285809Sscottl */ 2966285809Sscottl/** bit definitions for sspOption 2967285809Sscottl Bit 0-1: Transport Layer Retry setting for other phase: 2968285809Sscottl 00b: No retry 2969285809Sscottl 01b: Retry on ACK/NAK timeout 2970285809Sscottl 10b: Retry on NAK received 2971285809Sscottl 11b: Retry on both ACK/NAK timeout and NAK received 2972285809Sscottl Bit 2-3: Transport Layer Retry setting for data phase: 2973285809Sscottl 00b: No retry 2974285809Sscottl 01b: Retry on ACK/NAK timeout 2975285809Sscottl 10b: Retry on NAK received 2976285809Sscottl 11b: Retry on both ACK/NAK timeout and NAK received 2977285809Sscottl Bit 4: Retry Data Frame. Valid only on write command. Indicates whether Target supports RTL for this particular IO. 2978285809Sscottl 1b: enabled 2979285809Sscottl 0b: disabled 2980285809Sscottl Bit 5: Auto good response on successful read (data transfer from target to initiator) request. 2981285809Sscottl 1b: Enabled 2982285809Sscottl 0b: Disabled 2983285809Sscottl Bits 6-15 : Reserved. 2984285809Sscottl */ 2985285809Sscottltypedef struct agsaSSPTargetRequest_s 2986285809Sscottl{ 2987285809Sscottl agsaSgl_t agSgl; /**< This structure is used to define either an ESGL list or 2988285809Sscottl a single SGL for the target read or write operation */ 2989285809Sscottl bit32 dataLength; /**< Specifies the amount of data to be sent in this data phase */ 2990285809Sscottl bit32 offset; /**< Specifies the offset into the overall data block 2991285809Sscottl where this data phase is to begin */ 2992285809Sscottl bit16 agTag; /**< Tag from ossaSSPReqReceived(). */ 2993285809Sscottl bit16 sspOption; /**< SSP option for retry */ 2994285809Sscottl agsaDif_t dif; 2995285809Sscottl} agsaSSPTargetRequest_t; 2996285809Sscottl 2997285809Sscottl#define SSP_OPTION_BITS 0x3F /**< bit5-AGR, bit4-RDF bit3,2-RTE, bit1,0-AN */ 2998285809Sscottl#define SSP_OPTION_ODS 0x8000 /**< bit15-ODS */ 2999285809Sscottl 3000285809Sscottl#define SSP_OPTION_OTHR_NO_RETRY 0 3001285809Sscottl#define SSP_OPTION_OTHR_RETRY_ON_ACK_NAK_TIMEOUT 1 3002285809Sscottl#define SSP_OPTION_OTHR_RETRY_ON_NAK_RECEIVED 2 3003285809Sscottl#define SSP_OPTION_OTHR_RETRY_ON_BOTH_ACK_NAK_TIMEOUT_AND_NAK_RECEIVED 3 3004285809Sscottl 3005285809Sscottl#define SSP_OPTION_DATA_NO_RETRY 0 3006285809Sscottl#define SSP_OPTION_DATA_RETRY_ON_ACK_NAK_TIMEOUT 1 3007285809Sscottl#define SSP_OPTION_DATA_RETRY_ON_NAK_RECEIVED 2 3008285809Sscottl#define SSP_OPTION_DATA_RETRY_ON_BOTH_ACK_NAK_TIMEOUT_AND_NAK_RECEIVED 3 3009285809Sscottl 3010285809Sscottl#define SSP_OPTION_RETRY_DATA_FRAME_ENABLED (1 << SHIFT4) 3011285809Sscottl#define SSP_OPTION_AUTO_GOOD_RESPONSE (1 << SHIFT5) 3012285809Sscottl#define SSP_OPTION_ENCRYPT (1 << SHIFT6) 3013285809Sscottl#define SSP_OPTION_DIF (1 << SHIFT7) 3014285809Sscottl#define SSP_OPTION_OVERRIDE_DEVICE_STATE (1 << SHIFT15) 3015285809Sscottl 3016285809Sscottl 3017285809Sscottl/** \brief data structure describes a SAS SSP target response to be issued 3018285809Sscottl * on the port 3019285809Sscottl * 3020285809Sscottl * This data structure is one instance of the generic request issued to 3021285809Sscottl * saSSPStart() and is passed as an agsaSASRequestBody_t 3022285809Sscottl * 3023285809Sscottl */ 3024285809Sscottltypedef struct agsaSSPTargetResponse_s 3025285809Sscottl{ 3026285809Sscottl bit32 agTag; /**< Tag from ossaSSPReqReceived(). */ 3027285809Sscottl void *frameBuf; 3028285809Sscottl bit32 respBufLength; /**< Specifies the length of the Response buffer */ 3029285809Sscottl bit32 respBufUpper; /**< Upper 32 bit of physical address of OS Layer 3030285809Sscottl allocated the Response buffer 3031285809Sscottl (agsaSSPResponseInfoUnit_t). 3032285809Sscottl Valid only when respBufLength is not zero */ 3033285809Sscottl bit32 respBufLower; /**< Lower 32 bit of physical address of OS Layer 3034285809Sscottl allocated the Response buffer 3035285809Sscottl (agsaSSPResponseInfoUnit_t). 3036285809Sscottl Valid only when respBufLength is not zero */ 3037285809Sscottl bit32 respOption; /**< Bit 0-1: ACK and NAK retry option: 3038285809Sscottl 00b: No retry 3039285809Sscottl 01b: Retry on ACK/NAK timeout 3040285809Sscottl 10b: Retry on NAK received 3041285809Sscottl 11b: Retry on both ACK/NAK timeout and NAK received */ 3042285809Sscottl} agsaSSPTargetResponse_t; 3043285809Sscottl 3044285809Sscottl#define RESP_OPTION_BITS 0x3 /** bit0-1 */ 3045285809Sscottl#define RESP_OPTION_ODS 0x8000 /** bit15 */ 3046285809Sscottl 3047285809Sscottl/** \brief data structure describes a SMP request or response frame to be sent on the SAS port 3048285809Sscottl * 3049285809Sscottl * The agsaSMPFrame_t data structure describes a SMP request or response 3050285809Sscottl * frame to be issued or sent on the SAS port. 3051285809Sscottl * 3052285809Sscottl * This data structure is one instance of the generic request issued to 3053285809Sscottl * saSMPStart() and is passed as an agsaSASRequestBody_t . 3054285809Sscottl * 3055285809Sscottl */ 3056285809Sscottltypedef struct agsaSMPFrame_s 3057285809Sscottl{ 3058285809Sscottl void *outFrameBuf; /**< if payload is less than 32 bytes,A virtual 3059285809Sscottl frameBuf can be used. instead of physical 3060285809Sscottl address. Set to NULL and use physical 3061285809Sscottl address if payload is > 32 bytes */ 3062285809Sscottl bit32 outFrameAddrUpper32; /**< The upper 32 bits of the 64-bit physical 3063285809Sscottl DMA address of the SMP frame buffer */ 3064285809Sscottl bit32 outFrameAddrLower32; /**< The lower 32 bits of the 64-bit physical 3065285809Sscottl DMA address of the SMP frame buffer */ 3066285809Sscottl bit32 outFrameLen; /**< Specifies the length of the SMP request 3067285809Sscottl frame excluding the CRC field in bytes */ 3068285809Sscottl bit32 inFrameAddrUpper32; /**< The upper 32 bits of the 64-bit phsical address 3069285809Sscottl of DMA address of response SMP Frame buffer */ 3070285809Sscottl bit32 inFrameAddrLower32; /**< The lower 32 bits of the 64-bit phsical address 3071285809Sscottl of DMA address of response SMP Frame buffer */ 3072285809Sscottl bit32 inFrameLen; /**< Specifies the length of the SMP response 3073285809Sscottl frame excluding the CRC field in bytes */ 3074285809Sscottl bit32 expectedRespLen; /**< Specifies the length of SMP Response */ 3075285809Sscottl bit32 flag; /** For the SPCv controller: 3076285809Sscottl Bit 0: Indirect Response (IR). This indicates 3077285809Sscottl direct or indirect mode for SMP response frame 3078285809Sscottl to be received. 3079285809Sscottl 0b: Direct mode 3080285809Sscottl 1b: Indirect mode 3081285809Sscottl 3082285809Sscottl Bit 1: Indirect Payload (IP). This indicates 3083285809Sscottl direct or indirect mode for SMP request frame 3084285809Sscottl to be sent. 3085285809Sscottl 0b: Direct mode 3086285809Sscottl 1b: Indirect mode 3087285809Sscottl 3088285809Sscottl Bits 2-31: Reserved 3089285809Sscottl For the SPC controller: This is not applicable. 3090285809Sscottl */ 3091285809Sscottl 3092285809Sscottl} agsaSMPFrame_t; 3093285809Sscottl 3094285809Sscottl#define smpFrameFlagDirectResponse 0 3095285809Sscottl#define smpFrameFlagIndirectResponse 1 3096285809Sscottl#define smpFrameFlagDirectPayload 0 3097285809Sscottl#define smpFrameFlagIndirectPayload 2 3098285809Sscottl 3099285809Sscottl/** \brief union data structure specifies a request 3100285809Sscottl * 3101285809Sscottl * union data structure specifies a request 3102285809Sscottl */ 3103285809Sscottltypedef union agsaSASRequestBody_u 3104285809Sscottl{ 3105285809Sscottl agsaSSPInitiatorRequest_t sspInitiatorReq; /**< Structure containing the SSP initiator request, Support up to 16 bytes CDB */ 3106285809Sscottl agsaSSPInitiatorRequestExt_t sspInitiatorReqExt; /**< Structure containing the SSP initiator request for CDB > 16 bytes */ 3107285809Sscottl agsaSSPInitiatorRequestIndirect_t sspInitiatorReqIndirect; /**< Structure containing the SSP indirect initiator request */ 3108285809Sscottl agsaSSPTargetRequest_t sspTargetReq; /**< Structure containing the SSP Target request */ 3109285809Sscottl agsaSSPScsiTaskMgntReq_t sspTaskMgntReq; /**< Structure containing the SSP SCSI Task Management request */ 3110285809Sscottl agsaSSPTargetResponse_t sspTargetResponse; /**< Structure containing the SSP Target response. */ 3111285809Sscottl agsaSMPFrame_t smpFrame; /**< Structure containing SMP request or response frame */ 3112285809Sscottl}agsaSASRequestBody_t; 3113285809Sscottl 3114285809Sscottl 3115285809Sscottl 3116285809Sscottl 3117285809Sscottl/** \brief data structure describes an STP or direct connect SATA command 3118285809Sscottl * 3119285809Sscottl * The agsaSATAInitiatorRequest_t data structure describes an STP or direct 3120285809Sscottl * connect SATA command request to be sent to the device and 3121285809Sscottl * passed as a parameter to saSATAStart() function. 3122285809Sscottl * 3123285809Sscottl * This structure is an encapsulation of SATA FIS (Frame Information 3124285809Sscottl * Structures), which enables the execution of ATA command 3125285809Sscottl * descriptor using SATA transport 3126285809Sscottl * 3127285809Sscottl */ 3128285809Sscottltypedef struct agsaSATAInitiatorRequest_s 3129285809Sscottl{ 3130285809Sscottl agsaSgl_t agSgl; /**< This structure is used to define either an ESGL 3131285809Sscottl list or a single SGL for operation that involves 3132285809Sscottl DMA transfer */ 3133285809Sscottl 3134285809Sscottl bit32 dataLength; /**< Total data length in bytes */ 3135285809Sscottl 3136285809Sscottl bit32 option; /**< Operational option, defined using the bit field. 3137285809Sscottl b7-1: reserved 3138285809Sscottl b0: AGSA-STP-CLOSE-CLEAR-AFFILIATION */ 3139285809Sscottl 3140285809Sscottl agsaSATAHostFis_t fis; /**< The FIS request */ 3141285809Sscottl agsaDif_t dif; 3142285809Sscottl agsaEncrypt_t encrypt; 3143285809Sscottl bit8 scsiCDB[16]; 3144285809Sscottl#ifdef SA_TESTBASE_EXTRA 3145285809Sscottl /* Added by TestBase */ 3146285809Sscottl bit16 bstIndex; 3147285809Sscottl#endif /* SA_TESTBASE_EXTRA */ 3148285809Sscottl} agsaSATAInitiatorRequest_t; 3149285809Sscottl 3150285809Sscottl 3151285809Sscottl/* controller Configuration page */ 3152285809Sscottl#define AGSA_SAS_PROTOCOL_TIMER_CONFIG_PAGE 0x04 3153285809Sscottl#define AGSA_INTERRUPT_CONFIGURATION_PAGE 0x05 3154285809Sscottl#define AGSA_IO_GENERAL_CONFIG_PAGE 0x06 3155285809Sscottl#define AGSA_ENCRYPTION_GENERAL_CONFIG_PAGE 0x20 3156285809Sscottl#define AGSA_ENCRYPTION_DEK_CONFIG_PAGE 0x21 3157285809Sscottl#define AGSA_ENCRYPTION_CONTROL_PARM_PAGE 0x22 3158285809Sscottl#define AGSA_ENCRYPTION_HMAC_CONFIG_PAGE 0x23 3159285809Sscottl 3160285809Sscottl#ifdef HIALEAH_ENCRYPTION 3161285809Sscottltypedef struct agsaEncryptGeneralPage_s { 3162285809Sscottl bit32 numberOfKeksPageCode; /* 0x20 */ 3163285809Sscottl bit32 KeyCardIdKekIndex; 3164285809Sscottl bit32 KeyCardId3_0; 3165285809Sscottl bit32 KeyCardId7_4; 3166285809Sscottl bit32 KeyCardId11_8; 3167285809Sscottl} agsaEncryptGeneralPage_t; 3168285809Sscottl#else 3169285809Sscottltypedef struct agsaEncryptGeneralPage_s { 3170285809Sscottl bit32 pageCode; /* 0x20 */ 3171285809Sscottl bit32 numberOfDeks; 3172285809Sscottl} agsaEncryptGeneralPage_t; 3173285809Sscottl#endif /* HIALEAH_ENCRYPTION */ 3174285809Sscottl 3175285809Sscottl#define AGSA_ENC_CONFIG_PAGE_KEK_NUMBER 0x0000FF00 3176285809Sscottl#define AGSA_ENC_CONFIG_PAGE_KEK_SHIFT 8 3177285809Sscottl 3178285809Sscottl/* sTSDK 4.14 */ 3179285809Sscottltypedef struct agsaEncryptDekConfigPage_s { 3180285809Sscottl bit32 pageCode; 3181285809Sscottl bit32 table0AddrLo; 3182285809Sscottl bit32 table0AddrHi; 3183285809Sscottl bit32 table0Entries; 3184285809Sscottl bit32 table0BFES; 3185285809Sscottl bit32 table1AddrLo; 3186285809Sscottl bit32 table1AddrHi; 3187285809Sscottl bit32 table1Entries; 3188285809Sscottl bit32 table1BFES; 3189285809Sscottl} agsaEncryptDekConfigPage_t; 3190285809Sscottl 3191285809Sscottl#define AGSA_ENC_DEK_CONFIG_PAGE_DEK_TABLE_NUMBER 0xF0000000 3192285809Sscottl#define AGSA_ENC_DEK_CONFIG_PAGE_DEK_TABLE_SHIFT SHIFT28 3193285809Sscottl#define AGSA_ENC_DEK_CONFIG_PAGE_DEK_CACHE_WAY 0x0F000000 3194285809Sscottl#define AGSA_ENC_DEK_CONFIG_PAGE_DEK_CACHE_SHIFT SHIFT24 3195285809Sscottl 3196285809Sscottl/*sTSDK 4.18 */ 3197285809Sscottl/* CCS (Current Crypto Services) and NOPR (Number of Operators) are valid only in GET_CONTROLLER_CONFIG */ 3198285809Sscottl/* NAR, CORCAP and USRCAP are valid only when AUT==1 */ 3199285809Sscottltypedef struct agsaEncryptControlParamPage_s { 3200285809Sscottl bit32 pageCode; /* 0x22 */ 3201285809Sscottl bit32 CORCAP; /* Crypto Officer Role Capabilities */ 3202285809Sscottl bit32 USRCAP; /* User Role Capabilities */ 3203285809Sscottl bit32 CCS; /* Current Crypto Services */ 3204285809Sscottl bit32 NOPR; /* Number of Operators */ 3205285809Sscottl} agsaEncryptControlParamPage_t; 3206285809Sscottl 3207285809Sscottltypedef struct agsaEncryptInfo_s { 3208285809Sscottl bit32 encryptionCipherMode; 3209285809Sscottl bit32 encryptionSecurityMode; 3210285809Sscottl bit32 status; 3211285809Sscottl bit32 flag; 3212285809Sscottl} agsaEncryptInfo_t; 3213285809Sscottl 3214285809Sscottl 3215285809Sscottl#define OperatorAuthenticationEnable_AUT 1 3216285809Sscottl#define ReturnToFactoryMode_ARF 2 3217285809Sscottl 3218285809Sscottl/*sTSDK 4.19 */ 3219285809Sscottltypedef struct agsaEncryptSelfTestBitMap_s { 3220285809Sscottl bit32 AES_Test; 3221285809Sscottl bit32 KEY_WRAP_Test; 3222285809Sscottl bit32 HMAC_Test; 3223285809Sscottl} agsaEncryptSelfTestBitMap_t; 3224285809Sscottl 3225285809Sscottltypedef struct agsaEncryptSelfTestStatusBitMap_s{ 3226285809Sscottl bit32 AES_Status; 3227285809Sscottl bit32 KEY_WRAP_Status; 3228285809Sscottl bit32 HMAC_Status; 3229285809Sscottl} agsaEncryptSelfTestStatusBitMap_t; 3230285809Sscottl 3231285809Sscottltypedef struct agsaEncryptHMACTestDescriptor_s 3232285809Sscottl{ 3233285809Sscottl bit32 Dword0; 3234285809Sscottl bit32 MsgAddrLo; 3235285809Sscottl bit32 MsgAddrHi; 3236285809Sscottl bit32 MsgLen; 3237285809Sscottl bit32 DigestAddrLo; 3238285809Sscottl bit32 DigestAddrHi; 3239285809Sscottl bit32 KeyAddrLo; 3240285809Sscottl bit32 KeyAddrHi; 3241285809Sscottl bit32 KeyLen; 3242285809Sscottl} agsaEncryptHMACTestDescriptor_t; 3243285809Sscottl 3244285809Sscottltypedef struct agsaEncryptHMACTestResult_s 3245285809Sscottl{ 3246285809Sscottl bit32 Dword0; 3247285809Sscottl bit32 Dword[12]; 3248285809Sscottl} agsaEncryptHMACTestResult_t; 3249285809Sscottl 3250285809Sscottltypedef struct agsaEncryptSHATestDescriptor_s 3251285809Sscottl{ 3252285809Sscottl bit32 Dword0; 3253285809Sscottl bit32 MsgAddrLo; 3254285809Sscottl bit32 MsgAddrHi; 3255285809Sscottl bit32 MsgLen; 3256285809Sscottl bit32 DigestAddrLo; 3257285809Sscottl bit32 DigestAddrHi; 3258285809Sscottl} agsaEncryptSHATestDescriptor_t; 3259285809Sscottl 3260285809Sscottltypedef struct agsaEncryptSHATestResult_s 3261285809Sscottl{ 3262285809Sscottl bit32 Dword0; 3263285809Sscottl bit32 Dword[12]; 3264285809Sscottl} agsaEncryptSHATestResult_t; 3265285809Sscottl 3266285809Sscottl/* types of self test */ 3267285809Sscottl#define AGSA_BIST_TEST 0x1 3268285809Sscottl#define AGSA_HMAC_TEST 0x2 3269285809Sscottl#define AGSA_SHA_TEST 0x3 3270285809Sscottl 3271285809Sscottl 3272285809Sscottl/*sTSDK 4.13 */ 3273285809Sscottltypedef struct agsaEncryptDekBlob_s { 3274285809Sscottl bit8 dekBlob[80]; 3275285809Sscottl} agsaEncryptDekBlob_t; 3276285809Sscottl 3277285809Sscottltypedef struct agsaEncryptKekBlob_s { 3278285809Sscottl bit8 kekBlob[48]; 3279285809Sscottl} agsaEncryptKekBlob_t; 3280285809Sscottl 3281285809Sscottl/*sTSDK 4.45 */ 3282285809Sscottltypedef struct agsaEncryptHMACConfigPage_s 3283285809Sscottl{ 3284285809Sscottl bit32 PageCode; 3285285809Sscottl bit32 CustomerTag; 3286285809Sscottl bit32 KeyAddrLo; 3287285809Sscottl bit32 KeyAddrHi; 3288285809Sscottl} agsaEncryptHMACConfigPage_t; 3289285809Sscottl 3290285809Sscottl/*sTSDK 4.38 */ 3291285809Sscottl#define AGSA_ID_SIZE 31 3292285809Sscottltypedef struct agsaID_s { 3293285809Sscottl bit8 ID[AGSA_ID_SIZE]; 3294285809Sscottl}agsaID_t; 3295285809Sscottl 3296285809Sscottl 3297285809Sscottl#define SA_OPR_MGMNT_FLAG_MASK 0x00003000 3298285809Sscottl#define SA_OPR_MGMNT_FLAG_SHIFT 12 3299285809Sscottl 3300285809Sscottl/* */ 3301285809Sscottltypedef struct agsaSASPhyMiscPage_s { 3302285809Sscottl bit32 Dword0; 3303285809Sscottl bit32 Dword1; 3304285809Sscottl} agsaSASPhyMiscPage_t ; 3305285809Sscottl 3306285809Sscottl 3307285809Sscottltypedef struct agsaHWEventEncrypt_s { 3308285809Sscottl bit32 encryptOperation; 3309285809Sscottl bit32 status; 3310285809Sscottl bit32 eq; /* error qualifier */ 3311285809Sscottl bit32 info; 3312285809Sscottl void *handle; 3313285809Sscottl void *param; 3314285809Sscottl} agsaHWEventEncrypt_t; 3315285809Sscottl 3316285809Sscottl/*sTSDK 4.32 */ 3317285809Sscottltypedef struct agsaHWEventMode_s { 3318285809Sscottl bit32 modePageOperation; 3319285809Sscottl bit32 status; 3320285809Sscottl bit32 modePageLen; 3321285809Sscottl void *modePage; 3322285809Sscottl void *context; 3323285809Sscottl} agsaHWEventMode_t; 3324285809Sscottl 3325285809Sscottl/*sTSDK 4.33 */ 3326285809Sscottltypedef struct agsaInterruptConfigPage_s { 3327285809Sscottl bit32 pageCode; 3328285809Sscottl bit32 vectorMask0; 3329285809Sscottl bit32 vectorMask1; 3330285809Sscottl bit32 ICTC0; 3331285809Sscottl bit32 ICTC1; 3332285809Sscottl bit32 ICTC2; 3333285809Sscottl bit32 ICTC3; 3334285809Sscottl bit32 ICTC4; 3335285809Sscottl bit32 ICTC5; 3336285809Sscottl bit32 ICTC6; 3337285809Sscottl bit32 ICTC7; 3338285809Sscottl} agsaInterruptConfigPage_t; 3339285809Sscottltypedef struct agsaIoGeneralPage_s { 3340285809Sscottl bit32 pageCode; /* 0x06 */ 3341285809Sscottl bit32 ActiveMask; 3342285809Sscottl bit32 QrntTime; 3343285809Sscottl} agsaIoGeneralPage_t; 3344285809Sscottl 3345285809Sscottl/* \brief data structure defines detail information about Agilent Error 3346285809Sscottl* Detection Code (DIF) errors. 3347285809Sscottl* 3348285809Sscottl* The agsaDifDetails_t data structure defines detail information about 3349285809Sscottl* PMC Error Detection Code (DIF) error. Please refer to the latest T10 SBC 3350285809Sscottl* and SPC draft/specification for the definition of the Protection 3351285809Sscottl* Information. 3352285809Sscottl* 3353285809Sscottl* This structure is filled by the function saGetDifErrorDetails(). 3354285809Sscottl*/ 3355285809Sscottl 3356285809Sscottltypedef struct agsaDifDetails_s { 3357285809Sscottl bit32 UpperLBA; 3358285809Sscottl bit32 LowerLBA; 3359285809Sscottl bit8 sasAddressHi[4]; 3360285809Sscottl bit8 sasAddressLo[4]; 3361285809Sscottl bit32 ExpectedCRCUDT01; 3362285809Sscottl bit32 ExpectedUDT2345; 3363285809Sscottl bit32 ActualCRCUDT01; 3364285809Sscottl bit32 ActualUDT2345; 3365285809Sscottl bit32 DIFErrDevID; 3366285809Sscottl bit32 ErrBoffsetEDataLen; 3367285809Sscottl void * frame; 3368285809Sscottl} agsaDifDetails_t; 3369285809Sscottl 3370285809Sscottl/** \brief data structure for SAS protocol timer configuration page. 3371285809Sscottl * 3372285809Sscottl */ 3373285809Sscottltypedef struct agsaSASProtocolTimerConfigurationPage_s{ 3374285809Sscottl bit32 pageCode; /* 0 */ 3375285809Sscottl bit32 MST_MSI; /* 1 */ 3376285809Sscottl bit32 STP_SSP_MCT_TMO; /* 2 */ 3377285809Sscottl bit32 STP_FRM_TMO; /* 3 */ 3378285809Sscottl bit32 STP_IDLE_TMO; /* 4 */ 3379285809Sscottl bit32 OPNRJT_RTRY_INTVL; /* 5 */ 3380285809Sscottl bit32 Data_Cmd_OPNRJT_RTRY_TMO; /* 6 */ 3381285809Sscottl bit32 Data_Cmd_OPNRJT_RTRY_THR; /* 7 */ 3382285809Sscottl bit32 MAX_AIP; /* 8 */ 3383285809Sscottl} agsaSASProtocolTimerConfigurationPage_t; 3384285809Sscottl 3385285809Sscottl 3386285809Sscottl/** \brief data structure for firmware flash update saFwFlashUpdate(). 3387285809Sscottl * 3388285809Sscottl * The agsaUpdateFwFlash data structure specifies a request to saFwFlashUpdate() 3389285809Sscottl */ 3390285809Sscottltypedef struct agsaUpdateFwFlash_s 3391285809Sscottl{ 3392285809Sscottl bit32 currentImageOffset; 3393285809Sscottl bit32 currentImageLen; 3394285809Sscottl bit32 totalImageLen; 3395285809Sscottl agsaSgl_t agSgl; 3396285809Sscottl} agsaUpdateFwFlash_t; 3397285809Sscottl 3398285809Sscottl 3399285809Sscottl 3400285809Sscottl/** \brief data structure for extended firmware flash update saFwFlashExtUpdate(). 3401285809Sscottl * 3402285809Sscottl * The agsaFlashExtExecute_s data structure specifies a request to saFwFlashExtUpdate() 3403285809Sscottl */ 3404285809Sscottltypedef struct agsaFlashExtExecute_s 3405285809Sscottl{ 3406285809Sscottl bit32 command; 3407285809Sscottl bit32 partOffset; 3408285809Sscottl bit32 dataLen; 3409285809Sscottl agsaSgl_t *agSgl; 3410285809Sscottl} agsaFlashExtExecute_t; 3411285809Sscottl 3412285809Sscottl 3413285809Sscottl/** \brief data structure for firmware flash update saFwFlashUpdate(). 3414285809Sscottl * 3415285809Sscottl * The agsaFlashExtResponse_t data structure specifies a request to ossaFlashExtExecuteCB().() 3416285809Sscottl */ 3417285809Sscottltypedef struct agsaFlashExtResponse_s 3418285809Sscottl{ 3419285809Sscottl bit32 epart_size; 3420285809Sscottl bit32 epart_sect_size; 3421285809Sscottl} agsaFlashExtResponse_t; 3422285809Sscottl 3423285809Sscottl 3424285809Sscottl/** \brief data structure for set fields in MPI table. 3425285809Sscottl * The agsaMPIContext_t data structure is used to set fields in MPI table. 3426285809Sscottl * For details of MPI table, refer to PM8001 Tachyon SPC 8x6G Programmers' 3427285809Sscottl * Manual PMC-2080222 or PM8008/PM8009/PM8018 Tachyon SPCv/SPCve/SPCv+ Programmers Manual 3428285809Sscottl * PMC-2091148/PMC-2102373. 3429285809Sscottl sTSDK section 4.39 3430285809Sscottl */ 3431285809Sscottl 3432285809Sscottltypedef struct agsaMPIContext_s 3433285809Sscottl{ 3434285809Sscottl bit32 MPITableType; 3435285809Sscottl bit32 offset; 3436285809Sscottl bit32 value; 3437285809Sscottl} agsaMPIContext_t; 3438285809Sscottl 3439285809Sscottl#define AGSA_MPI_MAIN_CONFIGURATION_TABLE 1 3440285809Sscottl#define AGSA_MPI_GENERAL_STATUS_TABLE 2 3441285809Sscottl#define AGSA_MPI_INBOUND_QUEUE_CONFIGURATION_TABLE 3 3442285809Sscottl#define AGSA_MPI_OUTBOUND_QUEUE_CONFIGURATION_TABLE 4 3443285809Sscottl#define AGSA_MPI_SAS_PHY_ANALOG_SETUP_TABLE 5 3444285809Sscottl#define AGSA_MPI_INTERRUPT_VECTOR_TABLE 6 3445285809Sscottl#define AGSA_MPI_PER_SAS_PHY_ATTRIBUTE_TABLE 7 3446285809Sscottl#define AGSA_MPI_OUTBOUND_QUEUE_FAILOVER_TABLE 8 3447285809Sscottl 3448285809Sscottl 3449285809Sscottl/************************************************************/ 3450285809Sscottl/*This flag and datastructure are specific for fw profiling, Now defined as compiler flag*/ 3451285809Sscottl//#define SPC_ENABLE_PROFILE 3452285809Sscottl 3453285809Sscottl#ifdef SPC_ENABLE_PROFILE 3454285809Sscottltypedef struct agsaFwProfile_s 3455285809Sscottl{ 3456285809Sscottl bit32 tcid; 3457285809Sscottl bit32 processor; 3458285809Sscottl bit32 cmd; 3459285809Sscottl bit32 len; 3460285809Sscottl bit32 codeStartAdd; 3461285809Sscottl bit32 codeEndAdd; 3462285809Sscottl agsaSgl_t agSgl; 3463285809Sscottl} agsaFwProfile_t; 3464285809Sscottl#endif 3465285809Sscottl/************************************************************/ 3466285809Sscottl/** \brief Callback definition for .ossaDeviceRegistration 3467285809Sscottl * 3468285809Sscottl */ 3469285809Sscottltypedef void (*ossaDeviceRegistrationCB_t)( 3470285809Sscottl agsaRoot_t *agRoot, 3471285809Sscottl agsaContext_t *agContext, 3472285809Sscottl bit32 status, 3473285809Sscottl agsaDevHandle_t *agDevHandle, 3474285809Sscottl bit32 deviceID 3475285809Sscottl ); 3476285809Sscottl 3477285809Sscottl/** \brief Callback definition for 3478285809Sscottl * 3479285809Sscottl */ 3480285809Sscottltypedef void (*ossaDeregisterDeviceHandleCB_t)( 3481285809Sscottl agsaRoot_t *agRoot, 3482285809Sscottl agsaContext_t *agContext, 3483285809Sscottl agsaDevHandle_t *agDevHandle, 3484285809Sscottl bit32 status 3485285809Sscottl ); 3486285809Sscottl 3487285809Sscottl/** \brief Callback definition for 3488285809Sscottl * 3489285809Sscottl */ 3490285809Sscottltypedef void (*ossaGenericCB_t)(void); 3491285809Sscottl 3492285809Sscottl 3493285809Sscottl/** \brief Callback definition for abort SMP SSP SATA callback 3494285809Sscottl * 3495285809Sscottl */ 3496285809Sscottltypedef void (*ossaGenericAbortCB_t)( 3497285809Sscottl agsaRoot_t *agRoot, 3498285809Sscottl agsaIORequest_t *agIORequest, 3499285809Sscottl bit32 flag, 3500285809Sscottl bit32 status 3501285809Sscottl ); 3502285809Sscottl 3503285809Sscottl 3504285809Sscottltypedef void (*ossaLocalPhyControlCB_t)( 3505285809Sscottl agsaRoot_t *agRoot, 3506285809Sscottl agsaContext_t *agContext, 3507285809Sscottl bit32 phyId, 3508285809Sscottl bit32 phyOperation, 3509285809Sscottl bit32 status, 3510285809Sscottl void *parm 3511285809Sscottl ); 3512285809Sscottl 3513285809Sscottl 3514285809Sscottl/** \brief Callback definition for 3515285809Sscottl * 3516285809Sscottl */ 3517285809Sscottltypedef void (*ossaSATACompletedCB_t)( 3518285809Sscottl agsaRoot_t *agRoot, 3519285809Sscottl agsaIORequest_t *agIORequest, 3520285809Sscottl bit32 agIOStatus, 3521285809Sscottl void *agFirstDword, 3522285809Sscottl bit32 agIOInfoLen, 3523285809Sscottl void *agParam 3524285809Sscottl ); 3525285809Sscottl 3526285809Sscottl 3527285809Sscottl/** \brief Callback definition for 3528285809Sscottl * 3529285809Sscottl */ 3530285809Sscottltypedef void (*ossaSMPCompletedCB_t)( 3531285809Sscottl agsaRoot_t *agRoot, 3532285809Sscottl agsaIORequest_t *agIORequest, 3533285809Sscottl bit32 agIOStatus, 3534285809Sscottl bit32 agIOInfoLen, 3535285809Sscottl agsaFrameHandle_t agFrameHandle 3536285809Sscottl ); 3537285809Sscottl 3538285809Sscottl 3539285809Sscottl/** \brief Callback definition for 3540285809Sscottl * 3541285809Sscottl */ 3542285809Sscottltypedef void (*ossaSSPCompletedCB_t)( 3543285809Sscottl agsaRoot_t *agRoot, 3544285809Sscottl agsaIORequest_t *agIORequest, 3545285809Sscottl bit32 agIOStatus, 3546285809Sscottl bit32 agIOInfoLen, 3547285809Sscottl void *agParam, 3548285809Sscottl bit16 sspTag, 3549285809Sscottl bit32 agOtherInfo 3550285809Sscottl ); 3551285809Sscottl 3552285809Sscottl/** \brief Callback definition for 3553285809Sscottl * 3554285809Sscottl */ 3555285809Sscottltypedef void (*ossaSetDeviceInfoCB_t) ( 3556285809Sscottl agsaRoot_t *agRoot, 3557285809Sscottl agsaContext_t *agContext, 3558285809Sscottl agsaDevHandle_t *agDevHandle, 3559285809Sscottl bit32 status, 3560285809Sscottl bit32 option, 3561285809Sscottl bit32 param 3562285809Sscottl ); 3563285809Sscottl 3564285809Sscottltypedef struct agsaOffloadDifDetails_s 3565285809Sscottl{ 3566285809Sscottl bit32 ExpectedCRCUDT01; 3567285809Sscottl bit32 ExpectedUDT2345; 3568285809Sscottl bit32 ActualCRCUDT01; 3569285809Sscottl bit32 ActualUDT2345; 3570285809Sscottl bit32 DIFErr; 3571285809Sscottl bit32 ErrBoffset; 3572285809Sscottl} agsaOffloadDifDetails_t; 3573285809Sscottl 3574285809Sscottltypedef struct agsaDifEncPayload_s 3575285809Sscottl{ 3576285809Sscottl agsaSgl_t SrcSgl; 3577285809Sscottl bit32 SrcDL; 3578285809Sscottl agsaSgl_t DstSgl; 3579285809Sscottl bit32 DstDL; 3580285809Sscottl agsaDif_t dif; 3581285809Sscottl agsaEncrypt_t encrypt; 3582285809Sscottl} agsaDifEncPayload_t; 3583285809Sscottl 3584285809Sscottltypedef void (*ossaVhistCaptureCB_t) ( 3585285809Sscottl agsaRoot_t *agRoot, 3586285809Sscottl agsaContext_t *agContext, 3587285809Sscottl bit32 status, 3588285809Sscottl bit32 len); 3589285809Sscottl 3590285809Sscottltypedef void (*ossaDIFEncryptionOffloadStartCB_t) ( 3591285809Sscottl agsaRoot_t *agRoot, 3592285809Sscottl agsaContext_t *agContext, 3593285809Sscottl bit32 status, 3594285809Sscottl agsaOffloadDifDetails_t *agsaOffloadDifDetails 3595285809Sscottl ); 3596285809Sscottl 3597285809Sscottl#define SA_RESERVED_REQUEST_COUNT 16 3598285809Sscottl 3599285809Sscottl#ifdef SA_FW_TIMER_READS_STATUS 3600285809Sscottl#define SA_FW_TIMER_READS_STATUS_INTERVAL 20 3601285809Sscottl#endif /* SA_FW_TIMER_READS_STATUS */ 3602285809Sscottl 3603285809Sscottl#define SIZE_DW 4 /**< Size in bytes */ 3604285809Sscottl#define SIZE_QW 8 /**< Size in bytes */ 3605285809Sscottl 3606285809Sscottl#define PCIBAR0 0 /**< PCI Base Address 0 */ 3607285809Sscottl#define PCIBAR1 1 /**< PCI Base Address 1 */ 3608285809Sscottl#define PCIBAR2 2 /**< PCI Base Address 2 */ 3609285809Sscottl#define PCIBAR3 3 /**< PCI Base Address 3 */ 3610285809Sscottl#define PCIBAR4 4 /**< PCI Base Address 4 */ 3611285809Sscottl#define PCIBAR5 5 /**< PCI Base Address 5 */ 3612285809Sscottl 3613285809Sscottl/** \brief describe an element of SPC-SPCV converter 3614285809Sscottl * 3615285809Sscottl * This structure is used 3616285809Sscottl * 3617285809Sscottl */ 3618285809Sscottltypedef struct agsaBarOffset_s 3619285809Sscottl{ 3620285809Sscottl bit32 Generic; /* */ 3621285809Sscottl bit32 Bar; /* */ 3622285809Sscottl bit32 Offset; /* */ 3623285809Sscottl bit32 Length; /* */ 3624285809Sscottl} agsaBarOffset_t; 3625285809Sscottl 3626285809Sscottltypedef union agsabit32bit64_U 3627285809Sscottl{ 3628285809Sscottl bit32 S32[2]; 3629285809Sscottl bit64 B64; 3630285809Sscottl} agsabit32bit64; 3631285809Sscottl 3632285809Sscottl/* 3633285809SscottlThe agsaIOErrorEventStats_t data structure is used as parameter in ossaGetIOErrorStatsCB(),ossaGetIOEventStatsCB(). 3634285809SscottlThis data structure contains the number of IO error and event. 3635285809Sscottl*/ 3636285809Sscottltypedef struct agsaIOErrorEventStats_s 3637285809Sscottl{ 3638285809Sscottl bit32 agOSSA_IO_COMPLETED_ERROR_SCSI_STATUS; 3639285809Sscottl bit32 agOSSA_IO_ABORTED; 3640285809Sscottl bit32 agOSSA_IO_OVERFLOW; 3641285809Sscottl bit32 agOSSA_IO_UNDERFLOW; 3642285809Sscottl bit32 agOSSA_IO_FAILED; 3643285809Sscottl bit32 agOSSA_IO_ABORT_RESET; 3644285809Sscottl bit32 agOSSA_IO_NOT_VALID; 3645285809Sscottl bit32 agOSSA_IO_NO_DEVICE; 3646285809Sscottl bit32 agOSSA_IO_ILLEGAL_PARAMETER; 3647285809Sscottl bit32 agOSSA_IO_LINK_FAILURE; 3648285809Sscottl bit32 agOSSA_IO_PROG_ERROR; 3649285809Sscottl bit32 agOSSA_IO_DIF_IN_ERROR; 3650285809Sscottl bit32 agOSSA_IO_DIF_OUT_ERROR; 3651285809Sscottl bit32 agOSSA_IO_ERROR_HW_TIMEOUT; 3652285809Sscottl bit32 agOSSA_IO_XFER_ERROR_BREAK; 3653285809Sscottl bit32 agOSSA_IO_XFER_ERROR_PHY_NOT_READY; 3654285809Sscottl bit32 agOSSA_IO_OPEN_CNX_ERROR_PROTOCOL_NOT_SUPPORTED; 3655285809Sscottl bit32 agOSSA_IO_OPEN_CNX_ERROR_ZONE_VIOLATION; 3656285809Sscottl bit32 agOSSA_IO_OPEN_CNX_ERROR_BREAK; 3657285809Sscottl bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS; 3658285809Sscottl bit32 agOSSA_IO_OPEN_CNX_ERROR_BAD_DESTINATION; 3659285809Sscottl bit32 agOSSA_IO_OPEN_CNX_ERROR_CONNECTION_RATE_NOT_SUPPORTED; 3660285809Sscottl bit32 agOSSA_IO_OPEN_CNX_ERROR_STP_RESOURCES_BUSY; 3661285809Sscottl bit32 agOSSA_IO_OPEN_CNX_ERROR_WRONG_DESTINATION; 3662285809Sscottl bit32 agOSSA_IO_OPEN_CNX_ERROR_UNKNOWN_ERROR; 3663285809Sscottl bit32 agOSSA_IO_XFER_ERROR_NAK_RECEIVED; 3664285809Sscottl bit32 agOSSA_IO_XFER_ERROR_ACK_NAK_TIMEOUT; 3665285809Sscottl bit32 agOSSA_IO_XFER_ERROR_PEER_ABORTED; 3666285809Sscottl bit32 agOSSA_IO_XFER_ERROR_RX_FRAME; 3667285809Sscottl bit32 agOSSA_IO_XFER_ERROR_DMA; 3668285809Sscottl bit32 agOSSA_IO_XFER_ERROR_CREDIT_TIMEOUT; 3669285809Sscottl bit32 agOSSA_IO_XFER_ERROR_SATA_LINK_TIMEOUT; 3670285809Sscottl bit32 agOSSA_IO_XFER_ERROR_SATA; 3671285809Sscottl bit32 agOSSA_IO_XFER_ERROR_ABORTED_DUE_TO_SRST; 3672285809Sscottl bit32 agOSSA_IO_XFER_ERROR_REJECTED_NCQ_MODE; 3673285809Sscottl bit32 agOSSA_IO_XFER_ERROR_ABORTED_NCQ_MODE; 3674285809Sscottl bit32 agOSSA_IO_XFER_OPEN_RETRY_TIMEOUT; 3675285809Sscottl bit32 agOSSA_IO_XFER_SMP_RESP_CONNECTION_ERROR; 3676285809Sscottl bit32 agOSSA_IO_XFER_ERROR_UNEXPECTED_PHASE; 3677285809Sscottl bit32 agOSSA_IO_XFER_ERROR_XFER_RDY_OVERRUN; 3678285809Sscottl bit32 agOSSA_IO_XFER_ERROR_XFER_RDY_NOT_EXPECTED; 3679285809Sscottl bit32 agOSSA_IO_XFER_ERROR_CMD_ISSUE_ACK_NAK_TIMEOUT; 3680285809Sscottl bit32 agOSSA_IO_XFER_ERROR_CMD_ISSUE_BREAK_BEFORE_ACK_NAK; 3681285809Sscottl bit32 agOSSA_IO_XFER_ERROR_CMD_ISSUE_PHY_DOWN_BEFORE_ACK_NAK; 3682285809Sscottl bit32 agOSSA_IO_XFER_ERROR_OFFSET_MISMATCH; 3683285809Sscottl bit32 agOSSA_IO_XFER_ERROR_XFER_ZERO_DATA_LEN; 3684285809Sscottl bit32 agOSSA_IO_XFER_CMD_FRAME_ISSUED; 3685285809Sscottl bit32 agOSSA_IO_ERROR_INTERNAL_SMP_RESOURCE; 3686285809Sscottl bit32 agOSSA_IO_PORT_IN_RESET; 3687285809Sscottl bit32 agOSSA_IO_DS_NON_OPERATIONAL; 3688285809Sscottl bit32 agOSSA_IO_DS_IN_RECOVERY; 3689285809Sscottl bit32 agOSSA_IO_TM_TAG_NOT_FOUND; 3690285809Sscottl bit32 agOSSA_IO_XFER_PIO_SETUP_ERROR; 3691285809Sscottl bit32 agOSSA_IO_SSP_EXT_IU_ZERO_LEN_ERROR; 3692285809Sscottl bit32 agOSSA_IO_DS_IN_ERROR; 3693285809Sscottl bit32 agOSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY; 3694285809Sscottl bit32 agOSSA_IO_ABORT_IN_PROGRESS; 3695285809Sscottl bit32 agOSSA_IO_ABORT_DELAYED; 3696285809Sscottl bit32 agOSSA_IO_INVALID_LENGTH; 3697285809Sscottl bit32 agOSSA_IO_OPEN_CNX_ERROR_HW_RESOURCE_BUSY_ALT; 3698285809Sscottl bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_RETRY_BACKOFF_THRESHOLD_REACHED; 3699285809Sscottl bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_TMO; 3700285809Sscottl bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_NO_DEST; 3701285809Sscottl bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_OPEN_COLLIDE; 3702285809Sscottl bit32 agOSSA_IO_OPEN_CNX_ERROR_IT_NEXUS_LOSS_PATHWAY_BLOCKED; 3703285809Sscottl bit32 agOSSA_IO_DS_INVALID; 3704285809Sscottl bit32 agOSSA_IO_XFER_READ_COMPL_ERR; 3705285809Sscottl bit32 agOSSA_IO_XFER_ERR_LAST_PIO_DATAIN_CRC_ERR; 3706285809Sscottl bit32 agOSSA_IO_XFR_ERROR_INTERNAL_CRC_ERROR; 3707285809Sscottl bit32 agOSSA_MPI_IO_RQE_BUSY_FULL; 3708285809Sscottl bit32 agOSSA_MPI_ERR_IO_RESOURCE_UNAVAILABLE; 3709285809Sscottl bit32 agOSSA_MPI_ERR_ATAPI_DEVICE_BUSY; 3710285809Sscottl bit32 agOSSA_IO_XFR_ERROR_DEK_KEY_CACHE_MISS; 3711285809Sscottl bit32 agOSSA_IO_XFR_ERROR_DEK_KEY_TAG_MISMATCH; 3712285809Sscottl bit32 agOSSA_IO_XFR_ERROR_CIPHER_MODE_INVALID; 3713285809Sscottl bit32 agOSSA_IO_XFR_ERROR_DEK_IV_MISMATCH; 3714285809Sscottl bit32 agOSSA_IO_XFR_ERROR_DEK_RAM_INTERFACE_ERROR; 3715285809Sscottl bit32 agOSSA_IO_XFR_ERROR_INTERNAL_RAM; 3716285809Sscottl bit32 agOSSA_IO_XFR_ERROR_DIF_MISMATCH; 3717285809Sscottl bit32 agOSSA_IO_XFR_ERROR_DIF_APPLICATION_TAG_MISMATCH; 3718285809Sscottl bit32 agOSSA_IO_XFR_ERROR_DIF_REFERENCE_TAG_MISMATCH; 3719285809Sscottl bit32 agOSSA_IO_XFR_ERROR_DIF_CRC_MISMATCH; 3720285809Sscottl bit32 agOSSA_IO_XFR_ERROR_INVALID_SSP_RSP_FRAME; 3721285809Sscottl bit32 agOSSA_IO_XFER_ERR_EOB_DATA_OVERRUN; 3722285809Sscottl bit32 agOSSA_IO_XFR_ERROR_DEK_INDEX_OUT_OF_BOUNDS; 3723285809Sscottl bit32 agOSSA_IO_OPEN_CNX_ERROR_OPEN_PREEMPTED; 3724285809Sscottl bit32 agOSSA_IO_XFR_ERROR_DEK_ILLEGAL_TABLE; 3725285809Sscottl bit32 agOSSA_IO_XFER_ERROR_DIF_INTERNAL_ERROR; 3726285809Sscottl bit32 agOSSA_MPI_ERR_OFFLOAD_DIF_OR_ENC_NOT_ENABLED; 3727285809Sscottl bit32 agOSSA_IO_XFER_ERROR_DMA_ACTIVATE_TIMEOUT; 3728285809Sscottl bit32 agOSSA_IO_UNKNOWN_ERROR; 3729285809Sscottl} agsaIOErrorEventStats_t; 3730285809Sscottl 3731285809Sscottl 3732285809Sscottl/************************************************************************************ 3733285809Sscottl * * 3734285809Sscottl * Data Structures Defined for LL API ends * 3735285809Sscottl * * 3736285809Sscottl ************************************************************************************/ 3737285809Sscottl#ifdef SALL_API_TEST 3738285809Sscottltypedef struct agsaIOCountInfo_s 3739285809Sscottl{ 3740285809Sscottl bit32 numSSPStarted; // saSSPStart() 3741285809Sscottl bit32 numSSPAborted; // saSSPAbort() 3742285809Sscottl bit32 numSSPAbortedCB; // ossaSSPAbortCB() 3743285809Sscottl bit32 numSSPCompleted; // includes success and aborted IOs 3744285809Sscottl bit32 numSMPStarted; // saSMPStart() 3745285809Sscottl bit32 numSMPAborted; // saSMPAbort() 3746285809Sscottl bit32 numSMPAbortedCB; // ossaSMPAbortCB() 3747285809Sscottl bit32 numSMPCompleted; // includes success and aborted IOs 3748285809Sscottl bit32 numSataStarted; // saSATAStart() 3749285809Sscottl bit32 numSataAborted; // saSATAAbort() 3750285809Sscottl bit32 numSataAbortedCB; // ossaSATAAbortCB() 3751285809Sscottl bit32 numSataCompleted; // includes success and aborted IOs 3752285809Sscottl bit32 numEchoSent; // saEchoCommand() 3753285809Sscottl bit32 numEchoCB; // ossaEchoCB() 3754285809Sscottl bit32 numUNKNWRespIOMB; // unknow Response IOMB received 3755285809Sscottl bit32 numOurIntCount; //InterruptHandler() counter 3756285809Sscottl bit32 numSpuriousInt; //spurious interrupts 3757285809Sscottl// bit32 numSpInts[64]; //spuriours interrupts count for each OBQ (PI=CI) 3758285809Sscottl// bit32 numSpInts1[64]; //spuriours interrupts count for each OBQ (PI!=CI) 3759285809Sscottl} agsaIOCountInfo_t; 3760285809Sscottl 3761285809Sscottl/* Total IO Counter */ 3762285809Sscottl#define LL_COUNTERS 17 3763285809Sscottl/* Counter Bit Map */ 3764285809Sscottl#define COUNTER_SSP_START 0x000001 3765285809Sscottl#define COUNTER_SSP_ABORT 0x000002 3766285809Sscottl#define COUNTER_SSPABORT_CB 0x000004 3767285809Sscottl#define COUNTER_SSP_COMPLETEED 0x000008 3768285809Sscottl#define COUNTER_SMP_START 0x000010 3769285809Sscottl#define COUNTER_SMP_ABORT 0x000020 3770285809Sscottl#define COUNTER_SMPABORT_CB 0x000040 3771285809Sscottl#define COUNTER_SMP_COMPLETEED 0x000080 3772285809Sscottl#define COUNTER_SATA_START 0x000100 3773285809Sscottl#define COUNTER_SATA_ABORT 0x000200 3774285809Sscottl#define COUNTER_SATAABORT_CB 0x000400 3775285809Sscottl#define COUNTER_SATA_COMPLETEED 0x000800 3776285809Sscottl#define COUNTER_ECHO_SENT 0x001000 3777285809Sscottl#define COUNTER_ECHO_CB 0x002000 3778285809Sscottl#define COUNTER_UNKWN_IOMB 0x004000 3779285809Sscottl#define COUNTER_OUR_INT 0x008000 3780285809Sscottl#define COUNTER_SPUR_INT 0x010000 3781285809Sscottl#define ALL_COUNTERS 0xFFFFFF 3782285809Sscottl 3783285809Sscottltypedef union agsaLLCountInfo_s 3784285809Sscottl{ 3785285809Sscottl agsaIOCountInfo_t IOCounter; 3786285809Sscottl bit32 arrayIOCounter[LL_COUNTERS]; 3787285809Sscottl} agsaLLCountInfo_t; 3788285809Sscottl 3789285809Sscottl#endif /* SALL_API_TEST */ 3790285809Sscottl 3791285809Sscottl#define MAX_IO_DEVICE_ENTRIES 4096 /**< Maximum Device Entries */ 3792285809Sscottl 3793285809Sscottl 3794285809Sscottl#ifdef SA_ENABLE_POISION_TLP 3795285809Sscottl#define SA_PTNFE_POISION_TLP 1 /* Enable if one */ 3796285809Sscottl#else /* SA_ENABLE_POISION_TLP */ 3797285809Sscottl#define SA_PTNFE_POISION_TLP 0 /* Disable if zero default setting */ 3798285809Sscottl#endif /* SA_ENABLE_POISION_TLP */ 3799285809Sscottl 3800285809Sscottl#ifdef SA_DISABLE_MDFD 3801285809Sscottl#define SA_MDFD_MULTI_DATA_FETCH 1 /* Disable if one */ 3802285809Sscottl#else /* SA_DISABLE_MDFD */ 3803285809Sscottl#define SA_MDFD_MULTI_DATA_FETCH 0 /* Enable if zero default setting */ 3804285809Sscottl#endif /* SA_DISABLE_MDFD */ 3805285809Sscottl 3806285809Sscottl#ifdef SA_ENABLE_ARBTE 3807285809Sscottl#define SA_ARBTE 1 /* Enable if one */ 3808285809Sscottl#else /* SA_ENABLE_ARBTE */ 3809285809Sscottl#define SA_ARBTE 0 /* Disable if zero default setting */ 3810285809Sscottl#endif /* SA_ENABLE_ARBTE */ 3811285809Sscottl 3812285809Sscottl#ifdef SA_DISABLE_OB_COAL 3813285809Sscottl#define SA_OUTBOUND_COALESCE 0 /* Disable if zero */ 3814285809Sscottl#else /* SA_DISABLE_OB_COAL */ 3815285809Sscottl#define SA_OUTBOUND_COALESCE 1 /* Enable if one default setting */ 3816285809Sscottl#endif /* SA_DISABLE_OB_COAL */ 3817285809Sscottl 3818285809Sscottl 3819285809Sscottl/*********************************************************************************** 3820285809Sscottl * * 3821285809Sscottl * The OS Layer Functions Declarations start * 3822285809Sscottl * * 3823285809Sscottl ***********************************************************************************/ 3824285809Sscottl#include "saosapi.h" 3825285809Sscottl/*********************************************************************************** 3826285809Sscottl * * 3827285809Sscottl * The OS Layer Functions Declarations end * 3828285809Sscottl * * 3829285809Sscottl ***********************************************************************************/ 3830285809Sscottl 3831285809Sscottl/*********************************************************************************** 3832285809Sscottl * * 3833285809Sscottl * The LL Layer Functions Declarations start * 3834285809Sscottl * * 3835285809Sscottl ***********************************************************************************/ 3836285809Sscottl 3837285809Sscottl#ifdef FAST_IO_TEST 3838285809Sscottl/* needs to be allocated by the xPrepare() caller, one struct per IO */ 3839285809Sscottltypedef struct agsaFastCBBuf_s 3840285809Sscottl{ 3841285809Sscottl void *cb; 3842285809Sscottl void *cbArg; 3843285809Sscottl void *pSenseData; 3844285809Sscottl bit8 *senseLen; 3845285809Sscottl /* internal */ 3846285809Sscottl void *oneDeviceData; /* tdsaDeviceData_t */ 3847285809Sscottl} agsaFastCBBuf_t; 3848285809Sscottl 3849285809Sscottltypedef struct agsaFastCommand_s 3850285809Sscottl{ 3851285809Sscottl /* in */ 3852285809Sscottl void *agRoot; 3853285809Sscottl /* modified by TD tiFastPrepare() */ 3854285809Sscottl void *devHandle; /* agsaDevHandle_t* */ 3855285809Sscottl void *agSgl; /* agsaSgl_t* */ 3856285809Sscottl bit32 dataLength; 3857285809Sscottl bit32 extDataLength; 3858285809Sscottl bit8 additionalCdbLen; 3859285809Sscottl bit8 *cdb; 3860285809Sscottl bit8 *lun; 3861285809Sscottl /* modified by TD tiFastPrepare() */ 3862285809Sscottl bit8 taskAttribute; /* TD_xxx */ 3863285809Sscottl bit16 flag; /* TLR_MASK */ 3864285809Sscottl bit32 agRequestType; 3865285809Sscottl bit32 queueNum; 3866285809Sscottl agsaFastCBBuf_t *safb; 3867285809Sscottl} agsaFastCommand_t; 3868285809Sscottl#endif 3869285809Sscottl 3870285809Sscottl 3871285809Sscottl 3872285809Sscottl/* Enable test by setting bits in gFPGA_TEST */ 3873285809Sscottl 3874285809Sscottl#define EnableFPGA_TEST_ICCcontrol 0x01 3875285809Sscottl#define EnableFPGA_TEST_ReadDEV 0x02 3876285809Sscottl#define EnableFPGA_TEST_WriteCALAll 0x04 3877285809Sscottl#define EnableFPGA_TEST_ReconfigSASParams 0x08 3878285809Sscottl#define EnableFPGA_TEST_LocalPhyControl 0x10 3879285809Sscottl#define EnableFPGA_TEST_PortControl 0x20 3880285809Sscottl 3881285809Sscottl 3882285809Sscottl/* 3883285809SscottlPM8001/PM8008/PM8009/PM8018 sTSDK Low-Level Architecture Specification 3884285809SscottlSDK2 3885285809Sscottl3.3 Encryption Status Definitions 3886285809SscottlEncryption engine generated errors. 3887285809SscottlTable 7 Encryption Engine Generated Errors 3888285809SscottlError Definition 3889285809Sscottl*/ 3890285809Sscottl 3891285809Sscottl/* 3892285809SscottlPM 1.01 3893285809Sscottlsection 4.26.12.6 Encryption Errors 3894285809SscottlTable 51 lists initialization errors related to encryption functionality. For information on errors reported 3895285809Sscottlfor inbound IOMB commands, refer to the corresponding outbound response sections. The error codes 3896285809Sscottllisted in Table 51 are reported in the Scratchpad 3 Register. 3897285809Sscottl*/ 3898285809Sscottl#define OSSA_ENCRYPT_ENGINE_FAILURE_MASK 0x00FF0000 /* Encrypt Engine failed the BIST Test */ 3899285809Sscottl#define OSSA_ENCRYPT_SEEPROM_NOT_FOUND 0x01 /* SEEPROM is not installed. This condition is reported based on the bootstrap pin setting. */ 3900285809Sscottl#define OSSA_ENCRYPT_SEEPROM_IPW_RD_ACCESS_TMO 0x02 /* SEEPROM access timeout detected while reading initialization password or Allowable Cipher Modes. */ 3901285809Sscottl#define OSSA_ENCRYPT_SEEPROM_IPW_RD_CRC_ERR 0x03 /* CRC Error detected when reading initialization password or Allowable Cipher Modes. */ 3902285809Sscottl#define OSSA_ENCRYPT_SEEPROM_IPW_INVALID 0x04 /* Initialization password read from SEEPROM doesn't match any valid password value. This could also mean SEEPROM is blank. */ 3903285809Sscottl#define OSSA_ENCRYPT_SEEPROM_WR_ACCESS_TMO 0x05 /* access timeout detected while writing initialization password or Allowable Cipher Modes. */ 3904285809Sscottl#define OSSA_ENCRYPT_FLASH_ACCESS_TMO 0x20 /* Timeout while reading flash memory. */ 3905285809Sscottl#define OSSA_ENCRYPT_FLASH_SECTOR_ERASE_TMO 0x21 /* Flash sector erase timeout while writing to flash memory. */ 3906285809Sscottl#define OSSA_ENCRYPT_FLASH_SECTOR_ERASE_ERR 0x22 /* Flash sector erase failure while writing to flash memory. */ 3907285809Sscottl#define OSSA_ENCRYPT_FLASH_ECC_CHECK_ERR 0x23 /* Flash ECC check failure. */ 3908285809Sscottl#define OSSA_ENCRYPT_FLASH_NOT_INSTALLED 0x24 /* Flash memory not installed, this error is only detected in Security Mode B. */ 3909285809Sscottl#define OSSA_ENCRYPT_INITIAL_KEK_NOT_FOUND 0x40 /* Initial KEK is not found in the flash memory. This error is only detected in Security Mode B. */ 3910285809Sscottl#define OSSA_ENCRYPT_AES_BIST_ERR 0x41 /* Built-In Test Failure */ 3911285809Sscottl#define OSSA_ENCRYPT_KWP_BIST_FAILURE 0x42 /* Built-In Test Failed on Key Wrap Engine */ 3912285809Sscottl 3913285809Sscottl/* 0x01:ENC_ERR_SEEPROM_NOT_INSTALLED */ 3914285809Sscottl/* 0x02:ENC_ERR_SEEPROM_IPW_RD_ACCESS_TMO */ 3915285809Sscottl/* 0x03:ENC_ERR_SEEPROM_IPW_RD_CRC_ERR */ 3916285809Sscottl/* 0x04:ENC_ERR_SEEPROM_IPW_INVALID */ 3917285809Sscottl/* 0x05:ENC_ERR_SEEPROM_WR_ACCESS_TMO */ 3918285809Sscottl/* 0x20:ENC_ERR_FLASH_ACCESS_TMO */ 3919285809Sscottl/* 0x21:ENC_ERR_FLASH_SECTOR_ERASE_TMO */ 3920285809Sscottl/* 0x22:ENC_ERR_FLASH_SECTOR_ERASE_FAILURE */ 3921285809Sscottl/* 0x23:ENC_ERR_FLASH_ECC_CHECK_FAILURE */ 3922285809Sscottl/* 0x24:ENC_ERR_FLASH_NOT_INSTALLED */ 3923285809Sscottl/* 0x40:ENC_ERR_INITIAL_KEK_NOT_FOUND */ 3924285809Sscottl/* 0x41:ENC_ERR_AES_BIST_FAILURE */ 3925285809Sscottl/* 0x42:ENC_ERR_KWP_BIST_FAILURE */ 3926285809Sscottl 3927285809Sscottl/* 3928285809SscottlThis field indicates self test failure in DIF engine bits [27:24]. 3929285809Sscottl*/ 3930285809Sscottl 3931285809Sscottl#define OSSA_DIF_ENGINE_FAILURE_MASK 0x0F000000 /* DIF Engine failed the BIST Test */ 3932285809Sscottl 3933285809Sscottl#define OSSA_DIF_ENGINE_0_BIST_FAILURE 0x1 /* DIF Engine 0 failed the BIST Test */ 3934285809Sscottl#define OSSA_DIF_ENGINE_1_BIST_FAILURE 0x2 /* DIF Engine 1 failed the BIST Test */ 3935285809Sscottl#define OSSA_DIF_ENGINE_2_BIST_FAILURE 0x4 /* DIF Engine 2 failed the BIST Test */ 3936285809Sscottl#define OSSA_DIF_ENGINE_3_BIST_FAILURE 0x8 /* DIF Engine 3 failed the BIST Test */ 3937285809Sscottl 3938285809Sscottl#define SA_ROLE_CAPABILITIES_CSP 0x001 3939285809Sscottl#define SA_ROLE_CAPABILITIES_OPR 0x002 3940285809Sscottl#define SA_ROLE_CAPABILITIES_SCO 0x004 3941285809Sscottl#define SA_ROLE_CAPABILITIES_STS 0x008 3942285809Sscottl#define SA_ROLE_CAPABILITIES_TST 0x010 3943285809Sscottl#define SA_ROLE_CAPABILITIES_KEK 0x020 3944285809Sscottl#define SA_ROLE_CAPABILITIES_DEK 0x040 3945285809Sscottl#define SA_ROLE_CAPABILITIES_IOS 0x080 3946285809Sscottl#define SA_ROLE_CAPABILITIES_FWU 0x100 3947285809Sscottl#define SA_ROLE_CAPABILITIES_PRM 0x200 3948285809Sscottl 3949285809Sscottl 3950285809Sscottl#include "saapi.h" 3951285809Sscottl/*********************************************************************************** 3952285809Sscottl * * 3953285809Sscottl * The LL Layer Functions Declarations end * 3954285809Sscottl * * 3955285809Sscottl ***********************************************************************************/ 3956285809Sscottl 3957285809Sscottl#endif /*__SA_H__ */ 3958