pcivar.h revision 294289
1/*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: stable/10/sys/dev/pci/pcivar.h 294289 2016-01-18 19:52:20Z jhb $ 27 * 28 */ 29 30#ifndef _PCIVAR_H_ 31#define _PCIVAR_H_ 32 33#include <sys/queue.h> 34 35/* some PCI bus constants */ 36#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 37#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 38#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 39 40typedef uint64_t pci_addr_t; 41 42/* Interesting values for PCI power management */ 43struct pcicfg_pp { 44 uint16_t pp_cap; /* PCI power management capabilities */ 45 uint8_t pp_status; /* conf. space addr. of PM control/status reg */ 46 uint8_t pp_bse; /* conf. space addr. of PM BSE reg */ 47 uint8_t pp_data; /* conf. space addr. of PM data reg */ 48}; 49 50struct pci_map { 51 pci_addr_t pm_value; /* Raw BAR value */ 52 pci_addr_t pm_size; 53 uint8_t pm_reg; 54 STAILQ_ENTRY(pci_map) pm_link; 55}; 56 57struct vpd_readonly { 58 char keyword[2]; 59 char *value; 60 int len; 61}; 62 63struct vpd_write { 64 char keyword[2]; 65 char *value; 66 int start; 67 int len; 68}; 69 70struct pcicfg_vpd { 71 uint8_t vpd_reg; /* base register, + 2 for addr, + 4 data */ 72 char vpd_cached; 73 char *vpd_ident; /* string identifier */ 74 int vpd_rocnt; 75 struct vpd_readonly *vpd_ros; 76 int vpd_wcnt; 77 struct vpd_write *vpd_w; 78}; 79 80/* Interesting values for PCI MSI */ 81struct pcicfg_msi { 82 uint16_t msi_ctrl; /* Message Control */ 83 uint8_t msi_location; /* Offset of MSI capability registers. */ 84 uint8_t msi_msgnum; /* Number of messages */ 85 int msi_alloc; /* Number of allocated messages. */ 86 uint64_t msi_addr; /* Contents of address register. */ 87 uint16_t msi_data; /* Contents of data register. */ 88 u_int msi_handlers; 89}; 90 91/* Interesting values for PCI MSI-X */ 92struct msix_vector { 93 uint64_t mv_address; /* Contents of address register. */ 94 uint32_t mv_data; /* Contents of data register. */ 95 int mv_irq; 96}; 97 98struct msix_table_entry { 99 u_int mte_vector; /* 1-based index into msix_vectors array. */ 100 u_int mte_handlers; 101}; 102 103struct pcicfg_msix { 104 uint16_t msix_ctrl; /* Message Control */ 105 uint16_t msix_msgnum; /* Number of messages */ 106 uint8_t msix_location; /* Offset of MSI-X capability registers. */ 107 uint8_t msix_table_bar; /* BAR containing vector table. */ 108 uint8_t msix_pba_bar; /* BAR containing PBA. */ 109 uint32_t msix_table_offset; 110 uint32_t msix_pba_offset; 111 int msix_alloc; /* Number of allocated vectors. */ 112 int msix_table_len; /* Length of virtual table. */ 113 struct msix_table_entry *msix_table; /* Virtual table. */ 114 struct msix_vector *msix_vectors; /* Array of allocated vectors. */ 115 struct resource *msix_table_res; /* Resource containing vector table. */ 116 struct resource *msix_pba_res; /* Resource containing PBA. */ 117}; 118 119/* Interesting values for HyperTransport */ 120struct pcicfg_ht { 121 uint8_t ht_slave; /* Non-zero if device is an HT slave. */ 122 uint8_t ht_msimap; /* Offset of MSI mapping cap registers. */ 123 uint16_t ht_msictrl; /* MSI mapping control */ 124 uint64_t ht_msiaddr; /* MSI mapping base address */ 125}; 126 127/* Interesting values for PCI-express */ 128struct pcicfg_pcie { 129 uint8_t pcie_location; /* Offset of PCI-e capability registers. */ 130 uint8_t pcie_type; /* Device type. */ 131 uint16_t pcie_flags; /* Device capabilities register. */ 132 uint16_t pcie_device_ctl; /* Device control register. */ 133 uint16_t pcie_link_ctl; /* Link control register. */ 134 uint16_t pcie_slot_ctl; /* Slot control register. */ 135 uint16_t pcie_root_ctl; /* Root control register. */ 136 uint16_t pcie_device_ctl2; /* Second device control register. */ 137 uint16_t pcie_link_ctl2; /* Second link control register. */ 138 uint16_t pcie_slot_ctl2; /* Second slot control register. */ 139}; 140 141struct pcicfg_pcix { 142 uint16_t pcix_command; 143 uint8_t pcix_location; /* Offset of PCI-X capability registers. */ 144}; 145 146/* config header information common to all header types */ 147typedef struct pcicfg { 148 struct device *dev; /* device which owns this */ 149 150 STAILQ_HEAD(, pci_map) maps; /* BARs */ 151 152 uint16_t subvendor; /* card vendor ID */ 153 uint16_t subdevice; /* card device ID, assigned by card vendor */ 154 uint16_t vendor; /* chip vendor ID */ 155 uint16_t device; /* chip device ID, assigned by chip vendor */ 156 157 uint16_t cmdreg; /* disable/enable chip and PCI options */ 158 uint16_t statreg; /* supported PCI features and error state */ 159 160 uint8_t baseclass; /* chip PCI class */ 161 uint8_t subclass; /* chip PCI subclass */ 162 uint8_t progif; /* chip PCI programming interface */ 163 uint8_t revid; /* chip revision ID */ 164 165 uint8_t hdrtype; /* chip config header type */ 166 uint8_t cachelnsz; /* cache line size in 4byte units */ 167 uint8_t intpin; /* PCI interrupt pin */ 168 uint8_t intline; /* interrupt line (IRQ for PC arch) */ 169 170 uint8_t mingnt; /* min. useful bus grant time in 250ns units */ 171 uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 172 uint8_t lattimer; /* latency timer in units of 30ns bus cycles */ 173 174 uint8_t mfdev; /* multi-function device (from hdrtype reg) */ 175 uint8_t nummaps; /* actual number of PCI maps used */ 176 177 uint32_t domain; /* PCI domain */ 178 uint8_t bus; /* config space bus address */ 179 uint8_t slot; /* config space slot address */ 180 uint8_t func; /* config space function number */ 181 182 struct pcicfg_pp pp; /* Power management */ 183 struct pcicfg_vpd vpd; /* Vital product data */ 184 struct pcicfg_msi msi; /* PCI MSI */ 185 struct pcicfg_msix msix; /* PCI MSI-X */ 186 struct pcicfg_ht ht; /* HyperTransport */ 187 struct pcicfg_pcie pcie; /* PCI Express */ 188 struct pcicfg_pcix pcix; /* PCI-X */ 189} pcicfgregs; 190 191/* additional type 1 device config header information (PCI to PCI bridge) */ 192 193typedef struct { 194 pci_addr_t pmembase; /* base address of prefetchable memory */ 195 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 196 uint32_t membase; /* base address of memory window */ 197 uint32_t memlimit; /* topmost address of memory window */ 198 uint32_t iobase; /* base address of port window */ 199 uint32_t iolimit; /* topmost address of port window */ 200 uint16_t secstat; /* secondary bus status register */ 201 uint16_t bridgectl; /* bridge control register */ 202 uint8_t seclat; /* CardBus latency timer */ 203} pcih1cfgregs; 204 205/* additional type 2 device config header information (CardBus bridge) */ 206 207typedef struct { 208 uint32_t membase0; /* base address of memory window */ 209 uint32_t memlimit0; /* topmost address of memory window */ 210 uint32_t membase1; /* base address of memory window */ 211 uint32_t memlimit1; /* topmost address of memory window */ 212 uint32_t iobase0; /* base address of port window */ 213 uint32_t iolimit0; /* topmost address of port window */ 214 uint32_t iobase1; /* base address of port window */ 215 uint32_t iolimit1; /* topmost address of port window */ 216 uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 217 uint16_t secstat; /* secondary bus status register */ 218 uint16_t bridgectl; /* bridge control register */ 219 uint8_t seclat; /* CardBus latency timer */ 220} pcih2cfgregs; 221 222extern uint32_t pci_numdevs; 223 224/* Only if the prerequisites are present */ 225#if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_) 226struct pci_devinfo { 227 STAILQ_ENTRY(pci_devinfo) pci_links; 228 struct resource_list resources; 229 pcicfgregs cfg; 230 struct pci_conf conf; 231}; 232#endif 233 234#ifdef _SYS_BUS_H_ 235 236#include "pci_if.h" 237 238enum pci_device_ivars { 239 PCI_IVAR_SUBVENDOR, 240 PCI_IVAR_SUBDEVICE, 241 PCI_IVAR_VENDOR, 242 PCI_IVAR_DEVICE, 243 PCI_IVAR_DEVID, 244 PCI_IVAR_CLASS, 245 PCI_IVAR_SUBCLASS, 246 PCI_IVAR_PROGIF, 247 PCI_IVAR_REVID, 248 PCI_IVAR_INTPIN, 249 PCI_IVAR_IRQ, 250 PCI_IVAR_DOMAIN, 251 PCI_IVAR_BUS, 252 PCI_IVAR_SLOT, 253 PCI_IVAR_FUNCTION, 254 PCI_IVAR_ETHADDR, 255 PCI_IVAR_CMDREG, 256 PCI_IVAR_CACHELNSZ, 257 PCI_IVAR_MINGNT, 258 PCI_IVAR_MAXLAT, 259 PCI_IVAR_LATTIMER 260}; 261 262/* 263 * Simplified accessors for pci devices 264 */ 265#define PCI_ACCESSOR(var, ivar, type) \ 266 __BUS_ACCESSOR(pci, var, PCI, ivar, type) 267 268PCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t) 269PCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t) 270PCI_ACCESSOR(vendor, VENDOR, uint16_t) 271PCI_ACCESSOR(device, DEVICE, uint16_t) 272PCI_ACCESSOR(devid, DEVID, uint32_t) 273PCI_ACCESSOR(class, CLASS, uint8_t) 274PCI_ACCESSOR(subclass, SUBCLASS, uint8_t) 275PCI_ACCESSOR(progif, PROGIF, uint8_t) 276PCI_ACCESSOR(revid, REVID, uint8_t) 277PCI_ACCESSOR(intpin, INTPIN, uint8_t) 278PCI_ACCESSOR(irq, IRQ, uint8_t) 279PCI_ACCESSOR(domain, DOMAIN, uint32_t) 280PCI_ACCESSOR(bus, BUS, uint8_t) 281PCI_ACCESSOR(slot, SLOT, uint8_t) 282PCI_ACCESSOR(function, FUNCTION, uint8_t) 283PCI_ACCESSOR(ether, ETHADDR, uint8_t *) 284PCI_ACCESSOR(cmdreg, CMDREG, uint8_t) 285PCI_ACCESSOR(cachelnsz, CACHELNSZ, uint8_t) 286PCI_ACCESSOR(mingnt, MINGNT, uint8_t) 287PCI_ACCESSOR(maxlat, MAXLAT, uint8_t) 288PCI_ACCESSOR(lattimer, LATTIMER, uint8_t) 289 290#undef PCI_ACCESSOR 291 292/* 293 * Operations on configuration space. 294 */ 295static __inline uint32_t 296pci_read_config(device_t dev, int reg, int width) 297{ 298 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 299} 300 301static __inline void 302pci_write_config(device_t dev, int reg, uint32_t val, int width) 303{ 304 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 305} 306 307/* 308 * Ivars for pci bridges. 309 */ 310 311/*typedef enum pci_device_ivars pcib_device_ivars;*/ 312enum pcib_device_ivars { 313 PCIB_IVAR_DOMAIN, 314 PCIB_IVAR_BUS 315}; 316 317#define PCIB_ACCESSOR(var, ivar, type) \ 318 __BUS_ACCESSOR(pcib, var, PCIB, ivar, type) 319 320PCIB_ACCESSOR(domain, DOMAIN, uint32_t) 321PCIB_ACCESSOR(bus, BUS, uint32_t) 322 323#undef PCIB_ACCESSOR 324 325/* 326 * PCI interrupt validation. Invalid interrupt values such as 0 or 128 327 * on i386 or other platforms should be mapped out in the MD pcireadconf 328 * code and not here, since the only MI invalid IRQ is 255. 329 */ 330#define PCI_INVALID_IRQ 255 331#define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ) 332 333/* 334 * Convenience functions. 335 * 336 * These should be used in preference to manually manipulating 337 * configuration space. 338 */ 339static __inline int 340pci_enable_busmaster(device_t dev) 341{ 342 return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev)); 343} 344 345static __inline int 346pci_disable_busmaster(device_t dev) 347{ 348 return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev)); 349} 350 351static __inline int 352pci_enable_io(device_t dev, int space) 353{ 354 return(PCI_ENABLE_IO(device_get_parent(dev), dev, space)); 355} 356 357static __inline int 358pci_disable_io(device_t dev, int space) 359{ 360 return(PCI_DISABLE_IO(device_get_parent(dev), dev, space)); 361} 362 363static __inline int 364pci_get_vpd_ident(device_t dev, const char **identptr) 365{ 366 return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr)); 367} 368 369static __inline int 370pci_get_vpd_readonly(device_t dev, const char *kw, const char **vptr) 371{ 372 return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, vptr)); 373} 374 375/* 376 * Check if the address range falls within the VGA defined address range(s) 377 */ 378static __inline int 379pci_is_vga_ioport_range(u_long start, u_long end) 380{ 381 382 return (((start >= 0x3b0 && end <= 0x3bb) || 383 (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0); 384} 385 386static __inline int 387pci_is_vga_memory_range(u_long start, u_long end) 388{ 389 390 return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0); 391} 392 393/* 394 * PCI power states are as defined by ACPI: 395 * 396 * D0 State in which device is on and running. It is receiving full 397 * power from the system and delivering full functionality to the user. 398 * D1 Class-specific low-power state in which device context may or may not 399 * be lost. Buses in D1 cannot do anything to the bus that would force 400 * devices on that bus to lose context. 401 * D2 Class-specific low-power state in which device context may or may 402 * not be lost. Attains greater power savings than D1. Buses in D2 403 * can cause devices on that bus to lose some context. Devices in D2 404 * must be prepared for the bus to be in D2 or higher. 405 * D3 State in which the device is off and not running. Device context is 406 * lost. Power can be removed from the device. 407 */ 408#define PCI_POWERSTATE_D0 0 409#define PCI_POWERSTATE_D1 1 410#define PCI_POWERSTATE_D2 2 411#define PCI_POWERSTATE_D3 3 412#define PCI_POWERSTATE_UNKNOWN -1 413 414static __inline int 415pci_set_powerstate(device_t dev, int state) 416{ 417 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state); 418} 419 420static __inline int 421pci_get_powerstate(device_t dev) 422{ 423 return PCI_GET_POWERSTATE(device_get_parent(dev), dev); 424} 425 426static __inline int 427pci_find_cap(device_t dev, int capability, int *capreg) 428{ 429 return (PCI_FIND_CAP(device_get_parent(dev), dev, capability, capreg)); 430} 431 432static __inline int 433pci_find_extcap(device_t dev, int capability, int *capreg) 434{ 435 return (PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg)); 436} 437 438static __inline int 439pci_find_htcap(device_t dev, int capability, int *capreg) 440{ 441 return (PCI_FIND_HTCAP(device_get_parent(dev), dev, capability, capreg)); 442} 443 444static __inline int 445pci_alloc_msi(device_t dev, int *count) 446{ 447 return (PCI_ALLOC_MSI(device_get_parent(dev), dev, count)); 448} 449 450static __inline int 451pci_alloc_msix(device_t dev, int *count) 452{ 453 return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count)); 454} 455 456static __inline void 457pci_enable_msi(device_t dev, uint64_t address, uint16_t data) 458{ 459 PCI_ENABLE_MSI(device_get_parent(dev), dev, address, data); 460} 461 462static __inline void 463pci_enable_msix(device_t dev, u_int index, uint64_t address, uint32_t data) 464{ 465 PCI_ENABLE_MSIX(device_get_parent(dev), dev, index, address, data); 466} 467 468static __inline void 469pci_disable_msi(device_t dev) 470{ 471 PCI_DISABLE_MSI(device_get_parent(dev), dev); 472} 473 474static __inline int 475pci_remap_msix(device_t dev, int count, const u_int *vectors) 476{ 477 return (PCI_REMAP_MSIX(device_get_parent(dev), dev, count, vectors)); 478} 479 480static __inline int 481pci_release_msi(device_t dev) 482{ 483 return (PCI_RELEASE_MSI(device_get_parent(dev), dev)); 484} 485 486static __inline int 487pci_msi_count(device_t dev) 488{ 489 return (PCI_MSI_COUNT(device_get_parent(dev), dev)); 490} 491 492static __inline int 493pci_msix_count(device_t dev) 494{ 495 return (PCI_MSIX_COUNT(device_get_parent(dev), dev)); 496} 497 498static __inline uint16_t 499pci_get_rid(device_t dev) 500{ 501 return (PCI_GET_RID(device_get_parent(dev), dev)); 502} 503 504static __inline void 505pci_child_added(device_t dev) 506{ 507 508 return (PCI_CHILD_ADDED(device_get_parent(dev), dev)); 509} 510 511device_t pci_find_bsf(uint8_t, uint8_t, uint8_t); 512device_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t); 513device_t pci_find_device(uint16_t, uint16_t); 514device_t pci_find_class(uint8_t class, uint8_t subclass); 515 516/* Can be used by drivers to manage the MSI-X table. */ 517int pci_pending_msix(device_t dev, u_int index); 518 519int pci_msi_device_blacklisted(device_t dev); 520int pci_msix_device_blacklisted(device_t dev); 521 522void pci_ht_map_msi(device_t dev, uint64_t addr); 523 524device_t pci_find_pcie_root_port(device_t dev); 525int pci_get_max_read_req(device_t dev); 526void pci_restore_state(device_t dev); 527void pci_save_state(device_t dev); 528int pci_set_max_read_req(device_t dev, int size); 529uint32_t pcie_read_config(device_t dev, int reg, int width); 530void pcie_write_config(device_t dev, int reg, uint32_t value, int width); 531uint32_t pcie_adjust_config(device_t dev, int reg, uint32_t mask, 532 uint32_t value, int width); 533 534 535#ifdef BUS_SPACE_MAXADDR 536#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF) 537#define PCI_DMA_BOUNDARY 0x100000000 538#else 539#define PCI_DMA_BOUNDARY 0 540#endif 541#endif 542 543#endif /* _SYS_BUS_H_ */ 544 545/* 546 * cdev switch for control device, initialised in generic PCI code 547 */ 548extern struct cdevsw pcicdev; 549 550/* 551 * List of all PCI devices, generation count for the list. 552 */ 553STAILQ_HEAD(devlist, pci_devinfo); 554 555extern struct devlist pci_devq; 556extern uint32_t pci_generation; 557 558struct pci_map *pci_find_bar(device_t dev, int reg); 559int pci_bar_enabled(device_t dev, struct pci_map *pm); 560struct pcicfg_vpd *pci_fetch_vpd_list(device_t dev); 561 562#define VGA_PCI_BIOS_SHADOW_ADDR 0xC0000 563#define VGA_PCI_BIOS_SHADOW_SIZE 131072 564 565int vga_pci_is_boot_display(device_t dev); 566void * vga_pci_map_bios(device_t dev, size_t *size); 567void vga_pci_unmap_bios(device_t dev, void *bios); 568 569#endif /* _PCIVAR_H_ */ 570