pcireg.h revision 279470
1/*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: stable/10/sys/dev/pci/pcireg.h 279470 2015-03-01 04:22:06Z rstone $ 27 * 28 */ 29 30/* 31 * PCIM_xxx: mask to locate subfield in register 32 * PCIR_xxx: config register offset 33 * PCIC_xxx: device class 34 * PCIS_xxx: device subclass 35 * PCIP_xxx: device programming interface 36 * PCIV_xxx: PCI vendor ID (only required to fixup ancient devices) 37 * PCID_xxx: device ID 38 * PCIY_xxx: capability identification number 39 * PCIZ_xxx: extended capability identification number 40 */ 41 42/* some PCI bus constants */ 43#define PCI_DOMAINMAX 65535 /* highest supported domain number */ 44#define PCI_BUSMAX 255 /* highest supported bus number */ 45#define PCI_SLOTMAX 31 /* highest supported slot number */ 46#define PCI_FUNCMAX 7 /* highest supported function number */ 47#define PCI_REGMAX 255 /* highest supported config register addr. */ 48#define PCIE_REGMAX 4095 /* highest supported config register addr. */ 49#define PCI_MAXHDRTYPE 2 50 51#define PCIE_ARI_SLOTMAX 0 52#define PCIE_ARI_FUNCMAX 255 53 54#define PCI_RID_BUS_SHIFT 8 55#define PCI_RID_SLOT_SHIFT 3 56#define PCI_RID_FUNC_SHIFT 0 57 58#define PCI_RID(bus, slot, func) \ 59 ((((bus) & PCI_BUSMAX) << PCI_RID_BUS_SHIFT) | \ 60 (((slot) & PCI_SLOTMAX) << PCI_RID_SLOT_SHIFT) | \ 61 (((func) & PCI_FUNCMAX) << PCI_RID_FUNC_SHIFT)) 62 63#define PCI_ARI_RID(bus, func) \ 64 ((((bus) & PCI_BUSMAX) << PCI_RID_BUS_SHIFT) | \ 65 (((func) & PCIE_ARI_FUNCMAX) << PCI_RID_FUNC_SHIFT)) 66 67#define PCI_RID2BUS(rid) (((rid) >> PCI_RID_BUS_SHIFT) & PCI_BUSMAX) 68#define PCI_RID2SLOT(rid) (((rid) >> PCI_RID_SLOT_SHIFT) & PCI_SLOTMAX) 69#define PCI_RID2FUNC(rid) (((rid) >> PCI_RID_FUNC_SHIFT) & PCI_FUNCMAX) 70 71#define PCIE_ARI_SLOT(func) (((func) >> PCI_RID_SLOT_SHIFT) & PCI_SLOTMAX) 72#define PCIE_ARI_FUNC(func) (((func) >> PCI_RID_FUNC_SHIFT) & PCI_FUNCMAX) 73 74/* PCI config header registers for all devices */ 75 76#define PCIR_DEVVENDOR 0x00 77#define PCIR_VENDOR 0x00 78#define PCIR_DEVICE 0x02 79#define PCIR_COMMAND 0x04 80#define PCIM_CMD_PORTEN 0x0001 81#define PCIM_CMD_MEMEN 0x0002 82#define PCIM_CMD_BUSMASTEREN 0x0004 83#define PCIM_CMD_SPECIALEN 0x0008 84#define PCIM_CMD_MWRICEN 0x0010 85#define PCIM_CMD_PERRESPEN 0x0040 86#define PCIM_CMD_SERRESPEN 0x0100 87#define PCIM_CMD_BACKTOBACK 0x0200 88#define PCIM_CMD_INTxDIS 0x0400 89#define PCIR_STATUS 0x06 90#define PCIM_STATUS_INTxSTATE 0x0008 91#define PCIM_STATUS_CAPPRESENT 0x0010 92#define PCIM_STATUS_66CAPABLE 0x0020 93#define PCIM_STATUS_BACKTOBACK 0x0080 94#define PCIM_STATUS_MDPERR 0x0100 95#define PCIM_STATUS_SEL_FAST 0x0000 96#define PCIM_STATUS_SEL_MEDIMUM 0x0200 97#define PCIM_STATUS_SEL_SLOW 0x0400 98#define PCIM_STATUS_SEL_MASK 0x0600 99#define PCIM_STATUS_STABORT 0x0800 100#define PCIM_STATUS_RTABORT 0x1000 101#define PCIM_STATUS_RMABORT 0x2000 102#define PCIM_STATUS_SERR 0x4000 103#define PCIM_STATUS_PERR 0x8000 104#define PCIR_REVID 0x08 105#define PCIR_PROGIF 0x09 106#define PCIR_SUBCLASS 0x0a 107#define PCIR_CLASS 0x0b 108#define PCIR_CACHELNSZ 0x0c 109#define PCIR_LATTIMER 0x0d 110#define PCIR_HDRTYPE 0x0e 111#define PCIM_HDRTYPE 0x7f 112#define PCIM_HDRTYPE_NORMAL 0x00 113#define PCIM_HDRTYPE_BRIDGE 0x01 114#define PCIM_HDRTYPE_CARDBUS 0x02 115#define PCIM_MFDEV 0x80 116#define PCIR_BIST 0x0f 117 118/* Capability Register Offsets */ 119 120#define PCICAP_ID 0x0 121#define PCICAP_NEXTPTR 0x1 122 123/* Capability Identification Numbers */ 124 125#define PCIY_PMG 0x01 /* PCI Power Management */ 126#define PCIY_AGP 0x02 /* AGP */ 127#define PCIY_VPD 0x03 /* Vital Product Data */ 128#define PCIY_SLOTID 0x04 /* Slot Identification */ 129#define PCIY_MSI 0x05 /* Message Signaled Interrupts */ 130#define PCIY_CHSWP 0x06 /* CompactPCI Hot Swap */ 131#define PCIY_PCIX 0x07 /* PCI-X */ 132#define PCIY_HT 0x08 /* HyperTransport */ 133#define PCIY_VENDOR 0x09 /* Vendor Unique */ 134#define PCIY_DEBUG 0x0a /* Debug port */ 135#define PCIY_CRES 0x0b /* CompactPCI central resource control */ 136#define PCIY_HOTPLUG 0x0c /* PCI Hot-Plug */ 137#define PCIY_SUBVENDOR 0x0d /* PCI-PCI bridge subvendor ID */ 138#define PCIY_AGP8X 0x0e /* AGP 8x */ 139#define PCIY_SECDEV 0x0f /* Secure Device */ 140#define PCIY_EXPRESS 0x10 /* PCI Express */ 141#define PCIY_MSIX 0x11 /* MSI-X */ 142#define PCIY_SATA 0x12 /* SATA */ 143#define PCIY_PCIAF 0x13 /* PCI Advanced Features */ 144 145/* Extended Capability Register Fields */ 146 147#define PCIR_EXTCAP 0x100 148#define PCIM_EXTCAP_ID 0x0000ffff 149#define PCIM_EXTCAP_VER 0x000f0000 150#define PCIM_EXTCAP_NEXTPTR 0xfff00000 151#define PCI_EXTCAP_ID(ecap) ((ecap) & PCIM_EXTCAP_ID) 152#define PCI_EXTCAP_VER(ecap) (((ecap) & PCIM_EXTCAP_VER) >> 16) 153#define PCI_EXTCAP_NEXTPTR(ecap) (((ecap) & PCIM_EXTCAP_NEXTPTR) >> 20) 154 155/* Extended Capability Identification Numbers */ 156 157#define PCIZ_AER 0x0001 /* Advanced Error Reporting */ 158#define PCIZ_VC 0x0002 /* Virtual Channel if MFVC Ext Cap not set */ 159#define PCIZ_SERNUM 0x0003 /* Device Serial Number */ 160#define PCIZ_PWRBDGT 0x0004 /* Power Budgeting */ 161#define PCIZ_RCLINK_DCL 0x0005 /* Root Complex Link Declaration */ 162#define PCIZ_RCLINK_CTL 0x0006 /* Root Complex Internal Link Control */ 163#define PCIZ_RCEC_ASSOC 0x0007 /* Root Complex Event Collector Association */ 164#define PCIZ_MFVC 0x0008 /* Multi-Function Virtual Channel */ 165#define PCIZ_VC2 0x0009 /* Virtual Channel if MFVC Ext Cap set */ 166#define PCIZ_RCRB 0x000a /* RCRB Header */ 167#define PCIZ_VENDOR 0x000b /* Vendor Unique */ 168#define PCIZ_CAC 0x000c /* Configuration Access Correction -- obsolete */ 169#define PCIZ_ACS 0x000d /* Access Control Services */ 170#define PCIZ_ARI 0x000e /* Alternative Routing-ID Interpretation */ 171#define PCIZ_ATS 0x000f /* Address Translation Services */ 172#define PCIZ_SRIOV 0x0010 /* Single Root IO Virtualization */ 173#define PCIZ_MRIOV 0x0011 /* Multiple Root IO Virtualization */ 174#define PCIZ_MULTICAST 0x0012 /* Multicast */ 175#define PCIZ_PAGE_REQ 0x0013 /* Page Request */ 176#define PCIZ_AMD 0x0014 /* Reserved for AMD */ 177#define PCIZ_RESIZE_BAR 0x0015 /* Resizable BAR */ 178#define PCIZ_DPA 0x0016 /* Dynamic Power Allocation */ 179#define PCIZ_TPH_REQ 0x0017 /* TPH Requester */ 180#define PCIZ_LTR 0x0018 /* Latency Tolerance Reporting */ 181#define PCIZ_SEC_PCIE 0x0019 /* Secondary PCI Express */ 182#define PCIZ_PMUX 0x001a /* Protocol Multiplexing */ 183#define PCIZ_PASID 0x001b /* Process Address Space ID */ 184#define PCIZ_LN_REQ 0x001c /* LN Requester */ 185#define PCIZ_DPC 0x001d /* Downstream Porto Containment */ 186#define PCIZ_L1PM 0x001e /* L1 PM Substates */ 187 188/* config registers for header type 0 devices */ 189 190#define PCIR_BARS 0x10 191#define PCIR_BAR(x) (PCIR_BARS + (x) * 4) 192#define PCIR_MAX_BAR_0 5 193#define PCI_RID2BAR(rid) (((rid) - PCIR_BARS) / 4) 194#define PCI_BAR_IO(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_IO_SPACE) 195#define PCI_BAR_MEM(x) (((x) & PCIM_BAR_SPACE) == PCIM_BAR_MEM_SPACE) 196#define PCIM_BAR_SPACE 0x00000001 197#define PCIM_BAR_MEM_SPACE 0 198#define PCIM_BAR_IO_SPACE 1 199#define PCIM_BAR_MEM_TYPE 0x00000006 200#define PCIM_BAR_MEM_32 0 201#define PCIM_BAR_MEM_1MB 2 /* Locate below 1MB in PCI <= 2.1 */ 202#define PCIM_BAR_MEM_64 4 203#define PCIM_BAR_MEM_PREFETCH 0x00000008 204#define PCIM_BAR_MEM_BASE 0xfffffffffffffff0ULL 205#define PCIM_BAR_IO_RESERVED 0x00000002 206#define PCIM_BAR_IO_BASE 0xfffffffc 207#define PCIR_CIS 0x28 208#define PCIM_CIS_ASI_MASK 0x00000007 209#define PCIM_CIS_ASI_CONFIG 0 210#define PCIM_CIS_ASI_BAR0 1 211#define PCIM_CIS_ASI_BAR1 2 212#define PCIM_CIS_ASI_BAR2 3 213#define PCIM_CIS_ASI_BAR3 4 214#define PCIM_CIS_ASI_BAR4 5 215#define PCIM_CIS_ASI_BAR5 6 216#define PCIM_CIS_ASI_ROM 7 217#define PCIM_CIS_ADDR_MASK 0x0ffffff8 218#define PCIM_CIS_ROM_MASK 0xf0000000 219#define PCIM_CIS_CONFIG_MASK 0xff 220#define PCIR_SUBVEND_0 0x2c 221#define PCIR_SUBDEV_0 0x2e 222#define PCIR_BIOS 0x30 223#define PCIM_BIOS_ENABLE 0x01 224#define PCIM_BIOS_ADDR_MASK 0xfffff800 225#define PCIR_CAP_PTR 0x34 226#define PCIR_INTLINE 0x3c 227#define PCIR_INTPIN 0x3d 228#define PCIR_MINGNT 0x3e 229#define PCIR_MAXLAT 0x3f 230 231/* config registers for header type 1 (PCI-to-PCI bridge) devices */ 232 233#define PCIR_MAX_BAR_1 1 234#define PCIR_SECSTAT_1 0x1e 235 236#define PCIR_PRIBUS_1 0x18 237#define PCIR_SECBUS_1 0x19 238#define PCIR_SUBBUS_1 0x1a 239#define PCIR_SECLAT_1 0x1b 240 241#define PCIR_IOBASEL_1 0x1c 242#define PCIR_IOLIMITL_1 0x1d 243#define PCIR_IOBASEH_1 0x30 244#define PCIR_IOLIMITH_1 0x32 245#define PCIM_BRIO_16 0x0 246#define PCIM_BRIO_32 0x1 247#define PCIM_BRIO_MASK 0xf 248 249#define PCIR_MEMBASE_1 0x20 250#define PCIR_MEMLIMIT_1 0x22 251 252#define PCIR_PMBASEL_1 0x24 253#define PCIR_PMLIMITL_1 0x26 254#define PCIR_PMBASEH_1 0x28 255#define PCIR_PMLIMITH_1 0x2c 256#define PCIM_BRPM_32 0x0 257#define PCIM_BRPM_64 0x1 258#define PCIM_BRPM_MASK 0xf 259 260#define PCIR_BIOS_1 0x38 261#define PCIR_BRIDGECTL_1 0x3e 262 263/* config registers for header type 2 (CardBus) devices */ 264 265#define PCIR_MAX_BAR_2 0 266#define PCIR_CAP_PTR_2 0x14 267#define PCIR_SECSTAT_2 0x16 268 269#define PCIR_PRIBUS_2 0x18 270#define PCIR_SECBUS_2 0x19 271#define PCIR_SUBBUS_2 0x1a 272#define PCIR_SECLAT_2 0x1b 273 274#define PCIR_MEMBASE0_2 0x1c 275#define PCIR_MEMLIMIT0_2 0x20 276#define PCIR_MEMBASE1_2 0x24 277#define PCIR_MEMLIMIT1_2 0x28 278#define PCIR_IOBASE0_2 0x2c 279#define PCIR_IOLIMIT0_2 0x30 280#define PCIR_IOBASE1_2 0x34 281#define PCIR_IOLIMIT1_2 0x38 282 283#define PCIR_BRIDGECTL_2 0x3e 284 285#define PCIR_SUBVEND_2 0x40 286#define PCIR_SUBDEV_2 0x42 287 288#define PCIR_PCCARDIF_2 0x44 289 290/* PCI device class, subclass and programming interface definitions */ 291 292#define PCIC_OLD 0x00 293#define PCIS_OLD_NONVGA 0x00 294#define PCIS_OLD_VGA 0x01 295 296#define PCIC_STORAGE 0x01 297#define PCIS_STORAGE_SCSI 0x00 298#define PCIS_STORAGE_IDE 0x01 299#define PCIP_STORAGE_IDE_MODEPRIM 0x01 300#define PCIP_STORAGE_IDE_PROGINDPRIM 0x02 301#define PCIP_STORAGE_IDE_MODESEC 0x04 302#define PCIP_STORAGE_IDE_PROGINDSEC 0x08 303#define PCIP_STORAGE_IDE_MASTERDEV 0x80 304#define PCIS_STORAGE_FLOPPY 0x02 305#define PCIS_STORAGE_IPI 0x03 306#define PCIS_STORAGE_RAID 0x04 307#define PCIS_STORAGE_ATA_ADMA 0x05 308#define PCIS_STORAGE_SATA 0x06 309#define PCIP_STORAGE_SATA_AHCI_1_0 0x01 310#define PCIS_STORAGE_SAS 0x07 311#define PCIS_STORAGE_NVM 0x08 312#define PCIP_STORAGE_NVM_NVMHCI_1_0 0x01 313#define PCIP_STORAGE_NVM_ENTERPRISE_NVMHCI_1_0 0x02 314#define PCIS_STORAGE_OTHER 0x80 315 316#define PCIC_NETWORK 0x02 317#define PCIS_NETWORK_ETHERNET 0x00 318#define PCIS_NETWORK_TOKENRING 0x01 319#define PCIS_NETWORK_FDDI 0x02 320#define PCIS_NETWORK_ATM 0x03 321#define PCIS_NETWORK_ISDN 0x04 322#define PCIS_NETWORK_WORLDFIP 0x05 323#define PCIS_NETWORK_PICMG 0x06 324#define PCIS_NETWORK_OTHER 0x80 325 326#define PCIC_DISPLAY 0x03 327#define PCIS_DISPLAY_VGA 0x00 328#define PCIS_DISPLAY_XGA 0x01 329#define PCIS_DISPLAY_3D 0x02 330#define PCIS_DISPLAY_OTHER 0x80 331 332#define PCIC_MULTIMEDIA 0x04 333#define PCIS_MULTIMEDIA_VIDEO 0x00 334#define PCIS_MULTIMEDIA_AUDIO 0x01 335#define PCIS_MULTIMEDIA_TELE 0x02 336#define PCIS_MULTIMEDIA_HDA 0x03 337#define PCIS_MULTIMEDIA_OTHER 0x80 338 339#define PCIC_MEMORY 0x05 340#define PCIS_MEMORY_RAM 0x00 341#define PCIS_MEMORY_FLASH 0x01 342#define PCIS_MEMORY_OTHER 0x80 343 344#define PCIC_BRIDGE 0x06 345#define PCIS_BRIDGE_HOST 0x00 346#define PCIS_BRIDGE_ISA 0x01 347#define PCIS_BRIDGE_EISA 0x02 348#define PCIS_BRIDGE_MCA 0x03 349#define PCIS_BRIDGE_PCI 0x04 350#define PCIP_BRIDGE_PCI_SUBTRACTIVE 0x01 351#define PCIS_BRIDGE_PCMCIA 0x05 352#define PCIS_BRIDGE_NUBUS 0x06 353#define PCIS_BRIDGE_CARDBUS 0x07 354#define PCIS_BRIDGE_RACEWAY 0x08 355#define PCIS_BRIDGE_PCI_TRANSPARENT 0x09 356#define PCIS_BRIDGE_INFINIBAND 0x0a 357#define PCIS_BRIDGE_OTHER 0x80 358 359#define PCIC_SIMPLECOMM 0x07 360#define PCIS_SIMPLECOMM_UART 0x00 361#define PCIP_SIMPLECOMM_UART_8250 0x00 362#define PCIP_SIMPLECOMM_UART_16450A 0x01 363#define PCIP_SIMPLECOMM_UART_16550A 0x02 364#define PCIP_SIMPLECOMM_UART_16650A 0x03 365#define PCIP_SIMPLECOMM_UART_16750A 0x04 366#define PCIP_SIMPLECOMM_UART_16850A 0x05 367#define PCIP_SIMPLECOMM_UART_16950A 0x06 368#define PCIS_SIMPLECOMM_PAR 0x01 369#define PCIS_SIMPLECOMM_MULSER 0x02 370#define PCIS_SIMPLECOMM_MODEM 0x03 371#define PCIS_SIMPLECOMM_GPIB 0x04 372#define PCIS_SIMPLECOMM_SMART_CARD 0x05 373#define PCIS_SIMPLECOMM_OTHER 0x80 374 375#define PCIC_BASEPERIPH 0x08 376#define PCIS_BASEPERIPH_PIC 0x00 377#define PCIP_BASEPERIPH_PIC_8259A 0x00 378#define PCIP_BASEPERIPH_PIC_ISA 0x01 379#define PCIP_BASEPERIPH_PIC_EISA 0x02 380#define PCIP_BASEPERIPH_PIC_IO_APIC 0x10 381#define PCIP_BASEPERIPH_PIC_IOX_APIC 0x20 382#define PCIS_BASEPERIPH_DMA 0x01 383#define PCIS_BASEPERIPH_TIMER 0x02 384#define PCIS_BASEPERIPH_RTC 0x03 385#define PCIS_BASEPERIPH_PCIHOT 0x04 386#define PCIS_BASEPERIPH_SDHC 0x05 387#define PCIS_BASEPERIPH_IOMMU 0x06 388#define PCIS_BASEPERIPH_OTHER 0x80 389 390#define PCIC_INPUTDEV 0x09 391#define PCIS_INPUTDEV_KEYBOARD 0x00 392#define PCIS_INPUTDEV_DIGITIZER 0x01 393#define PCIS_INPUTDEV_MOUSE 0x02 394#define PCIS_INPUTDEV_SCANNER 0x03 395#define PCIS_INPUTDEV_GAMEPORT 0x04 396#define PCIS_INPUTDEV_OTHER 0x80 397 398#define PCIC_DOCKING 0x0a 399#define PCIS_DOCKING_GENERIC 0x00 400#define PCIS_DOCKING_OTHER 0x80 401 402#define PCIC_PROCESSOR 0x0b 403#define PCIS_PROCESSOR_386 0x00 404#define PCIS_PROCESSOR_486 0x01 405#define PCIS_PROCESSOR_PENTIUM 0x02 406#define PCIS_PROCESSOR_ALPHA 0x10 407#define PCIS_PROCESSOR_POWERPC 0x20 408#define PCIS_PROCESSOR_MIPS 0x30 409#define PCIS_PROCESSOR_COPROC 0x40 410 411#define PCIC_SERIALBUS 0x0c 412#define PCIS_SERIALBUS_FW 0x00 413#define PCIS_SERIALBUS_ACCESS 0x01 414#define PCIS_SERIALBUS_SSA 0x02 415#define PCIS_SERIALBUS_USB 0x03 416#define PCIP_SERIALBUS_USB_UHCI 0x00 417#define PCIP_SERIALBUS_USB_OHCI 0x10 418#define PCIP_SERIALBUS_USB_EHCI 0x20 419#define PCIP_SERIALBUS_USB_XHCI 0x30 420#define PCIP_SERIALBUS_USB_DEVICE 0xfe 421#define PCIS_SERIALBUS_FC 0x04 422#define PCIS_SERIALBUS_SMBUS 0x05 423#define PCIS_SERIALBUS_INFINIBAND 0x06 424#define PCIS_SERIALBUS_IPMI 0x07 425#define PCIP_SERIALBUS_IPMI_SMIC 0x00 426#define PCIP_SERIALBUS_IPMI_KCS 0x01 427#define PCIP_SERIALBUS_IPMI_BT 0x02 428#define PCIS_SERIALBUS_SERCOS 0x08 429#define PCIS_SERIALBUS_CANBUS 0x09 430 431#define PCIC_WIRELESS 0x0d 432#define PCIS_WIRELESS_IRDA 0x00 433#define PCIS_WIRELESS_IR 0x01 434#define PCIS_WIRELESS_RF 0x10 435#define PCIS_WIRELESS_BLUETOOTH 0x11 436#define PCIS_WIRELESS_BROADBAND 0x12 437#define PCIS_WIRELESS_80211A 0x20 438#define PCIS_WIRELESS_80211B 0x21 439#define PCIS_WIRELESS_OTHER 0x80 440 441#define PCIC_INTELLIIO 0x0e 442#define PCIS_INTELLIIO_I2O 0x00 443 444#define PCIC_SATCOM 0x0f 445#define PCIS_SATCOM_TV 0x01 446#define PCIS_SATCOM_AUDIO 0x02 447#define PCIS_SATCOM_VOICE 0x03 448#define PCIS_SATCOM_DATA 0x04 449 450#define PCIC_CRYPTO 0x10 451#define PCIS_CRYPTO_NETCOMP 0x00 452#define PCIS_CRYPTO_ENTERTAIN 0x10 453#define PCIS_CRYPTO_OTHER 0x80 454 455#define PCIC_DASP 0x11 456#define PCIS_DASP_DPIO 0x00 457#define PCIS_DASP_PERFCNTRS 0x01 458#define PCIS_DASP_COMM_SYNC 0x10 459#define PCIS_DASP_MGMT_CARD 0x20 460#define PCIS_DASP_OTHER 0x80 461 462#define PCIC_OTHER 0xff 463 464/* Bridge Control Values. */ 465#define PCIB_BCR_PERR_ENABLE 0x0001 466#define PCIB_BCR_SERR_ENABLE 0x0002 467#define PCIB_BCR_ISA_ENABLE 0x0004 468#define PCIB_BCR_VGA_ENABLE 0x0008 469#define PCIB_BCR_MASTER_ABORT_MODE 0x0020 470#define PCIB_BCR_SECBUS_RESET 0x0040 471#define PCIB_BCR_SECBUS_BACKTOBACK 0x0080 472#define PCIB_BCR_PRI_DISCARD_TIMEOUT 0x0100 473#define PCIB_BCR_SEC_DISCARD_TIMEOUT 0x0200 474#define PCIB_BCR_DISCARD_TIMER_STATUS 0x0400 475#define PCIB_BCR_DISCARD_TIMER_SERREN 0x0800 476 477/* PCI power manangement */ 478#define PCIR_POWER_CAP 0x2 479#define PCIM_PCAP_SPEC 0x0007 480#define PCIM_PCAP_PMEREQCLK 0x0008 481#define PCIM_PCAP_DEVSPECINIT 0x0020 482#define PCIM_PCAP_AUXPWR_0 0x0000 483#define PCIM_PCAP_AUXPWR_55 0x0040 484#define PCIM_PCAP_AUXPWR_100 0x0080 485#define PCIM_PCAP_AUXPWR_160 0x00c0 486#define PCIM_PCAP_AUXPWR_220 0x0100 487#define PCIM_PCAP_AUXPWR_270 0x0140 488#define PCIM_PCAP_AUXPWR_320 0x0180 489#define PCIM_PCAP_AUXPWR_375 0x01c0 490#define PCIM_PCAP_AUXPWRMASK 0x01c0 491#define PCIM_PCAP_D1SUPP 0x0200 492#define PCIM_PCAP_D2SUPP 0x0400 493#define PCIM_PCAP_D0PME 0x0800 494#define PCIM_PCAP_D1PME 0x1000 495#define PCIM_PCAP_D2PME 0x2000 496#define PCIM_PCAP_D3PME_HOT 0x4000 497#define PCIM_PCAP_D3PME_COLD 0x8000 498 499#define PCIR_POWER_STATUS 0x4 500#define PCIM_PSTAT_D0 0x0000 501#define PCIM_PSTAT_D1 0x0001 502#define PCIM_PSTAT_D2 0x0002 503#define PCIM_PSTAT_D3 0x0003 504#define PCIM_PSTAT_DMASK 0x0003 505#define PCIM_PSTAT_NOSOFTRESET 0x0008 506#define PCIM_PSTAT_PMEENABLE 0x0100 507#define PCIM_PSTAT_D0POWER 0x0000 508#define PCIM_PSTAT_D1POWER 0x0200 509#define PCIM_PSTAT_D2POWER 0x0400 510#define PCIM_PSTAT_D3POWER 0x0600 511#define PCIM_PSTAT_D0HEAT 0x0800 512#define PCIM_PSTAT_D1HEAT 0x0a00 513#define PCIM_PSTAT_D2HEAT 0x0c00 514#define PCIM_PSTAT_D3HEAT 0x0e00 515#define PCIM_PSTAT_DATASELMASK 0x1e00 516#define PCIM_PSTAT_DATAUNKN 0x0000 517#define PCIM_PSTAT_DATADIV10 0x2000 518#define PCIM_PSTAT_DATADIV100 0x4000 519#define PCIM_PSTAT_DATADIV1000 0x6000 520#define PCIM_PSTAT_DATADIVMASK 0x6000 521#define PCIM_PSTAT_PME 0x8000 522 523#define PCIR_POWER_BSE 0x6 524#define PCIM_PMCSR_BSE_D3B3 0x00 525#define PCIM_PMCSR_BSE_D3B2 0x40 526#define PCIM_PMCSR_BSE_BPCCE 0x80 527 528#define PCIR_POWER_DATA 0x7 529 530/* VPD capability registers */ 531#define PCIR_VPD_ADDR 0x2 532#define PCIR_VPD_DATA 0x4 533 534/* PCI Message Signalled Interrupts (MSI) */ 535#define PCIR_MSI_CTRL 0x2 536#define PCIM_MSICTRL_VECTOR 0x0100 537#define PCIM_MSICTRL_64BIT 0x0080 538#define PCIM_MSICTRL_MME_MASK 0x0070 539#define PCIM_MSICTRL_MME_1 0x0000 540#define PCIM_MSICTRL_MME_2 0x0010 541#define PCIM_MSICTRL_MME_4 0x0020 542#define PCIM_MSICTRL_MME_8 0x0030 543#define PCIM_MSICTRL_MME_16 0x0040 544#define PCIM_MSICTRL_MME_32 0x0050 545#define PCIM_MSICTRL_MMC_MASK 0x000E 546#define PCIM_MSICTRL_MMC_1 0x0000 547#define PCIM_MSICTRL_MMC_2 0x0002 548#define PCIM_MSICTRL_MMC_4 0x0004 549#define PCIM_MSICTRL_MMC_8 0x0006 550#define PCIM_MSICTRL_MMC_16 0x0008 551#define PCIM_MSICTRL_MMC_32 0x000A 552#define PCIM_MSICTRL_MSI_ENABLE 0x0001 553#define PCIR_MSI_ADDR 0x4 554#define PCIR_MSI_ADDR_HIGH 0x8 555#define PCIR_MSI_DATA 0x8 556#define PCIR_MSI_DATA_64BIT 0xc 557#define PCIR_MSI_MASK 0x10 558#define PCIR_MSI_PENDING 0x14 559 560/* PCI-X definitions */ 561 562/* For header type 0 devices */ 563#define PCIXR_COMMAND 0x2 564#define PCIXM_COMMAND_DPERR_E 0x0001 /* Data Parity Error Recovery */ 565#define PCIXM_COMMAND_ERO 0x0002 /* Enable Relaxed Ordering */ 566#define PCIXM_COMMAND_MAX_READ 0x000c /* Maximum Burst Read Count */ 567#define PCIXM_COMMAND_MAX_READ_512 0x0000 568#define PCIXM_COMMAND_MAX_READ_1024 0x0004 569#define PCIXM_COMMAND_MAX_READ_2048 0x0008 570#define PCIXM_COMMAND_MAX_READ_4096 0x000c 571#define PCIXM_COMMAND_MAX_SPLITS 0x0070 /* Maximum Split Transactions */ 572#define PCIXM_COMMAND_MAX_SPLITS_1 0x0000 573#define PCIXM_COMMAND_MAX_SPLITS_2 0x0010 574#define PCIXM_COMMAND_MAX_SPLITS_3 0x0020 575#define PCIXM_COMMAND_MAX_SPLITS_4 0x0030 576#define PCIXM_COMMAND_MAX_SPLITS_8 0x0040 577#define PCIXM_COMMAND_MAX_SPLITS_12 0x0050 578#define PCIXM_COMMAND_MAX_SPLITS_16 0x0060 579#define PCIXM_COMMAND_MAX_SPLITS_32 0x0070 580#define PCIXM_COMMAND_VERSION 0x3000 581#define PCIXR_STATUS 0x4 582#define PCIXM_STATUS_DEVFN 0x000000FF 583#define PCIXM_STATUS_BUS 0x0000FF00 584#define PCIXM_STATUS_64BIT 0x00010000 585#define PCIXM_STATUS_133CAP 0x00020000 586#define PCIXM_STATUS_SC_DISCARDED 0x00040000 587#define PCIXM_STATUS_UNEXP_SC 0x00080000 588#define PCIXM_STATUS_COMPLEX_DEV 0x00100000 589#define PCIXM_STATUS_MAX_READ 0x00600000 590#define PCIXM_STATUS_MAX_READ_512 0x00000000 591#define PCIXM_STATUS_MAX_READ_1024 0x00200000 592#define PCIXM_STATUS_MAX_READ_2048 0x00400000 593#define PCIXM_STATUS_MAX_READ_4096 0x00600000 594#define PCIXM_STATUS_MAX_SPLITS 0x03800000 595#define PCIXM_STATUS_MAX_SPLITS_1 0x00000000 596#define PCIXM_STATUS_MAX_SPLITS_2 0x00800000 597#define PCIXM_STATUS_MAX_SPLITS_3 0x01000000 598#define PCIXM_STATUS_MAX_SPLITS_4 0x01800000 599#define PCIXM_STATUS_MAX_SPLITS_8 0x02000000 600#define PCIXM_STATUS_MAX_SPLITS_12 0x02800000 601#define PCIXM_STATUS_MAX_SPLITS_16 0x03000000 602#define PCIXM_STATUS_MAX_SPLITS_32 0x03800000 603#define PCIXM_STATUS_MAX_CUM_READ 0x1C000000 604#define PCIXM_STATUS_RCVD_SC_ERR 0x20000000 605#define PCIXM_STATUS_266CAP 0x40000000 606#define PCIXM_STATUS_533CAP 0x80000000 607 608/* For header type 1 devices (PCI-X bridges) */ 609#define PCIXR_SEC_STATUS 0x2 610#define PCIXM_SEC_STATUS_64BIT 0x0001 611#define PCIXM_SEC_STATUS_133CAP 0x0002 612#define PCIXM_SEC_STATUS_SC_DISC 0x0004 613#define PCIXM_SEC_STATUS_UNEXP_SC 0x0008 614#define PCIXM_SEC_STATUS_SC_OVERRUN 0x0010 615#define PCIXM_SEC_STATUS_SR_DELAYED 0x0020 616#define PCIXM_SEC_STATUS_BUS_MODE 0x03c0 617#define PCIXM_SEC_STATUS_VERSION 0x3000 618#define PCIXM_SEC_STATUS_266CAP 0x4000 619#define PCIXM_SEC_STATUS_533CAP 0x8000 620#define PCIXR_BRIDGE_STATUS 0x4 621#define PCIXM_BRIDGE_STATUS_DEVFN 0x000000FF 622#define PCIXM_BRIDGE_STATUS_BUS 0x0000FF00 623#define PCIXM_BRIDGE_STATUS_64BIT 0x00010000 624#define PCIXM_BRIDGE_STATUS_133CAP 0x00020000 625#define PCIXM_BRIDGE_STATUS_SC_DISCARDED 0x00040000 626#define PCIXM_BRIDGE_STATUS_UNEXP_SC 0x00080000 627#define PCIXM_BRIDGE_STATUS_SC_OVERRUN 0x00100000 628#define PCIXM_BRIDGE_STATUS_SR_DELAYED 0x00200000 629#define PCIXM_BRIDGE_STATUS_DEVID_MSGCAP 0x20000000 630#define PCIXM_BRIDGE_STATUS_266CAP 0x40000000 631#define PCIXM_BRIDGE_STATUS_533CAP 0x80000000 632 633/* HT (HyperTransport) Capability definitions */ 634#define PCIR_HT_COMMAND 0x2 635#define PCIM_HTCMD_CAP_MASK 0xf800 /* Capability type. */ 636#define PCIM_HTCAP_SLAVE 0x0000 /* 000xx */ 637#define PCIM_HTCAP_HOST 0x2000 /* 001xx */ 638#define PCIM_HTCAP_SWITCH 0x4000 /* 01000 */ 639#define PCIM_HTCAP_INTERRUPT 0x8000 /* 10000 */ 640#define PCIM_HTCAP_REVISION_ID 0x8800 /* 10001 */ 641#define PCIM_HTCAP_UNITID_CLUMPING 0x9000 /* 10010 */ 642#define PCIM_HTCAP_EXT_CONFIG_SPACE 0x9800 /* 10011 */ 643#define PCIM_HTCAP_ADDRESS_MAPPING 0xa000 /* 10100 */ 644#define PCIM_HTCAP_MSI_MAPPING 0xa800 /* 10101 */ 645#define PCIM_HTCAP_DIRECT_ROUTE 0xb000 /* 10110 */ 646#define PCIM_HTCAP_VCSET 0xb800 /* 10111 */ 647#define PCIM_HTCAP_RETRY_MODE 0xc000 /* 11000 */ 648#define PCIM_HTCAP_X86_ENCODING 0xc800 /* 11001 */ 649#define PCIM_HTCAP_GEN3 0xd000 /* 11010 */ 650#define PCIM_HTCAP_FLE 0xd800 /* 11011 */ 651#define PCIM_HTCAP_PM 0xe000 /* 11100 */ 652#define PCIM_HTCAP_HIGH_NODE_COUNT 0xe800 /* 11101 */ 653 654/* HT MSI Mapping Capability definitions. */ 655#define PCIM_HTCMD_MSI_ENABLE 0x0001 656#define PCIM_HTCMD_MSI_FIXED 0x0002 657#define PCIR_HTMSI_ADDRESS_LO 0x4 658#define PCIR_HTMSI_ADDRESS_HI 0x8 659 660/* PCI Vendor capability definitions */ 661#define PCIR_VENDOR_LENGTH 0x2 662#define PCIR_VENDOR_DATA 0x3 663 664/* PCI EHCI Debug Port definitions */ 665#define PCIR_DEBUG_PORT 0x2 666#define PCIM_DEBUG_PORT_OFFSET 0x1FFF 667#define PCIM_DEBUG_PORT_BAR 0xe000 668 669/* PCI-PCI Bridge Subvendor definitions */ 670#define PCIR_SUBVENDCAP_ID 0x4 671 672/* PCI Express definitions */ 673#define PCIER_FLAGS 0x2 674#define PCIEM_FLAGS_VERSION 0x000F 675#define PCIEM_FLAGS_TYPE 0x00F0 676#define PCIEM_TYPE_ENDPOINT 0x0000 677#define PCIEM_TYPE_LEGACY_ENDPOINT 0x0010 678#define PCIEM_TYPE_ROOT_PORT 0x0040 679#define PCIEM_TYPE_UPSTREAM_PORT 0x0050 680#define PCIEM_TYPE_DOWNSTREAM_PORT 0x0060 681#define PCIEM_TYPE_PCI_BRIDGE 0x0070 682#define PCIEM_TYPE_PCIE_BRIDGE 0x0080 683#define PCIEM_TYPE_ROOT_INT_EP 0x0090 684#define PCIEM_TYPE_ROOT_EC 0x00a0 685#define PCIEM_FLAGS_SLOT 0x0100 686#define PCIEM_FLAGS_IRQ 0x3e00 687#define PCIER_DEVICE_CAP 0x4 688#define PCIEM_CAP_MAX_PAYLOAD 0x00000007 689#define PCIEM_CAP_PHANTHOM_FUNCS 0x00000018 690#define PCIEM_CAP_EXT_TAG_FIELD 0x00000020 691#define PCIEM_CAP_L0S_LATENCY 0x000001c0 692#define PCIEM_CAP_L1_LATENCY 0x00000e00 693#define PCIEM_CAP_ROLE_ERR_RPT 0x00008000 694#define PCIEM_CAP_SLOT_PWR_LIM_VAL 0x03fc0000 695#define PCIEM_CAP_SLOT_PWR_LIM_SCALE 0x0c000000 696#define PCIEM_CAP_FLR 0x10000000 697#define PCIER_DEVICE_CTL 0x8 698#define PCIEM_CTL_COR_ENABLE 0x0001 699#define PCIEM_CTL_NFER_ENABLE 0x0002 700#define PCIEM_CTL_FER_ENABLE 0x0004 701#define PCIEM_CTL_URR_ENABLE 0x0008 702#define PCIEM_CTL_RELAXED_ORD_ENABLE 0x0010 703#define PCIEM_CTL_MAX_PAYLOAD 0x00e0 704#define PCIEM_CTL_EXT_TAG_FIELD 0x0100 705#define PCIEM_CTL_PHANTHOM_FUNCS 0x0200 706#define PCIEM_CTL_AUX_POWER_PM 0x0400 707#define PCIEM_CTL_NOSNOOP_ENABLE 0x0800 708#define PCIEM_CTL_MAX_READ_REQUEST 0x7000 709#define PCIEM_CTL_BRDG_CFG_RETRY 0x8000 /* PCI-E - PCI/PCI-X bridges */ 710#define PCIEM_CTL_INITIATE_FLR 0x8000 /* FLR capable endpoints */ 711#define PCIER_DEVICE_STA 0xa 712#define PCIEM_STA_CORRECTABLE_ERROR 0x0001 713#define PCIEM_STA_NON_FATAL_ERROR 0x0002 714#define PCIEM_STA_FATAL_ERROR 0x0004 715#define PCIEM_STA_UNSUPPORTED_REQ 0x0008 716#define PCIEM_STA_AUX_POWER 0x0010 717#define PCIEM_STA_TRANSACTION_PND 0x0020 718#define PCIER_LINK_CAP 0xc 719#define PCIEM_LINK_CAP_MAX_SPEED 0x0000000f 720#define PCIEM_LINK_CAP_MAX_WIDTH 0x000003f0 721#define PCIEM_LINK_CAP_ASPM 0x00000c00 722#define PCIEM_LINK_CAP_L0S_EXIT 0x00007000 723#define PCIEM_LINK_CAP_L1_EXIT 0x00038000 724#define PCIEM_LINK_CAP_CLOCK_PM 0x00040000 725#define PCIEM_LINK_CAP_SURPRISE_DOWN 0x00080000 726#define PCIEM_LINK_CAP_DL_ACTIVE 0x00100000 727#define PCIEM_LINK_CAP_LINK_BW_NOTIFY 0x00200000 728#define PCIEM_LINK_CAP_ASPM_COMPLIANCE 0x00400000 729#define PCIEM_LINK_CAP_PORT 0xff000000 730#define PCIER_LINK_CTL 0x10 731#define PCIEM_LINK_CTL_ASPMC_DIS 0x0000 732#define PCIEM_LINK_CTL_ASPMC_L0S 0x0001 733#define PCIEM_LINK_CTL_ASPMC_L1 0x0002 734#define PCIEM_LINK_CTL_ASPMC 0x0003 735#define PCIEM_LINK_CTL_RCB 0x0008 736#define PCIEM_LINK_CTL_LINK_DIS 0x0010 737#define PCIEM_LINK_CTL_RETRAIN_LINK 0x0020 738#define PCIEM_LINK_CTL_COMMON_CLOCK 0x0040 739#define PCIEM_LINK_CTL_EXTENDED_SYNC 0x0080 740#define PCIEM_LINK_CTL_ECPM 0x0100 741#define PCIEM_LINK_CTL_HAWD 0x0200 742#define PCIEM_LINK_CTL_LBMIE 0x0400 743#define PCIEM_LINK_CTL_LABIE 0x0800 744#define PCIER_LINK_STA 0x12 745#define PCIEM_LINK_STA_SPEED 0x000f 746#define PCIEM_LINK_STA_WIDTH 0x03f0 747#define PCIEM_LINK_STA_TRAINING_ERROR 0x0400 748#define PCIEM_LINK_STA_TRAINING 0x0800 749#define PCIEM_LINK_STA_SLOT_CLOCK 0x1000 750#define PCIEM_LINK_STA_DL_ACTIVE 0x2000 751#define PCIEM_LINK_STA_LINK_BW_MGMT 0x4000 752#define PCIEM_LINK_STA_LINK_AUTO_BW 0x8000 753#define PCIER_SLOT_CAP 0x14 754#define PCIEM_SLOT_CAP_APB 0x00000001 755#define PCIEM_SLOT_CAP_PCP 0x00000002 756#define PCIEM_SLOT_CAP_MRLSP 0x00000004 757#define PCIEM_SLOT_CAP_AIP 0x00000008 758#define PCIEM_SLOT_CAP_PIP 0x00000010 759#define PCIEM_SLOT_CAP_HPS 0x00000020 760#define PCIEM_SLOT_CAP_HPC 0x00000040 761#define PCIEM_SLOT_CAP_SPLV 0x00007f80 762#define PCIEM_SLOT_CAP_SPLS 0x00018000 763#define PCIEM_SLOT_CAP_EIP 0x00020000 764#define PCIEM_SLOT_CAP_NCCS 0x00040000 765#define PCIEM_SLOT_CAP_PSN 0xfff80000 766#define PCIER_SLOT_CTL 0x18 767#define PCIEM_SLOT_CTL_ABPE 0x0001 768#define PCIEM_SLOT_CTL_PFDE 0x0002 769#define PCIEM_SLOT_CTL_MRLSCE 0x0004 770#define PCIEM_SLOT_CTL_PDCE 0x0008 771#define PCIEM_SLOT_CTL_CCIE 0x0010 772#define PCIEM_SLOT_CTL_HPIE 0x0020 773#define PCIEM_SLOT_CTL_AIC 0x00c0 774#define PCIEM_SLOT_CTL_PIC 0x0300 775#define PCIEM_SLOT_CTL_PCC 0x0400 776#define PCIEM_SLOT_CTL_EIC 0x0800 777#define PCIEM_SLOT_CTL_DLLSCE 0x1000 778#define PCIER_SLOT_STA 0x1a 779#define PCIEM_SLOT_STA_ABP 0x0001 780#define PCIEM_SLOT_STA_PFD 0x0002 781#define PCIEM_SLOT_STA_MRLSC 0x0004 782#define PCIEM_SLOT_STA_PDC 0x0008 783#define PCIEM_SLOT_STA_CC 0x0010 784#define PCIEM_SLOT_STA_MRLSS 0x0020 785#define PCIEM_SLOT_STA_PDS 0x0040 786#define PCIEM_SLOT_STA_EIS 0x0080 787#define PCIEM_SLOT_STA_DLLSC 0x0100 788#define PCIER_ROOT_CTL 0x1c 789#define PCIEM_ROOT_CTL_SERR_CORR 0x0001 790#define PCIEM_ROOT_CTL_SERR_NONFATAL 0x0002 791#define PCIEM_ROOT_CTL_SERR_FATAL 0x0004 792#define PCIEM_ROOT_CTL_PME 0x0008 793#define PCIEM_ROOT_CTL_CRS_VIS 0x0010 794#define PCIER_ROOT_CAP 0x1e 795#define PCIEM_ROOT_CAP_CRS_VIS 0x0001 796#define PCIER_ROOT_STA 0x20 797#define PCIEM_ROOT_STA_PME_REQID_MASK 0x0000ffff 798#define PCIEM_ROOT_STA_PME_STATUS 0x00010000 799#define PCIEM_ROOT_STA_PME_PEND 0x00020000 800#define PCIER_DEVICE_CAP2 0x24 801#define PCIEM_CAP2_ARI 0x20 802#define PCIER_DEVICE_CTL2 0x28 803#define PCIEM_CTL2_COMP_TIMEOUT_VAL 0x000f 804#define PCIEM_CTL2_COMP_TIMEOUT_DIS 0x0010 805#define PCIEM_CTL2_ARI 0x0020 806#define PCIEM_CTL2_ATOMIC_REQ_ENABLE 0x0040 807#define PCIEM_CTL2_ATOMIC_EGR_BLOCK 0x0080 808#define PCIEM_CTL2_ID_ORDERED_REQ_EN 0x0100 809#define PCIEM_CTL2_ID_ORDERED_CMP_EN 0x0200 810#define PCIEM_CTL2_LTR_ENABLE 0x0400 811#define PCIEM_CTL2_OBFF 0x6000 812#define PCIEM_OBFF_DISABLE 0x0000 813#define PCIEM_OBFF_MSGA_ENABLE 0x2000 814#define PCIEM_OBFF_MSGB_ENABLE 0x4000 815#define PCIEM_OBFF_WAKE_ENABLE 0x6000 816#define PCIEM_CTL2_END2END_TLP 0x8000 817#define PCIER_DEVICE_STA2 0x2a 818#define PCIER_LINK_CAP2 0x2c 819#define PCIER_LINK_CTL2 0x30 820#define PCIER_LINK_STA2 0x32 821#define PCIER_SLOT_CAP2 0x34 822#define PCIER_SLOT_CTL2 0x38 823#define PCIER_SLOT_STA2 0x3a 824 825/* MSI-X definitions */ 826#define PCIR_MSIX_CTRL 0x2 827#define PCIM_MSIXCTRL_MSIX_ENABLE 0x8000 828#define PCIM_MSIXCTRL_FUNCTION_MASK 0x4000 829#define PCIM_MSIXCTRL_TABLE_SIZE 0x07FF 830#define PCIR_MSIX_TABLE 0x4 831#define PCIR_MSIX_PBA 0x8 832#define PCIM_MSIX_BIR_MASK 0x7 833#define PCIM_MSIX_BIR_BAR_10 0 834#define PCIM_MSIX_BIR_BAR_14 1 835#define PCIM_MSIX_BIR_BAR_18 2 836#define PCIM_MSIX_BIR_BAR_1C 3 837#define PCIM_MSIX_BIR_BAR_20 4 838#define PCIM_MSIX_BIR_BAR_24 5 839#define PCIM_MSIX_VCTRL_MASK 0x1 840 841/* PCI Advanced Features definitions */ 842#define PCIR_PCIAF_CAP 0x3 843#define PCIM_PCIAFCAP_TP 0x01 844#define PCIM_PCIAFCAP_FLR 0x02 845#define PCIR_PCIAF_CTRL 0x4 846#define PCIR_PCIAFCTRL_FLR 0x01 847#define PCIR_PCIAF_STATUS 0x5 848#define PCIR_PCIAFSTATUS_TP 0x01 849 850/* Advanced Error Reporting */ 851#define PCIR_AER_UC_STATUS 0x04 852#define PCIM_AER_UC_TRAINING_ERROR 0x00000001 853#define PCIM_AER_UC_DL_PROTOCOL_ERROR 0x00000010 854#define PCIM_AER_UC_SURPRISE_LINK_DOWN 0x00000020 855#define PCIM_AER_UC_POISONED_TLP 0x00001000 856#define PCIM_AER_UC_FC_PROTOCOL_ERROR 0x00002000 857#define PCIM_AER_UC_COMPLETION_TIMEOUT 0x00004000 858#define PCIM_AER_UC_COMPLETER_ABORT 0x00008000 859#define PCIM_AER_UC_UNEXPECTED_COMPLETION 0x00010000 860#define PCIM_AER_UC_RECEIVER_OVERFLOW 0x00020000 861#define PCIM_AER_UC_MALFORMED_TLP 0x00040000 862#define PCIM_AER_UC_ECRC_ERROR 0x00080000 863#define PCIM_AER_UC_UNSUPPORTED_REQUEST 0x00100000 864#define PCIM_AER_UC_ACS_VIOLATION 0x00200000 865#define PCIM_AER_UC_INTERNAL_ERROR 0x00400000 866#define PCIM_AER_UC_MC_BLOCKED_TLP 0x00800000 867#define PCIM_AER_UC_ATOMIC_EGRESS_BLK 0x01000000 868#define PCIM_AER_UC_TLP_PREFIX_BLOCKED 0x02000000 869#define PCIR_AER_UC_MASK 0x08 /* Shares bits with UC_STATUS */ 870#define PCIR_AER_UC_SEVERITY 0x0c /* Shares bits with UC_STATUS */ 871#define PCIR_AER_COR_STATUS 0x10 872#define PCIM_AER_COR_RECEIVER_ERROR 0x00000001 873#define PCIM_AER_COR_BAD_TLP 0x00000040 874#define PCIM_AER_COR_BAD_DLLP 0x00000080 875#define PCIM_AER_COR_REPLAY_ROLLOVER 0x00000100 876#define PCIM_AER_COR_REPLAY_TIMEOUT 0x00001000 877#define PCIM_AER_COR_ADVISORY_NF_ERROR 0x00002000 878#define PCIM_AER_COR_INTERNAL_ERROR 0x00004000 879#define PCIM_AER_COR_HEADER_LOG_OVFLOW 0x00008000 880#define PCIR_AER_COR_MASK 0x14 /* Shares bits with COR_STATUS */ 881#define PCIR_AER_CAP_CONTROL 0x18 882#define PCIM_AER_FIRST_ERROR_PTR 0x0000001f 883#define PCIM_AER_ECRC_GEN_CAPABLE 0x00000020 884#define PCIM_AER_ECRC_GEN_ENABLE 0x00000040 885#define PCIM_AER_ECRC_CHECK_CAPABLE 0x00000080 886#define PCIM_AER_ECRC_CHECK_ENABLE 0x00000100 887#define PCIM_AER_MULT_HDR_CAPABLE 0x00000200 888#define PCIM_AER_MULT_HDR_ENABLE 0x00000400 889#define PCIM_AER_TLP_PREFIX_LOG_PRESENT 0x00000800 890#define PCIR_AER_HEADER_LOG 0x1c 891#define PCIR_AER_ROOTERR_CMD 0x2c /* Only for root complex ports */ 892#define PCIM_AER_ROOTERR_COR_ENABLE 0x00000001 893#define PCIM_AER_ROOTERR_NF_ENABLE 0x00000002 894#define PCIM_AER_ROOTERR_F_ENABLE 0x00000004 895#define PCIR_AER_ROOTERR_STATUS 0x30 /* Only for root complex ports */ 896#define PCIM_AER_ROOTERR_COR_ERR 0x00000001 897#define PCIM_AER_ROOTERR_MULTI_COR_ERR 0x00000002 898#define PCIM_AER_ROOTERR_UC_ERR 0x00000004 899#define PCIM_AER_ROOTERR_MULTI_UC_ERR 0x00000008 900#define PCIM_AER_ROOTERR_FIRST_UC_FATAL 0x00000010 901#define PCIM_AER_ROOTERR_NF_ERR 0x00000020 902#define PCIM_AER_ROOTERR_F_ERR 0x00000040 903#define PCIM_AER_ROOTERR_INT_MESSAGE 0xf8000000 904#define PCIR_AER_COR_SOURCE_ID 0x34 /* Only for root complex ports */ 905#define PCIR_AER_ERR_SOURCE_ID 0x36 /* Only for root complex ports */ 906#define PCIR_AER_TLP_PREFIX_LOG 0x38 /* Only for TLP prefix functions */ 907 908/* Virtual Channel definitions */ 909#define PCIR_VC_CAP1 0x04 910#define PCIM_VC_CAP1_EXT_COUNT 0x00000007 911#define PCIM_VC_CAP1_LOWPRI_EXT_COUNT 0x00000070 912#define PCIR_VC_CAP2 0x08 913#define PCIR_VC_CONTROL 0x0C 914#define PCIR_VC_STATUS 0x0E 915#define PCIR_VC_RESOURCE_CAP(n) (0x10 + (n) * 0x0C) 916#define PCIR_VC_RESOURCE_CTL(n) (0x14 + (n) * 0x0C) 917#define PCIR_VC_RESOURCE_STA(n) (0x18 + (n) * 0x0C) 918 919/* Serial Number definitions */ 920#define PCIR_SERIAL_LOW 0x04 921#define PCIR_SERIAL_HIGH 0x08 922 923