pci_pci.c revision 279470
1/*- 2 * Copyright (c) 1994,1995 Stefan Esser, Wolfgang StanglMeier 3 * Copyright (c) 2000 Michael Smith <msmith@freebsd.org> 4 * Copyright (c) 2000 BSDi 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31#include <sys/cdefs.h> 32__FBSDID("$FreeBSD: stable/10/sys/dev/pci/pci_pci.c 279470 2015-03-01 04:22:06Z rstone $"); 33 34/* 35 * PCI:PCI bridge support. 36 */ 37 38#include <sys/param.h> 39#include <sys/bus.h> 40#include <sys/kernel.h> 41#include <sys/malloc.h> 42#include <sys/module.h> 43#include <sys/rman.h> 44#include <sys/sysctl.h> 45#include <sys/systm.h> 46 47#include <dev/pci/pcivar.h> 48#include <dev/pci/pcireg.h> 49#include <dev/pci/pci_private.h> 50#include <dev/pci/pcib_private.h> 51 52#include "pcib_if.h" 53 54static int pcib_probe(device_t dev); 55static int pcib_suspend(device_t dev); 56static int pcib_resume(device_t dev); 57static int pcib_power_for_sleep(device_t pcib, device_t dev, 58 int *pstate); 59static uint16_t pcib_ari_get_rid(device_t pcib, device_t dev); 60static uint32_t pcib_read_config(device_t dev, u_int b, u_int s, 61 u_int f, u_int reg, int width); 62static void pcib_write_config(device_t dev, u_int b, u_int s, 63 u_int f, u_int reg, uint32_t val, int width); 64static int pcib_ari_maxslots(device_t dev); 65static int pcib_ari_maxfuncs(device_t dev); 66static int pcib_try_enable_ari(device_t pcib, device_t dev); 67 68static device_method_t pcib_methods[] = { 69 /* Device interface */ 70 DEVMETHOD(device_probe, pcib_probe), 71 DEVMETHOD(device_attach, pcib_attach), 72 DEVMETHOD(device_detach, bus_generic_detach), 73 DEVMETHOD(device_shutdown, bus_generic_shutdown), 74 DEVMETHOD(device_suspend, pcib_suspend), 75 DEVMETHOD(device_resume, pcib_resume), 76 77 /* Bus interface */ 78 DEVMETHOD(bus_read_ivar, pcib_read_ivar), 79 DEVMETHOD(bus_write_ivar, pcib_write_ivar), 80 DEVMETHOD(bus_alloc_resource, pcib_alloc_resource), 81#ifdef NEW_PCIB 82 DEVMETHOD(bus_adjust_resource, pcib_adjust_resource), 83 DEVMETHOD(bus_release_resource, pcib_release_resource), 84#else 85 DEVMETHOD(bus_adjust_resource, bus_generic_adjust_resource), 86 DEVMETHOD(bus_release_resource, bus_generic_release_resource), 87#endif 88 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 89 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 90 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 91 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 92 93 /* pcib interface */ 94 DEVMETHOD(pcib_maxslots, pcib_ari_maxslots), 95 DEVMETHOD(pcib_maxfuncs, pcib_ari_maxfuncs), 96 DEVMETHOD(pcib_read_config, pcib_read_config), 97 DEVMETHOD(pcib_write_config, pcib_write_config), 98 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt), 99 DEVMETHOD(pcib_alloc_msi, pcib_alloc_msi), 100 DEVMETHOD(pcib_release_msi, pcib_release_msi), 101 DEVMETHOD(pcib_alloc_msix, pcib_alloc_msix), 102 DEVMETHOD(pcib_release_msix, pcib_release_msix), 103 DEVMETHOD(pcib_map_msi, pcib_map_msi), 104 DEVMETHOD(pcib_power_for_sleep, pcib_power_for_sleep), 105 DEVMETHOD(pcib_get_rid, pcib_ari_get_rid), 106 DEVMETHOD(pcib_try_enable_ari, pcib_try_enable_ari), 107 108 DEVMETHOD_END 109}; 110 111static devclass_t pcib_devclass; 112 113DEFINE_CLASS_0(pcib, pcib_driver, pcib_methods, sizeof(struct pcib_softc)); 114DRIVER_MODULE(pcib, pci, pcib_driver, pcib_devclass, NULL, NULL); 115 116#ifdef NEW_PCIB 117SYSCTL_DECL(_hw_pci); 118 119static int pci_clear_pcib; 120TUNABLE_INT("hw.pci.clear_pcib", &pci_clear_pcib); 121SYSCTL_INT(_hw_pci, OID_AUTO, clear_pcib, CTLFLAG_RDTUN, &pci_clear_pcib, 0, 122 "Clear firmware-assigned resources for PCI-PCI bridge I/O windows."); 123 124/* 125 * Is a resource from a child device sub-allocated from one of our 126 * resource managers? 127 */ 128static int 129pcib_is_resource_managed(struct pcib_softc *sc, int type, struct resource *r) 130{ 131 132 switch (type) { 133 case SYS_RES_IOPORT: 134 return (rman_is_region_manager(r, &sc->io.rman)); 135 case SYS_RES_MEMORY: 136 /* Prefetchable resources may live in either memory rman. */ 137 if (rman_get_flags(r) & RF_PREFETCHABLE && 138 rman_is_region_manager(r, &sc->pmem.rman)) 139 return (1); 140 return (rman_is_region_manager(r, &sc->mem.rman)); 141 } 142 return (0); 143} 144 145static int 146pcib_is_window_open(struct pcib_window *pw) 147{ 148 149 return (pw->valid && pw->base < pw->limit); 150} 151 152/* 153 * XXX: If RF_ACTIVE did not also imply allocating a bus space tag and 154 * handle for the resource, we could pass RF_ACTIVE up to the PCI bus 155 * when allocating the resource windows and rely on the PCI bus driver 156 * to do this for us. 157 */ 158static void 159pcib_activate_window(struct pcib_softc *sc, int type) 160{ 161 162 PCI_ENABLE_IO(device_get_parent(sc->dev), sc->dev, type); 163} 164 165static void 166pcib_write_windows(struct pcib_softc *sc, int mask) 167{ 168 device_t dev; 169 uint32_t val; 170 171 dev = sc->dev; 172 if (sc->io.valid && mask & WIN_IO) { 173 val = pci_read_config(dev, PCIR_IOBASEL_1, 1); 174 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 175 pci_write_config(dev, PCIR_IOBASEH_1, 176 sc->io.base >> 16, 2); 177 pci_write_config(dev, PCIR_IOLIMITH_1, 178 sc->io.limit >> 16, 2); 179 } 180 pci_write_config(dev, PCIR_IOBASEL_1, sc->io.base >> 8, 1); 181 pci_write_config(dev, PCIR_IOLIMITL_1, sc->io.limit >> 8, 1); 182 } 183 184 if (mask & WIN_MEM) { 185 pci_write_config(dev, PCIR_MEMBASE_1, sc->mem.base >> 16, 2); 186 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->mem.limit >> 16, 2); 187 } 188 189 if (sc->pmem.valid && mask & WIN_PMEM) { 190 val = pci_read_config(dev, PCIR_PMBASEL_1, 2); 191 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) { 192 pci_write_config(dev, PCIR_PMBASEH_1, 193 sc->pmem.base >> 32, 4); 194 pci_write_config(dev, PCIR_PMLIMITH_1, 195 sc->pmem.limit >> 32, 4); 196 } 197 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmem.base >> 16, 2); 198 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmem.limit >> 16, 2); 199 } 200} 201 202/* 203 * This is used to reject I/O port allocations that conflict with an 204 * ISA alias range. 205 */ 206static int 207pcib_is_isa_range(struct pcib_softc *sc, u_long start, u_long end, u_long count) 208{ 209 u_long next_alias; 210 211 if (!(sc->bridgectl & PCIB_BCR_ISA_ENABLE)) 212 return (0); 213 214 /* Only check fixed ranges for overlap. */ 215 if (start + count - 1 != end) 216 return (0); 217 218 /* ISA aliases are only in the lower 64KB of I/O space. */ 219 if (start >= 65536) 220 return (0); 221 222 /* Check for overlap with 0x000 - 0x0ff as a special case. */ 223 if (start < 0x100) 224 goto alias; 225 226 /* 227 * If the start address is an alias, the range is an alias. 228 * Otherwise, compute the start of the next alias range and 229 * check if it is before the end of the candidate range. 230 */ 231 if ((start & 0x300) != 0) 232 goto alias; 233 next_alias = (start & ~0x3fful) | 0x100; 234 if (next_alias <= end) 235 goto alias; 236 return (0); 237 238alias: 239 if (bootverbose) 240 device_printf(sc->dev, 241 "I/O range %#lx-%#lx overlaps with an ISA alias\n", start, 242 end); 243 return (1); 244} 245 246static void 247pcib_add_window_resources(struct pcib_window *w, struct resource **res, 248 int count) 249{ 250 struct resource **newarray; 251 int error, i; 252 253 newarray = malloc(sizeof(struct resource *) * (w->count + count), 254 M_DEVBUF, M_WAITOK); 255 if (w->res != NULL) 256 bcopy(w->res, newarray, sizeof(struct resource *) * w->count); 257 bcopy(res, newarray + w->count, sizeof(struct resource *) * count); 258 free(w->res, M_DEVBUF); 259 w->res = newarray; 260 w->count += count; 261 262 for (i = 0; i < count; i++) { 263 error = rman_manage_region(&w->rman, rman_get_start(res[i]), 264 rman_get_end(res[i])); 265 if (error) 266 panic("Failed to add resource to rman"); 267 } 268} 269 270typedef void (nonisa_callback)(u_long start, u_long end, void *arg); 271 272static void 273pcib_walk_nonisa_ranges(u_long start, u_long end, nonisa_callback *cb, 274 void *arg) 275{ 276 u_long next_end; 277 278 /* 279 * If start is within an ISA alias range, move up to the start 280 * of the next non-alias range. As a special case, addresses 281 * in the range 0x000 - 0x0ff should also be skipped since 282 * those are used for various system I/O devices in ISA 283 * systems. 284 */ 285 if (start <= 65535) { 286 if (start < 0x100 || (start & 0x300) != 0) { 287 start &= ~0x3ff; 288 start += 0x400; 289 } 290 } 291 292 /* ISA aliases are only in the lower 64KB of I/O space. */ 293 while (start <= MIN(end, 65535)) { 294 next_end = MIN(start | 0xff, end); 295 cb(start, next_end, arg); 296 start += 0x400; 297 } 298 299 if (start <= end) 300 cb(start, end, arg); 301} 302 303static void 304count_ranges(u_long start, u_long end, void *arg) 305{ 306 int *countp; 307 308 countp = arg; 309 (*countp)++; 310} 311 312struct alloc_state { 313 struct resource **res; 314 struct pcib_softc *sc; 315 int count, error; 316}; 317 318static void 319alloc_ranges(u_long start, u_long end, void *arg) 320{ 321 struct alloc_state *as; 322 struct pcib_window *w; 323 int rid; 324 325 as = arg; 326 if (as->error != 0) 327 return; 328 329 w = &as->sc->io; 330 rid = w->reg; 331 if (bootverbose) 332 device_printf(as->sc->dev, 333 "allocating non-ISA range %#lx-%#lx\n", start, end); 334 as->res[as->count] = bus_alloc_resource(as->sc->dev, SYS_RES_IOPORT, 335 &rid, start, end, end - start + 1, 0); 336 if (as->res[as->count] == NULL) 337 as->error = ENXIO; 338 else 339 as->count++; 340} 341 342static int 343pcib_alloc_nonisa_ranges(struct pcib_softc *sc, u_long start, u_long end) 344{ 345 struct alloc_state as; 346 int i, new_count; 347 348 /* First, see how many ranges we need. */ 349 new_count = 0; 350 pcib_walk_nonisa_ranges(start, end, count_ranges, &new_count); 351 352 /* Second, allocate the ranges. */ 353 as.res = malloc(sizeof(struct resource *) * new_count, M_DEVBUF, 354 M_WAITOK); 355 as.sc = sc; 356 as.count = 0; 357 as.error = 0; 358 pcib_walk_nonisa_ranges(start, end, alloc_ranges, &as); 359 if (as.error != 0) { 360 for (i = 0; i < as.count; i++) 361 bus_release_resource(sc->dev, SYS_RES_IOPORT, 362 sc->io.reg, as.res[i]); 363 free(as.res, M_DEVBUF); 364 return (as.error); 365 } 366 KASSERT(as.count == new_count, ("%s: count mismatch", __func__)); 367 368 /* Third, add the ranges to the window. */ 369 pcib_add_window_resources(&sc->io, as.res, as.count); 370 free(as.res, M_DEVBUF); 371 return (0); 372} 373 374static void 375pcib_alloc_window(struct pcib_softc *sc, struct pcib_window *w, int type, 376 int flags, pci_addr_t max_address) 377{ 378 struct resource *res; 379 char buf[64]; 380 int error, rid; 381 382 if (max_address != (u_long)max_address) 383 max_address = ~0ul; 384 w->rman.rm_start = 0; 385 w->rman.rm_end = max_address; 386 w->rman.rm_type = RMAN_ARRAY; 387 snprintf(buf, sizeof(buf), "%s %s window", 388 device_get_nameunit(sc->dev), w->name); 389 w->rman.rm_descr = strdup(buf, M_DEVBUF); 390 error = rman_init(&w->rman); 391 if (error) 392 panic("Failed to initialize %s %s rman", 393 device_get_nameunit(sc->dev), w->name); 394 395 if (!pcib_is_window_open(w)) 396 return; 397 398 if (w->base > max_address || w->limit > max_address) { 399 device_printf(sc->dev, 400 "initial %s window has too many bits, ignoring\n", w->name); 401 return; 402 } 403 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE) 404 (void)pcib_alloc_nonisa_ranges(sc, w->base, w->limit); 405 else { 406 rid = w->reg; 407 res = bus_alloc_resource(sc->dev, type, &rid, w->base, w->limit, 408 w->limit - w->base + 1, flags); 409 if (res != NULL) 410 pcib_add_window_resources(w, &res, 1); 411 } 412 if (w->res == NULL) { 413 device_printf(sc->dev, 414 "failed to allocate initial %s window: %#jx-%#jx\n", 415 w->name, (uintmax_t)w->base, (uintmax_t)w->limit); 416 w->base = max_address; 417 w->limit = 0; 418 pcib_write_windows(sc, w->mask); 419 return; 420 } 421 pcib_activate_window(sc, type); 422} 423 424/* 425 * Initialize I/O windows. 426 */ 427static void 428pcib_probe_windows(struct pcib_softc *sc) 429{ 430 pci_addr_t max; 431 device_t dev; 432 uint32_t val; 433 434 dev = sc->dev; 435 436 if (pci_clear_pcib) { 437 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1); 438 pci_write_config(dev, PCIR_IOBASEH_1, 0xffff, 2); 439 pci_write_config(dev, PCIR_IOLIMITL_1, 0, 1); 440 pci_write_config(dev, PCIR_IOLIMITH_1, 0, 2); 441 pci_write_config(dev, PCIR_MEMBASE_1, 0xffff, 2); 442 pci_write_config(dev, PCIR_MEMLIMIT_1, 0, 2); 443 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2); 444 pci_write_config(dev, PCIR_PMBASEH_1, 0xffffffff, 4); 445 pci_write_config(dev, PCIR_PMLIMITL_1, 0, 2); 446 pci_write_config(dev, PCIR_PMLIMITH_1, 0, 4); 447 } 448 449 /* Determine if the I/O port window is implemented. */ 450 val = pci_read_config(dev, PCIR_IOBASEL_1, 1); 451 if (val == 0) { 452 /* 453 * If 'val' is zero, then only 16-bits of I/O space 454 * are supported. 455 */ 456 pci_write_config(dev, PCIR_IOBASEL_1, 0xff, 1); 457 if (pci_read_config(dev, PCIR_IOBASEL_1, 1) != 0) { 458 sc->io.valid = 1; 459 pci_write_config(dev, PCIR_IOBASEL_1, 0, 1); 460 } 461 } else 462 sc->io.valid = 1; 463 464 /* Read the existing I/O port window. */ 465 if (sc->io.valid) { 466 sc->io.reg = PCIR_IOBASEL_1; 467 sc->io.step = 12; 468 sc->io.mask = WIN_IO; 469 sc->io.name = "I/O port"; 470 if ((val & PCIM_BRIO_MASK) == PCIM_BRIO_32) { 471 sc->io.base = PCI_PPBIOBASE( 472 pci_read_config(dev, PCIR_IOBASEH_1, 2), val); 473 sc->io.limit = PCI_PPBIOLIMIT( 474 pci_read_config(dev, PCIR_IOLIMITH_1, 2), 475 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 476 max = 0xffffffff; 477 } else { 478 sc->io.base = PCI_PPBIOBASE(0, val); 479 sc->io.limit = PCI_PPBIOLIMIT(0, 480 pci_read_config(dev, PCIR_IOLIMITL_1, 1)); 481 max = 0xffff; 482 } 483 pcib_alloc_window(sc, &sc->io, SYS_RES_IOPORT, 0, max); 484 } 485 486 /* Read the existing memory window. */ 487 sc->mem.valid = 1; 488 sc->mem.reg = PCIR_MEMBASE_1; 489 sc->mem.step = 20; 490 sc->mem.mask = WIN_MEM; 491 sc->mem.name = "memory"; 492 sc->mem.base = PCI_PPBMEMBASE(0, 493 pci_read_config(dev, PCIR_MEMBASE_1, 2)); 494 sc->mem.limit = PCI_PPBMEMLIMIT(0, 495 pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 496 pcib_alloc_window(sc, &sc->mem, SYS_RES_MEMORY, 0, 0xffffffff); 497 498 /* Determine if the prefetchable memory window is implemented. */ 499 val = pci_read_config(dev, PCIR_PMBASEL_1, 2); 500 if (val == 0) { 501 /* 502 * If 'val' is zero, then only 32-bits of memory space 503 * are supported. 504 */ 505 pci_write_config(dev, PCIR_PMBASEL_1, 0xffff, 2); 506 if (pci_read_config(dev, PCIR_PMBASEL_1, 2) != 0) { 507 sc->pmem.valid = 1; 508 pci_write_config(dev, PCIR_PMBASEL_1, 0, 2); 509 } 510 } else 511 sc->pmem.valid = 1; 512 513 /* Read the existing prefetchable memory window. */ 514 if (sc->pmem.valid) { 515 sc->pmem.reg = PCIR_PMBASEL_1; 516 sc->pmem.step = 20; 517 sc->pmem.mask = WIN_PMEM; 518 sc->pmem.name = "prefetch"; 519 if ((val & PCIM_BRPM_MASK) == PCIM_BRPM_64) { 520 sc->pmem.base = PCI_PPBMEMBASE( 521 pci_read_config(dev, PCIR_PMBASEH_1, 4), val); 522 sc->pmem.limit = PCI_PPBMEMLIMIT( 523 pci_read_config(dev, PCIR_PMLIMITH_1, 4), 524 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 525 max = 0xffffffffffffffff; 526 } else { 527 sc->pmem.base = PCI_PPBMEMBASE(0, val); 528 sc->pmem.limit = PCI_PPBMEMLIMIT(0, 529 pci_read_config(dev, PCIR_PMLIMITL_1, 2)); 530 max = 0xffffffff; 531 } 532 pcib_alloc_window(sc, &sc->pmem, SYS_RES_MEMORY, 533 RF_PREFETCHABLE, max); 534 } 535} 536 537#else 538 539/* 540 * Is the prefetch window open (eg, can we allocate memory in it?) 541 */ 542static int 543pcib_is_prefetch_open(struct pcib_softc *sc) 544{ 545 return (sc->pmembase > 0 && sc->pmembase < sc->pmemlimit); 546} 547 548/* 549 * Is the nonprefetch window open (eg, can we allocate memory in it?) 550 */ 551static int 552pcib_is_nonprefetch_open(struct pcib_softc *sc) 553{ 554 return (sc->membase > 0 && sc->membase < sc->memlimit); 555} 556 557/* 558 * Is the io window open (eg, can we allocate ports in it?) 559 */ 560static int 561pcib_is_io_open(struct pcib_softc *sc) 562{ 563 return (sc->iobase > 0 && sc->iobase < sc->iolimit); 564} 565 566/* 567 * Get current I/O decode. 568 */ 569static void 570pcib_get_io_decode(struct pcib_softc *sc) 571{ 572 device_t dev; 573 uint32_t iolow; 574 575 dev = sc->dev; 576 577 iolow = pci_read_config(dev, PCIR_IOBASEL_1, 1); 578 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) 579 sc->iobase = PCI_PPBIOBASE( 580 pci_read_config(dev, PCIR_IOBASEH_1, 2), iolow); 581 else 582 sc->iobase = PCI_PPBIOBASE(0, iolow); 583 584 iolow = pci_read_config(dev, PCIR_IOLIMITL_1, 1); 585 if ((iolow & PCIM_BRIO_MASK) == PCIM_BRIO_32) 586 sc->iolimit = PCI_PPBIOLIMIT( 587 pci_read_config(dev, PCIR_IOLIMITH_1, 2), iolow); 588 else 589 sc->iolimit = PCI_PPBIOLIMIT(0, iolow); 590} 591 592/* 593 * Get current memory decode. 594 */ 595static void 596pcib_get_mem_decode(struct pcib_softc *sc) 597{ 598 device_t dev; 599 pci_addr_t pmemlow; 600 601 dev = sc->dev; 602 603 sc->membase = PCI_PPBMEMBASE(0, 604 pci_read_config(dev, PCIR_MEMBASE_1, 2)); 605 sc->memlimit = PCI_PPBMEMLIMIT(0, 606 pci_read_config(dev, PCIR_MEMLIMIT_1, 2)); 607 608 pmemlow = pci_read_config(dev, PCIR_PMBASEL_1, 2); 609 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64) 610 sc->pmembase = PCI_PPBMEMBASE( 611 pci_read_config(dev, PCIR_PMBASEH_1, 4), pmemlow); 612 else 613 sc->pmembase = PCI_PPBMEMBASE(0, pmemlow); 614 615 pmemlow = pci_read_config(dev, PCIR_PMLIMITL_1, 2); 616 if ((pmemlow & PCIM_BRPM_MASK) == PCIM_BRPM_64) 617 sc->pmemlimit = PCI_PPBMEMLIMIT( 618 pci_read_config(dev, PCIR_PMLIMITH_1, 4), pmemlow); 619 else 620 sc->pmemlimit = PCI_PPBMEMLIMIT(0, pmemlow); 621} 622 623/* 624 * Restore previous I/O decode. 625 */ 626static void 627pcib_set_io_decode(struct pcib_softc *sc) 628{ 629 device_t dev; 630 uint32_t iohi; 631 632 dev = sc->dev; 633 634 iohi = sc->iobase >> 16; 635 if (iohi > 0) 636 pci_write_config(dev, PCIR_IOBASEH_1, iohi, 2); 637 pci_write_config(dev, PCIR_IOBASEL_1, sc->iobase >> 8, 1); 638 639 iohi = sc->iolimit >> 16; 640 if (iohi > 0) 641 pci_write_config(dev, PCIR_IOLIMITH_1, iohi, 2); 642 pci_write_config(dev, PCIR_IOLIMITL_1, sc->iolimit >> 8, 1); 643} 644 645/* 646 * Restore previous memory decode. 647 */ 648static void 649pcib_set_mem_decode(struct pcib_softc *sc) 650{ 651 device_t dev; 652 pci_addr_t pmemhi; 653 654 dev = sc->dev; 655 656 pci_write_config(dev, PCIR_MEMBASE_1, sc->membase >> 16, 2); 657 pci_write_config(dev, PCIR_MEMLIMIT_1, sc->memlimit >> 16, 2); 658 659 pmemhi = sc->pmembase >> 32; 660 if (pmemhi > 0) 661 pci_write_config(dev, PCIR_PMBASEH_1, pmemhi, 4); 662 pci_write_config(dev, PCIR_PMBASEL_1, sc->pmembase >> 16, 2); 663 664 pmemhi = sc->pmemlimit >> 32; 665 if (pmemhi > 0) 666 pci_write_config(dev, PCIR_PMLIMITH_1, pmemhi, 4); 667 pci_write_config(dev, PCIR_PMLIMITL_1, sc->pmemlimit >> 16, 2); 668} 669#endif 670 671/* 672 * Get current bridge configuration. 673 */ 674static void 675pcib_cfg_save(struct pcib_softc *sc) 676{ 677 device_t dev; 678 679 dev = sc->dev; 680 681 sc->command = pci_read_config(dev, PCIR_COMMAND, 2); 682 sc->pribus = pci_read_config(dev, PCIR_PRIBUS_1, 1); 683 sc->secbus = pci_read_config(dev, PCIR_SECBUS_1, 1); 684 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); 685 sc->bridgectl = pci_read_config(dev, PCIR_BRIDGECTL_1, 2); 686 sc->seclat = pci_read_config(dev, PCIR_SECLAT_1, 1); 687#ifndef NEW_PCIB 688 if (sc->command & PCIM_CMD_PORTEN) 689 pcib_get_io_decode(sc); 690 if (sc->command & PCIM_CMD_MEMEN) 691 pcib_get_mem_decode(sc); 692#endif 693} 694 695/* 696 * Restore previous bridge configuration. 697 */ 698static void 699pcib_cfg_restore(struct pcib_softc *sc) 700{ 701 device_t dev; 702 703 dev = sc->dev; 704 705 pci_write_config(dev, PCIR_COMMAND, sc->command, 2); 706 pci_write_config(dev, PCIR_PRIBUS_1, sc->pribus, 1); 707 pci_write_config(dev, PCIR_SECBUS_1, sc->secbus, 1); 708 pci_write_config(dev, PCIR_SUBBUS_1, sc->subbus, 1); 709 pci_write_config(dev, PCIR_BRIDGECTL_1, sc->bridgectl, 2); 710 pci_write_config(dev, PCIR_SECLAT_1, sc->seclat, 1); 711#ifdef NEW_PCIB 712 pcib_write_windows(sc, WIN_IO | WIN_MEM | WIN_PMEM); 713#else 714 if (sc->command & PCIM_CMD_PORTEN) 715 pcib_set_io_decode(sc); 716 if (sc->command & PCIM_CMD_MEMEN) 717 pcib_set_mem_decode(sc); 718#endif 719} 720 721/* 722 * Generic device interface 723 */ 724static int 725pcib_probe(device_t dev) 726{ 727 if ((pci_get_class(dev) == PCIC_BRIDGE) && 728 (pci_get_subclass(dev) == PCIS_BRIDGE_PCI)) { 729 device_set_desc(dev, "PCI-PCI bridge"); 730 return(-10000); 731 } 732 return(ENXIO); 733} 734 735void 736pcib_attach_common(device_t dev) 737{ 738 struct pcib_softc *sc; 739 struct sysctl_ctx_list *sctx; 740 struct sysctl_oid *soid; 741 int comma; 742 743 sc = device_get_softc(dev); 744 sc->dev = dev; 745 746 /* 747 * Get current bridge configuration. 748 */ 749 sc->domain = pci_get_domain(dev); 750 sc->secstat = pci_read_config(dev, PCIR_SECSTAT_1, 2); 751 pcib_cfg_save(sc); 752 753 /* 754 * Setup sysctl reporting nodes 755 */ 756 sctx = device_get_sysctl_ctx(dev); 757 soid = device_get_sysctl_tree(dev); 758 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "domain", 759 CTLFLAG_RD, &sc->domain, 0, "Domain number"); 760 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "pribus", 761 CTLFLAG_RD, &sc->pribus, 0, "Primary bus number"); 762 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "secbus", 763 CTLFLAG_RD, &sc->secbus, 0, "Secondary bus number"); 764 SYSCTL_ADD_UINT(sctx, SYSCTL_CHILDREN(soid), OID_AUTO, "subbus", 765 CTLFLAG_RD, &sc->subbus, 0, "Subordinate bus number"); 766 767 /* 768 * Quirk handling. 769 */ 770 switch (pci_get_devid(dev)) { 771 case 0x12258086: /* Intel 82454KX/GX (Orion) */ 772 { 773 uint8_t supbus; 774 775 supbus = pci_read_config(dev, 0x41, 1); 776 if (supbus != 0xff) { 777 sc->secbus = supbus + 1; 778 sc->subbus = supbus + 1; 779 } 780 break; 781 } 782 783 /* 784 * The i82380FB mobile docking controller is a PCI-PCI bridge, 785 * and it is a subtractive bridge. However, the ProgIf is wrong 786 * so the normal setting of PCIB_SUBTRACTIVE bit doesn't 787 * happen. There's also a Toshiba bridge that behaves this 788 * way. 789 */ 790 case 0x124b8086: /* Intel 82380FB Mobile */ 791 case 0x060513d7: /* Toshiba ???? */ 792 sc->flags |= PCIB_SUBTRACTIVE; 793 break; 794 795 /* Compaq R3000 BIOS sets wrong subordinate bus number. */ 796 case 0x00dd10de: 797 { 798 char *cp; 799 800 if ((cp = getenv("smbios.planar.maker")) == NULL) 801 break; 802 if (strncmp(cp, "Compal", 6) != 0) { 803 freeenv(cp); 804 break; 805 } 806 freeenv(cp); 807 if ((cp = getenv("smbios.planar.product")) == NULL) 808 break; 809 if (strncmp(cp, "08A0", 4) != 0) { 810 freeenv(cp); 811 break; 812 } 813 freeenv(cp); 814 if (sc->subbus < 0xa) { 815 pci_write_config(dev, PCIR_SUBBUS_1, 0xa, 1); 816 sc->subbus = pci_read_config(dev, PCIR_SUBBUS_1, 1); 817 } 818 break; 819 } 820 } 821 822 if (pci_msi_device_blacklisted(dev)) 823 sc->flags |= PCIB_DISABLE_MSI; 824 825 if (pci_msix_device_blacklisted(dev)) 826 sc->flags |= PCIB_DISABLE_MSIX; 827 828 /* 829 * Intel 815, 845 and other chipsets say they are PCI-PCI bridges, 830 * but have a ProgIF of 0x80. The 82801 family (AA, AB, BAM/CAM, 831 * BA/CA/DB and E) PCI bridges are HUB-PCI bridges, in Intelese. 832 * This means they act as if they were subtractively decoding 833 * bridges and pass all transactions. Mark them and real ProgIf 1 834 * parts as subtractive. 835 */ 836 if ((pci_get_devid(dev) & 0xff00ffff) == 0x24008086 || 837 pci_read_config(dev, PCIR_PROGIF, 1) == PCIP_BRIDGE_PCI_SUBTRACTIVE) 838 sc->flags |= PCIB_SUBTRACTIVE; 839 840#ifdef NEW_PCIB 841 pcib_probe_windows(sc); 842#endif 843 if (bootverbose) { 844 device_printf(dev, " domain %d\n", sc->domain); 845 device_printf(dev, " secondary bus %d\n", sc->secbus); 846 device_printf(dev, " subordinate bus %d\n", sc->subbus); 847#ifdef NEW_PCIB 848 if (pcib_is_window_open(&sc->io)) 849 device_printf(dev, " I/O decode 0x%jx-0x%jx\n", 850 (uintmax_t)sc->io.base, (uintmax_t)sc->io.limit); 851 if (pcib_is_window_open(&sc->mem)) 852 device_printf(dev, " memory decode 0x%jx-0x%jx\n", 853 (uintmax_t)sc->mem.base, (uintmax_t)sc->mem.limit); 854 if (pcib_is_window_open(&sc->pmem)) 855 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n", 856 (uintmax_t)sc->pmem.base, (uintmax_t)sc->pmem.limit); 857#else 858 if (pcib_is_io_open(sc)) 859 device_printf(dev, " I/O decode 0x%x-0x%x\n", 860 sc->iobase, sc->iolimit); 861 if (pcib_is_nonprefetch_open(sc)) 862 device_printf(dev, " memory decode 0x%jx-0x%jx\n", 863 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit); 864 if (pcib_is_prefetch_open(sc)) 865 device_printf(dev, " prefetched decode 0x%jx-0x%jx\n", 866 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 867#endif 868 if (sc->bridgectl & (PCIB_BCR_ISA_ENABLE | PCIB_BCR_VGA_ENABLE) || 869 sc->flags & PCIB_SUBTRACTIVE) { 870 device_printf(dev, " special decode "); 871 comma = 0; 872 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE) { 873 printf("ISA"); 874 comma = 1; 875 } 876 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE) { 877 printf("%sVGA", comma ? ", " : ""); 878 comma = 1; 879 } 880 if (sc->flags & PCIB_SUBTRACTIVE) 881 printf("%ssubtractive", comma ? ", " : ""); 882 printf("\n"); 883 } 884 } 885 886 /* 887 * XXX If the secondary bus number is zero, we should assign a bus number 888 * since the BIOS hasn't, then initialise the bridge. A simple 889 * bus_alloc_resource with the a couple of busses seems like the right 890 * approach, but we don't know what busses the BIOS might have already 891 * assigned to other bridges on this bus that probe later than we do. 892 * 893 * If the subordinate bus number is less than the secondary bus number, 894 * we should pick a better value. One sensible alternative would be to 895 * pick 255; the only tradeoff here is that configuration transactions 896 * would be more widely routed than absolutely necessary. We could 897 * then do a walk of the tree later and fix it. 898 */ 899 900 /* 901 * Always enable busmastering on bridges so that transactions 902 * initiated on the secondary bus are passed through to the 903 * primary bus. 904 */ 905 pci_enable_busmaster(dev); 906} 907 908int 909pcib_attach(device_t dev) 910{ 911 struct pcib_softc *sc; 912 device_t child; 913 914 pcib_attach_common(dev); 915 sc = device_get_softc(dev); 916 if (sc->secbus != 0) { 917 child = device_add_child(dev, "pci", sc->secbus); 918 if (child != NULL) 919 return(bus_generic_attach(dev)); 920 } 921 922 /* no secondary bus; we should have fixed this */ 923 return(0); 924} 925 926int 927pcib_suspend(device_t dev) 928{ 929 device_t pcib; 930 int dstate, error; 931 932 pcib_cfg_save(device_get_softc(dev)); 933 error = bus_generic_suspend(dev); 934 if (error == 0 && pci_do_power_suspend) { 935 dstate = PCI_POWERSTATE_D3; 936 pcib = device_get_parent(device_get_parent(dev)); 937 if (PCIB_POWER_FOR_SLEEP(pcib, dev, &dstate) == 0) 938 pci_set_powerstate(dev, dstate); 939 } 940 return (error); 941} 942 943int 944pcib_resume(device_t dev) 945{ 946 device_t pcib; 947 int dstate; 948 949 if (pci_do_power_resume) { 950 pcib = device_get_parent(device_get_parent(dev)); 951 dstate = PCI_POWERSTATE_D0; 952 if (PCIB_POWER_FOR_SLEEP(pcib, dev, &dstate) == 0) 953 pci_set_powerstate(dev, dstate); 954 } 955 pcib_cfg_restore(device_get_softc(dev)); 956 return (bus_generic_resume(dev)); 957} 958 959int 960pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 961{ 962 struct pcib_softc *sc = device_get_softc(dev); 963 964 switch (which) { 965 case PCIB_IVAR_DOMAIN: 966 *result = sc->domain; 967 return(0); 968 case PCIB_IVAR_BUS: 969 *result = sc->secbus; 970 return(0); 971 } 972 return(ENOENT); 973} 974 975int 976pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 977{ 978 struct pcib_softc *sc = device_get_softc(dev); 979 980 switch (which) { 981 case PCIB_IVAR_DOMAIN: 982 return(EINVAL); 983 case PCIB_IVAR_BUS: 984 sc->secbus = value; 985 return(0); 986 } 987 return(ENOENT); 988} 989 990#ifdef NEW_PCIB 991/* 992 * Attempt to allocate a resource from the existing resources assigned 993 * to a window. 994 */ 995static struct resource * 996pcib_suballoc_resource(struct pcib_softc *sc, struct pcib_window *w, 997 device_t child, int type, int *rid, u_long start, u_long end, u_long count, 998 u_int flags) 999{ 1000 struct resource *res; 1001 1002 if (!pcib_is_window_open(w)) 1003 return (NULL); 1004 1005 res = rman_reserve_resource(&w->rman, start, end, count, 1006 flags & ~RF_ACTIVE, child); 1007 if (res == NULL) 1008 return (NULL); 1009 1010 if (bootverbose) 1011 device_printf(sc->dev, 1012 "allocated %s range (%#lx-%#lx) for rid %x of %s\n", 1013 w->name, rman_get_start(res), rman_get_end(res), *rid, 1014 pcib_child_name(child)); 1015 rman_set_rid(res, *rid); 1016 1017 /* 1018 * If the resource should be active, pass that request up the 1019 * tree. This assumes the parent drivers can handle 1020 * activating sub-allocated resources. 1021 */ 1022 if (flags & RF_ACTIVE) { 1023 if (bus_activate_resource(child, type, *rid, res) != 0) { 1024 rman_release_resource(res); 1025 return (NULL); 1026 } 1027 } 1028 1029 return (res); 1030} 1031 1032/* Allocate a fresh resource range for an unconfigured window. */ 1033static int 1034pcib_alloc_new_window(struct pcib_softc *sc, struct pcib_window *w, int type, 1035 u_long start, u_long end, u_long count, u_int flags) 1036{ 1037 struct resource *res; 1038 u_long base, limit, wmask; 1039 int rid; 1040 1041 /* 1042 * If this is an I/O window on a bridge with ISA enable set 1043 * and the start address is below 64k, then try to allocate an 1044 * initial window of 0x1000 bytes long starting at address 1045 * 0xf000 and walking down. Note that if the original request 1046 * was larger than the non-aliased range size of 0x100 our 1047 * caller would have raised the start address up to 64k 1048 * already. 1049 */ 1050 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE && 1051 start < 65536) { 1052 for (base = 0xf000; (long)base >= 0; base -= 0x1000) { 1053 limit = base + 0xfff; 1054 1055 /* 1056 * Skip ranges that wouldn't work for the 1057 * original request. Note that the actual 1058 * window that overlaps are the non-alias 1059 * ranges within [base, limit], so this isn't 1060 * quite a simple comparison. 1061 */ 1062 if (start + count > limit - 0x400) 1063 continue; 1064 if (base == 0) { 1065 /* 1066 * The first open region for the window at 1067 * 0 is 0x400-0x4ff. 1068 */ 1069 if (end - count + 1 < 0x400) 1070 continue; 1071 } else { 1072 if (end - count + 1 < base) 1073 continue; 1074 } 1075 1076 if (pcib_alloc_nonisa_ranges(sc, base, limit) == 0) { 1077 w->base = base; 1078 w->limit = limit; 1079 return (0); 1080 } 1081 } 1082 return (ENOSPC); 1083 } 1084 1085 wmask = (1ul << w->step) - 1; 1086 if (RF_ALIGNMENT(flags) < w->step) { 1087 flags &= ~RF_ALIGNMENT_MASK; 1088 flags |= RF_ALIGNMENT_LOG2(w->step); 1089 } 1090 start &= ~wmask; 1091 end |= wmask; 1092 count = roundup2(count, 1ul << w->step); 1093 rid = w->reg; 1094 res = bus_alloc_resource(sc->dev, type, &rid, start, end, count, 1095 flags & ~RF_ACTIVE); 1096 if (res == NULL) 1097 return (ENOSPC); 1098 pcib_add_window_resources(w, &res, 1); 1099 pcib_activate_window(sc, type); 1100 w->base = rman_get_start(res); 1101 w->limit = rman_get_end(res); 1102 return (0); 1103} 1104 1105/* Try to expand an existing window to the requested base and limit. */ 1106static int 1107pcib_expand_window(struct pcib_softc *sc, struct pcib_window *w, int type, 1108 u_long base, u_long limit) 1109{ 1110 struct resource *res; 1111 int error, i, force_64k_base; 1112 1113 KASSERT(base <= w->base && limit >= w->limit, 1114 ("attempting to shrink window")); 1115 1116 /* 1117 * XXX: pcib_grow_window() doesn't try to do this anyway and 1118 * the error handling for all the edge cases would be tedious. 1119 */ 1120 KASSERT(limit == w->limit || base == w->base, 1121 ("attempting to grow both ends of a window")); 1122 1123 /* 1124 * Yet more special handling for requests to expand an I/O 1125 * window behind an ISA-enabled bridge. Since I/O windows 1126 * have to grow in 0x1000 increments and the end of the 0xffff 1127 * range is an alias, growing a window below 64k will always 1128 * result in allocating new resources and never adjusting an 1129 * existing resource. 1130 */ 1131 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE && 1132 (limit <= 65535 || (base <= 65535 && base != w->base))) { 1133 KASSERT(limit == w->limit || limit <= 65535, 1134 ("attempting to grow both ends across 64k ISA alias")); 1135 1136 if (base != w->base) 1137 error = pcib_alloc_nonisa_ranges(sc, base, w->base - 1); 1138 else 1139 error = pcib_alloc_nonisa_ranges(sc, w->limit + 1, 1140 limit); 1141 if (error == 0) { 1142 w->base = base; 1143 w->limit = limit; 1144 } 1145 return (error); 1146 } 1147 1148 /* 1149 * Find the existing resource to adjust. Usually there is only one, 1150 * but for an ISA-enabled bridge we might be growing the I/O window 1151 * above 64k and need to find the existing resource that maps all 1152 * of the area above 64k. 1153 */ 1154 for (i = 0; i < w->count; i++) { 1155 if (rman_get_end(w->res[i]) == w->limit) 1156 break; 1157 } 1158 KASSERT(i != w->count, ("did not find existing resource")); 1159 res = w->res[i]; 1160 1161 /* 1162 * Usually the resource we found should match the window's 1163 * existing range. The one exception is the ISA-enabled case 1164 * mentioned above in which case the resource should start at 1165 * 64k. 1166 */ 1167 if (type == SYS_RES_IOPORT && sc->bridgectl & PCIB_BCR_ISA_ENABLE && 1168 w->base <= 65535) { 1169 KASSERT(rman_get_start(res) == 65536, 1170 ("existing resource mismatch")); 1171 force_64k_base = 1; 1172 } else { 1173 KASSERT(w->base == rman_get_start(res), 1174 ("existing resource mismatch")); 1175 force_64k_base = 0; 1176 } 1177 1178 error = bus_adjust_resource(sc->dev, type, res, force_64k_base ? 1179 rman_get_start(res) : base, limit); 1180 if (error) 1181 return (error); 1182 1183 /* Add the newly allocated region to the resource manager. */ 1184 if (w->base != base) { 1185 error = rman_manage_region(&w->rman, base, w->base - 1); 1186 w->base = base; 1187 } else { 1188 error = rman_manage_region(&w->rman, w->limit + 1, limit); 1189 w->limit = limit; 1190 } 1191 if (error) { 1192 if (bootverbose) 1193 device_printf(sc->dev, 1194 "failed to expand %s resource manager\n", w->name); 1195 (void)bus_adjust_resource(sc->dev, type, res, force_64k_base ? 1196 rman_get_start(res) : w->base, w->limit); 1197 } 1198 return (error); 1199} 1200 1201/* 1202 * Attempt to grow a window to make room for a given resource request. 1203 */ 1204static int 1205pcib_grow_window(struct pcib_softc *sc, struct pcib_window *w, int type, 1206 u_long start, u_long end, u_long count, u_int flags) 1207{ 1208 u_long align, start_free, end_free, front, back, wmask; 1209 int error; 1210 1211 /* 1212 * Clamp the desired resource range to the maximum address 1213 * this window supports. Reject impossible requests. 1214 * 1215 * For I/O port requests behind a bridge with the ISA enable 1216 * bit set, force large allocations to start above 64k. 1217 */ 1218 if (!w->valid) 1219 return (EINVAL); 1220 if (sc->bridgectl & PCIB_BCR_ISA_ENABLE && count > 0x100 && 1221 start < 65536) 1222 start = 65536; 1223 if (end > w->rman.rm_end) 1224 end = w->rman.rm_end; 1225 if (start + count - 1 > end || start + count < start) 1226 return (EINVAL); 1227 wmask = (1ul << w->step) - 1; 1228 1229 /* 1230 * If there is no resource at all, just try to allocate enough 1231 * aligned space for this resource. 1232 */ 1233 if (w->res == NULL) { 1234 error = pcib_alloc_new_window(sc, w, type, start, end, count, 1235 flags); 1236 if (error) { 1237 if (bootverbose) 1238 device_printf(sc->dev, 1239 "failed to allocate initial %s window (%#lx-%#lx,%#lx)\n", 1240 w->name, start, end, count); 1241 return (error); 1242 } 1243 if (bootverbose) 1244 device_printf(sc->dev, 1245 "allocated initial %s window of %#jx-%#jx\n", 1246 w->name, (uintmax_t)w->base, (uintmax_t)w->limit); 1247 goto updatewin; 1248 } 1249 1250 /* 1251 * See if growing the window would help. Compute the minimum 1252 * amount of address space needed on both the front and back 1253 * ends of the existing window to satisfy the allocation. 1254 * 1255 * For each end, build a candidate region adjusting for the 1256 * required alignment, etc. If there is a free region at the 1257 * edge of the window, grow from the inner edge of the free 1258 * region. Otherwise grow from the window boundary. 1259 * 1260 * Growing an I/O window below 64k for a bridge with the ISA 1261 * enable bit doesn't require any special magic as the step 1262 * size of an I/O window (1k) always includes multiple 1263 * non-alias ranges when it is grown in either direction. 1264 * 1265 * XXX: Special case: if w->res is completely empty and the 1266 * request size is larger than w->res, we should find the 1267 * optimal aligned buffer containing w->res and allocate that. 1268 */ 1269 if (bootverbose) 1270 device_printf(sc->dev, 1271 "attempting to grow %s window for (%#lx-%#lx,%#lx)\n", 1272 w->name, start, end, count); 1273 align = 1ul << RF_ALIGNMENT(flags); 1274 if (start < w->base) { 1275 if (rman_first_free_region(&w->rman, &start_free, &end_free) != 1276 0 || start_free != w->base) 1277 end_free = w->base; 1278 if (end_free > end) 1279 end_free = end + 1; 1280 1281 /* Move end_free down until it is properly aligned. */ 1282 end_free &= ~(align - 1); 1283 end_free--; 1284 front = end_free - (count - 1); 1285 1286 /* 1287 * The resource would now be allocated at (front, 1288 * end_free). Ensure that fits in the (start, end) 1289 * bounds. end_free is checked above. If 'front' is 1290 * ok, ensure it is properly aligned for this window. 1291 * Also check for underflow. 1292 */ 1293 if (front >= start && front <= end_free) { 1294 if (bootverbose) 1295 printf("\tfront candidate range: %#lx-%#lx\n", 1296 front, end_free); 1297 front &= ~wmask; 1298 front = w->base - front; 1299 } else 1300 front = 0; 1301 } else 1302 front = 0; 1303 if (end > w->limit) { 1304 if (rman_last_free_region(&w->rman, &start_free, &end_free) != 1305 0 || end_free != w->limit) 1306 start_free = w->limit + 1; 1307 if (start_free < start) 1308 start_free = start; 1309 1310 /* Move start_free up until it is properly aligned. */ 1311 start_free = roundup2(start_free, align); 1312 back = start_free + count - 1; 1313 1314 /* 1315 * The resource would now be allocated at (start_free, 1316 * back). Ensure that fits in the (start, end) 1317 * bounds. start_free is checked above. If 'back' is 1318 * ok, ensure it is properly aligned for this window. 1319 * Also check for overflow. 1320 */ 1321 if (back <= end && start_free <= back) { 1322 if (bootverbose) 1323 printf("\tback candidate range: %#lx-%#lx\n", 1324 start_free, back); 1325 back |= wmask; 1326 back -= w->limit; 1327 } else 1328 back = 0; 1329 } else 1330 back = 0; 1331 1332 /* 1333 * Try to allocate the smallest needed region first. 1334 * If that fails, fall back to the other region. 1335 */ 1336 error = ENOSPC; 1337 while (front != 0 || back != 0) { 1338 if (front != 0 && (front <= back || back == 0)) { 1339 error = pcib_expand_window(sc, w, type, w->base - front, 1340 w->limit); 1341 if (error == 0) 1342 break; 1343 front = 0; 1344 } else { 1345 error = pcib_expand_window(sc, w, type, w->base, 1346 w->limit + back); 1347 if (error == 0) 1348 break; 1349 back = 0; 1350 } 1351 } 1352 1353 if (error) 1354 return (error); 1355 if (bootverbose) 1356 device_printf(sc->dev, "grew %s window to %#jx-%#jx\n", 1357 w->name, (uintmax_t)w->base, (uintmax_t)w->limit); 1358 1359updatewin: 1360 /* Write the new window. */ 1361 KASSERT((w->base & wmask) == 0, ("start address is not aligned")); 1362 KASSERT((w->limit & wmask) == wmask, ("end address is not aligned")); 1363 pcib_write_windows(sc, w->mask); 1364 return (0); 1365} 1366 1367/* 1368 * We have to trap resource allocation requests and ensure that the bridge 1369 * is set up to, or capable of handling them. 1370 */ 1371struct resource * 1372pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 1373 u_long start, u_long end, u_long count, u_int flags) 1374{ 1375 struct pcib_softc *sc; 1376 struct resource *r; 1377 1378 sc = device_get_softc(dev); 1379 1380 /* 1381 * VGA resources are decoded iff the VGA enable bit is set in 1382 * the bridge control register. VGA resources do not fall into 1383 * the resource windows and are passed up to the parent. 1384 */ 1385 if ((type == SYS_RES_IOPORT && pci_is_vga_ioport_range(start, end)) || 1386 (type == SYS_RES_MEMORY && pci_is_vga_memory_range(start, end))) { 1387 if (sc->bridgectl & PCIB_BCR_VGA_ENABLE) 1388 return (bus_generic_alloc_resource(dev, child, type, 1389 rid, start, end, count, flags)); 1390 else 1391 return (NULL); 1392 } 1393 1394 switch (type) { 1395 case SYS_RES_IOPORT: 1396 if (pcib_is_isa_range(sc, start, end, count)) 1397 return (NULL); 1398 r = pcib_suballoc_resource(sc, &sc->io, child, type, rid, start, 1399 end, count, flags); 1400 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0) 1401 break; 1402 if (pcib_grow_window(sc, &sc->io, type, start, end, count, 1403 flags) == 0) 1404 r = pcib_suballoc_resource(sc, &sc->io, child, type, 1405 rid, start, end, count, flags); 1406 break; 1407 case SYS_RES_MEMORY: 1408 /* 1409 * For prefetchable resources, prefer the prefetchable 1410 * memory window, but fall back to the regular memory 1411 * window if that fails. Try both windows before 1412 * attempting to grow a window in case the firmware 1413 * has used a range in the regular memory window to 1414 * map a prefetchable BAR. 1415 */ 1416 if (flags & RF_PREFETCHABLE) { 1417 r = pcib_suballoc_resource(sc, &sc->pmem, child, type, 1418 rid, start, end, count, flags); 1419 if (r != NULL) 1420 break; 1421 } 1422 r = pcib_suballoc_resource(sc, &sc->mem, child, type, rid, 1423 start, end, count, flags); 1424 if (r != NULL || (sc->flags & PCIB_SUBTRACTIVE) != 0) 1425 break; 1426 if (flags & RF_PREFETCHABLE) { 1427 if (pcib_grow_window(sc, &sc->pmem, type, start, end, 1428 count, flags) == 0) { 1429 r = pcib_suballoc_resource(sc, &sc->pmem, child, 1430 type, rid, start, end, count, flags); 1431 if (r != NULL) 1432 break; 1433 } 1434 } 1435 if (pcib_grow_window(sc, &sc->mem, type, start, end, count, 1436 flags & ~RF_PREFETCHABLE) == 0) 1437 r = pcib_suballoc_resource(sc, &sc->mem, child, type, 1438 rid, start, end, count, flags); 1439 break; 1440 default: 1441 return (bus_generic_alloc_resource(dev, child, type, rid, 1442 start, end, count, flags)); 1443 } 1444 1445 /* 1446 * If attempts to suballocate from the window fail but this is a 1447 * subtractive bridge, pass the request up the tree. 1448 */ 1449 if (sc->flags & PCIB_SUBTRACTIVE && r == NULL) 1450 return (bus_generic_alloc_resource(dev, child, type, rid, 1451 start, end, count, flags)); 1452 return (r); 1453} 1454 1455int 1456pcib_adjust_resource(device_t bus, device_t child, int type, struct resource *r, 1457 u_long start, u_long end) 1458{ 1459 struct pcib_softc *sc; 1460 1461 sc = device_get_softc(bus); 1462 if (pcib_is_resource_managed(sc, type, r)) 1463 return (rman_adjust_resource(r, start, end)); 1464 return (bus_generic_adjust_resource(bus, child, type, r, start, end)); 1465} 1466 1467int 1468pcib_release_resource(device_t dev, device_t child, int type, int rid, 1469 struct resource *r) 1470{ 1471 struct pcib_softc *sc; 1472 int error; 1473 1474 sc = device_get_softc(dev); 1475 if (pcib_is_resource_managed(sc, type, r)) { 1476 if (rman_get_flags(r) & RF_ACTIVE) { 1477 error = bus_deactivate_resource(child, type, rid, r); 1478 if (error) 1479 return (error); 1480 } 1481 return (rman_release_resource(r)); 1482 } 1483 return (bus_generic_release_resource(dev, child, type, rid, r)); 1484} 1485#else 1486/* 1487 * We have to trap resource allocation requests and ensure that the bridge 1488 * is set up to, or capable of handling them. 1489 */ 1490struct resource * 1491pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 1492 u_long start, u_long end, u_long count, u_int flags) 1493{ 1494 struct pcib_softc *sc = device_get_softc(dev); 1495 const char *name, *suffix; 1496 int ok; 1497 1498 /* 1499 * Fail the allocation for this range if it's not supported. 1500 */ 1501 name = device_get_nameunit(child); 1502 if (name == NULL) { 1503 name = ""; 1504 suffix = ""; 1505 } else 1506 suffix = " "; 1507 switch (type) { 1508 case SYS_RES_IOPORT: 1509 ok = 0; 1510 if (!pcib_is_io_open(sc)) 1511 break; 1512 ok = (start >= sc->iobase && end <= sc->iolimit); 1513 1514 /* 1515 * Make sure we allow access to VGA I/O addresses when the 1516 * bridge has the "VGA Enable" bit set. 1517 */ 1518 if (!ok && pci_is_vga_ioport_range(start, end)) 1519 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 1520 1521 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 1522 if (!ok) { 1523 if (start < sc->iobase) 1524 start = sc->iobase; 1525 if (end > sc->iolimit) 1526 end = sc->iolimit; 1527 if (start < end) 1528 ok = 1; 1529 } 1530 } else { 1531 ok = 1; 1532#if 0 1533 /* 1534 * If we overlap with the subtractive range, then 1535 * pick the upper range to use. 1536 */ 1537 if (start < sc->iolimit && end > sc->iobase) 1538 start = sc->iolimit + 1; 1539#endif 1540 } 1541 if (end < start) { 1542 device_printf(dev, "ioport: end (%lx) < start (%lx)\n", 1543 end, start); 1544 start = 0; 1545 end = 0; 1546 ok = 0; 1547 } 1548 if (!ok) { 1549 device_printf(dev, "%s%srequested unsupported I/O " 1550 "range 0x%lx-0x%lx (decoding 0x%x-0x%x)\n", 1551 name, suffix, start, end, sc->iobase, sc->iolimit); 1552 return (NULL); 1553 } 1554 if (bootverbose) 1555 device_printf(dev, 1556 "%s%srequested I/O range 0x%lx-0x%lx: in range\n", 1557 name, suffix, start, end); 1558 break; 1559 1560 case SYS_RES_MEMORY: 1561 ok = 0; 1562 if (pcib_is_nonprefetch_open(sc)) 1563 ok = ok || (start >= sc->membase && end <= sc->memlimit); 1564 if (pcib_is_prefetch_open(sc)) 1565 ok = ok || (start >= sc->pmembase && end <= sc->pmemlimit); 1566 1567 /* 1568 * Make sure we allow access to VGA memory addresses when the 1569 * bridge has the "VGA Enable" bit set. 1570 */ 1571 if (!ok && pci_is_vga_memory_range(start, end)) 1572 ok = (sc->bridgectl & PCIB_BCR_VGA_ENABLE) ? 1 : 0; 1573 1574 if ((sc->flags & PCIB_SUBTRACTIVE) == 0) { 1575 if (!ok) { 1576 ok = 1; 1577 if (flags & RF_PREFETCHABLE) { 1578 if (pcib_is_prefetch_open(sc)) { 1579 if (start < sc->pmembase) 1580 start = sc->pmembase; 1581 if (end > sc->pmemlimit) 1582 end = sc->pmemlimit; 1583 } else { 1584 ok = 0; 1585 } 1586 } else { /* non-prefetchable */ 1587 if (pcib_is_nonprefetch_open(sc)) { 1588 if (start < sc->membase) 1589 start = sc->membase; 1590 if (end > sc->memlimit) 1591 end = sc->memlimit; 1592 } else { 1593 ok = 0; 1594 } 1595 } 1596 } 1597 } else if (!ok) { 1598 ok = 1; /* subtractive bridge: always ok */ 1599#if 0 1600 if (pcib_is_nonprefetch_open(sc)) { 1601 if (start < sc->memlimit && end > sc->membase) 1602 start = sc->memlimit + 1; 1603 } 1604 if (pcib_is_prefetch_open(sc)) { 1605 if (start < sc->pmemlimit && end > sc->pmembase) 1606 start = sc->pmemlimit + 1; 1607 } 1608#endif 1609 } 1610 if (end < start) { 1611 device_printf(dev, "memory: end (%lx) < start (%lx)\n", 1612 end, start); 1613 start = 0; 1614 end = 0; 1615 ok = 0; 1616 } 1617 if (!ok && bootverbose) 1618 device_printf(dev, 1619 "%s%srequested unsupported memory range %#lx-%#lx " 1620 "(decoding %#jx-%#jx, %#jx-%#jx)\n", 1621 name, suffix, start, end, 1622 (uintmax_t)sc->membase, (uintmax_t)sc->memlimit, 1623 (uintmax_t)sc->pmembase, (uintmax_t)sc->pmemlimit); 1624 if (!ok) 1625 return (NULL); 1626 if (bootverbose) 1627 device_printf(dev,"%s%srequested memory range " 1628 "0x%lx-0x%lx: good\n", 1629 name, suffix, start, end); 1630 break; 1631 1632 default: 1633 break; 1634 } 1635 /* 1636 * Bridge is OK decoding this resource, so pass it up. 1637 */ 1638 return (bus_generic_alloc_resource(dev, child, type, rid, start, end, 1639 count, flags)); 1640} 1641#endif 1642 1643/* 1644 * If ARI is enabled on this downstream port, translate the function number 1645 * to the non-ARI slot/function. The downstream port will convert it back in 1646 * hardware. If ARI is not enabled slot and func are not modified. 1647 */ 1648static __inline void 1649pcib_xlate_ari(device_t pcib, int bus, int *slot, int *func) 1650{ 1651 struct pcib_softc *sc; 1652 int ari_func; 1653 1654 sc = device_get_softc(pcib); 1655 ari_func = *func; 1656 1657 if (sc->flags & PCIB_ENABLE_ARI) { 1658 KASSERT(*slot == 0, 1659 ("Non-zero slot number with ARI enabled!")); 1660 *slot = PCIE_ARI_SLOT(ari_func); 1661 *func = PCIE_ARI_FUNC(ari_func); 1662 } 1663} 1664 1665 1666static void 1667pcib_enable_ari(struct pcib_softc *sc, uint32_t pcie_pos) 1668{ 1669 uint32_t ctl2; 1670 1671 ctl2 = pci_read_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, 4); 1672 ctl2 |= PCIEM_CTL2_ARI; 1673 pci_write_config(sc->dev, pcie_pos + PCIER_DEVICE_CTL2, ctl2, 4); 1674 1675 sc->flags |= PCIB_ENABLE_ARI; 1676} 1677 1678/* 1679 * PCIB interface. 1680 */ 1681int 1682pcib_maxslots(device_t dev) 1683{ 1684 return (PCI_SLOTMAX); 1685} 1686 1687static int 1688pcib_ari_maxslots(device_t dev) 1689{ 1690 struct pcib_softc *sc; 1691 1692 sc = device_get_softc(dev); 1693 1694 if (sc->flags & PCIB_ENABLE_ARI) 1695 return (PCIE_ARI_SLOTMAX); 1696 else 1697 return (PCI_SLOTMAX); 1698} 1699 1700static int 1701pcib_ari_maxfuncs(device_t dev) 1702{ 1703 struct pcib_softc *sc; 1704 1705 sc = device_get_softc(dev); 1706 1707 if (sc->flags & PCIB_ENABLE_ARI) 1708 return (PCIE_ARI_FUNCMAX); 1709 else 1710 return (PCI_FUNCMAX); 1711} 1712 1713/* 1714 * Since we are a child of a PCI bus, its parent must support the pcib interface. 1715 */ 1716static uint32_t 1717pcib_read_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, int width) 1718{ 1719 1720 pcib_xlate_ari(dev, b, &s, &f); 1721 return(PCIB_READ_CONFIG(device_get_parent(device_get_parent(dev)), b, s, 1722 f, reg, width)); 1723} 1724 1725static void 1726pcib_write_config(device_t dev, u_int b, u_int s, u_int f, u_int reg, uint32_t val, int width) 1727{ 1728 1729 pcib_xlate_ari(dev, b, &s, &f); 1730 PCIB_WRITE_CONFIG(device_get_parent(device_get_parent(dev)), b, s, f, 1731 reg, val, width); 1732} 1733 1734/* 1735 * Route an interrupt across a PCI bridge. 1736 */ 1737int 1738pcib_route_interrupt(device_t pcib, device_t dev, int pin) 1739{ 1740 device_t bus; 1741 int parent_intpin; 1742 int intnum; 1743 1744 /* 1745 * 1746 * The PCI standard defines a swizzle of the child-side device/intpin to 1747 * the parent-side intpin as follows. 1748 * 1749 * device = device on child bus 1750 * child_intpin = intpin on child bus slot (0-3) 1751 * parent_intpin = intpin on parent bus slot (0-3) 1752 * 1753 * parent_intpin = (device + child_intpin) % 4 1754 */ 1755 parent_intpin = (pci_get_slot(dev) + (pin - 1)) % 4; 1756 1757 /* 1758 * Our parent is a PCI bus. Its parent must export the pcib interface 1759 * which includes the ability to route interrupts. 1760 */ 1761 bus = device_get_parent(pcib); 1762 intnum = PCIB_ROUTE_INTERRUPT(device_get_parent(bus), pcib, parent_intpin + 1); 1763 if (PCI_INTERRUPT_VALID(intnum) && bootverbose) { 1764 device_printf(pcib, "slot %d INT%c is routed to irq %d\n", 1765 pci_get_slot(dev), 'A' + pin - 1, intnum); 1766 } 1767 return(intnum); 1768} 1769 1770/* Pass request to alloc MSI/MSI-X messages up to the parent bridge. */ 1771int 1772pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount, int *irqs) 1773{ 1774 struct pcib_softc *sc = device_get_softc(pcib); 1775 device_t bus; 1776 1777 if (sc->flags & PCIB_DISABLE_MSI) 1778 return (ENXIO); 1779 bus = device_get_parent(pcib); 1780 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount, 1781 irqs)); 1782} 1783 1784/* Pass request to release MSI/MSI-X messages up to the parent bridge. */ 1785int 1786pcib_release_msi(device_t pcib, device_t dev, int count, int *irqs) 1787{ 1788 device_t bus; 1789 1790 bus = device_get_parent(pcib); 1791 return (PCIB_RELEASE_MSI(device_get_parent(bus), dev, count, irqs)); 1792} 1793 1794/* Pass request to alloc an MSI-X message up to the parent bridge. */ 1795int 1796pcib_alloc_msix(device_t pcib, device_t dev, int *irq) 1797{ 1798 struct pcib_softc *sc = device_get_softc(pcib); 1799 device_t bus; 1800 1801 if (sc->flags & PCIB_DISABLE_MSIX) 1802 return (ENXIO); 1803 bus = device_get_parent(pcib); 1804 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq)); 1805} 1806 1807/* Pass request to release an MSI-X message up to the parent bridge. */ 1808int 1809pcib_release_msix(device_t pcib, device_t dev, int irq) 1810{ 1811 device_t bus; 1812 1813 bus = device_get_parent(pcib); 1814 return (PCIB_RELEASE_MSIX(device_get_parent(bus), dev, irq)); 1815} 1816 1817/* Pass request to map MSI/MSI-X message up to parent bridge. */ 1818int 1819pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr, 1820 uint32_t *data) 1821{ 1822 device_t bus; 1823 int error; 1824 1825 bus = device_get_parent(pcib); 1826 error = PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data); 1827 if (error) 1828 return (error); 1829 1830 pci_ht_map_msi(pcib, *addr); 1831 return (0); 1832} 1833 1834/* Pass request for device power state up to parent bridge. */ 1835int 1836pcib_power_for_sleep(device_t pcib, device_t dev, int *pstate) 1837{ 1838 device_t bus; 1839 1840 bus = device_get_parent(pcib); 1841 return (PCIB_POWER_FOR_SLEEP(bus, dev, pstate)); 1842} 1843 1844static uint16_t 1845pcib_ari_get_rid(device_t pcib, device_t dev) 1846{ 1847 struct pcib_softc *sc; 1848 uint8_t bus, slot, func; 1849 1850 sc = device_get_softc(pcib); 1851 1852 if (sc->flags & PCIB_ENABLE_ARI) { 1853 bus = pci_get_bus(dev); 1854 func = pci_get_function(dev); 1855 1856 return (PCI_ARI_RID(bus, func)); 1857 } else { 1858 bus = pci_get_bus(dev); 1859 slot = pci_get_slot(dev); 1860 func = pci_get_function(dev); 1861 1862 return (PCI_RID(bus, slot, func)); 1863 } 1864} 1865 1866/* 1867 * Check that the downstream port (pcib) and the endpoint device (dev) both 1868 * support ARI. If so, enable it and return 0, otherwise return an error. 1869 */ 1870static int 1871pcib_try_enable_ari(device_t pcib, device_t dev) 1872{ 1873 struct pcib_softc *sc; 1874 int error; 1875 uint32_t cap2; 1876 int ari_cap_off; 1877 uint32_t ari_ver; 1878 uint32_t pcie_pos; 1879 1880 sc = device_get_softc(pcib); 1881 1882 /* 1883 * ARI is controlled in a register in the PCIe capability structure. 1884 * If the downstream port does not have the PCIe capability structure 1885 * then it does not support ARI. 1886 */ 1887 error = pci_find_cap(pcib, PCIY_EXPRESS, &pcie_pos); 1888 if (error != 0) 1889 return (ENODEV); 1890 1891 /* Check that the PCIe port advertises ARI support. */ 1892 cap2 = pci_read_config(pcib, pcie_pos + PCIER_DEVICE_CAP2, 4); 1893 if (!(cap2 & PCIEM_CAP2_ARI)) 1894 return (ENODEV); 1895 1896 /* 1897 * Check that the endpoint device advertises ARI support via the ARI 1898 * extended capability structure. 1899 */ 1900 error = pci_find_extcap(dev, PCIZ_ARI, &ari_cap_off); 1901 if (error != 0) 1902 return (ENODEV); 1903 1904 /* 1905 * Finally, check that the endpoint device supports the same version 1906 * of ARI that we do. 1907 */ 1908 ari_ver = pci_read_config(dev, ari_cap_off, 4); 1909 if (PCI_EXTCAP_VER(ari_ver) != PCIB_SUPPORTED_ARI_VER) { 1910 if (bootverbose) 1911 device_printf(pcib, 1912 "Unsupported version of ARI (%d) detected\n", 1913 PCI_EXTCAP_VER(ari_ver)); 1914 1915 return (ENXIO); 1916 } 1917 1918 pcib_enable_ari(sc, pcie_pos); 1919 1920 return (0); 1921} 1922 1923