164987Smsmith/*- 264987Smsmith * Copyright (c) 2000 Michael Smith 364987Smsmith * Copyright (c) 2000 BSDi 464987Smsmith * All rights reserved. 564987Smsmith * 664987Smsmith * Redistribution and use in source and binary forms, with or without 764987Smsmith * modification, are permitted provided that the following conditions 864987Smsmith * are met: 964987Smsmith * 1. Redistributions of source code must retain the above copyright 1064987Smsmith * notice, this list of conditions and the following disclaimer. 1164987Smsmith * 2. Redistributions in binary form must reproduce the above copyright 1264987Smsmith * notice, this list of conditions and the following disclaimer in the 1364987Smsmith * documentation and/or other materials provided with the distribution. 1464987Smsmith * 1564987Smsmith * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1664987Smsmith * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1764987Smsmith * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1864987Smsmith * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1964987Smsmith * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 2064987Smsmith * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2164987Smsmith * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2264987Smsmith * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2364987Smsmith * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2464987Smsmith * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2564987Smsmith * SUCH DAMAGE. 2664987Smsmith * 2764987Smsmith * $FreeBSD$ 2864987Smsmith */ 2964987Smsmith 3064987Smsmith/* 3164987Smsmith * Section numbers in this document refer to the Mylex "Firmware Software Interface" 3264987Smsmith * document ('FSI'), revision 0.11 04/11/00 unless otherwise qualified. 3364987Smsmith * 3464987Smsmith * Reference is made to the Mylex "Programming Guide for 6.x Controllers" document 3564987Smsmith * ('PG6'), document #771242 revision 0.02, 04/11/00 3664987Smsmith * 3764987Smsmith * Note that fields marked N/A are not supported by the PCI controllers, but are 3864987Smsmith * defined here to hold place in datastructures that are shared with the SCSI 3964987Smsmith * controllers. Items not relevant to PCI controllers are not described here. 4064987Smsmith * 4164987Smsmith * Ordering of items in this file is a little odd due to the constraints of 4264987Smsmith * nested declarations. 4364987Smsmith */ 4464987Smsmith 4564987Smsmith/* 4664987Smsmith * 2.1 (Scatter Gather List Format) 4764987Smsmith */ 4864987Smsmithstruct mly_sg_entry { 4964987Smsmith u_int64_t physaddr; 5064987Smsmith u_int64_t length; 51103870Salfred} __packed; 5264987Smsmith 5364987Smsmith/* 5464987Smsmith * 5.2 System Device Access 5564987Smsmith * 5664987Smsmith * This is corroborated by the layout of the MDACIOCTL_GETCONTROLLERINFO data 5764987Smsmith * in 21.8 5864987Smsmith */ 5964987Smsmith#define MLY_MAX_CHANNELS 6 6064987Smsmith#define MLY_MAX_TARGETS 16 6164987Smsmith#define MLY_MAX_LUNS 1 6264987Smsmith 6364987Smsmith/* 6464987Smsmith * 8.1 Different Device States 6564987Smsmith */ 6664987Smsmith#define MLY_DEVICE_STATE_OFFLINE 0x08 /* DEAD/OFFLINE */ 6764987Smsmith#define MLY_DEVICE_STATE_UNCONFIGURED 0x00 6864987Smsmith#define MLY_DEVICE_STATE_ONLINE 0x01 6964987Smsmith#define MLY_DEVICE_STATE_CRITICAL 0x09 7064987Smsmith#define MLY_DEVICE_STATE_WRITEONLY 0x03 7164987Smsmith#define MLY_DEVICE_STATE_STANDBY 0x21 7264987Smsmith#define MLY_DEVICE_STATE_MISSING 0x04 /* or-ed with (ONLINE or WRITEONLY or STANDBY) */ 7364987Smsmith 7464987Smsmith/* 7564987Smsmith * 8.2 Device Type Field definitions 7664987Smsmith */ 7764987Smsmith#define MLY_DEVICE_TYPE_RAID0 0x0 /* RAID 0 */ 7864987Smsmith#define MLY_DEVICE_TYPE_RAID1 0x1 /* RAID 1 */ 7964987Smsmith#define MLY_DEVICE_TYPE_RAID3 0x3 /* RAID 3 right asymmetric parity */ 8064987Smsmith#define MLY_DEVICE_TYPE_RAID5 0x5 /* RAID 5 right asymmetric parity */ 8164987Smsmith#define MLY_DEVICE_TYPE_RAID6 0x6 /* RAID 6 (Mylex RAID 6) */ 8264987Smsmith#define MLY_DEVICE_TYPE_RAID7 0x7 /* RAID 7 (JBOD) */ 8364987Smsmith#define MLY_DEVICE_TYPE_NEWSPAN 0x8 /* New Mylex SPAN */ 8464987Smsmith#define MLY_DEVICE_TYPE_RAID3F 0x9 /* RAID 3 fixed parity */ 8564987Smsmith#define MLY_DEVICE_TYPE_RAID3L 0xb /* RAID 3 left symmetric parity */ 8664987Smsmith#define MLY_DEVICE_TYPE_SPAN 0xc /* current spanning implementation */ 8764987Smsmith#define MLY_DEVICE_TYPE_RAID5L 0xd /* RAID 5 left symmetric parity */ 8864987Smsmith#define MLY_DEVICE_TYPE_RAIDE 0xe /* RAID E (concatenation) */ 8964987Smsmith#define MLY_DEVICE_TYPE_PHYSICAL 0xf /* physical device */ 9064987Smsmith 9164987Smsmith/* 9264987Smsmith * 8.3 Stripe Size 9364987Smsmith */ 9464987Smsmith#define MLY_STRIPE_ZERO 0x0 /* no stripe (RAID 1, RAID 7, etc) */ 9564987Smsmith#define MLY_STRIPE_512b 0x1 9664987Smsmith#define MLY_STRIPE_1k 0x2 9764987Smsmith#define MLY_STRIPE_2k 0x3 9864987Smsmith#define MLY_STRIPE_4k 0x4 9964987Smsmith#define MLY_STRIPE_8k 0x5 10064987Smsmith#define MLY_STRIPE_16k 0x6 10164987Smsmith#define MLY_STRIPE_32k 0x7 10264987Smsmith#define MLY_STRIPE_64k 0x8 10364987Smsmith#define MLY_STRIPE_128k 0x9 10464987Smsmith#define MLY_STRIPE_256k 0xa 10564987Smsmith#define MLY_STRIPE_512k 0xb 10664987Smsmith#define MLY_STRIPE_1m 0xc 10764987Smsmith 10864987Smsmith/* 10964987Smsmith * 8.4 Cacheline Size 11064987Smsmith */ 11164987Smsmith#define MLY_CACHELINE_ZERO 0x0 /* caching cannot be enabled */ 11264987Smsmith#define MLY_CACHELINE_512b 0x1 11364987Smsmith#define MLY_CACHELINE_1k 0x2 11464987Smsmith#define MLY_CACHELINE_2k 0x3 11564987Smsmith#define MLY_CACHELINE_4k 0x4 11664987Smsmith#define MLY_CACHELINE_8k 0x5 11764987Smsmith#define MLY_CACHELINE_16k 0x6 11864987Smsmith#define MLY_CACHELINE_32k 0x7 11964987Smsmith#define MLY_CACHELINE_64k 0x8 12064987Smsmith 12164987Smsmith/* 12264987Smsmith * 8.5 Read/Write control 12364987Smsmith */ 12464987Smsmith#define MLY_RWCtl_INITTED (1<<7) /* if set, the logical device is initialised */ 12564987Smsmith /* write control */ 12664987Smsmith#define MLY_RWCtl_WCD (0) /* write cache disabled */ 12764987Smsmith#define MLY_RWCtl_WDISABLE (1<<3) /* writing disabled */ 12864987Smsmith#define MLY_RWCtl_WCE (2<<3) /* write cache enabled */ 12964987Smsmith#define MLY_RWCtl_IWCE (3<<3) /* intelligent write cache enabled */ 13064987Smsmith /* read control */ 13164987Smsmith#define MLY_RWCtl_RCD (0) /* read cache is disabled */ 13264987Smsmith#define MLY_RWCtl_RCE (1) /* read cache enabled */ 13364987Smsmith#define MLY_RWCtl_RAHEAD (2) /* readahead enabled */ 13464987Smsmith#define MLY_RWCtl_IRAHEAD (3) /* intelligent readahead enabled */ 13564987Smsmith 13664987Smsmith/* 13764987Smsmith * 9.0 LUN Map Format 13864987Smsmith */ 13964987Smsmithstruct mly_lun_map { 14064987Smsmith u_int8_t res1:4; 14164987Smsmith u_int8_t host_port_mapped:1; /* this system drive visibile to host on this controller/port combination */ 14264987Smsmith u_int8_t tid_valid:1; /* target ID valid */ 14364987Smsmith u_int8_t hid_valid:1; /* host ID valid */ 14464987Smsmith u_int8_t lun_valid:1; /* LUN valid */ 14564987Smsmith u_int8_t res2; 14664987Smsmith u_int8_t lun; /* LUN */ 14764987Smsmith u_int8_t tid; /* TID */ 14864987Smsmith u_int8_t hid[32]; /* HID (one bit for each host) */ 149103870Salfred} __packed; 15064987Smsmith 15164987Smsmith/* 15264987Smsmith * 10.1 Controller Parameters 15364987Smsmith */ 15464987Smsmithstruct mly_param_controller { 15564987Smsmith u_int8_t rdahen:1; /* N/A */ 15664987Smsmith u_int8_t bilodly:1; /* N/A */ 15764987Smsmith u_int8_t fua_disable:1; 15864987Smsmith u_int8_t reass1s:1; /* N/A */ 15964987Smsmith u_int8_t truvrfy:1; /* N/A */ 16064987Smsmith u_int8_t dwtvrfy:1; /* N/A */ 16164987Smsmith u_int8_t background_initialisation:1; 16264987Smsmith u_int8_t clustering:1; /* N/A */ 16364987Smsmith 16464987Smsmith u_int8_t bios_disable:1; 16564987Smsmith u_int8_t boot_from_cdrom:1; 16664987Smsmith u_int8_t drive_coercion:1; 16764987Smsmith u_int8_t write_same_disable:1; 16864987Smsmith u_int8_t hba_mode:1; /* N/A */ 16964987Smsmith u_int8_t bios_geometry:2; 17064987Smsmith#define MLY_BIOSGEOM_2G 0x0 17164987Smsmith#define MLY_BIOSGEOM_8G 0x1 17264987Smsmith u_int8_t res1:1; /* N/A */ 17364987Smsmith 17464987Smsmith u_int8_t res2[2]; /* N/A */ 17564987Smsmith 17664987Smsmith u_int8_t v_dec:1; 17764987Smsmith u_int8_t safte:1; /* N/A */ 17864987Smsmith u_int8_t ses:1; /* N/A */ 17964987Smsmith u_int8_t res3:2; /* N/A */ 18064987Smsmith u_int8_t v_arm:1; 18164987Smsmith u_int8_t v_ofm:1; 18264987Smsmith u_int8_t res4:1; /* N/A */ 18364987Smsmith 18464987Smsmith u_int8_t rebuild_check_rate; 18564987Smsmith u_int8_t cache_line_size; /* see 8.4 */ 18664987Smsmith u_int8_t oem_code; 18764987Smsmith#define MLY_OEM_MYLEX 0x00 18864987Smsmith#define MLY_OEM_IBM 0x08 18964987Smsmith#define MLY_OEM_HP 0x0a 19064987Smsmith#define MLY_OEM_DEC 0x0c 19164987Smsmith#define MLY_OEM_SIEMENS 0x10 19264987Smsmith#define MLY_OEM_INTEL 0x12 19364987Smsmith u_int8_t spinup_mode; 19464987Smsmith#define MLY_SPIN_AUTO 0 19564987Smsmith#define MLY_SPIN_PWRSPIN 1 19664987Smsmith#define MLY_SPIN_WSSUSPIN 2 19764987Smsmith u_int8_t spinup_devices; 19864987Smsmith u_int8_t spinup_interval; 19964987Smsmith u_int8_t spinup_wait_time; 20064987Smsmith 20164987Smsmith u_int8_t res5:3; /* N/A */ 20264987Smsmith u_int8_t vutursns:1; /* N/A */ 20364987Smsmith u_int8_t dccfil:1; /* N/A */ 20464987Smsmith u_int8_t nopause:1; /* N/A */ 20564987Smsmith u_int8_t disqfull:1; /* N/A */ 20664987Smsmith u_int8_t disbusy:1; /* N/A */ 20764987Smsmith 20864987Smsmith u_int8_t res6:2; /* N/A */ 20964987Smsmith u_int8_t failover_node_name; /* N/A */ 21064987Smsmith u_int8_t res7:1; /* N/A */ 21164987Smsmith u_int8_t ftopo:3; /* N/A */ 21264987Smsmith u_int8_t disable_ups:1; /* N/A */ 21364987Smsmith 21464987Smsmith u_int8_t res8:1; /* N/A */ 21564987Smsmith u_int8_t propagate_reset:1; /* N/A */ 21664987Smsmith u_int8_t nonstd_mp_reset:1; /* N/A */ 21764987Smsmith u_int8_t res9:5; /* N/A */ 21864987Smsmith 21964987Smsmith u_int8_t res10; /* N/A */ 22064987Smsmith u_int8_t serial_port_baud_rate; /* N/A */ 22164987Smsmith u_int8_t serial_port_control; /* N/A */ 22264987Smsmith u_int8_t change_stripe_ok_developer_flag_only; /* N/A */ 22364987Smsmith 22464987Smsmith u_int8_t small_large_host_transfers:2; /* N/A */ 22564987Smsmith u_int8_t frame_control:2; /* N/A */ 22664987Smsmith u_int8_t pci_latency_control:2; /* N/A */ 22764987Smsmith u_int8_t treat_lip_as_reset:1; /* N/A */ 22864987Smsmith u_int8_t res11:1; /* N/A */ 22964987Smsmith 23064987Smsmith u_int8_t ms_autorest:1; /* N/A */ 23164987Smsmith u_int8_t res12:7; /* N/A */ 23264987Smsmith 23364987Smsmith u_int8_t ms_aa_fsim:1; /* N/A */ 23464987Smsmith u_int8_t ms_aa_ccach:1; /* N/A */ 23564987Smsmith u_int8_t ms_aa_fault_signals:1; /* N/A */ 23664987Smsmith u_int8_t ms_aa_c4_faults:1; /* N/A */ 23764987Smsmith u_int8_t ms_aa_host_reset_delay_mask:4; /* N/A */ 23864987Smsmith 23964987Smsmith u_int8_t ms_flg_simplex_no_rstcom:1; /* N/A */ 24064987Smsmith u_int8_t res13:7; /* N/A */ 24164987Smsmith 24264987Smsmith u_int8_t res14; /* N/A */ 24364987Smsmith u_int8_t hardloopid[2][2]; /* N/A */ 24464987Smsmith u_int8_t ctrlname[2][16+1]; /* N/A */ 24564987Smsmith u_int8_t initiator_id; 24664987Smsmith u_int8_t startup_option; 24764987Smsmith#define MLY_STARTUP_IF_NO_CHANGE 0x0 24864987Smsmith#define MLY_STARTUP_IF_NO_LUN_CHANGE 0x1 24964987Smsmith#define MLY_STARTUP_IF_NO_LUN_OFFLINE 0x2 25064987Smsmith#define MLY_STARTUP_IF_LUN0_NO_CHANGE 0x3 25164987Smsmith#define MLY_STARTUP_IF_LUN0_NOT_OFFLINE 0x4 25264987Smsmith#define MLY_STARTUP_ALWAYS 0x5 25364987Smsmith 25464987Smsmith u_int8_t res15[62]; 255103870Salfred} __packed; 25664987Smsmith 25764987Smsmith/* 25864987Smsmith * 10.2 Physical Device Parameters 25964987Smsmith */ 26064987Smsmithstruct mly_param_physical_device { 26164987Smsmith u_int16_t tags; 26264987Smsmith u_int16_t speed; 26364987Smsmith u_int8_t width; 26464987Smsmith u_int8_t combing:1; 26564987Smsmith u_int8_t res1:7; 26664987Smsmith u_int8_t res2[3]; 267103870Salfred} __packed; 26864987Smsmith 26964987Smsmith/* 27064987Smsmith * 10.3 Logical Device Parameters 27164987Smsmith */ 27264987Smsmithstruct mly_param_logical_device { 27364987Smsmith u_int8_t type; /* see 8.2 */ 27464987Smsmith u_int8_t state; /* see 8.1 */ 27564987Smsmith u_int16_t raid_device; 27664987Smsmith u_int8_t res1; 27764987Smsmith u_int8_t bios_geometry; /* BIOS control word? */ 27864987Smsmith u_int8_t stripe_size; /* see 8.3 */ 27964987Smsmith u_int8_t read_write_control; /* see 8.5 */ 28064987Smsmith u_int8_t res2[8]; 281103870Salfred} __packed; 28264987Smsmith 28364987Smsmith/* 28464987Smsmith * 12.3 Health Status Buffer 28564987Smsmith * 28664987Smsmith * Pad to 128 bytes. 28764987Smsmith */ 28864987Smsmithstruct mly_health_status { 28964987Smsmith u_int32_t uptime_us; /* N/A */ 29064987Smsmith u_int32_t uptime_ms; /* N/A */ 29164987Smsmith u_int32_t realtime; /* N/A */ 29264987Smsmith u_int32_t res1; /* N/A */ 29364987Smsmith u_int32_t change_counter; 29464987Smsmith u_int32_t res2; /* N/A */ 29564987Smsmith u_int32_t debug_message_index; /* N/A */ 29664987Smsmith u_int32_t bios_message_index; /* N/A */ 29764987Smsmith u_int32_t trace_page; /* N/A */ 29864987Smsmith u_int32_t profiler_page; /* N/A */ 29964987Smsmith u_int32_t next_event; 30064987Smsmith u_int8_t res3[4 + 16 + 64]; /* N/A */ 301103870Salfred} __packed; 30264987Smsmith 30364987Smsmith/* 30464987Smsmith * 14.2 Timeout Bit Format 30564987Smsmith */ 30664987Smsmithstruct mly_timeout { 30764987Smsmith u_int8_t value:6; 30864987Smsmith u_int8_t scale:2; 30964987Smsmith#define MLY_TIMEOUT_SECONDS 0x0 31064987Smsmith#define MLY_TIMEOUT_MINUTES 0x1 31164987Smsmith#define MLY_TIMEOUT_HOURS 0x2 312103870Salfred} __packed; 31364987Smsmith 31464987Smsmith/* 31564987Smsmith * 14.3 Operation Device 31664987Smsmith */ 31764987Smsmith#define MLY_OPDEVICE_PHYSICAL_DEVICE 0x0 31864987Smsmith#define MLY_OPDEVICE_RAID_DEVICE 0x1 31964987Smsmith#define MLY_OPDEVICE_PHYSICAL_CHANNEL 0x2 32064987Smsmith#define MLY_OPDEVICE_RAID_CHANNEL 0x3 32164987Smsmith#define MLY_OPDEVICE_PHYSICAL_CONTROLLER 0x4 32264987Smsmith#define MLY_OPDEVICE_RAID_CONTROLLER 0x5 32364987Smsmith#define MLY_OPDEVICE_CONFIGURATION_GROUP 0x10 32464987Smsmith 32564987Smsmith/* 32664987Smsmith * 14.4 Status Bit Format 32764987Smsmith * 32864987Smsmith * AKA Status Mailbox Format 32964987Smsmith * 33064987Smsmith * XXX format conflict between FSI and PG6 over the ordering of the 33164987Smsmith * status and sense length fields. 33264987Smsmith */ 33364987Smsmithstruct mly_status { 33464987Smsmith u_int16_t command_id; 33564987Smsmith u_int8_t status; 33664987Smsmith u_int8_t sense_length; 33764987Smsmith int32_t residue; 338103870Salfred} __packed; 33964987Smsmith 34064987Smsmith/* 34164987Smsmith * 14.5 Command Control Bit (CCB) format 34264987Smsmith * 34364987Smsmith * This byte is unfortunately named. 34464987Smsmith */ 34564987Smsmithstruct mly_command_control { 34664987Smsmith u_int8_t force_unit_access:1; 34764987Smsmith u_int8_t disable_page_out:1; 34864987Smsmith u_int8_t res1:1; 34964987Smsmith u_int8_t extended_sg_table:1; 35064987Smsmith u_int8_t data_direction:1; 35164987Smsmith#define MLY_CCB_WRITE 1 35264987Smsmith#define MLY_CCB_READ 0 35364987Smsmith u_int8_t res2:1; 35464987Smsmith u_int8_t no_auto_sense:1; 35564987Smsmith u_int8_t disable_disconnect:1; 356103870Salfred} __packed; 35764987Smsmith 35864987Smsmith/* 35964987Smsmith * 15.0 Commands 36064987Smsmith * 36164987Smsmith * We use the command names as given by Mylex 36264987Smsmith */ 36364987Smsmith#define MDACMD_MEMCOPY 0x1 /* memory to memory copy */ 36464987Smsmith#define MDACMD_SCSIPT 0x2 /* SCSI passthrough (small command) */ 36564987Smsmith#define MDACMD_SCSILCPT 0x3 /* SCSI passthrough (large command) */ 36664987Smsmith#define MDACMD_SCSI 0x4 /* SCSI command for logical/phyiscal device (small command) */ 36764987Smsmith#define MDACMD_SCSILC 0x5 /* SCSI command for logical/phyiscal device (large command) */ 36864987Smsmith#define MDACMD_IOCTL 0x20 /* Management command */ 36964987Smsmith#define MDACMD_IOCTLCHECK 0x23 /* Validate management command (not implemented) */ 37064987Smsmith 37164987Smsmith/* 37264987Smsmith * 16.0 IOCTL command 37364987Smsmith * 37464987Smsmith * We use the IOCTL names as given by Mylex 37564987Smsmith * Note that only ioctls supported by the PCI controller family are listed 37664987Smsmith */ 37764987Smsmith#define MDACIOCTL_GETCONTROLLERINFO 0x1 37864987Smsmith#define MDACIOCTL_GETLOGDEVINFOVALID 0x3 37964987Smsmith#define MDACIOCTL_GETPHYSDEVINFOVALID 0x5 38064987Smsmith#define MDACIOCTL_GETCONTROLLERSTATISTICS 0xb 38164987Smsmith#define MDACIOCTL_GETLOGDEVSTATISTICS 0xd 38264987Smsmith#define MDACIOCTL_GETPHYSDEVSTATISTICS 0xf 38364987Smsmith#define MDACIOCTL_GETHEALTHSTATUS 0x11 38464987Smsmith#define MDACIOCTL_GETEVENT 0x15 38564987Smsmith/* flash update */ 38664987Smsmith#define MDACIOCTL_STOREIMAGE 0x2c 38764987Smsmith#define MDACIOCTL_READIMAGE 0x2d 38864987Smsmith#define MDACIOCTL_FLASHIMAGES 0x2e 38964987Smsmith/* battery backup unit */ 39064987Smsmith#define MDACIOCTL_GET_SUBSYSTEM_DATA 0x70 39164987Smsmith#define MDACIOCTL_SET_SUBSYSTEM_DATA 0x71 39264987Smsmith/* non-data commands */ 39364987Smsmith#define MDACIOCTL_STARTDISOCVERY 0x81 39464987Smsmith#define MDACIOCTL_SETRAIDDEVSTATE 0x82 39564987Smsmith#define MDACIOCTL_INITPHYSDEVSTART 0x84 39664987Smsmith#define MDACIOCTL_INITPHYSDEVSTOP 0x85 39764987Smsmith#define MDACIOCTL_INITRAIDDEVSTART 0x86 39864987Smsmith#define MDACIOCTL_INITRAIDDEVSTOP 0x87 39964987Smsmith#define MDACIOCTL_REBUILDRAIDDEVSTART 0x88 40064987Smsmith#define MDACIOCTL_REBUILDRAIDDEVSTOP 0x89 40164987Smsmith#define MDACIOCTL_MAKECONSISTENTDATASTART 0x8a 40264987Smsmith#define MDACIOCTL_MAKECONSISTENTDATASTOP 0x8b 40364987Smsmith#define MDACIOCTL_CONSISTENCYCHECKSTART 0x8c 40464987Smsmith#define MDACIOCTL_CONSISTENCYCHECKSTOP 0x8d 40564987Smsmith#define MDACIOCTL_SETMEMORYMAILBOX 0x8e 40664987Smsmith#define MDACIOCTL_RESETDEVICE 0x90 40764987Smsmith#define MDACIOCTL_FLUSHDEVICEDATA 0x91 40864987Smsmith#define MDACIOCTL_PAUSEDEVICE 0x92 40964987Smsmith#define MDACIOCTL_UNPAUSEDEVICE 0x93 41064987Smsmith#define MDACIOCTL_LOCATEDEVICE 0x94 41164987Smsmith#define MDACIOCTL_SETMASTERSLAVEMODE 0x95 41264987Smsmith#define MDACIOCTL_SETREALTIMECLOCK 0xac 41364987Smsmith/* RAID configuration */ 41464987Smsmith#define MDACIOCTL_CREATENEWCONF 0xc0 41564987Smsmith#define MDACIOCTL_DELETERAIDDEV 0xc1 41664987Smsmith#define MDACIOCTL_REPLACEINTERNALDEV 0xc2 41764987Smsmith#define MDACIOCTL_RENAMERAIDDEV 0xc3 41864987Smsmith#define MDACIOCTL_ADDNEWCONF 0xc4 41964987Smsmith#define MDACIOCTL_XLATEPHYSDEVTORAIDDEV 0xc5 42064987Smsmith#define MDACIOCTL_MORE 0xc6 42164987Smsmith#define MDACIOCTL_SETPHYSDEVPARAMETER 0xc8 42264987Smsmith#define MDACIOCTL_GETPHYSDEVPARAMETER 0xc9 42364987Smsmith#define MDACIOCTL_CLEARCONF 0xca 42464987Smsmith#define MDACIOCTL_GETDEVCONFINFO 0xcb 42564987Smsmith#define MDACIOCTL_GETGROUPCONFINFO 0xcc 42664987Smsmith#define MDACIOCTL_GETFREESPACELIST 0xcd 42764987Smsmith#define MDACIOCTL_GETLOGDEVPARAMETER 0xce 42864987Smsmith#define MDACIOCTL_SETLOGDEVPARAMETER 0xcf 42964987Smsmith#define MDACIOCTL_GETCONTROLLERPARAMETER 0xd0 43064987Smsmith#define MDACIOCTL_SETCONTRLLERPARAMETER 0xd1 43164987Smsmith#define MDACIOCTL_CLEARCONFSUSPMODE 0xd2 43264987Smsmith#define MDACIOCTL_GETBDT_FOR_SYSDRIVE 0xe0 43364987Smsmith 43464987Smsmith/* 43564987Smsmith * 17.1.4 Data Transfer Memory Address Without SG List 43664987Smsmith */ 43764987Smsmithstruct mly_short_transfer { 43864987Smsmith struct mly_sg_entry sg[2]; 439103870Salfred} __packed; 44064987Smsmith 44164987Smsmith/* 44264987Smsmith * 17.1.5 Data Transfer Memory Address With SG List 44364987Smsmith * 44464987Smsmith * Note that only the first s/g table is currently used. 44564987Smsmith */ 44664987Smsmithstruct mly_sg_transfer { 44764987Smsmith u_int16_t entries[3]; 44864987Smsmith u_int16_t res1; 44964987Smsmith u_int64_t table_physaddr[3]; 450103870Salfred} __packed; 45164987Smsmith 45264987Smsmith/* 45364987Smsmith * 17.1.3 Data Transfer Memory Address Format 45464987Smsmith */ 45564987Smsmithunion mly_command_transfer { 45664987Smsmith struct mly_short_transfer direct; 45764987Smsmith struct mly_sg_transfer indirect; 45864987Smsmith}; 45964987Smsmith 46064987Smsmith/* 46164987Smsmith * 21.1 MDACIOCTL_SETREALTIMECLOCK 46264987Smsmith * 21.7 MDACIOCTL_GETHEALTHSTATUS 46364987Smsmith * 21.8 MDACIOCTL_GETCONTROLLERINFO 46464987Smsmith * 21.9 MDACIOCTL_GETLOGDEVINFOVALID 46564987Smsmith * 21.10 MDACIOCTL_GETPHYSDEVINFOVALID 46664987Smsmith * 21.11 MDACIOCTL_GETPHYSDEVSTATISTICS 46764987Smsmith * 21.12 MDACIOCTL_GETLOGDEVSTATISTICS 46864987Smsmith * 21.13 MDACIOCTL_GETCONTROLLERSTATISTICS 46964987Smsmith * 21.27 MDACIOCTL_GETBDT_FOR_SYSDRIVE 47064987Smsmith * 23.4 MDACIOCTL_CREATENEWCONF 47164987Smsmith * 23.5 MDACIOCTL_ADDNEWCONF 47264987Smsmith * 23.8 MDACIOCTL_GETDEVCONFINFO 47364987Smsmith * 23.9 MDACIOCTL_GETFREESPACELIST 47464987Smsmith * 24.1 MDACIOCTL_MORE 47564987Smsmith * 25.1 MDACIOCTL_GETPHYSDEVPARAMETER 47664987Smsmith * 25.2 MDACIOCTL_SETPHYSDEVPARAMETER 47764987Smsmith * 25.3 MDACIOCTL_GETLOGDEVPARAMETER 47864987Smsmith * 25.4 MDACIOCTL_SETLOGDEVPARAMETER 47964987Smsmith * 25.5 MDACIOCTL_GETCONTROLLERPARAMETER 48064987Smsmith * 25.6 MDACIOCTL_SETCONTROLLERPARAMETER 48164987Smsmith * 48264987Smsmith * These commands just transfer data 48364987Smsmith */ 48464987Smsmithstruct mly_ioctl_param_data { 48564987Smsmith u_int8_t param[10]; 48664987Smsmith union mly_command_transfer transfer; 487103870Salfred} __packed; 48864987Smsmith 48964987Smsmith/* 49064987Smsmith * 21.2 MDACIOCTL_SETMEMORYMAILBOX 49164987Smsmith */ 49264987Smsmithstruct mly_ioctl_param_setmemorymailbox { 49364987Smsmith u_int8_t health_buffer_size; 49464987Smsmith u_int8_t res1; 49564987Smsmith u_int64_t health_buffer_physaddr; 49664987Smsmith u_int64_t command_mailbox_physaddr; 49764987Smsmith u_int64_t status_mailbox_physaddr; 49864987Smsmith u_int64_t res2[2]; 499103870Salfred} __packed; 50064987Smsmith 50164987Smsmith/* 50264987Smsmith * 21.8.2 MDACIOCTL_GETCONTROLLERINFO: Data Format 50364987Smsmith */ 50464987Smsmithstruct mly_ioctl_getcontrollerinfo { 50564987Smsmith u_int8_t res1; /* N/A */ 50664987Smsmith u_int8_t interface_type; 50764987Smsmith u_int8_t controller_type; 50864987Smsmith u_int8_t res2; /* N/A */ 50964987Smsmith u_int16_t interface_speed; 51064987Smsmith u_int8_t interface_width; 51164987Smsmith u_int8_t res3[9]; /* N/A */ 51264987Smsmith char interface_name[16]; 51364987Smsmith char controller_name[16]; 51464987Smsmith u_int8_t res4[16]; /* N/A */ 51564987Smsmith /* firmware release information */ 51664987Smsmith u_int8_t fw_major; 51764987Smsmith u_int8_t fw_minor; 51864987Smsmith u_int8_t fw_turn; 51964987Smsmith u_int8_t fw_build; 52064987Smsmith u_int8_t fw_day; 52164987Smsmith u_int8_t fw_month; 52264987Smsmith u_int8_t fw_century; 52364987Smsmith u_int8_t fw_year; 52464987Smsmith /* hardware release information */ 52564987Smsmith u_int8_t hw_revision; /* N/A */ 52664987Smsmith u_int8_t res5[3]; /* N/A */ 52764987Smsmith u_int8_t hw_release_day; /* N/A */ 52864987Smsmith u_int8_t hw_release_month; /* N/A */ 52964987Smsmith u_int8_t hw_release_century; /* N/A */ 53064987Smsmith u_int8_t hw_release_year; /* N/A */ 53164987Smsmith /* hardware manufacturing information */ 53264987Smsmith u_int8_t batch_number; /* N/A */ 53364987Smsmith u_int8_t res6; /* N/A */ 53464987Smsmith u_int8_t plant_number; 53564987Smsmith u_int8_t res7; 53664987Smsmith u_int8_t hw_manuf_day; 53764987Smsmith u_int8_t hw_manuf_month; 53864987Smsmith u_int8_t hw_manuf_century; 53964987Smsmith u_int8_t hw_manuf_year; 54064987Smsmith u_int8_t max_pdd_per_xldd; 54164987Smsmith u_int8_t max_ildd_per_xldd; 54264987Smsmith u_int16_t nvram_size; 54364987Smsmith u_int8_t max_number_of_xld; /* N/A */ 54464987Smsmith u_int8_t res8[3]; /* N/A */ 54564987Smsmith /* unique information per controller */ 54664987Smsmith char serial_number[16]; 54764987Smsmith u_int8_t res9[16]; /* N/A */ 54864987Smsmith /* vendor information */ 54964987Smsmith u_int8_t res10[3]; /* N/A */ 55064987Smsmith u_int8_t oem_information; 55164987Smsmith char vendor_name[16]; /* N/A */ 55264987Smsmith /* other physical/controller/operation information */ 55364987Smsmith u_int8_t bbu_present:1; 55464987Smsmith u_int8_t active_clustering:1; 55564987Smsmith u_int8_t res11:6; /* N/A */ 55664987Smsmith u_int8_t res12[3]; /* N/A */ 55764987Smsmith /* physical device scan information */ 55864987Smsmith u_int8_t physical_scan_active:1; 55964987Smsmith u_int8_t res13:7; /* N/A */ 56064987Smsmith u_int8_t physical_scan_channel; 56164987Smsmith u_int8_t physical_scan_target; 56264987Smsmith u_int8_t physical_scan_lun; 56364987Smsmith /* maximum command data transfer size */ 56464987Smsmith u_int16_t maximum_block_count; 56564987Smsmith u_int16_t maximum_sg_entries; 56664987Smsmith /* logical/physical device counts */ 56764987Smsmith u_int16_t logical_devices_present; 56864987Smsmith u_int16_t logical_devices_critical; 56964987Smsmith u_int16_t logical_devices_offline; 57064987Smsmith u_int16_t physical_devices_present; 57164987Smsmith u_int16_t physical_disks_present; 57264987Smsmith u_int16_t physical_disks_critical; /* N/A */ 57364987Smsmith u_int16_t physical_disks_offline; 57464987Smsmith u_int16_t maximum_parallel_commands; 57564987Smsmith /* channel and target ID information */ 57664987Smsmith u_int8_t physical_channels_present; 57764987Smsmith u_int8_t virtual_channels_present; 57864987Smsmith u_int8_t physical_channels_possible; 57964987Smsmith u_int8_t virtual_channels_possible; 58064987Smsmith u_int8_t maximum_targets_possible[16]; /* N/A (6 and up) */ 58164987Smsmith u_int8_t res14[12]; /* N/A */ 58264987Smsmith /* memory/cache information */ 58364987Smsmith u_int16_t memory_size; 58464987Smsmith u_int16_t cache_size; 58564987Smsmith u_int32_t valid_cache_size; /* N/A */ 58664987Smsmith u_int32_t dirty_cache_size; /* N/A */ 58764987Smsmith u_int16_t memory_speed; 58864987Smsmith u_int8_t memory_width; 58964987Smsmith u_int8_t memory_type:5; 59064987Smsmith u_int8_t res15:1; /* N/A */ 59164987Smsmith u_int8_t memory_parity:1; 59264987Smsmith u_int8_t memory_ecc:1; 59364987Smsmith char memory_information[16]; /* N/A */ 59464987Smsmith /* execution memory information */ 59564987Smsmith u_int16_t exmemory_size; 59664987Smsmith u_int16_t l2cache_size; /* N/A */ 59764987Smsmith u_int8_t res16[8]; /* N/A */ 59864987Smsmith u_int16_t exmemory_speed; 59964987Smsmith u_int8_t exmemory_width; 60064987Smsmith u_int8_t exmemory_type:5; 60164987Smsmith u_int8_t res17:1; /* N/A */ 60264987Smsmith u_int8_t exmemory_parity:1; 60364987Smsmith u_int8_t exmemory_ecc:1; 60464987Smsmith char exmemory_name[16]; /* N/A */ 60564987Smsmith /* CPU information */ 60664987Smsmith struct { 60764987Smsmith u_int16_t speed; 60864987Smsmith u_int8_t type; 60964987Smsmith u_int8_t number; 61064987Smsmith u_int8_t res1[12]; /* N/A */ 61164987Smsmith char name[16]; /* N/A */ 612103870Salfred } cpu[2] __packed; 61364987Smsmith /* debugging/profiling/command time tracing information */ 61464987Smsmith u_int16_t profiling_page; /* N/A */ 61564987Smsmith u_int16_t profiling_programs; /* N/A */ 61664987Smsmith u_int16_t time_trace_page; /* N/A */ 61764987Smsmith u_int16_t time_trace_programs; /* N/A */ 61864987Smsmith u_int8_t res18[8]; /* N/A */ 61964987Smsmith /* error counters on physical devices */ 62064987Smsmith u_int16_t physical_device_bus_resets; /* N/A */ 62164987Smsmith u_int16_t physical_device_parity_errors; /* N/A */ 62264987Smsmith u_int16_t physical_device_soft_errors; /* N/A */ 62364987Smsmith u_int16_t physical_device_commands_failed; /* N/A */ 62464987Smsmith u_int16_t physical_device_miscellaneous_errors; /* N/A */ 62564987Smsmith u_int16_t physical_device_command_timeouts; /* N/A */ 62664987Smsmith u_int16_t physical_device_selection_timeouts; /* N/A */ 62764987Smsmith u_int16_t physical_device_retries; /* N/A */ 62864987Smsmith u_int16_t physical_device_aborts; /* N/A */ 62964987Smsmith u_int16_t physical_device_host_command_aborts; /* N/A */ 63064987Smsmith u_int16_t physical_device_PFAs_detected; /* N/A */ 63164987Smsmith u_int16_t physical_device_host_commands_failed; /* N/A */ 63264987Smsmith u_int8_t res19[8]; /* N/A */ 63364987Smsmith /* error counters on logical devices */ 63464987Smsmith u_int16_t logical_device_soft_errors; /* N/A */ 63564987Smsmith u_int16_t logical_device_commands_failed; /* N/A */ 63664987Smsmith u_int16_t logical_device_host_command_aborts; /* N/A */ 63764987Smsmith u_int16_t res20; /* N/A */ 63864987Smsmith /* error counters on controller */ 63964987Smsmith u_int16_t controller_parity_ecc_errors; 64064987Smsmith u_int16_t controller_host_command_aborts; /* N/A */ 64164987Smsmith u_int8_t res21[4]; /* N/A */ 64264987Smsmith /* long duration activity information */ 64364987Smsmith u_int16_t background_inits_active; 64464987Smsmith u_int16_t logical_inits_active; 64564987Smsmith u_int16_t physical_inits_active; 64664987Smsmith u_int16_t consistency_checks_active; 64764987Smsmith u_int16_t rebuilds_active; 64864987Smsmith u_int16_t MORE_active; 64964987Smsmith u_int16_t patrol_active; /* N/A */ 65064987Smsmith u_int8_t long_operation_status; /* N/A */ 65164987Smsmith u_int8_t res22; /* N/A */ 65264987Smsmith /* flash ROM information */ 65364987Smsmith u_int8_t flash_type; /* N/A */ 65464987Smsmith u_int8_t res23; /* N/A */ 65564987Smsmith u_int16_t flash_size; 65664987Smsmith u_int32_t flash_maximum_age; 65764987Smsmith u_int32_t flash_age; 65864987Smsmith u_int8_t res24[4]; /* N/A */ 65964987Smsmith char flash_name[16]; /* N/A */ 66064987Smsmith /* firmware runtime information */ 66164987Smsmith u_int8_t rebuild_rate; 66264987Smsmith u_int8_t background_init_rate; 66364987Smsmith u_int8_t init_rate; 66464987Smsmith u_int8_t consistency_check_rate; 66564987Smsmith u_int8_t res25[4]; /* N/A */ 66664987Smsmith u_int32_t maximum_dp; 66764987Smsmith u_int32_t free_dp; 66864987Smsmith u_int32_t maximum_iop; 66964987Smsmith u_int32_t free_iop; 67064987Smsmith u_int16_t maximum_comb_length; 67164987Smsmith u_int16_t maximum_configuration_groups; 67264987Smsmith u_int8_t installation_abort:1; 67364987Smsmith u_int8_t maintenance:1; 67464987Smsmith u_int8_t res26:6; /* N/A */ 67564987Smsmith u_int8_t res27[3]; /* N/A */ 67664987Smsmith u_int8_t res28[32 + 512]; /* N/A */ 677103870Salfred} __packed; 67864987Smsmith 67964987Smsmith/* 68064987Smsmith * 21.9.2 MDACIOCTL_GETLOGDEVINFOVALID 68164987Smsmith */ 68264987Smsmithstruct mly_ioctl_getlogdevinfovalid { 68364987Smsmith u_int8_t res1; /* N/A */ 68464987Smsmith u_int8_t channel; 68564987Smsmith u_int8_t target; 68664987Smsmith u_int8_t lun; 68764987Smsmith u_int8_t state; /* see 8.1 */ 68864987Smsmith u_int8_t raid_level; /* see 8.2 */ 68964987Smsmith u_int8_t stripe_size; /* see 8.3 */ 69064987Smsmith u_int8_t cache_line_size; /* see 8.4 */ 69164987Smsmith u_int8_t read_write_control; /* see 8.5 */ 69264987Smsmith u_int8_t consistency_check:1; 69364987Smsmith u_int8_t rebuild:1; 69464987Smsmith u_int8_t make_consistent:1; 69564987Smsmith u_int8_t initialisation:1; 69664987Smsmith u_int8_t migration:1; 69764987Smsmith u_int8_t patrol:1; 69864987Smsmith u_int8_t res2:2; /* N/A */ 69964987Smsmith u_int8_t ar5_limit; 70064987Smsmith u_int8_t ar5_algo; 70164987Smsmith u_int16_t logical_device_number; 70264987Smsmith u_int16_t bios_control; 70364987Smsmith /* erorr counters */ 70464987Smsmith u_int16_t soft_errors; /* N/A */ 70564987Smsmith u_int16_t commands_failed; /* N/A */ 70664987Smsmith u_int16_t host_command_aborts; /* N/A */ 70764987Smsmith u_int16_t deferred_write_errors; /* N/A */ 70864987Smsmith u_int8_t res3[8]; /* N/A */ 70964987Smsmith /* device size information */ 71064987Smsmith u_int8_t res4[2]; /* N/A */ 71164987Smsmith u_int16_t device_block_size; 71264987Smsmith u_int32_t original_device_size; /* N/A */ 71364987Smsmith u_int32_t device_size; /* XXX "blocks or MB" Huh? */ 71464987Smsmith u_int8_t res5[4]; /* N/A */ 71564987Smsmith char device_name[32]; /* N/A */ 71664987Smsmith u_int8_t inquiry[36]; 71764987Smsmith u_int8_t res6[12]; /* N/A */ 71864987Smsmith u_int64_t last_read_block; /* N/A */ 71964987Smsmith u_int64_t last_written_block; /* N/A */ 72064987Smsmith u_int64_t consistency_check_block; 72164987Smsmith u_int64_t rebuild_block; 72264987Smsmith u_int64_t make_consistent_block; 72364987Smsmith u_int64_t initialisation_block; 72464987Smsmith u_int64_t migration_block; 72564987Smsmith u_int64_t patrol_block; /* N/A */ 72664987Smsmith u_int8_t res7[64]; /* N/A */ 727103870Salfred} __packed; 72864987Smsmith 72964987Smsmith/* 73064987Smsmith * 21.10.2 MDACIOCTL_GETPHYSDEVINFOVALID: Data Format 73164987Smsmith */ 73264987Smsmithstruct mly_ioctl_getphysdevinfovalid { 73364987Smsmith u_int8_t res1; 73464987Smsmith u_int8_t channel; 73564987Smsmith u_int8_t target; 73664987Smsmith u_int8_t lun; 73764987Smsmith u_int8_t raid_ft:1; /* configuration status */ 73864987Smsmith u_int8_t res2:1; /* N/A */ 73964987Smsmith u_int8_t local:1; 74064987Smsmith u_int8_t res3:5; 74164987Smsmith u_int8_t host_dead:1; /* multiple host/controller status *//* N/A */ 74264987Smsmith u_int8_t host_connection_dead:1; /* N/A */ 74364987Smsmith u_int8_t res4:6; /* N/A */ 74464987Smsmith u_int8_t state; /* see 8.1 */ 74564987Smsmith u_int8_t width; 74664987Smsmith u_int16_t speed; 74764987Smsmith /* multiported physical device information */ 74864987Smsmith u_int8_t ports_available; /* N/A */ 74964987Smsmith u_int8_t ports_inuse; /* N/A */ 75064987Smsmith u_int8_t res5[4]; 75164987Smsmith u_int8_t ether_address[16]; /* N/A */ 75264987Smsmith u_int16_t command_tags; 75364987Smsmith u_int8_t consistency_check:1; /* N/A */ 75464987Smsmith u_int8_t rebuild:1; /* N/A */ 75564987Smsmith u_int8_t make_consistent:1; /* N/A */ 75664987Smsmith u_int8_t initialisation:1; 75764987Smsmith u_int8_t migration:1; /* N/A */ 75864987Smsmith u_int8_t patrol:1; /* N/A */ 75964987Smsmith u_int8_t res6:2; 76064987Smsmith u_int8_t long_operation_status; /* N/A */ 76164987Smsmith u_int8_t parity_errors; 76264987Smsmith u_int8_t soft_errors; 76364987Smsmith u_int8_t hard_errors; 76464987Smsmith u_int8_t miscellaneous_errors; 76564987Smsmith u_int8_t command_timeouts; /* N/A */ 76664987Smsmith u_int8_t retries; /* N/A */ 76764987Smsmith u_int8_t aborts; /* N/A */ 76864987Smsmith u_int8_t PFAs_detected; /* N/A */ 76964987Smsmith u_int8_t res7[6]; 77064987Smsmith u_int16_t block_size; 77164987Smsmith u_int32_t original_device_size; /* XXX "blocks or MB" Huh? */ 77264987Smsmith u_int32_t device_size; /* XXX "blocks or MB" Huh? */ 77364987Smsmith u_int8_t res8[4]; 77464987Smsmith char name[16]; /* N/A */ 77564987Smsmith u_int8_t res9[16 + 32]; 77664987Smsmith u_int8_t inquiry[36]; 77764987Smsmith u_int8_t res10[12 + 16]; 77864987Smsmith u_int64_t last_read_block; /* N/A */ 77964987Smsmith u_int64_t last_written_block; /* N/A */ 78064987Smsmith u_int64_t consistency_check_block; /* N/A */ 78164987Smsmith u_int64_t rebuild_block; /* N/A */ 78264987Smsmith u_int64_t make_consistent_block; /* N/A */ 78364987Smsmith u_int64_t initialisation_block; /* N/A */ 78464987Smsmith u_int64_t migration_block; /* N/A */ 78564987Smsmith u_int64_t patrol_block; /* N/A */ 78664987Smsmith u_int8_t res11[256]; 787103870Salfred} __packed; 78864987Smsmith 78964987Smsmithunion mly_devinfo { 79064987Smsmith struct mly_ioctl_getlogdevinfovalid logdev; 79164987Smsmith struct mly_ioctl_getphysdevinfovalid physdev; 79264987Smsmith}; 79364987Smsmith 79464987Smsmith/* 79564987Smsmith * 21.11.2 MDACIOCTL_GETPHYSDEVSTATISTICS: Data Format 79664987Smsmith * 21.12.2 MDACIOCTL_GETLOGDEVSTATISTICS: Data Format 79764987Smsmith */ 79864987Smsmithstruct mly_ioctl_getdevstatistics { 79964987Smsmith u_int32_t uptime_ms; /* getphysedevstatistics only */ 80064987Smsmith u_int8_t res1[5]; /* N/A */ 80164987Smsmith u_int8_t channel; 80264987Smsmith u_int8_t target; 80364987Smsmith u_int8_t lun; 80464987Smsmith u_int16_t raid_device; /* getlogdevstatistics only */ 80564987Smsmith u_int8_t res2[2]; /* N/A */ 80664987Smsmith /* total read/write performance including cache data */ 80764987Smsmith u_int32_t total_reads; 80864987Smsmith u_int32_t total_writes; 80964987Smsmith u_int32_t total_read_size; 81064987Smsmith u_int32_t total_write_size; 81164987Smsmith /* cache read/write performance */ 81264987Smsmith u_int32_t cache_reads; /* N/A */ 81364987Smsmith u_int32_t cache_writes; /* N/A */ 81464987Smsmith u_int32_t cache_read_size; /* N/A */ 81564987Smsmith u_int32_t cache_write_size; /* N/A */ 81664987Smsmith /* commands active/wait information */ 81764987Smsmith u_int32_t command_waits_done; /* N/A */ 81864987Smsmith u_int16_t active_commands; /* N/A */ 81964987Smsmith u_int16_t waiting_commands; /* N/A */ 82064987Smsmith u_int8_t res3[8]; /* N/A */ 821103870Salfred} __packed; 82264987Smsmith 82364987Smsmith/* 82464987Smsmith * 21.13.2 MDACIOCTL_GETCONTROLLERSTATISTICS: Data Format 82564987Smsmith */ 82664987Smsmithstruct mly_ioctl_getcontrollerstatistics { 82764987Smsmith u_int32_t uptime_ms; /* N/A */ 82864987Smsmith u_int8_t res1[12]; /* N/A */ 82964987Smsmith /* target physical device performance data information */ 83064987Smsmith u_int32_t target_physical_device_interrupts; /* N/A */ 83164987Smsmith u_int32_t target_physical_device_stray_interrupts; /* N/A */ 83264987Smsmith u_int8_t res2[8]; /* N/A */ 83364987Smsmith u_int32_t target_physical_device_reads; /* N/A */ 83464987Smsmith u_int32_t target_physical_device_writes; /* N/A */ 83564987Smsmith u_int32_t target_physical_device_read_size; /* N/A */ 83664987Smsmith u_int32_t target_physical_device_write_size; /* N/A */ 83764987Smsmith /* host system performance data information */ 83864987Smsmith u_int32_t host_system_interrupts; /* N/A */ 83964987Smsmith u_int32_t host_system_stray_interrupts; /* N/A */ 84064987Smsmith u_int32_t host_system_sent_interrupts; /* N/A */ 84164987Smsmith u_int8_t res3[4]; /* N/A */ 84264987Smsmith u_int32_t physical_device_reads; /* N/A */ 84364987Smsmith u_int32_t physical_device_writes; /* N/A */ 84464987Smsmith u_int32_t physical_device_read_size; /* N/A */ 84564987Smsmith u_int32_t physical_device_write_size; /* N/A */ 84664987Smsmith u_int32_t physical_device_cache_reads; /* N/A */ 84764987Smsmith u_int32_t physical_device_cache_writes; /* N/A */ 84864987Smsmith u_int32_t physical_device_cache_read_size; /* N/A */ 84964987Smsmith u_int32_t physical_device_cache_write_size; /* N/A */ 85064987Smsmith u_int32_t logical_device_reads; /* N/A */ 85164987Smsmith u_int32_t logical_device_writes; /* N/A */ 85264987Smsmith u_int32_t logical_device_read_size; /* N/A */ 85364987Smsmith u_int32_t logical_device_write_size; /* N/A */ 85464987Smsmith u_int32_t logical_device_cache_reads; /* N/A */ 85564987Smsmith u_int32_t logical_device_cache_writes; /* N/A */ 85664987Smsmith u_int32_t logical_device_cache_read_size; /* N/A */ 85764987Smsmith u_int32_t logical_device_cache_write_size; /* N/A */ 85864987Smsmith u_int16_t target_physical_device_commands_active; /* N/A */ 85964987Smsmith u_int16_t target_physical_device_commands_waiting; /* N/A */ 86064987Smsmith u_int16_t host_system_commands_active; /* N/A */ 86164987Smsmith u_int16_t host_system_commands_waiting; /* N/A */ 86264987Smsmith u_int8_t res4[48 + 64]; /* N/A */ 863103870Salfred} __packed; 86464987Smsmith 86564987Smsmith/* 86664987Smsmith * 21.2 MDACIOCTL_SETRAIDDEVSTATE 86764987Smsmith */ 86864987Smsmithstruct mly_ioctl_param_setraiddevstate { 86964987Smsmith u_int8_t state; 870103870Salfred} __packed; 87164987Smsmith 87264987Smsmith/* 87364987Smsmith * 21.27.2 MDACIOCTL_GETBDT_FOR_SYSDRIVE: Data Format 87464987Smsmith */ 87564987Smsmith#define MLY_MAX_BDT_ENTRIES 1022 87664987Smsmithstruct mly_ioctl_getbdt_for_sysdrive { 87764987Smsmith u_int32_t num_of_bdt_entries; 87864987Smsmith u_int32_t bad_data_block_address[MLY_MAX_BDT_ENTRIES]; 879103870Salfred} __packed; 88064987Smsmith 88164987Smsmith/* 88264987Smsmith * 22.1 Physical Device Definition (PDD) 88364987Smsmith */ 88464987Smsmithstruct mly_pdd { 88564987Smsmith u_int8_t type; /* see 8.2 */ 88664987Smsmith u_int8_t state; /* see 8.1 */ 88764987Smsmith u_int16_t raid_device; 88864987Smsmith u_int32_t device_size; /* XXX "block or MB" Huh? */ 88964987Smsmith u_int8_t controller; 89064987Smsmith u_int8_t channel; 89164987Smsmith u_int8_t target; 89264987Smsmith u_int8_t lun; 89364987Smsmith u_int32_t start_address; 894103870Salfred} __packed; 89564987Smsmith 89664987Smsmith/* 89764987Smsmith * 22.2 RAID Device Use Definition (UDD) 89864987Smsmith */ 89964987Smsmithstruct mly_udd { 90064987Smsmith u_int8_t res1; 90164987Smsmith u_int8_t state; /* see 8.1 */ 90264987Smsmith u_int16_t raid_device; 90364987Smsmith u_int32_t start_address; 904103870Salfred} __packed; 90564987Smsmith 90664987Smsmith/* 90764987Smsmith * RAID Device Definition (LDD) 90864987Smsmith */ 90964987Smsmithstruct mly_ldd { 91064987Smsmith u_int8_t type; /* see 8.2 */ 91164987Smsmith u_int8_t state; /* see 8.1 */ 91264987Smsmith u_int16_t raid_device; 91364987Smsmith u_int32_t device_size; /* XXX "block or MB" Huh? */ 91464987Smsmith u_int8_t devices_used_count; 91564987Smsmith u_int8_t stripe_size; /* see 8.3 */ 91664987Smsmith u_int8_t cache_line_size; /* see 8.4 */ 91764987Smsmith u_int8_t read_write_control; /* see 8.5 */ 91864987Smsmith u_int32_t devices_used_size; /* XXX "block or MB" Huh? */ 91964987Smsmith u_int16_t devices_used[32]; /* XXX actual size of this field unknown! */ 920103870Salfred} __packed; 92164987Smsmith 92264987Smsmith/* 92364987Smsmith * Define a datastructure giving the smallest allocation that will hold 92464987Smsmith * a PDD, UDD or LDD for MDACIOCTL_GETDEVCONFINFO. 92564987Smsmith */ 92664987Smsmithstruct mly_devconf_hdr { 92764987Smsmith u_int8_t type; /* see 8.2 */ 92864987Smsmith u_int8_t state; /* see 8.1 */ 92964987Smsmith u_int16_t raid_device; 93064987Smsmith}; 93164987Smsmith 93264987Smsmithunion mly_ioctl_devconfinfo { 93364987Smsmith struct mly_pdd pdd; 93464987Smsmith struct mly_udd udd; 93564987Smsmith struct mly_ldd ldd; 93664987Smsmith struct mly_devconf_hdr hdr; 93764987Smsmith}; 93864987Smsmith 93964987Smsmith/* 94064987Smsmith * 22.3 MDACIOCTL_RENAMERAIDDEV 94164987Smsmith * 94264987Smsmith * XXX this command is listed as transferring data, but does not define the data. 94364987Smsmith */ 94464987Smsmithstruct mly_ioctl_param_renameraiddev { 94564987Smsmith u_int8_t new_raid_device; 946103870Salfred} __packed; 94764987Smsmith 94864987Smsmith/* 94964987Smsmith * 23.6.2 MDACIOCTL_XLATEPHYSDEVTORAIDDEV 95064987Smsmith * 95164987Smsmith * XXX documentation suggests this format will change 95264987Smsmith */ 95364987Smsmithstruct mly_ioctl_param_xlatephysdevtoraiddev { 95464987Smsmith u_int16_t raid_device; 95564987Smsmith u_int8_t res1[2]; 95664987Smsmith u_int8_t controller; 95764987Smsmith u_int8_t channel; 95864987Smsmith u_int8_t target; 95964987Smsmith u_int8_t lun; 960103870Salfred} __packed; 96164987Smsmith 96264987Smsmith/* 96364987Smsmith * 23.7 MDACIOCTL_GETGROUPCONFINFO 96464987Smsmith */ 96564987Smsmithstruct mly_ioctl_param_getgroupconfinfo { 96664987Smsmith u_int16_t group; 96764987Smsmith u_int8_t res1[8]; 96864987Smsmith union mly_command_transfer transfer; 969103870Salfred} __packed; 97064987Smsmith 97164987Smsmith/* 97264987Smsmith * 23.9.2 MDACIOCTL_GETFREESPACELIST: Data Format 97364987Smsmith * 97464987Smsmith * The controller will populate as much of this structure as is provided, 97564987Smsmith * or as is required to fully list the free space available. 97664987Smsmith */ 97764987Smsmithstruct mly_ioctl_getfreespacelist_entry { 97864987Smsmith u_int16_t raid_device; 97964987Smsmith u_int8_t res1[6]; 98064987Smsmith u_int32_t address; /* XXX "blocks or MB" Huh? */ 98164987Smsmith u_int32_t size; /* XXX "blocks or MB" Huh? */ 982103870Salfred} __packed; 98364987Smsmith 98464987Smsmithstruct mly_ioctl_getfrespacelist { 98564987Smsmith u_int16_t returned_entries; 98664987Smsmith u_int16_t total_entries; 98764987Smsmith u_int8_t res1[12]; 98864987Smsmith struct mly_ioctl_getfreespacelist_entry space[0]; /* expand to suit */ 989103870Salfred} __packed; 99064987Smsmith 99164987Smsmith/* 99264987Smsmith * 27.1 MDACIOCTL_GETSUBSYSTEMDATA 99364987Smsmith * 27.2 MDACIOCTL_SETSUBSYSTEMDATA 99464987Smsmith * 99564987Smsmith * PCI controller only supports a limited subset of the possible operations. 99664987Smsmith * 99764987Smsmith * XXX where does the status end up? (the command transfers no data) 99864987Smsmith */ 99964987Smsmithstruct mly_ioctl_param_subsystemdata { 100064987Smsmith u_int8_t operation:4; 100164987Smsmith#define MLY_BBU_GETSTATUS 0x00 100264987Smsmith#define MLY_BBU_SET_THRESHOLD 0x00 /* minutes in param[0,1] */ 100364987Smsmith u_int8_t subsystem:4; 100464987Smsmith#define MLY_SUBSYSTEM_BBU 0x01 100564987Smsmith u_int parameter[3]; /* only for SETSUBSYSTEMDATA */ 1006103870Salfred} __packed; 100764987Smsmith 100864987Smsmithstruct mly_ioctl_getsubsystemdata_bbustatus { 100964987Smsmith u_int16_t current_power; 101064987Smsmith u_int16_t maximum_power; 101164987Smsmith u_int16_t power_threshold; 101264987Smsmith u_int8_t charge_level; 101364987Smsmith u_int8_t hardware_version; 101464987Smsmith u_int8_t battery_type; 101564987Smsmith#define MLY_BBU_TYPE_UNKNOWN 0x00 101664987Smsmith#define MLY_BBU_TYPE_NICAD 0x01 101764987Smsmith#define MLY_BBU_TYPE_MISSING 0xfe 101864987Smsmith u_int8_t res1; 101964987Smsmith u_int8_t operation_status; 102064987Smsmith#define MLY_BBU_STATUS_NO_SYNC 0x01 102164987Smsmith#define MLY_BBU_STATUS_OUT_OF_SYNC 0x02 102264987Smsmith#define MLY_BBU_STATUS_FIRST_WARNING 0x04 102364987Smsmith#define MLY_BBU_STATUS_SECOND_WARNING 0x08 102464987Smsmith#define MLY_BBU_STATUS_RECONDITIONING 0x10 102564987Smsmith#define MLY_BBU_STATUS_DISCHARGING 0x20 102664987Smsmith#define MLY_BBU_STATUS_FASTCHARGING 0x40 102764987Smsmith u_int8_t res2; 1028103870Salfred} __packed; 102964987Smsmith 103064987Smsmith/* 103164987Smsmith * 28.9 MDACIOCTL_RESETDEVICE 103264987Smsmith * 28.10 MDACIOCTL_FLUSHDEVICEDATA 103364987Smsmith * 28.11 MDACIOCTL_PAUSEDEVICE 103464987Smsmith * 28.12 MDACIOCTL_UNPAUSEDEVICE 103564987Smsmith */ 103664987Smsmithstruct mly_ioctl_param_deviceoperation { 103764987Smsmith u_int8_t operation_device; /* see 14.3 */ 1038103870Salfred} __packed; 103964987Smsmith 104064987Smsmith/* 104164987Smsmith * 31.1 Event Data Format 104264987Smsmith */ 104364987Smsmithstruct mly_event { 104464987Smsmith u_int32_t sequence_number; 104564987Smsmith u_int32_t timestamp; 104664987Smsmith u_int32_t code; 104764987Smsmith u_int8_t controller; 104864987Smsmith u_int8_t channel; 104964987Smsmith u_int8_t target; /* also enclosure */ 105064987Smsmith u_int8_t lun; /* also enclosure unit */ 105164987Smsmith u_int8_t res1[4]; 105264987Smsmith u_int32_t param; 105364987Smsmith u_int8_t sense[40]; 1054103870Salfred} __packed; 105564987Smsmith 105664987Smsmith/* 105764987Smsmith * 31.2 MDACIOCTL_GETEVENT 105864987Smsmith */ 105964987Smsmithstruct mly_ioctl_param_getevent { 106064987Smsmith u_int16_t sequence_number_low; 106164987Smsmith u_int8_t res1[8]; 106264987Smsmith union mly_command_transfer transfer; 1063103870Salfred} __packed; 106464987Smsmith 106564987Smsmithunion mly_ioctl_param { 106664987Smsmith struct mly_ioctl_param_data data; 106764987Smsmith struct mly_ioctl_param_setmemorymailbox setmemorymailbox; 106864987Smsmith struct mly_ioctl_param_setraiddevstate setraiddevstate; 106964987Smsmith struct mly_ioctl_param_renameraiddev renameraiddev; 107064987Smsmith struct mly_ioctl_param_xlatephysdevtoraiddev xlatephysdevtoraiddev; 107164987Smsmith struct mly_ioctl_param_getgroupconfinfo getgroupconfinfo; 107264987Smsmith struct mly_ioctl_param_subsystemdata subsystemdata; 107364987Smsmith struct mly_ioctl_param_deviceoperation deviceoperation; 107464987Smsmith struct mly_ioctl_param_getevent getevent; 107564987Smsmith}; 107664987Smsmith 107764987Smsmith/* 107864987Smsmith * 19 SCSI Command Format 107964987Smsmith */ 108064987Smsmithstruct mly_command_address_physical { 108164987Smsmith u_int8_t lun; 108264987Smsmith u_int8_t target; 108364987Smsmith u_int8_t channel:3; 108464987Smsmith u_int8_t controller:5; 1085103870Salfred} __packed; 108664987Smsmith 108764987Smsmithstruct mly_command_address_logical { 108864987Smsmith u_int16_t logdev; 108964987Smsmith u_int8_t res1:3; 109064987Smsmith u_int8_t controller:5; 1091103870Salfred} __packed; 109264987Smsmith 109364987Smsmithunion mly_command_address { 109464987Smsmith struct mly_command_address_physical phys; 109564987Smsmith struct mly_command_address_logical log; 109664987Smsmith}; 109764987Smsmith 109864987Smsmithstruct mly_command_generic { 109964987Smsmith u_int16_t command_id; 110064987Smsmith u_int8_t opcode; 110164987Smsmith struct mly_command_control command_control; 110264987Smsmith u_int32_t data_size; 110364987Smsmith u_int64_t sense_buffer_address; 110464987Smsmith union mly_command_address addr; 110564987Smsmith struct mly_timeout timeout; 110664987Smsmith u_int8_t maximum_sense_size; 110764987Smsmith u_int8_t res1[11]; 110864987Smsmith union mly_command_transfer transfer; 1109103870Salfred} __packed; 111064987Smsmith 111164987Smsmith 111264987Smsmith/* 111364987Smsmith * 19.1 MDACMD_SCSI & MDACMD_SCSIPT 111464987Smsmith */ 111564987Smsmith#define MLY_CMD_SCSI_SMALL_CDB 10 111664987Smsmithstruct mly_command_scsi_small { 111764987Smsmith u_int16_t command_id; 111864987Smsmith u_int8_t opcode; 111964987Smsmith struct mly_command_control command_control; 112064987Smsmith u_int32_t data_size; 112164987Smsmith u_int64_t sense_buffer_address; 112264987Smsmith union mly_command_address addr; 112364987Smsmith struct mly_timeout timeout; 112464987Smsmith u_int8_t maximum_sense_size; 112564987Smsmith u_int8_t cdb_length; 112664987Smsmith u_int8_t cdb[MLY_CMD_SCSI_SMALL_CDB]; 112764987Smsmith union mly_command_transfer transfer; 1128103870Salfred} __packed; 112964987Smsmith 113064987Smsmith/* 113164987Smsmith * 19.2 MDACMD_SCSILC & MDACMD_SCSILCPT 113264987Smsmith */ 113364987Smsmithstruct mly_command_scsi_large { 113464987Smsmith u_int16_t command_id; 113564987Smsmith u_int8_t opcode; 113664987Smsmith struct mly_command_control command_control; 113764987Smsmith u_int32_t data_size; 113864987Smsmith u_int64_t sense_buffer_address; 113964987Smsmith union mly_command_address addr; 114064987Smsmith struct mly_timeout timeout; 114164987Smsmith u_int8_t maximum_sense_size; 114264987Smsmith u_int8_t cdb_length; 114364987Smsmith u_int16_t res1; 114464987Smsmith u_int64_t cdb_physaddr; 114564987Smsmith union mly_command_transfer transfer; 1146103870Salfred} __packed; 114764987Smsmith 114864987Smsmith/* 114964987Smsmith * 20.1 IOCTL Command Format: Internal Bus 115064987Smsmith */ 115164987Smsmithstruct mly_command_ioctl { 115264987Smsmith u_int16_t command_id; 115364987Smsmith u_int8_t opcode; 115464987Smsmith struct mly_command_control command_control; 115564987Smsmith u_int32_t data_size; 115664987Smsmith u_int64_t sense_buffer_address; 115764987Smsmith union mly_command_address addr; 115864987Smsmith struct mly_timeout timeout; 115964987Smsmith u_int8_t maximum_sense_size; 116064987Smsmith u_int8_t sub_ioctl; 116164987Smsmith union mly_ioctl_param param; 1162103870Salfred} __packed; 116364987Smsmith 116464987Smsmith/* 116564987Smsmith * PG6: 8.2.2 116664987Smsmith */ 116764987Smsmithstruct mly_command_mmbox { 116864987Smsmith u_int32_t flag; 116964987Smsmith u_int8_t data[60]; 1170103870Salfred} __packed; 117164987Smsmith 117264987Smsmithunion mly_command_packet { 117364987Smsmith struct mly_command_generic generic; 117464987Smsmith struct mly_command_scsi_small scsi_small; 117564987Smsmith struct mly_command_scsi_large scsi_large; 117664987Smsmith struct mly_command_ioctl ioctl; 117764987Smsmith struct mly_command_mmbox mmbox; 117864987Smsmith}; 117964987Smsmith 118064987Smsmith/* 118164987Smsmith * PG6: 5.3 118264987Smsmith */ 118364987Smsmith#define MLY_I960RX_COMMAND_MAILBOX 0x10 118464987Smsmith#define MLY_I960RX_STATUS_MAILBOX 0x18 118564987Smsmith#define MLY_I960RX_IDBR 0x20 118664987Smsmith#define MLY_I960RX_ODBR 0x2c 118764987Smsmith#define MLY_I960RX_ERROR_STATUS 0x2e 118864987Smsmith#define MLY_I960RX_INTERRUPT_STATUS 0x30 118964987Smsmith#define MLY_I960RX_INTERRUPT_MASK 0x34 119064987Smsmith 119164987Smsmith#define MLY_STRONGARM_COMMAND_MAILBOX 0x50 119264987Smsmith#define MLY_STRONGARM_STATUS_MAILBOX 0x58 119364987Smsmith#define MLY_STRONGARM_IDBR 0x60 119464987Smsmith#define MLY_STRONGARM_ODBR 0x61 119564987Smsmith#define MLY_STRONGARM_ERROR_STATUS 0x63 119664987Smsmith#define MLY_STRONGARM_INTERRUPT_STATUS 0x30 119764987Smsmith#define MLY_STRONGARM_INTERRUPT_MASK 0x34 119864987Smsmith 119964987Smsmith/* 120064987Smsmith * PG6: 5.4.3 Doorbell 0 120164987Smsmith */ 120264987Smsmith#define MLY_HM_CMDSENT (1<<0) 120364987Smsmith#define MLY_HM_STSACK (1<<1) 120464987Smsmith#define MLY_SOFT_RST (1<<3) 120564987Smsmith#define MLY_AM_CMDSENT (1<<4) 120664987Smsmith 120764987Smsmith/* 120864987Smsmith * PG6: 5.4.4 Doorbell 1 120964987Smsmith * 121064987Smsmith * Note that the documentation claims that these bits are set when the 121164987Smsmith * status queue(s) are empty, wheras the Linux driver and experience 121264987Smsmith * suggest they are set when there is status available. 121364987Smsmith */ 121464987Smsmith#define MLY_HM_STSREADY (1<<0) 121564987Smsmith#define MLY_AM_STSREADY (1<<1) 121664987Smsmith 121764987Smsmith/* 121864987Smsmith * PG6: 5.4.6 Doorbell 3 121964987Smsmith */ 122064987Smsmith#define MLY_MSG_EMPTY (1<<3) 122164987Smsmith#define MLY_MSG_SPINUP 0x08 122264987Smsmith#define MLY_MSG_RACE_RECOVERY_FAIL 0x60 122364987Smsmith#define MLY_MSG_RACE_IN_PROGRESS 0x70 122464987Smsmith#define MLY_MSG_RACE_ON_CRITICAL 0xb0 122564987Smsmith#define MLY_MSG_PARITY_ERROR 0xf0 122664987Smsmith 122764987Smsmith/* 122864987Smsmith * PG6: 5.4.8 Outbound Interrupt Mask 122964987Smsmith */ 123064987Smsmith#define MLY_INTERRUPT_MASK_DISABLE 0xff 123164987Smsmith#define MLY_INTERRUPT_MASK_ENABLE (0xff & ~(1<<2)) 123264987Smsmith 123364987Smsmith/* 123464987Smsmith * PG6: 8.2 Advanced Mailbox Scheme 123564987Smsmith * 123664987Smsmith * Note that this must be allocated on a 4k boundary, and all internal 123764987Smsmith * fields must also reside on a 4k boundary. 123864987Smsmith * We could dynamically size this structure, but the extra effort 123964987Smsmith * is probably unjustified. Note that these buffers do not need to be 124064987Smsmith * adjacent - we just group them to simplify allocation of the bus-visible 124164987Smsmith * buffer. 124264987Smsmith * 124364987Smsmith * XXX Note that for some reason, if MLY_MMBOX_COMMANDS is > 64, the controller 124464987Smsmith * fails to respond to the command at (MLY_MMBOX_COMMANDS - 64). It's not 124564987Smsmith * wrapping to 0 at this point (determined by experimentation). This is not 124664987Smsmith * consistent with the Linux driver's implementation. 124764987Smsmith * Whilst it's handy to have lots of room for status returns in case we end up 124864987Smsmith * being slow getting back to completed commands, it seems unlikely that we 124964987Smsmith * would get 64 commands ahead of the controller on the submissions side, so 125064987Smsmith * the current workaround is to simply limit the command ring to 64 entries. 125164987Smsmith */ 125264987Smsmithunion mly_status_packet { 125364987Smsmith struct mly_status status; 125464987Smsmith struct { 125564987Smsmith u_int32_t flag; 125664987Smsmith u_int8_t data[4]; 1257103870Salfred } __packed mmbox; 125864987Smsmith}; 125964987Smsmithunion mly_health_region { 126064987Smsmith struct mly_health_status status; 126164987Smsmith u_int8_t pad[1024]; 126264987Smsmith}; 126364987Smsmith 126464987Smsmith#define MLY_MMBOX_COMMANDS 64 126564987Smsmith#define MLY_MMBOX_STATUS 512 126664987Smsmithstruct mly_mmbox { 126764987Smsmith union mly_command_packet mmm_command[MLY_MMBOX_COMMANDS]; 126864987Smsmith union mly_status_packet mmm_status[MLY_MMBOX_STATUS]; 126964987Smsmith union mly_health_region mmm_health; 1270103870Salfred} __packed; 1271