mlx5_eq.c revision 292196
1/*- 2 * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 * $FreeBSD: stable/10/sys/dev/mlx5/mlx5_core/mlx5_eq.c 292196 2015-12-14 10:31:03Z hselasky $ 26 */ 27 28#include <linux/interrupt.h> 29#include <linux/module.h> 30#include <dev/mlx5/driver.h> 31#include <dev/mlx5/mlx5_ifc.h> 32#include "mlx5_core.h" 33 34#if (__FreeBSD_version >= 1100000) 35#include "opt_rss.h" 36#endif 37 38#ifdef RSS 39#include <net/rss_config.h> 40#include <netinet/in_rss.h> 41#endif 42 43enum { 44 MLX5_EQE_SIZE = sizeof(struct mlx5_eqe), 45 MLX5_EQE_OWNER_INIT_VAL = 0x1, 46}; 47 48enum { 49 MLX5_NUM_SPARE_EQE = 0x80, 50 MLX5_NUM_ASYNC_EQE = 0x100, 51 MLX5_NUM_CMD_EQE = 32, 52}; 53 54enum { 55 MLX5_EQ_DOORBEL_OFFSET = 0x40, 56}; 57 58#define MLX5_ASYNC_EVENT_MASK ((1ull << MLX5_EVENT_TYPE_PATH_MIG) | \ 59 (1ull << MLX5_EVENT_TYPE_COMM_EST) | \ 60 (1ull << MLX5_EVENT_TYPE_SQ_DRAINED) | \ 61 (1ull << MLX5_EVENT_TYPE_CQ_ERROR) | \ 62 (1ull << MLX5_EVENT_TYPE_WQ_CATAS_ERROR) | \ 63 (1ull << MLX5_EVENT_TYPE_PATH_MIG_FAILED) | \ 64 (1ull << MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR) | \ 65 (1ull << MLX5_EVENT_TYPE_WQ_ACCESS_ERROR) | \ 66 (1ull << MLX5_EVENT_TYPE_PORT_CHANGE) | \ 67 (1ull << MLX5_EVENT_TYPE_SRQ_CATAS_ERROR) | \ 68 (1ull << MLX5_EVENT_TYPE_SRQ_LAST_WQE) | \ 69 (1ull << MLX5_EVENT_TYPE_SRQ_RQ_LIMIT)) 70 71struct map_eq_in { 72 u64 mask; 73 u32 reserved; 74 u32 unmap_eqn; 75}; 76 77struct cre_des_eq { 78 u8 reserved[15]; 79 u8 eqn; 80}; 81 82/*Function prototype*/ 83static void mlx5_port_module_event(struct mlx5_core_dev *dev, 84 struct mlx5_eqe *eqe); 85 86static int mlx5_cmd_destroy_eq(struct mlx5_core_dev *dev, u8 eqn) 87{ 88 u32 in[MLX5_ST_SZ_DW(destroy_eq_in)]; 89 u32 out[MLX5_ST_SZ_DW(destroy_eq_out)]; 90 91 memset(in, 0, sizeof(in)); 92 93 MLX5_SET(destroy_eq_in, in, opcode, MLX5_CMD_OP_DESTROY_EQ); 94 MLX5_SET(destroy_eq_in, in, eq_number, eqn); 95 96 memset(out, 0, sizeof(out)); 97 return mlx5_cmd_exec_check_status(dev, in, sizeof(in), 98 out, sizeof(out)); 99} 100 101static struct mlx5_eqe *get_eqe(struct mlx5_eq *eq, u32 entry) 102{ 103 return mlx5_buf_offset(&eq->buf, entry * MLX5_EQE_SIZE); 104} 105 106static struct mlx5_eqe *next_eqe_sw(struct mlx5_eq *eq) 107{ 108 struct mlx5_eqe *eqe = get_eqe(eq, eq->cons_index & (eq->nent - 1)); 109 110 return ((eqe->owner & 1) ^ !!(eq->cons_index & eq->nent)) ? NULL : eqe; 111} 112 113static const char *eqe_type_str(u8 type) 114{ 115 switch (type) { 116 case MLX5_EVENT_TYPE_COMP: 117 return "MLX5_EVENT_TYPE_COMP"; 118 case MLX5_EVENT_TYPE_PATH_MIG: 119 return "MLX5_EVENT_TYPE_PATH_MIG"; 120 case MLX5_EVENT_TYPE_COMM_EST: 121 return "MLX5_EVENT_TYPE_COMM_EST"; 122 case MLX5_EVENT_TYPE_SQ_DRAINED: 123 return "MLX5_EVENT_TYPE_SQ_DRAINED"; 124 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 125 return "MLX5_EVENT_TYPE_SRQ_LAST_WQE"; 126 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT: 127 return "MLX5_EVENT_TYPE_SRQ_RQ_LIMIT"; 128 case MLX5_EVENT_TYPE_CQ_ERROR: 129 return "MLX5_EVENT_TYPE_CQ_ERROR"; 130 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 131 return "MLX5_EVENT_TYPE_WQ_CATAS_ERROR"; 132 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 133 return "MLX5_EVENT_TYPE_PATH_MIG_FAILED"; 134 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 135 return "MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR"; 136 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 137 return "MLX5_EVENT_TYPE_WQ_ACCESS_ERROR"; 138 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR: 139 return "MLX5_EVENT_TYPE_SRQ_CATAS_ERROR"; 140 case MLX5_EVENT_TYPE_INTERNAL_ERROR: 141 return "MLX5_EVENT_TYPE_INTERNAL_ERROR"; 142 case MLX5_EVENT_TYPE_PORT_CHANGE: 143 return "MLX5_EVENT_TYPE_PORT_CHANGE"; 144 case MLX5_EVENT_TYPE_GPIO_EVENT: 145 return "MLX5_EVENT_TYPE_GPIO_EVENT"; 146 case MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT: 147 return "MLX5_EVENT_TYPE_PORT_MODULE_EVENT"; 148 case MLX5_EVENT_TYPE_REMOTE_CONFIG: 149 return "MLX5_EVENT_TYPE_REMOTE_CONFIG"; 150 case MLX5_EVENT_TYPE_DB_BF_CONGESTION: 151 return "MLX5_EVENT_TYPE_DB_BF_CONGESTION"; 152 case MLX5_EVENT_TYPE_STALL_EVENT: 153 return "MLX5_EVENT_TYPE_STALL_EVENT"; 154 case MLX5_EVENT_TYPE_CMD: 155 return "MLX5_EVENT_TYPE_CMD"; 156 case MLX5_EVENT_TYPE_PAGE_REQUEST: 157 return "MLX5_EVENT_TYPE_PAGE_REQUEST"; 158 case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE: 159 return "MLX5_EVENT_TYPE_NIC_VPORT_CHANGE"; 160 default: 161 return "Unrecognized event"; 162 } 163} 164 165static enum mlx5_dev_event port_subtype_event(u8 subtype) 166{ 167 switch (subtype) { 168 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 169 return MLX5_DEV_EVENT_PORT_DOWN; 170 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 171 return MLX5_DEV_EVENT_PORT_UP; 172 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 173 return MLX5_DEV_EVENT_PORT_INITIALIZED; 174 case MLX5_PORT_CHANGE_SUBTYPE_LID: 175 return MLX5_DEV_EVENT_LID_CHANGE; 176 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 177 return MLX5_DEV_EVENT_PKEY_CHANGE; 178 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 179 return MLX5_DEV_EVENT_GUID_CHANGE; 180 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 181 return MLX5_DEV_EVENT_CLIENT_REREG; 182 } 183 return -1; 184} 185 186static void eq_update_ci(struct mlx5_eq *eq, int arm) 187{ 188 __be32 __iomem *addr = eq->doorbell + (arm ? 0 : 2); 189 u32 val = (eq->cons_index & 0xffffff) | (eq->eqn << 24); 190 __raw_writel((__force u32) cpu_to_be32(val), addr); 191 /* We still want ordering, just not swabbing, so add a barrier */ 192 mb(); 193} 194 195static int mlx5_eq_int(struct mlx5_core_dev *dev, struct mlx5_eq *eq) 196{ 197 struct mlx5_eqe *eqe; 198 int eqes_found = 0; 199 int set_ci = 0; 200 u32 cqn; 201 u32 rsn; 202 u8 port; 203 204 while ((eqe = next_eqe_sw(eq))) { 205 /* 206 * Make sure we read EQ entry contents after we've 207 * checked the ownership bit. 208 */ 209 rmb(); 210 211 mlx5_core_dbg(eq->dev, "eqn %d, eqe type %s\n", 212 eq->eqn, eqe_type_str(eqe->type)); 213 switch (eqe->type) { 214 case MLX5_EVENT_TYPE_COMP: 215 cqn = be32_to_cpu(eqe->data.comp.cqn) & 0xffffff; 216 mlx5_cq_completion(dev, cqn); 217 break; 218 219 case MLX5_EVENT_TYPE_PATH_MIG: 220 case MLX5_EVENT_TYPE_COMM_EST: 221 case MLX5_EVENT_TYPE_SQ_DRAINED: 222 case MLX5_EVENT_TYPE_SRQ_LAST_WQE: 223 case MLX5_EVENT_TYPE_WQ_CATAS_ERROR: 224 case MLX5_EVENT_TYPE_PATH_MIG_FAILED: 225 case MLX5_EVENT_TYPE_WQ_INVAL_REQ_ERROR: 226 case MLX5_EVENT_TYPE_WQ_ACCESS_ERROR: 227 rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff; 228 mlx5_core_dbg(dev, "event %s(%d) arrived on resource 0x%x\n", 229 eqe_type_str(eqe->type), eqe->type, rsn); 230 mlx5_rsc_event(dev, rsn, eqe->type); 231 break; 232 233 case MLX5_EVENT_TYPE_SRQ_RQ_LIMIT: 234 case MLX5_EVENT_TYPE_SRQ_CATAS_ERROR: 235 rsn = be32_to_cpu(eqe->data.qp_srq.qp_srq_n) & 0xffffff; 236 mlx5_core_dbg(dev, "SRQ event %s(%d): srqn 0x%x\n", 237 eqe_type_str(eqe->type), eqe->type, rsn); 238 mlx5_srq_event(dev, rsn, eqe->type); 239 break; 240 241 case MLX5_EVENT_TYPE_CMD: 242 mlx5_cmd_comp_handler(dev, be32_to_cpu(eqe->data.cmd.vector)); 243 break; 244 245 case MLX5_EVENT_TYPE_PORT_CHANGE: 246 port = (eqe->data.port.port >> 4) & 0xf; 247 switch (eqe->sub_type) { 248 case MLX5_PORT_CHANGE_SUBTYPE_DOWN: 249 case MLX5_PORT_CHANGE_SUBTYPE_ACTIVE: 250 case MLX5_PORT_CHANGE_SUBTYPE_LID: 251 case MLX5_PORT_CHANGE_SUBTYPE_PKEY: 252 case MLX5_PORT_CHANGE_SUBTYPE_GUID: 253 case MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG: 254 case MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED: 255 if (dev->event) 256 dev->event(dev, port_subtype_event(eqe->sub_type), 257 (unsigned long)port); 258 break; 259 default: 260 mlx5_core_warn(dev, "Port event with unrecognized subtype: port %d, sub_type %d\n", 261 port, eqe->sub_type); 262 } 263 break; 264 case MLX5_EVENT_TYPE_CQ_ERROR: 265 cqn = be32_to_cpu(eqe->data.cq_err.cqn) & 0xffffff; 266 mlx5_core_warn(dev, "CQ error on CQN 0x%x, syndrom 0x%x\n", 267 cqn, eqe->data.cq_err.syndrome); 268 mlx5_cq_event(dev, cqn, eqe->type); 269 break; 270 271 case MLX5_EVENT_TYPE_PAGE_REQUEST: 272 { 273 u16 func_id = be16_to_cpu(eqe->data.req_pages.func_id); 274 s32 npages = be32_to_cpu(eqe->data.req_pages.num_pages); 275 276 mlx5_core_dbg(dev, "page request for func 0x%x, npages %d\n", 277 func_id, npages); 278 mlx5_core_req_pages_handler(dev, func_id, npages); 279 } 280 break; 281 282 case MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT: 283 mlx5_port_module_event(dev, eqe); 284 break; 285 286 case MLX5_EVENT_TYPE_NIC_VPORT_CHANGE: 287 { 288 struct mlx5_eqe_vport_change *vc_eqe = 289 &eqe->data.vport_change; 290 u16 vport_num = be16_to_cpu(vc_eqe->vport_num); 291 292 if (dev->event) 293 dev->event(dev, 294 MLX5_DEV_EVENT_VPORT_CHANGE, 295 (unsigned long)vport_num); 296 } 297 break; 298 299 default: 300 mlx5_core_warn(dev, "Unhandled event 0x%x on EQ 0x%x\n", 301 eqe->type, eq->eqn); 302 break; 303 } 304 305 ++eq->cons_index; 306 eqes_found = 1; 307 ++set_ci; 308 309 /* The HCA will think the queue has overflowed if we 310 * don't tell it we've been processing events. We 311 * create our EQs with MLX5_NUM_SPARE_EQE extra 312 * entries, so we must update our consumer index at 313 * least that often. 314 */ 315 if (unlikely(set_ci >= MLX5_NUM_SPARE_EQE)) { 316 eq_update_ci(eq, 0); 317 set_ci = 0; 318 } 319 } 320 321 eq_update_ci(eq, 1); 322 323 return eqes_found; 324} 325 326static irqreturn_t mlx5_msix_handler(int irq, void *eq_ptr) 327{ 328 struct mlx5_eq *eq = eq_ptr; 329 struct mlx5_core_dev *dev = eq->dev; 330 331 mlx5_eq_int(dev, eq); 332 333 /* MSI-X vectors always belong to us */ 334 return IRQ_HANDLED; 335} 336 337static void init_eq_buf(struct mlx5_eq *eq) 338{ 339 struct mlx5_eqe *eqe; 340 int i; 341 342 for (i = 0; i < eq->nent; i++) { 343 eqe = get_eqe(eq, i); 344 eqe->owner = MLX5_EQE_OWNER_INIT_VAL; 345 } 346} 347 348int mlx5_create_map_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq, u8 vecidx, 349 int nent, u64 mask, const char *name, struct mlx5_uar *uar) 350{ 351 struct mlx5_priv *priv = &dev->priv; 352 struct mlx5_create_eq_mbox_in *in; 353 struct mlx5_create_eq_mbox_out out; 354 int err; 355 int inlen; 356 357 eq->nent = roundup_pow_of_two(nent + MLX5_NUM_SPARE_EQE); 358 err = mlx5_buf_alloc(dev, eq->nent * MLX5_EQE_SIZE, 2 * PAGE_SIZE, 359 &eq->buf); 360 if (err) 361 return err; 362 363 init_eq_buf(eq); 364 365 inlen = sizeof(*in) + sizeof(in->pas[0]) * eq->buf.npages; 366 in = mlx5_vzalloc(inlen); 367 if (!in) { 368 err = -ENOMEM; 369 goto err_buf; 370 } 371 memset(&out, 0, sizeof(out)); 372 373 mlx5_fill_page_array(&eq->buf, in->pas); 374 375 in->hdr.opcode = cpu_to_be16(MLX5_CMD_OP_CREATE_EQ); 376 in->ctx.log_sz_usr_page = cpu_to_be32(ilog2(eq->nent) << 24 | uar->index); 377 in->ctx.intr = vecidx; 378 in->ctx.log_page_size = eq->buf.page_shift - MLX5_ADAPTER_PAGE_SHIFT; 379 in->events_mask = cpu_to_be64(mask); 380 381 err = mlx5_cmd_exec(dev, in, inlen, &out, sizeof(out)); 382 if (err) 383 goto err_in; 384 385 if (out.hdr.status) { 386 err = mlx5_cmd_status_to_err(&out.hdr); 387 goto err_in; 388 } 389 390 eq->eqn = out.eq_number; 391 eq->irqn = vecidx; 392 eq->dev = dev; 393 eq->doorbell = uar->map + MLX5_EQ_DOORBEL_OFFSET; 394 snprintf(priv->irq_info[vecidx].name, MLX5_MAX_IRQ_NAME, "%s@pci:%s", 395 name, pci_name(dev->pdev)); 396 err = request_irq(priv->msix_arr[vecidx].vector, mlx5_msix_handler, 0, 397 priv->irq_info[vecidx].name, eq); 398 if (err) 399 goto err_eq; 400#ifdef RSS 401 if (vecidx >= MLX5_EQ_VEC_COMP_BASE) { 402 u8 bucket = vecidx - MLX5_EQ_VEC_COMP_BASE; 403 err = bind_irq_to_cpu(priv->msix_arr[vecidx].vector, 404 rss_getcpu(bucket % rss_getnumbuckets())); 405 if (err) 406 goto err_irq; 407 } 408#else 409 if (0) 410 goto err_irq; 411#endif 412 413 414 /* EQs are created in ARMED state 415 */ 416 eq_update_ci(eq, 1); 417 418 kvfree(in); 419 return 0; 420 421err_irq: 422 free_irq(priv->msix_arr[vecidx].vector, eq); 423 424err_eq: 425 mlx5_cmd_destroy_eq(dev, eq->eqn); 426 427err_in: 428 kvfree(in); 429 430err_buf: 431 mlx5_buf_free(dev, &eq->buf); 432 return err; 433} 434EXPORT_SYMBOL_GPL(mlx5_create_map_eq); 435 436int mlx5_destroy_unmap_eq(struct mlx5_core_dev *dev, struct mlx5_eq *eq) 437{ 438 int err; 439 440 free_irq(dev->priv.msix_arr[eq->irqn].vector, eq); 441 err = mlx5_cmd_destroy_eq(dev, eq->eqn); 442 if (err) 443 mlx5_core_warn(dev, "failed to destroy a previously created eq: eqn %d\n", 444 eq->eqn); 445 mlx5_buf_free(dev, &eq->buf); 446 447 return err; 448} 449EXPORT_SYMBOL_GPL(mlx5_destroy_unmap_eq); 450 451int mlx5_eq_init(struct mlx5_core_dev *dev) 452{ 453 int err; 454 455 spin_lock_init(&dev->priv.eq_table.lock); 456 457 err = 0; 458 459 return err; 460} 461 462 463void mlx5_eq_cleanup(struct mlx5_core_dev *dev) 464{ 465} 466 467int mlx5_start_eqs(struct mlx5_core_dev *dev) 468{ 469 struct mlx5_eq_table *table = &dev->priv.eq_table; 470 u32 async_event_mask = MLX5_ASYNC_EVENT_MASK; 471 int err; 472 473 if (MLX5_CAP_GEN(dev, port_module_event)) 474 async_event_mask |= (1ull << 475 MLX5_EVENT_TYPE_CODING_PORT_MODULE_EVENT); 476 477 if (MLX5_CAP_GEN(dev, nic_vport_change_event)) 478 async_event_mask |= (1ull << 479 MLX5_EVENT_TYPE_NIC_VPORT_CHANGE); 480 481 err = mlx5_create_map_eq(dev, &table->cmd_eq, MLX5_EQ_VEC_CMD, 482 MLX5_NUM_CMD_EQE, 1ull << MLX5_EVENT_TYPE_CMD, 483 "mlx5_cmd_eq", &dev->priv.uuari.uars[0]); 484 if (err) { 485 mlx5_core_warn(dev, "failed to create cmd EQ %d\n", err); 486 return err; 487 } 488 489 mlx5_cmd_use_events(dev); 490 491 err = mlx5_create_map_eq(dev, &table->async_eq, MLX5_EQ_VEC_ASYNC, 492 MLX5_NUM_ASYNC_EQE, async_event_mask, 493 "mlx5_async_eq", &dev->priv.uuari.uars[0]); 494 if (err) { 495 mlx5_core_warn(dev, "failed to create async EQ %d\n", err); 496 goto err1; 497 } 498 499 err = mlx5_create_map_eq(dev, &table->pages_eq, 500 MLX5_EQ_VEC_PAGES, 501 /* TODO: sriov max_vf + */ 1, 502 1 << MLX5_EVENT_TYPE_PAGE_REQUEST, "mlx5_pages_eq", 503 &dev->priv.uuari.uars[0]); 504 if (err) { 505 mlx5_core_warn(dev, "failed to create pages EQ %d\n", err); 506 goto err2; 507 } 508 509 return err; 510 511err2: 512 mlx5_destroy_unmap_eq(dev, &table->async_eq); 513 514err1: 515 mlx5_cmd_use_polling(dev); 516 mlx5_destroy_unmap_eq(dev, &table->cmd_eq); 517 return err; 518} 519 520int mlx5_stop_eqs(struct mlx5_core_dev *dev) 521{ 522 struct mlx5_eq_table *table = &dev->priv.eq_table; 523 int err; 524 525 err = mlx5_destroy_unmap_eq(dev, &table->pages_eq); 526 if (err) 527 return err; 528 529 mlx5_destroy_unmap_eq(dev, &table->async_eq); 530 mlx5_cmd_use_polling(dev); 531 532 err = mlx5_destroy_unmap_eq(dev, &table->cmd_eq); 533 if (err) 534 mlx5_cmd_use_events(dev); 535 536 return err; 537} 538 539int mlx5_core_eq_query(struct mlx5_core_dev *dev, struct mlx5_eq *eq, 540 struct mlx5_query_eq_mbox_out *out, int outlen) 541{ 542 struct mlx5_query_eq_mbox_in in; 543 int err; 544 545 memset(&in, 0, sizeof(in)); 546 memset(out, 0, outlen); 547 in.hdr.opcode = cpu_to_be16(MLX5_CMD_OP_QUERY_EQ); 548 in.eqn = eq->eqn; 549 err = mlx5_cmd_exec(dev, &in, sizeof(in), out, outlen); 550 if (err) 551 return err; 552 553 if (out->hdr.status) 554 err = mlx5_cmd_status_to_err(&out->hdr); 555 556 return err; 557} 558 559EXPORT_SYMBOL_GPL(mlx5_core_eq_query); 560 561static const char *mlx5_port_module_event_error_type_to_string(u8 error_type) 562{ 563 switch (error_type) { 564 case MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED: 565 return "Power Budget Exceeded"; 566 case MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE: 567 return "Long Range for non MLNX cable/module"; 568 case MLX5_MODULE_EVENT_ERROR_BUS_STUCK: 569 return "Bus stuck(I2C or data shorted)"; 570 case MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT: 571 return "No EEPROM/retry timeout"; 572 case MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST: 573 return "Enforce part number list"; 574 case MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER: 575 return "Unknown identifier"; 576 case MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE: 577 return "High Temperature"; 578 579 default: 580 return "Unknown error type"; 581 } 582} 583 584static void mlx5_port_module_event(struct mlx5_core_dev *dev, 585 struct mlx5_eqe *eqe) 586{ 587 unsigned int module_num; 588 unsigned int module_status; 589 unsigned int error_type; 590 struct mlx5_eqe_port_module_event *module_event_eqe; 591 struct pci_dev *pdev = dev->pdev; 592 593 module_event_eqe = &eqe->data.port_module_event; 594 595 module_num = (unsigned int)module_event_eqe->module; 596 module_status = (unsigned int)module_event_eqe->module_status & 597 PORT_MODULE_EVENT_MODULE_STATUS_MASK; 598 error_type = (unsigned int)module_event_eqe->error_type & 599 PORT_MODULE_EVENT_ERROR_TYPE_MASK; 600 601 switch (module_status) { 602 case MLX5_MODULE_STATUS_PLUGGED: 603 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: plugged", module_num); 604 break; 605 606 case MLX5_MODULE_STATUS_UNPLUGGED: 607 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: unplugged", module_num); 608 break; 609 610 case MLX5_MODULE_STATUS_ERROR: 611 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, status: error, %s", module_num, mlx5_port_module_event_error_type_to_string(error_type)); 612 break; 613 614 default: 615 device_printf((&pdev->dev)->bsddev, "INFO: ""Module %u, unknown status", module_num); 616 } 617} 618 619